Layout Gateset is not being considered

[dvnoble]

Greetings!

The Perth backennd in Qiskit has no H gate. You can check in https://github.com/Qiskit/qiskit-ibm-runtime/blob/stable/0.24/qiskit_ibm_runtime/fake_provider/backends/perth/conf_perth.json. Search for "basis_gates": ["cx", "id", "rz", "sx", "x"]
When I use the Perth layout according to the Qiskit specification (without H gates in the layout file) and I use the following dof script file:

qcir read benchmark/qft/qft_7.qasm
qcir print --stat
qc2zx
zx print --stat
zx copy
zx optimize --full
zx print --stat
zx2qc
qcir print --stat
qcir optimize
qcir print --stat

device read benchmark/topology/perth_7.layout
duostra -c
qcir print --stat

qcir list

qcir write examples/qft_7-opt.qasm

quit -f

The resulting circuit still includes H gates which I think is not the expected. I am using qsyn version 0.7.0.

[dvnoble]

There is the qc translate command to make sure that the result circuit obeys the gateset.

Edit: qc translate has only three options which I don't know if they represent the gateset in the layout. Here is the layout I used (note that I've removed the h from gateset):

NAME: perth_7
QUBITNUM: 7
GATESET: {x, rz, id, sx, cnot}
COUPLINGMAP: [[1], [0, 2, 3], [1], [1, 5], [5], [3, 4, 6], [5]]
SGERROR: [0, 0, 0, 0, 0, 0, 0]
SGTIME: [0, 0, 0, 0, 0, 0, 0]
CNOTERROR: [[1], [0, 2, 3], [1], [1, 5], [5], [3, 4, 6], [5]]
CNOTTIME: [[1], [0, 2, 3], [1], [1, 5], [5], [3, 4, 6], [5]]

[dvnoble]

Related to this, is there Qubit Re-mapping on Qsyn?