Calibrating PM Table

[dust0vich]

Feature Request

Adding 7700x PM table.

Use Case

What problem does this solve? Why do you need it?
Allows PM table listing to be full.

Proposed Solution

How should it work?
Calibrate table. I don't know if this is a ryzen_smu or a corecycler issue.

Alternatives Considered

What other approaches did you consider?
I have submitted SMU table to ryzen_smu, is closed report for 7xxx cpus.

Additional Context

Any reference implementations, documentation, or related projects.
amkillam/ryzen_smu#17 (comment)

[dust0vich]

Looks like zenstates power table has it as
{ 0x540104, 0x6A8, 0x118, 0x128, 0x138, 0xD0, 0x430, -1, -1, -1, 0xE0 },
I can confirm.