Simulator/Loop.c at master · LS1222/Simulator · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
#ifndef __LOOP_C__
#define __LOOP_C__

/*===================================
|           INCLUDES                |
====================================*/
#include "Loop.h"

/*===================================
|           FUNCTIONS               |
====================================*/
void mainLoop(Simulator* sim) {
	while (NO_ERROR == sim->status) {
		Fetch(sim);
		Decode(sim);

		// IRQ handling in normal operation.
		// Go to an ISR (Interrupt Service Routine).
		if (!sim->isr_mode) {

			// Get the irq status.
			sim->irq0 = sim->io_regs[IO_REGISTER_IRQ0_ENABLE] & sim->io_regs[IO_REGISTER_IRQ0_STATUS];
			sim->irq1 = sim->io_regs[IO_REGISTER_IRQ1_ENABLE] & sim->io_regs[IO_REGISTER_IRQ1_STATUS];
			sim->irq2 = sim->io_regs[IO_REGISTER_IRQ2_ENABLE] & sim->io_regs[IO_REGISTER_IRQ2_STATUS];

			// Store previous PC value (return address).
			sim->io_regs[IO_REGISTER_IRQ_RETURN] = sim->regs[REGISTER_PC];

			// The service routine is stored at the IRQ HANDLE io register.
			sim->regs[REGISTER_PC] = sim->io_regs[IO_REGISTER_IRQ_HANDLER];

			// Reset the interrupts (they have been read already).
			sim->io_regs[IO_REGISTER_IRQ0_STATUS] = REGISTER_DEFAULT;
			sim->io_regs[IO_REGISTER_IRQ1_STATUS] = REGISTER_DEFAULT;
			sim->io_regs[IO_REGISTER_IRQ2_STATUS] = REGISTER_DEFAULT;

		// Perform the opcode.
		} else {
			Execute(sim);
		}
	}
}

void Fetch(Simulator* sim) {
	sim->lines[0] = sim->mem[sim->regs[REGISTER_PC]];
	sim->lines[1] = sim->mem[(sim->regs[REGISTER_PC] + 1) % MEMORY_SIZE];
}

void Decode(Simulator* sim) {

	// Parse the command into I command or R command.
	// The default is R Command.
	sim->command.opcode = (sim->lines[0].word & OPCODE_MASK) >> 12;
	sim->command.rd = (sim->lines[0].word & RD_MASK) >> 8;
	sim->command.rs = (sim->lines[0].word & RS_MASK) >> 4;
	sim->command.rt = sim->lines[0].word & RT_MASK;

	// Advance the PC register.
	// R command by 1, I command by 2.
	sim->regs[REGISTER_PC]++;

	// Check for immidiate format in the registers' nums.
	if ((REGISTER_IMMIDIATE == sim->command.rd) ||
		(REGISTER_IMMIDIATE == sim->command.rs) ||
		(REGISTER_IMMIDIATE == sim->command.rt)) {

		// IFormat command.
		sim->command.imm = sim->lines[1].word;
		sim->regs[REGISTER_PC]++;

		// Advance the clock (load the immidiate register).
		sim->regs[REGISTER_IMMIDIATE] = sim->lines[1].word;
		sim->cycles++;

		// Advance the timer.
		if (sim->io_regs[IO_REGISTER_TIMER_ENABLE]) {
			sim->io_regs[IO_REGISTER_TIMER_CURRENT]++;

			if (sim->io_regs[IO_REGISTER_TIMER_CURRENT] == sim->io_regs[IO_REGISTER_TIMER_MAX]) {
				// Reset the value of the timer.
				sim->io_regs[IO_REGISTER_TIMER_CURRENT] = REGISTER_DEFAULT;

				// Set the interrupts.
				sim->io_regs[IO_REGISTER_IRQ0_STATUS] = 1;
			}
		}
	}
}

void Execute(Simulator* sim) {
	// Advance the clock.
	sim->cycles++;

	// Advance the timer.
	if (sim->io_regs[IO_REGISTER_TIMER_ENABLE]) {
		sim->io_regs[IO_REGISTER_TIMER_CURRENT]++;

		if (sim->io_regs[IO_REGISTER_TIMER_CURRENT] == sim->io_regs[IO_REGISTER_TIMER_MAX]) {
			// Reset the value of the timer.
			sim->io_regs[IO_REGISTER_TIMER_CURRENT] = REGISTER_DEFAULT;

			// Set the interrupts.
			sim->io_regs[IO_REGISTER_IRQ0_STATUS] = 1;
		}
	}

	// Perform the operation.
	opcode_functions[sim->command.opcode](sim);

	// Print Trace.
	fprintf(sim->files.trace->handle, "%03X ", sim->regs[REGISTER_PC]);
	fprintf(sim->files.trace->handle, "%08X ", sim->lines[0].word);
	for (RegisterOpcode i = REGISTER_ZERO; i <= REGISTER_STACK_POINTER; i++) {
		fprintf(sim->files.trace->handle, "%08X ", sim->regs[i]);
	}

	fprintf(sim->files.trace->handle, "%08X", sim->regs[REGISTER_RETURN_ADDRESS]);
	fflush(sim->files.trace->handle);
	if (OPCODE_HALT != sim->command.opcode) {
		fprintf(sim->files.trace->handle, "\n");
	}
}

#endif // __LOOP_C__