HW2/Decoder.vcd at master · LoganSweet/HW2 · GitHub

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$date
	Thu Sep 21 00:01:30 2017
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module behavioralDecoder $end
$var wire 1 ! address0 $end
$var wire 1 " address1 $end
$var wire 1 # enable $end
$var wire 1 $ out0 $end
$var wire 1 % out1 $end
$var wire 1 & out2 $end
$var wire 1 ' out3 $end
$upscope $end
$scope module testDecoder $end
$var wire 1 ( out0 $end
$var wire 1 ) out1 $end
$var wire 1 * out2 $end
$var wire 1 + out3 $end
$var reg 1 , addr0 $end
$var reg 1 - addr1 $end
$var reg 1 . enable $end
$scope module decode $end
$var wire 1 / A0 $end
$var wire 1 0 A0andA1 $end
$var wire 1 1 A0andnA1 $end
$var wire 1 2 A1 $end
$var wire 1 3 enable $end
$var wire 1 4 nA0 $end
$var wire 1 5 nA0andA1 $end
$var wire 1 6 nA0andnA1 $end
$var wire 1 7 nA1 $end
$var wire 1 ( out0 $end
$var wire 1 ) out1 $end
$var wire 1 * out2 $end
$var wire 1 + out3 $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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$end
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