Follow-up to #346 / SCHED_MIC (#385).
#346 asks that once a thread lands on an AMD CCD it avoid cross-CCD migration to preserve L3 locality. SCHED_MIC intentionally left the long-term balancer and work-stealing class-blind (they migrate by real load) to avoid placement/balancer ping-pong, so there is no CCD-boundary migration penalty beyond ULE's stock cache-level affinity.
Goal: add a CCD/last-level-cache affinity penalty in the migration paths (balancer / tdq_move / steal) so cross-CCD moves are discouraged unless they relieve real imbalance. Make it tunable and weigh it against the existing class-blind balancing decision documented in scheduler.md.
Relevant code: sched_balance_group(), tdq_move(), cpu_search_highest() in sys/kern/sched_mic.c.
Follow-up to #346 / SCHED_MIC (#385).
#346 asks that once a thread lands on an AMD CCD it avoid cross-CCD migration to preserve L3 locality. SCHED_MIC intentionally left the long-term balancer and work-stealing class-blind (they migrate by real load) to avoid placement/balancer ping-pong, so there is no CCD-boundary migration penalty beyond ULE's stock cache-level affinity.
Goal: add a CCD/last-level-cache affinity penalty in the migration paths (balancer /
tdq_move/ steal) so cross-CCD moves are discouraged unless they relieve real imbalance. Make it tunable and weigh it against the existing class-blind balancing decision documented inscheduler.md.Relevant code:
sched_balance_group(),tdq_move(),cpu_search_highest()insys/kern/sched_mic.c.