Thanks for your excellent work!
I'm reproducing your experiments and following the code, but I have some questions regarding the configuration in train_ERR_UHDLL.yml:
- Learning Rate Schedule: The paper mentions training with AdamW, starting at LR 0.0005 and reducing to 1e-7 via cosine annealing over 100k iterations. However, the config file shows the LR being reduced from 5e-4 to 1e-4 over 500k iterations.
- Training Patch Size: The paper specifies a patch size of 512x512 for UHDLL, while the config uses 768x768.
Could you please advise on whether I should use the settings in the config file or the parameters described in the paper? Any guidance would be greatly appreciated!
Thanks for your excellent work!
I'm reproducing your experiments and following the code, but I have some questions regarding the configuration in train_ERR_UHDLL.yml:
Could you please advise on whether I should use the settings in the config file or the parameters described in the paper? Any guidance would be greatly appreciated!