From 9066412bd7a15dfbcadd802c9485c8aeed54d5f5 Mon Sep 17 00:00:00 2001 From: Jimmy Pan Date: Sat, 4 Apr 2026 16:17:53 -0700 Subject: [PATCH 1/2] initalization on gimbal test stand --- .../firmware/gimbal_test_stand/.mxproject | 26 + .../gimbal_test_stand/.vscode/extensions.json | 7 + .../gimbal_test_stand/.vscode/launch.json | 46 + .../firmware/gimbal_test_stand/CMakeLists.txt | 68 + .../gimbal_test_stand/CMakePresets.json | 38 + .../gimbal_test_stand/Core/Inc/main.h | 80 + .../Core/Inc/stm32h5xx_hal_conf.h | 480 + .../gimbal_test_stand/Core/Inc/stm32h5xx_it.h | 67 + .../Core/Inc/stm32h5xx_nucleo_conf.h | 76 + .../gimbal_test_stand/Core/Src/main.c | 336 + .../Core/Src/stm32h5xx_hal_msp.c | 78 + .../gimbal_test_stand/Core/Src/stm32h5xx_it.c | 217 + .../gimbal_test_stand/Core/Src/syscalls.c | 244 + .../gimbal_test_stand/Core/Src/sysmem.c | 87 + .../Core/Src/system_stm32h5xx.c | 403 + .../BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c | 797 + .../BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.h | 420 + .../STM32H5xx_Nucleo/stm32h5xx_nucleo_errno.h | 45 + .../Device/ST/STM32H5xx/Include/stm32h533xx.h | 20685 ++ .../Device/ST/STM32H5xx/Include/stm32h5xx.h | 261 + .../ST/STM32H5xx/Include/system_stm32h5xx.h | 107 + .../CMSIS/Device/ST/STM32H5xx/LICENSE.txt | 6 + .../Drivers/CMSIS/Include/cachel1_armv7.h | 441 + .../Drivers/CMSIS/Include/cmsis_armcc.h | 888 + .../Drivers/CMSIS/Include/cmsis_armclang.h | 1503 + .../CMSIS/Include/cmsis_armclang_ltm.h | 1928 + .../Drivers/CMSIS/Include/cmsis_compiler.h | 283 + .../Drivers/CMSIS/Include/cmsis_gcc.h | 2211 + .../Drivers/CMSIS/Include/cmsis_iccarm.h | 1002 + .../Drivers/CMSIS/Include/cmsis_version.h | 39 + .../Drivers/CMSIS/Include/core_armv81mml.h | 4228 + .../Drivers/CMSIS/Include/core_armv8mbl.h | 2222 + .../Drivers/CMSIS/Include/core_armv8mml.h | 3209 + .../Drivers/CMSIS/Include/core_cm0.h | 952 + .../Drivers/CMSIS/Include/core_cm0plus.h | 1087 + .../Drivers/CMSIS/Include/core_cm1.h | 979 + .../Drivers/CMSIS/Include/core_cm23.h | 2297 + .../Drivers/CMSIS/Include/core_cm3.h | 1943 + .../Drivers/CMSIS/Include/core_cm33.h | 3277 + .../Drivers/CMSIS/Include/core_cm35p.h | 3277 + .../Drivers/CMSIS/Include/core_cm4.h | 2129 + .../Drivers/CMSIS/Include/core_cm55.h | 4817 + .../Drivers/CMSIS/Include/core_cm7.h | 2366 + .../Drivers/CMSIS/Include/core_cm85.h | 4672 + .../Drivers/CMSIS/Include/core_sc000.h | 1030 + .../Drivers/CMSIS/Include/core_sc300.h | 1917 + .../Drivers/CMSIS/Include/core_starmc1.h | 3592 + .../Drivers/CMSIS/Include/mpu_armv7.h | 275 + .../Drivers/CMSIS/Include/mpu_armv8.h | 352 + .../Drivers/CMSIS/Include/pac_armv81.h | 206 + .../Drivers/CMSIS/Include/pmu_armv8.h | 337 + .../Drivers/CMSIS/Include/tz_context.h | 70 + .../Drivers/CMSIS/LICENSE.txt | 201 + .../Inc/Legacy/stm32_hal_legacy.h | 4436 + .../STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h | 1005 + .../Inc/stm32h5xx_hal_cortex.h | 429 + .../Inc/stm32h5xx_hal_def.h | 232 + .../Inc/stm32h5xx_hal_dma.h | 1223 + .../Inc/stm32h5xx_hal_dma_ex.h | 803 + .../Inc/stm32h5xx_hal_exti.h | 534 + .../Inc/stm32h5xx_hal_flash.h | 960 + .../Inc/stm32h5xx_hal_flash_ex.h | 1178 + .../Inc/stm32h5xx_hal_gpio.h | 410 + .../Inc/stm32h5xx_hal_gpio_ex.h | 612 + .../Inc/stm32h5xx_hal_icache.h | 300 + .../Inc/stm32h5xx_hal_pwr.h | 695 + .../Inc/stm32h5xx_hal_pwr_ex.h | 605 + .../Inc/stm32h5xx_hal_rcc.h | 5953 + .../Inc/stm32h5xx_hal_rcc_ex.h | 4827 + .../Inc/stm32h5xx_hal_uart.h | 1775 + .../Inc/stm32h5xx_hal_uart_ex.h | 440 + .../Inc/stm32h5xx_hal_usart.h | 1293 + .../Inc/stm32h5xx_hal_usart_ex.h | 282 + .../Inc/stm32h5xx_ll_bus.h | 3016 + .../Inc/stm32h5xx_ll_cortex.h | 1388 + .../Inc/stm32h5xx_ll_crs.h | 812 + .../Inc/stm32h5xx_ll_dma.h | 7481 + .../Inc/stm32h5xx_ll_exti.h | 2892 + .../Inc/stm32h5xx_ll_gpio.h | 1182 + .../Inc/stm32h5xx_ll_icache.h | 788 + .../Inc/stm32h5xx_ll_pwr.h | 2269 + .../Inc/stm32h5xx_ll_rcc.h | 7029 + .../Inc/stm32h5xx_ll_system.h | 1934 + .../Inc/stm32h5xx_ll_utils.h | 376 + .../Drivers/STM32H5xx_HAL_Driver/LICENSE.txt | 6 + .../STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c | 1423 + .../Src/stm32h5xx_hal_cortex.c | 873 + .../Src/stm32h5xx_hal_dma.c | 1722 + .../Src/stm32h5xx_hal_dma_ex.c | 4777 + .../Src/stm32h5xx_hal_exti.c | 874 + .../Src/stm32h5xx_hal_flash.c | 983 + .../Src/stm32h5xx_hal_flash_ex.c | 2161 + .../Src/stm32h5xx_hal_gpio.c | 754 + .../Src/stm32h5xx_hal_icache.c | 657 + .../Src/stm32h5xx_hal_pwr.c | 674 + .../Src/stm32h5xx_hal_pwr_ex.c | 914 + .../Src/stm32h5xx_hal_rcc.c | 1901 + .../Src/stm32h5xx_hal_rcc_ex.c | 7331 + .../Src/stm32h5xx_hal_uart.c | 4854 + .../Src/stm32h5xx_hal_uart_ex.c | 1056 + .../Src/stm32h5xx_hal_usart.c | 4032 + .../Src/stm32h5xx_hal_usart_ex.c | 541 + .../gimbal_test_stand/STM32H533xx_FLASH.ld | 237 + .../gimbal_test_stand/STM32H533xx_RAM.ld | 237 + .../cmake/gcc-arm-none-eabi.cmake | 47 + .../gimbal_test_stand/cmake/starm-clang.cmake | 65 + .../cmake/stm32cubemx/CMakeLists.txt | 95 + .../gimbal_test_stand/gimbal_test_stand.ioc | 245 + .../platform/svd/STM32H533.svd | 180402 +++++++++++++++ .../gimbal_test_stand/startup_stm32h533xx.s | 647 + .../ulysses-flight-controller/Core/Src/main.c | 3 +- 111 files changed, 352973 insertions(+), 1 deletion(-) create mode 100644 embedded-software/firmware/gimbal_test_stand/.mxproject create mode 100644 embedded-software/firmware/gimbal_test_stand/.vscode/extensions.json create mode 100644 embedded-software/firmware/gimbal_test_stand/.vscode/launch.json create mode 100644 embedded-software/firmware/gimbal_test_stand/CMakeLists.txt create mode 100644 embedded-software/firmware/gimbal_test_stand/CMakePresets.json create mode 100644 embedded-software/firmware/gimbal_test_stand/Core/Inc/main.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_hal_conf.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_it.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_nucleo_conf.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Core/Src/main.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Core/Src/stm32h5xx_hal_msp.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Core/Src/stm32h5xx_it.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Core/Src/syscalls.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Core/Src/sysmem.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Core/Src/system_stm32h5xx.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo_errno.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/LICENSE.txt create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cachel1_armv7.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_armcc.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_armclang.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_armclang_ltm.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_compiler.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_gcc.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_iccarm.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_version.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_armv81mml.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_armv8mbl.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_armv8mml.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm0.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm0plus.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm1.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm23.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm3.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm33.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm35p.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm4.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm55.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm7.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm85.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_sc000.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_sc300.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_starmc1.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/mpu_armv7.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/mpu_armv8.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/pac_armv81.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/pmu_armv8.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/tz_context.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/LICENSE.txt create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/LICENSE.txt create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c create mode 100644 embedded-software/firmware/gimbal_test_stand/STM32H533xx_FLASH.ld create mode 100644 embedded-software/firmware/gimbal_test_stand/STM32H533xx_RAM.ld create mode 100644 embedded-software/firmware/gimbal_test_stand/cmake/gcc-arm-none-eabi.cmake create mode 100644 embedded-software/firmware/gimbal_test_stand/cmake/starm-clang.cmake create mode 100644 embedded-software/firmware/gimbal_test_stand/cmake/stm32cubemx/CMakeLists.txt create mode 100644 embedded-software/firmware/gimbal_test_stand/gimbal_test_stand.ioc create mode 100644 embedded-software/firmware/gimbal_test_stand/platform/svd/STM32H533.svd create mode 100644 embedded-software/firmware/gimbal_test_stand/startup_stm32h533xx.s diff --git a/embedded-software/firmware/gimbal_test_stand/.mxproject b/embedded-software/firmware/gimbal_test_stand/.mxproject new file mode 100644 index 00000000..f15a7cda --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/.mxproject @@ -0,0 +1,26 @@ +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=4 +HeaderFiles#0=../Core/Inc/stm32h5xx_nucleo_conf.h +HeaderFiles#1=../Core/Inc/stm32h5xx_it.h +HeaderFiles#2=../Core/Inc/stm32h5xx_hal_conf.h +HeaderFiles#3=../Core/Inc/main.h +HeaderFolderListSize=1 +HeaderPath#0=../Core/Inc +HeaderFiles=; +SourceFileListSize=3 +SourceFiles#0=../Core/Src/stm32h5xx_it.c +SourceFiles#1=../Core/Src/stm32h5xx_hal_msp.c +SourceFiles#2=../Core/Src/main.c +SourceFolderListSize=1 +SourcePath#0=../Core/Src +SourceFiles=; + +[PreviousLibFiles] +LibFiles=Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dmamux.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo_errno.h;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dmamux.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo_errno.h;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/pac_armv81.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/cachel1_armv7.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm85.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_starmc1.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/pmu_armv8.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm55.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm3.h; + +[PreviousUsedCMakes] +SourceFiles=Core/Src/main.c;Core/Src/stm32h5xx_it.c;Core/Src/stm32h5xx_hal_msp.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Core/Src/system_stm32h5xx.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Core/Src/system_stm32h5xx.c;;; +HeaderPath=Drivers/STM32H5xx_HAL_Driver/Inc;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy;Drivers/BSP/STM32H5xx_Nucleo;Drivers/CMSIS/Device/ST/STM32H5xx/Include;Drivers/CMSIS/Include;Core/Inc; +CDefines=USE_NUCLEO_64;USE_HAL_DRIVER;STM32H533xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + diff --git a/embedded-software/firmware/gimbal_test_stand/.vscode/extensions.json b/embedded-software/firmware/gimbal_test_stand/.vscode/extensions.json new file mode 100644 index 00000000..a1f5b97d --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/.vscode/extensions.json @@ -0,0 +1,7 @@ +{ + "recommendations": [ + "ms-vscode.cmake-tools", + "marus25.cortex-debug", + "ms-vscode.cpptools" + ] +} \ No newline at end of file diff --git a/embedded-software/firmware/gimbal_test_stand/.vscode/launch.json b/embedded-software/firmware/gimbal_test_stand/.vscode/launch.json new file mode 100644 index 00000000..a2112c7e --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/.vscode/launch.json @@ -0,0 +1,46 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "name": "Ulysses - Debug", + "cwd": "${workspaceFolder}", + "executable": "${config:cmake.buildDirectory}/debug/gimbal_test_stand.elf", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${env:STM32_OPENOCD_PATH}", + "configFiles": [ + "interface/stlink-dap.cfg", + "target/stm32h5x.cfg" + ], + "svdFile": "${workspaceFolder}/platform/svd/STM32H533.svd", + "searchDir": [ + "${env:STM32_OPENOCD_SCRIPTS_PATH}" + ], + "runToEntryPoint": "main", + "showDevDebugOutput": "raw" + }, + { + "name": "Ulysses - Release", + "cwd": "${workspaceFolder}", + "executable": "${config:cmake.buildDirectory}/release/gimbal_test_stand.elf", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${env:STM32_OPENOCD_PATH}", + "configFiles": [ + "interface/stlink-dap.cfg", + "target/stm32h5x.cfg" + ], + "svdFile": "${workspaceFolder}/platform/svd/STM32H533.svd", + "searchDir": [ + "${env:STM32_OPENOCD_SCRIPTS_PATH}" + ], + "runToEntryPoint": "main", + "showDevDebugOutput": "raw" + } + ] +} \ No newline at end of file diff --git a/embedded-software/firmware/gimbal_test_stand/CMakeLists.txt b/embedded-software/firmware/gimbal_test_stand/CMakeLists.txt new file mode 100644 index 00000000..326e3d22 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/CMakeLists.txt @@ -0,0 +1,68 @@ +cmake_minimum_required(VERSION 3.22) + +# +# This file is generated only once, +# and is not re-generated if converter is called multiple times. +# +# User is free to modify the file as much as necessary +# + +# Setup compiler settings +set(CMAKE_C_STANDARD 11) +set(CMAKE_C_STANDARD_REQUIRED ON) +set(CMAKE_C_EXTENSIONS ON) + + +# Define the build type +if(NOT CMAKE_BUILD_TYPE) + set(CMAKE_BUILD_TYPE "debug") +endif() + +# Set the project name +set(CMAKE_PROJECT_NAME gimbal_test_stand) + +# Enable compile command to ease indexing with e.g. clangd +set(CMAKE_EXPORT_COMPILE_COMMANDS TRUE) + +# Core project settings +project(${CMAKE_PROJECT_NAME}) +message("Build type: " ${CMAKE_BUILD_TYPE}) + +# Enable CMake support for ASM and C languages +enable_language(C ASM) + +# Create an executable object type +add_executable(${CMAKE_PROJECT_NAME}) + +# Add STM32CubeMX generated sources +add_subdirectory(cmake/stm32cubemx) + +# Link directories setup +target_link_directories(${CMAKE_PROJECT_NAME} PRIVATE + # Add user defined library search paths +) + +# Add sources to executable +target_sources(${CMAKE_PROJECT_NAME} PRIVATE + # Add user sources here +) + +# Add include paths +target_include_directories(${CMAKE_PROJECT_NAME} PRIVATE + # Add user defined include paths +) + +# Add project symbols (macros) +target_compile_definitions(${CMAKE_PROJECT_NAME} PRIVATE + # Add user defined symbols +) + +# Remove wrong libob.a library dependency when using cpp files +list(REMOVE_ITEM CMAKE_C_IMPLICIT_LINK_LIBRARIES ob) + +# Add linked libraries +target_link_libraries(${CMAKE_PROJECT_NAME} + stm32cubemx + + # Add user defined libraries +) diff --git a/embedded-software/firmware/gimbal_test_stand/CMakePresets.json b/embedded-software/firmware/gimbal_test_stand/CMakePresets.json new file mode 100644 index 00000000..d78d4ef7 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/CMakePresets.json @@ -0,0 +1,38 @@ +{ + "version": 3, + "configurePresets": [ + { + "name": "default", + "hidden": true, + "generator": "Ninja", + "binaryDir": "${sourceDir}/build/${presetName}", + "toolchainFile": "${sourceDir}/cmake/gcc-arm-none-eabi.cmake", + "cacheVariables": { + } + }, + { + "name": "debug", + "inherits": "default", + "cacheVariables": { + "CMAKE_BUILD_TYPE": "debug" + } + }, + { + "name": "release", + "inherits": "default", + "cacheVariables": { + "CMAKE_BUILD_TYPE": "release" + } + } + ], + "buildPresets": [ + { + "name": "debug", + "configurePreset": "debug" + }, + { + "name": "release", + "configurePreset": "release" + } + ] +} \ No newline at end of file diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Inc/main.h b/embedded-software/firmware/gimbal_test_stand/Core/Inc/main.h new file mode 100644 index 00000000..09cd3b06 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Core/Inc/main.h @@ -0,0 +1,80 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +#include "stm32h5xx_nucleo.h" +#include + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define SWDIO_Pin GPIO_PIN_13 +#define SWDIO_GPIO_Port GPIOA +#define SWCLK_Pin GPIO_PIN_14 +#define SWCLK_GPIO_Port GPIOA +#define JTDI_Pin GPIO_PIN_15 +#define JTDI_GPIO_Port GPIOA +#define SWO_Pin GPIO_PIN_3 +#define SWO_GPIO_Port GPIOB + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_hal_conf.h b/embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_hal_conf.h new file mode 100644 index 00000000..e147edda --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_hal_conf.h @@ -0,0 +1,480 @@ +/* USER CODE BEGIN Header */ +/** + ********************************************************************************************************************** + + * @file stm32h5xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ********************************************************************************************************************** + + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ + +#ifndef STM32H5xx_HAL_CONF_H +#define STM32H5xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/* Exported constants ------------------------------------------------------------------------------------------------*/ + +/* ########################################### Module Selection ##################################################### */ + +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED +/*#define HAL_CCB_MODULE_ENABLED */ +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_CEC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_DCACHE_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_DTS_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_GTZC_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I3C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_XSPI_MODULE_ENABLED */ +/*#define HAL_OTFDEC_MODULE_ENABLED */ +/*#define HAL_PKA_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SDIO_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_RAMCFG_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_PSSI_MODULE_ENABLED */ +#define HAL_ICACHE_MODULE_ENABLED +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ####################################### Oscillator Values adaptation ##############################################*/ + +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Core Speed oscillator (CSI) default value. + * This value is the default CSI range value after Reset. + */ +#if !defined (CSI_VALUE) + #define CSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ + +#if !defined (LSI_STARTUP_TIME) + #define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in us */ +#endif /* LSI_STARTUP_TIME */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ +/** + * @brief External clock source for SPI peripheral + * This value is used by the SPI HAL module to compute the SPI clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ############################################ System Configuration ################################################ */ + +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U /*!< Enable prefetch */ + +/* ############################################ Assert Selection #################################################### */ + +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ + +/* #define USE_FULL_ASSERT 1U */ + +/* ############################################ Register callback feature configuration ############################# */ + +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32h5xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CCB_REGISTER_CALLBACKS 0U /* CCB register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_I3C_REGISTER_CALLBACKS 0U /* I3C register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */ + +/* ############################################ SPI peripheral configuration ######################################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* ################## SDIO peripheral configuration ######################### */ + +#define USE_SDIO_TRANSCEIVER 0U +#define SDIO_MAX_IO_NUMBER 7U + +/* Includes ----------------------------------------------------------------------------------------------------------*/ + +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32h5xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32h5xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED + #include "stm32h5xx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_DCACHE_MODULE_ENABLED + #include "stm32h5xx_hal_dcache.h" +#endif /* HAL_DCACHE_MODULE_ENABLED */ + +#ifdef HAL_GTZC_MODULE_ENABLED + #include "stm32h5xx_hal_gtzc.h" +#endif /* HAL_GTZC_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32h5xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED + #include "stm32h5xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32h5xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED + #include "stm32h5xx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32h5xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32h5xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32h5xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32h5xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32h5xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32h5xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32h5xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32h5xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32h5xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32h5xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32h5xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32h5xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32h5xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED + #include "stm32h5xx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32h5xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32h5xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32h5xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED + #include "stm32h5xx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32h5xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32h5xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32h5xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32h5xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32h5xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32h5xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32h5xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32h5xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32h5xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32h5xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32h5xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32h5xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_CCB_MODULE_ENABLED +#include "stm32h5xx_hal_ccb.h" +#endif /* HAL_CCB_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32h5xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32h5xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32h5xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32h5xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32h5xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_OTFDEC_MODULE_ENABLED + #include "stm32h5xx_hal_otfdec.h" +#endif /* HAL_OTFDEC_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32h5xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED + #include "stm32h5xx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +/* Exported macro ----------------------------------------------------------------------------------------------------*/ + +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ----------------------------------------------------------------------------------------------- */ + + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_CONF_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_it.h b/embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_it.h new file mode 100644 index 00000000..991871bc --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_it.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h5xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H5xx_IT_H +#define __STM32H5xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void EXTI13_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H5xx_IT_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_nucleo_conf.h b/embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_nucleo_conf.h new file mode 100644 index 00000000..fe6a475e --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_nucleo_conf.h @@ -0,0 +1,76 @@ + +/** + ****************************************************************************** + * @file stm32h5xx_nucleo_conf.h + * @author MCD Application Team + * @brief STM32H5xx_Nucleo board configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5XX_NUCLEO_CONF_H +#define STM32H5XX_NUCLEO_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32H5XX_NUCLEO + * @{ + */ + +/** @defgroup STM32H5XX_NUCLEO_CONFIG Config + * @{ + */ + +/** @defgroup STM32H5XX_NUCLEO_CONFIG_Exported_Constants Exported Constants + * @{ + */ +/* Nucleo pin and part number defines */ +#define USE_NUCLEO_H533RE + +/* COM define */ +#define USE_COM_LOG 1U +#define USE_BSP_COM_FEATURE 1U + +/* IRQ priorities */ +#define BSP_BUTTON_USER_IT_PRIORITY 15U + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5XX_NUCLEO_CONF_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Src/main.c b/embedded-software/firmware/gimbal_test_stand/Core/Src/main.c new file mode 100644 index 00000000..cb81e8b6 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Core/Src/main.c @@ -0,0 +1,336 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +COM_InitTypeDef BspCOMInit; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MPU_Config(void); +static void MX_GPIO_Init(void); +static void MX_ICACHE_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* MPU Configuration--------------------------------------------------------*/ + MPU_Config(); + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_ICACHE_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Initialize leds */ + BSP_LED_Init(LED_GREEN); + + /* Initialize USER push-button, will be used to trigger an interrupt each time it's pressed.*/ + BSP_PB_Init(BUTTON_USER, BUTTON_MODE_EXTI); + + /* Initialize COM1 port (115200, 8 bits (7-bit data + 1 stop bit), no parity */ + BspCOMInit.BaudRate = 115200; + BspCOMInit.WordLength = COM_WORDLENGTH_8B; + BspCOMInit.StopBits = COM_STOPBITS_1; + BspCOMInit.Parity = COM_PARITY_NONE; + BspCOMInit.HwFlowCtl = COM_HWCONTROL_NONE; + if (BSP_COM_Init(COM1, &BspCOMInit) != BSP_ERROR_NONE) + { + Error_Handler(); + } + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + Error_Handler(); + } + + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_0); +} + +/** + * @brief ICACHE Initialization Function + * @param None + * @retval None + */ +static void MX_ICACHE_Init(void) +{ + + /* USER CODE BEGIN ICACHE_Init 0 */ + + /* USER CODE END ICACHE_Init 0 */ + + /* USER CODE BEGIN ICACHE_Init 1 */ + + /* USER CODE END ICACHE_Init 1 */ + + /** Enable instruction cache in 1-way (direct mapped cache) + */ + if (HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY) != HAL_OK) + { + Error_Handler(); + } + if (HAL_ICACHE_Enable() != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ICACHE_Init 2 */ + + /* USER CODE END ICACHE_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + + /*Configure GPIO pin : PB2 */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : PC6 PC7 */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pin : PC9 */ + GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pin : PA8 */ + GPIO_InitStruct.Pin = GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : PB6 PB7 */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + + /* MPU Configuration */ + +void MPU_Config(void) +{ + MPU_Region_InitTypeDef MPU_InitStruct = {0}; + MPU_Attributes_InitTypeDef MPU_AttributesInit = {0}; + + /* Disables the MPU */ + HAL_MPU_Disable(); + + /** Initializes and configures the Region 0 and the memory to be protected + */ + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + MPU_InitStruct.Number = MPU_REGION_NUMBER0; + MPU_InitStruct.BaseAddress = 0x08FFF000; + MPU_InitStruct.LimitAddress = 0x08FFFFFF; + MPU_InitStruct.AttributesIndex = MPU_ATTRIBUTES_NUMBER0; + MPU_InitStruct.AccessPermission = MPU_REGION_ALL_RO; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + + /** Initializes and configures the Attribute 0 and the memory to be protected + */ + MPU_AttributesInit.Number = MPU_ATTRIBUTES_NUMBER0; + MPU_AttributesInit.Attributes = INNER_OUTER(MPU_NOT_CACHEABLE); + + HAL_MPU_ConfigMemoryAttributes(&MPU_AttributesInit); + /* Enables the MPU */ + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); + +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Src/stm32h5xx_hal_msp.c b/embedded-software/firmware/gimbal_test_stand/Core/Src/stm32h5xx_hal_msp.c new file mode 100644 index 00000000..17b49a9d --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Core/Src/stm32h5xx_hal_msp.c @@ -0,0 +1,78 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h5xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Src/stm32h5xx_it.c b/embedded-software/firmware/gimbal_test_stand/Core/Src/stm32h5xx_it.c new file mode 100644 index 00000000..97798eaf --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Core/Src/stm32h5xx_it.c @@ -0,0 +1,217 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h5xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32h5xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32H5xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32h5xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles EXTI Line13 interrupt. + */ +void EXTI13_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI13_IRQn 0 */ + + /* USER CODE END EXTI13_IRQn 0 */ + BSP_PB_IRQHandler(BUTTON_USER); + /* USER CODE BEGIN EXTI13_IRQn 1 */ + + /* USER CODE END EXTI13_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Src/syscalls.c b/embedded-software/firmware/gimbal_test_stand/Core/Src/syscalls.c new file mode 100644 index 00000000..e10d76fa --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Core/Src/syscalls.c @@ -0,0 +1,244 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeMX + * @brief Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +clock_t _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(const char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} + +// --- Picolibc Specific Section --- +#if defined(__PICOLIBC__) + +/** + * @brief Picolibc helper function to output a character to a FILE stream. + * This redirects the output to the low-level __io_putchar function. + * @param c Character to write. + * @param file FILE stream pointer (ignored). + * @retval int The character written. + */ +static int starm_putc(char c, FILE *file) +{ + (void) file; + __io_putchar(c); + return c; +} + +/** + * @brief Picolibc helper function to input a character from a FILE stream. + * This redirects the input from the low-level __io_getchar function. + * @param file FILE stream pointer (ignored). + * @retval int The character read, cast to an unsigned char then int. + */ +static int starm_getc(FILE *file) +{ + unsigned char c; + (void) file; + c = __io_getchar(); + return c; +} + +// Define and initialize the standard I/O streams for Picolibc. +// FDEV_SETUP_STREAM connects the starm_putc and starm_getc helper functions to a FILE structure. +// _FDEV_SETUP_RW indicates the stream is for reading and writing. +static FILE __stdio = FDEV_SETUP_STREAM(starm_putc, + starm_getc, + NULL, + _FDEV_SETUP_RW); + +// Assign the standard stream pointers (stdin, stdout, stderr) to the initialized stream. +// Picolibc uses these pointers for standard I/O operations (printf, scanf, etc.). +FILE *const stdin = &__stdio; +__strong_reference(stdin, stdout); +__strong_reference(stdin, stderr); + +// Create strong aliases mapping standard C library function names (without underscore) +// to the implemented system call stubs (with underscore). Picolibc uses these +// standard names internally, so this linking is required. +__strong_reference(_read, read); +__strong_reference(_write, write); +__strong_reference(_times, times); +__strong_reference(_execve, execve); +__strong_reference(_fork, fork); +__strong_reference(_link, link); +__strong_reference(_unlink, unlink); +__strong_reference(_stat, stat); +__strong_reference(_wait, wait); +__strong_reference(_open, open); +__strong_reference(_close, close); +__strong_reference(_lseek, lseek); +__strong_reference(_isatty, isatty); +__strong_reference(_fstat, fstat); +__strong_reference(_exit, exit); +__strong_reference(_kill, kill); +__strong_reference(_getpid, getpid); + +#endif //__PICOLIBC__ diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Src/sysmem.c b/embedded-software/firmware/gimbal_test_stand/Core/Src/sysmem.c new file mode 100644 index 00000000..a875d42c --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Core/Src/sysmem.c @@ -0,0 +1,87 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeMX + * @brief System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} + +#if defined(__PICOLIBC__) + // Picolibc expects syscalls without the leading underscore. + // This creates a strong alias so that + // calls to `sbrk()` are resolved to our `_sbrk()` implementation. + __strong_reference(_sbrk, sbrk); +#endif diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Src/system_stm32h5xx.c b/embedded-software/firmware/gimbal_test_stand/Core/Src/system_stm32h5xx.c new file mode 100644 index 00000000..d4ea9600 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Core/Src/system_stm32h5xx.c @@ -0,0 +1,403 @@ +/** + ****************************************************************************** + * @file system_stm32h5xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h5xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (64 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32h5xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 64000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 64000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB3 Prescaler | 1 + *----------------------------------------------------------------------------- + * HSI Division factor | 1 + *----------------------------------------------------------------------------- + * PLL1_SRC | No clock + *----------------------------------------------------------------------------- + * PLL1_M | Prescaler disabled + *----------------------------------------------------------------------------- + * PLL1_N | 129 + *----------------------------------------------------------------------------- + * PLL1_P | 2 + *----------------------------------------------------------------------------- + * PLL1_Q | 2 + *----------------------------------------------------------------------------- + * PLL1_R | 2 + *----------------------------------------------------------------------------- + * PLL1_FRACN | 0 + *----------------------------------------------------------------------------- + * PLL2_SRC | No clock + *----------------------------------------------------------------------------- + * PLL2_M | Prescaler disabled + *----------------------------------------------------------------------------- + * PLL2_N | 129 + *----------------------------------------------------------------------------- + * PLL2_P | 2 + *----------------------------------------------------------------------------- + * PLL2_Q | 2 + *----------------------------------------------------------------------------- + * PLL2_R | 2 + *----------------------------------------------------------------------------- + * PLL2_FRACN | 0 + *----------------------------------------------------------------------------- + * PLL3_SRC | No clock + *----------------------------------------------------------------------------- + * PLL3_M | Prescaler disabled + *----------------------------------------------------------------------------- + * PLL3_N | 129 + *----------------------------------------------------------------------------- + * PLL3_P | 2 + *----------------------------------------------------------------------------- + * PLL3_Q | 2 + *----------------------------------------------------------------------------- + * PLL3_R | 2 + *----------------------------------------------------------------------------- + * PLL3_FRACN | 0 + *----------------------------------------------------------------------------- + *============================================================================= + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32H5xx_system + * @{ + */ + +/** @addtogroup STM32H5xx_System_Private_Includes + * @{ + */ + +#include "stm32h5xx.h" + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Defines + * @{ + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000U; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + uint32_t reg_opsr; + + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit while preserving the current HSIDIV value*/ + RCC->CR = (RCC->CR & RCC_CR_HSIDIV_Msk) | RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR1 = 0U; + RCC->CFGR2 = 0U; + + /* Reset HSEON, HSECSSON, HSEBYP, HSEEXT, HSIDIV, HSIKERON, CSION, CSIKERON, HSI48 and PLLxON bits */ +#if defined(RCC_CR_PLL3ON) + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIKERON | \ + RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); +#else + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIKERON | \ + RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON); +#endif + + /* Reset PLLxCFGR register */ + RCC->PLL1CFGR = 0U; + RCC->PLL2CFGR = 0U; +#if defined(RCC_CR_PLL3ON) + RCC->PLL3CFGR = 0U; +#endif /* RCC_CR_PLL3ON */ + + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x01010280U; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000U; + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x01010280U; + /* Reset PLL2FRACR register */ + RCC->PLL2FRACR = 0x00000000U; +#if defined(RCC_CR_PLL3ON) + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x01010280U; + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000U; +#endif /* RCC_CR_PLL3ON */ + + /* Reset HSEBYP bit */ + RCC->CR &= ~(RCC_CR_HSEBYP); + + /* Disable all interrupts */ + RCC->CIER = 0U; + + /* Configure the Vector Table location add offset address ------------------*/ + #ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + #else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + #endif /* VECT_TAB_SRAM */ + + /* Check OPSR register to verify if there is an ongoing swap or option bytes update interrupted by a reset */ + reg_opsr = FLASH->OPSR & FLASH_OPSR_CODE_OP; + if ((reg_opsr == FLASH_OPSR_CODE_OP) || (reg_opsr == (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1))) + { + /* Check FLASH Option Control Register access */ + if ((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != 0U) + { + /* Authorizes the Option Byte registers programming */ + FLASH->OPTKEYR = 0x08192A3BU; + FLASH->OPTKEYR = 0x4C5D6E7FU; + } + /* Launch the option bytes change operation */ + FLASH->OPTCR |= FLASH_OPTCR_OPTSTART; + + /* Lock the FLASH Option Control Register access */ + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; + } +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32h5xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + float_t fracn1, pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_SWS) + { + case 0x00UL: /* HSI used as system clock source */ + SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case 0x08UL: /* CSI used as system clock source */ + SystemCoreClock = CSI_VALUE; + break; + + case 0x10UL: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x18UL: /* PLL1 used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); + pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos); + pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos)); + + switch (pllsource) + { + case 0x01UL: /* HSI used as PLL clock source */ + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x02UL: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x03UL: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: /* No clock sent to PLL*/ + pllvco = (float_t) 0U; + break; + } + + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >>RCC_PLL1DIVR_PLL1P_Pos) + 1U ) ; + SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c b/embedded-software/firmware/gimbal_test_stand/Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c new file mode 100644 index 00000000..a667a67a --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c @@ -0,0 +1,797 @@ +/** + ****************************************************************************** + * @file stm32h5xx_nucleo.c + * @author MCD Application Team + * @brief This file provides set of firmware functions to manage: + * - LEDs and push-button available on STM32H5xx-Nucleo Kit + * from STMicroelectronics + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_nucleo.h" +#if defined(__ICCARM__) +#include +#endif /* __ICCARM__ */ + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32H5XX_NUCLEO + * @{ + */ + +/** @addtogroup STM32H5XX_NUCLEO_LOW_LEVEL + * @brief This file provides set of firmware functions to manage Leds and push-button + * available on STM32H5xx-Nucleo Kit from STMicroelectronics. + * @{ + */ + +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL_Private_Defines LOW LEVEL Private Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL_Private_TypesDefinitions LOW LEVEL Private Typedef + * @{ + */ +typedef void (* BSP_EXTI_LineCallback)(void); +/** + * @} + */ + +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL_Exported_Variables LOW LEVEL Exported Variables + * @{ + */ +EXTI_HandleTypeDef hpb_exti[BUTTON_NBR]; +#if (USE_BSP_COM_FEATURE > 0) +UART_HandleTypeDef hcom_uart[COM_NBR]; +USART_TypeDef *COM_USART[COM_NBR] = {COM1_UART}; +#endif /* USE_BSP_COM_FEATURE */ +/** + * @} + */ +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL_Private_Variables LOW LEVEL Private Variables + * @{ + */ +static GPIO_TypeDef *LED_PORT[LED_NBR] = +{ +#if defined (USE_NUCLEO_144) + LED1_GPIO_PORT, +#endif /* defined (USE_NUCLEO_144) */ + LED2_GPIO_PORT, +#if defined (USE_NUCLEO_144) + LED3_GPIO_PORT +#endif /* defined (USE_NUCLEO_144) */ +}; + +static const uint16_t LED_PIN[LED_NBR] = +{ +#if defined (USE_NUCLEO_144) + LED1_PIN, +#endif /* defined (USE_NUCLEO_144) */ + LED2_PIN, +#if defined (USE_NUCLEO_144) + LED3_PIN +#endif /* defined (USE_NUCLEO_144) */ +}; + +static GPIO_TypeDef *BUTTON_PORT[BUTTON_NBR] = {BUTTON_USER_GPIO_PORT}; +static const uint16_t BUTTON_PIN[BUTTON_NBR] = {BUTTON_USER_PIN}; +static const IRQn_Type BUTTON_IRQn[BUTTON_NBR] = {BUTTON_USER_EXTI_IRQ}; + +#if (USE_BSP_COM_FEATURE > 0) +#if (USE_COM_LOG > 0) +static COM_TypeDef COM_ActiveLogPort = COM1; +#endif /* USE_COM_LOG */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +static uint32_t IsComMspCbValid[COM_NBR] = {0}; +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 1) */ +#endif /* USE_BSP_COM_FEATURE */ + +/** + * @} + */ + +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL_Private_FunctionPrototypes LOW LEVEL Private functions Prototypes + * @{ + */ +static void BUTTON_USER_EXTI_Callback(void); +#if (USE_BSP_COM_FEATURE > 0) +static void COM1_MspInit(UART_HandleTypeDef *huart); +static void COM1_MspDeInit(UART_HandleTypeDef *huart); +#endif /* USE_BSP_COM_FEATURE */ + +#if defined(__ICCARM__) +/* New definition from EWARM V9, compatible with EWARM8 */ +int iar_fputc(int ch); +#define PUTCHAR_PROTOTYPE int iar_fputc(int ch) +#elif defined ( __CC_ARM ) || defined(__ARMCC_VERSION) +/* ARM Compiler 5/6*/ +#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#elif defined(__GNUC__) +#define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#endif /* __ICCARM__ */ + +/** + * @} + */ + +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL_Exported_Functions LOW LEVEL Exported Functions + * @{ + */ + +/** + * @brief This method returns the STM32H5XX NUCLEO BSP Driver revision + * @retval version: 0xXYZR (8bits for each decimal, R for RC) + */ +int32_t BSP_GetVersion(void) +{ + return (int32_t)STM32H5XX_NUCLEO_BSP_VERSION; +} + +/** + * @brief This method returns the board name + * @retval pointer to the board name string + */ +const uint8_t *BSP_GetBoardName(void) +{ + return (uint8_t *)STM32H5XX_NUCLEO_BSP_BOARD_NAME; +} + +/** + * @brief This method returns the board ID + * @retval pointer to the board name string + */ +const uint8_t *BSP_GetBoardID(void) +{ + return (uint8_t *)STM32H5XX_NUCLEO_BSP_BOARD_ID; +} + + +/** + * @brief Configures LED GPIO. + * @param Led Specifies the Led to be configured. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval BSP status + */ +int32_t BSP_LED_Init(Led_TypeDef Led) +{ + int32_t ret = BSP_ERROR_NONE; + GPIO_InitTypeDef gpio_init_structure; + + if ((Led != LED2) +#if defined (USE_NUCLEO_144) + && (Led != LED1) && (Led != LED3) +#endif /* defined (USE_NUCLEO_144) */ + ) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + /* Enable the GPIO LED Clock */ + if (Led == LED2) + { + LED2_GPIO_CLK_ENABLE(); + } +#if defined (USE_NUCLEO_144) + else if (Led == LED1) + { + LED1_GPIO_CLK_ENABLE(); + } + else + { + LED3_GPIO_CLK_ENABLE(); + } +#endif /* defined (USE_NUCLEO_144) */ + + /* Configure the GPIO_LED pin */ + gpio_init_structure.Pin = LED_PIN[Led]; + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + + HAL_GPIO_Init(LED_PORT[Led], &gpio_init_structure); + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_RESET); + +#if defined (USE_NUCLEO_H5E5ZJ) + if (Led != LED1) + { + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_SET); + } +#endif /* USE_NUCLEO_H5E5ZJ*/ + + } + + return ret; +} + +/** + * @brief DeInit LEDs. + * @param Led LED to be de-init. + * This parameter can be one of the following values: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @note Led DeInit does not disable the GPIO clock nor disable the Mfx + * @retval BSP status + */ +int32_t BSP_LED_DeInit(Led_TypeDef Led) +{ + int32_t ret = BSP_ERROR_NONE; + GPIO_InitTypeDef gpio_init_structure; + + if ((Led != LED2) +#if defined (USE_NUCLEO_144) + && (Led != LED1) && (Led != LED3) +#endif /* defined (USE_NUCLEO_144) */ + ) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + /* Turn off LED */ + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_RESET); + /* DeInit the GPIO_LED pin */ + gpio_init_structure.Pin = LED_PIN[Led]; + HAL_GPIO_DeInit(LED_PORT[Led], gpio_init_structure.Pin); + } + + return ret; +} + +/** + * @brief Turns selected LED On. + * @param Led Specifies the Led to be set on. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval BSP status + */ +int32_t BSP_LED_On(Led_TypeDef Led) +{ + int32_t ret = BSP_ERROR_NONE; + + if ((Led != LED2) +#if defined (USE_NUCLEO_144) + && (Led != LED1) && (Led != LED3) +#endif /* defined (USE_NUCLEO_144) */ + ) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_SET); + +#if defined (USE_NUCLEO_H5E5ZJ) + if (Led != LED1) + { + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_RESET); + } +#endif /* USE_NUCLEO_H5E5ZJ */ + } + + return ret; +} + +/** + * @brief Turns selected LED Off. + * @param Led: Specifies the Led to be set off. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval BSP status + */ +int32_t BSP_LED_Off(Led_TypeDef Led) +{ + int32_t ret = BSP_ERROR_NONE; + + if ((Led != LED2) +#if defined (USE_NUCLEO_144) + && (Led != LED1) && (Led != LED3) +#endif /* defined (USE_NUCLEO_144) */ + ) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_RESET); + +#if defined (USE_NUCLEO_H5E5ZJ) + if (Led != LED1) + { + HAL_GPIO_WritePin(LED_PORT[Led], LED_PIN[Led], GPIO_PIN_SET); + } +#endif /* USE_NUCLEO_H5E5ZJ */ + } + + return ret; +} + +/** + * @brief Toggles the selected LED. + * @param Led Specifies the Led to be toggled. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval BSP status + */ +int32_t BSP_LED_Toggle(Led_TypeDef Led) +{ + int32_t ret = BSP_ERROR_NONE; + + if ((Led != LED2) +#if defined (USE_NUCLEO_144) + && (Led != LED1) && (Led != LED3) +#endif /* defined (USE_NUCLEO_144) */ + ) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + HAL_GPIO_TogglePin(LED_PORT[Led], LED_PIN[Led]); + } + + return ret; +} + +/** + * @brief Get the state of the selected LED. + * @param Led LED to get its state + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @retval LED status + */ +int32_t BSP_LED_GetState(Led_TypeDef Led) +{ + int32_t ret; + + if ((Led != LED2) +#if defined (USE_NUCLEO_144) + && (Led != LED1) && (Led != LED3) +#endif /* defined (USE_NUCLEO_144) */ + ) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + ret = (int32_t)HAL_GPIO_ReadPin(LED_PORT [Led], LED_PIN [Led]); + } + + return ret; +} + +/** + * @brief Configures button GPIO and EXTI Line. + * @param Button Button to be configured + * This parameter can be one of the following values: + * @arg BUTTON_USER: Wakeup Push Button + * @param ButtonMode Button mode + * This parameter can be one of the following values: + * @arg BUTTON_MODE_GPIO: Button will be used as simple IO + * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line + * with interrupt generation capability + */ +int32_t BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode) +{ + GPIO_InitTypeDef gpio_init_structure; + static BSP_EXTI_LineCallback ButtonCallback[BUTTON_NBR] = {BUTTON_USER_EXTI_Callback}; + static uint32_t BSP_BUTTON_PRIO [BUTTON_NBR] = {BSP_BUTTON_USER_IT_PRIORITY}; + static const uint32_t BUTTON_EXTI_LINE[BUTTON_NBR] = {BUTTON_USER_EXTI_LINE}; + + /* Enable the BUTTON clock */ + BUTTON_USER_GPIO_CLK_ENABLE(); + + gpio_init_structure.Pin = BUTTON_PIN [Button]; + gpio_init_structure.Pull = GPIO_PULLDOWN; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH; + + if (ButtonMode == BUTTON_MODE_GPIO) + { + /* Configure Button pin as input */ + gpio_init_structure.Mode = GPIO_MODE_INPUT; + HAL_GPIO_Init(BUTTON_PORT [Button], &gpio_init_structure); + } + else /* (ButtonMode == BUTTON_MODE_EXTI) */ + { + /* Configure Button pin as input with External interrupt */ + gpio_init_structure.Mode = GPIO_MODE_IT_RISING; + + HAL_GPIO_Init(BUTTON_PORT[Button], &gpio_init_structure); + + (void)HAL_EXTI_GetHandle(&hpb_exti[Button], BUTTON_EXTI_LINE[Button]); + (void)HAL_EXTI_RegisterCallback(&hpb_exti[Button], HAL_EXTI_COMMON_CB_ID, ButtonCallback[Button]); + + /* Enable and set Button EXTI Interrupt to the lowest priority */ + HAL_NVIC_SetPriority((BUTTON_IRQn[Button]), BSP_BUTTON_PRIO[Button], 0x00); + HAL_NVIC_EnableIRQ((BUTTON_IRQn[Button])); + } + + return BSP_ERROR_NONE; +} + +/** + * @brief Push Button DeInit. + * @param Button Button to be configured + * This parameter can be one of the following values: + * @arg BUTTON_USER: Wakeup Push Button + * @note PB DeInit does not disable the GPIO clock + */ +int32_t BSP_PB_DeInit(Button_TypeDef Button) +{ + GPIO_InitTypeDef gpio_init_structure; + + gpio_init_structure.Pin = BUTTON_PIN[Button]; + HAL_NVIC_DisableIRQ((IRQn_Type)(BUTTON_IRQn[Button])); + HAL_GPIO_DeInit(BUTTON_PORT[Button], gpio_init_structure.Pin); + + return BSP_ERROR_NONE; +} + +/** + * @brief Returns the selected button state. + * @param Button Button to be checked + * This parameter can be one of the following values: + * @arg BUTTON_USER: Wakeup Push Button + * @retval The Button GPIO pin value (GPIO_PIN_RESET = button pressed) + */ +int32_t BSP_PB_GetState(Button_TypeDef Button) +{ + return (int32_t)HAL_GPIO_ReadPin(BUTTON_PORT[Button], BUTTON_PIN[Button]); +} + +/** + * @brief BSP Button IRQ handler + * @param Button Can only be BUTTON_USER + * @retval None + */ +void BSP_PB_IRQHandler(Button_TypeDef Button) +{ + HAL_EXTI_IRQHandler(&hpb_exti[Button]); +} + +/** + * @brief BSP Push Button callback + * @param Button Specifies the pin connected EXTI line + * @retval None + */ +__weak void BSP_PB_Callback(Button_TypeDef Button) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Button); + + /* This function should be implemented by the user application. + It is called into this driver when an event on Button is triggered. */ +} + +#if (USE_BSP_COM_FEATURE > 0) +/** + * @brief Configures COM port. + * @param COM COM port to be configured. + * This parameter can be COM1 + * @param COM_Init Pointer to a UART_HandleTypeDef structure that contains the + * configuration information for the specified USART peripheral. + * @retval BSP error code + */ +int32_t BSP_COM_Init(COM_TypeDef COM, COM_InitTypeDef *COM_Init) +{ + int32_t ret = BSP_ERROR_NONE; + + if (COM >= COM_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 0) + /* Init the UART Msp */ + COM1_MspInit(&hcom_uart[COM]); +#else + if (IsComMspCbValid[COM] == 0U) + { + if (BSP_COM_RegisterDefaultMspCallbacks(COM) != BSP_ERROR_NONE) + { + return BSP_ERROR_MSP_FAILURE; + } + } +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 0) */ + + if (MX_USART_Init(&hcom_uart[COM], COM_Init) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + } + + return ret; +} + +/** + * @brief DeInit COM port. + * @param COM COM port to be configured. + * This parameter can be COM1 + * @retval BSP status + */ +int32_t BSP_COM_DeInit(COM_TypeDef COM) +{ + int32_t ret = BSP_ERROR_NONE; + + if (COM >= COM_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + /* USART configuration */ + hcom_uart[COM].Instance = COM_USART[COM]; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 0) + COM1_MspDeInit(&hcom_uart[COM]); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 0) */ + + if (HAL_UART_DeInit(&hcom_uart[COM]) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + } + + return ret; +} + +/** + * @brief Configures COM port. + * @param huart USART handle + * @param COM_Init Pointer to a UART_HandleTypeDef structure that contains the + * configuration information for the specified USART peripheral. + * @retval HAL error code + */ +__weak HAL_StatusTypeDef MX_USART_Init(UART_HandleTypeDef *huart, MX_UART_InitTypeDef *COM_Init) +{ + /* USART configuration */ + huart->Instance = COM_USART[COM1]; + huart->Init.BaudRate = COM_Init->BaudRate; + huart->Init.Mode = UART_MODE_TX_RX; + huart->Init.Parity = (uint32_t)COM_Init->Parity; + huart->Init.WordLength = (uint32_t)COM_Init->WordLength; + huart->Init.StopBits = (uint32_t)COM_Init->StopBits; + huart->Init.HwFlowCtl = (uint32_t)COM_Init->HwFlowCtl; + huart->Init.OverSampling = UART_OVERSAMPLING_8; + huart->Init.ClockPrescaler = UART_PRESCALER_DIV1; + return HAL_UART_Init(huart); +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register Default COM Msp Callbacks + * @param COM COM port to be configured. + * This parameter can be COM1 + * @retval BSP status + */ +int32_t BSP_COM_RegisterDefaultMspCallbacks(COM_TypeDef COM) +{ + int32_t ret = BSP_ERROR_NONE; + + if (COM >= COM_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + __HAL_UART_RESET_HANDLE_STATE(&hcom_uart[COM]); + + /* Register default MspInit/MspDeInit Callback */ + if (HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPINIT_CB_ID, COM1_MspInit) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + else if (HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPDEINIT_CB_ID, COM1_MspDeInit) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + else + { + IsComMspCbValid[COM] = 1U; + } + } + + /* BSP status */ + return ret; +} + +/** + * @brief Register COM Msp Callback registering + * @param COM COM port to be configured. + * This parameter can be COM1 + * @param Callbacks pointer to COM1 MspInit/MspDeInit callback functions + * @retval BSP status + */ +int32_t BSP_COM_RegisterMspCallbacks(COM_TypeDef COM, BSP_COM_Cb_t *Callback) +{ + int32_t ret = BSP_ERROR_NONE; + + if (COM >= COM_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + __HAL_UART_RESET_HANDLE_STATE(&hcom_uart[COM]); + + /* Register MspInit/MspDeInit Callbacks */ + if (HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPINIT_CB_ID, Callback->pMspInitCb) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + else if (HAL_UART_RegisterCallback(&hcom_uart[COM], HAL_UART_MSPDEINIT_CB_ID, Callback->pMspDeInitCb) != HAL_OK) + { + ret = BSP_ERROR_PERIPH_FAILURE; + } + else + { + IsComMspCbValid[COM] = 1U; + } + } + /* BSP status */ + return ret; +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +#if (USE_COM_LOG > 0) +/** + * @brief Select the active COM port. + * @param COM COM port to be activated. + * This parameter can be COM1 + * @retval BSP status + */ +int32_t BSP_COM_SelectLogPort(COM_TypeDef COM) +{ + if (COM_ActiveLogPort != COM) + { + COM_ActiveLogPort = COM; + } + return BSP_ERROR_NONE; +} + +#if defined(__ICCARM__) +size_t __write(int file, unsigned char const *ptr, size_t len) +{ + size_t idx; + unsigned char const *pdata = ptr; + + for (idx = 0; idx < len; idx++) + { + iar_fputc((int)*pdata); + pdata++; + } + return len; +} +#endif /* __ICCARM__ */ + +/** + * @brief Redirect console output to COM + */ +PUTCHAR_PROTOTYPE +{ + HAL_UART_Transmit(&hcom_uart [COM_ActiveLogPort], (uint8_t *) &ch, 1, COM_POLL_TIMEOUT); + return ch; +} +#endif /* USE_COM_LOG */ +#endif /* USE_BSP_COM_FEATURE */ + +/** + * @} + */ + +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL_Private_Functions LOW LEVEL Private functions + * @{ + */ +/** + * @brief Key EXTI line detection callbacks. + * @retval BSP status + */ +static void BUTTON_USER_EXTI_Callback(void) +{ + BSP_PB_Callback(BUTTON_USER); +} + +#if (USE_BSP_COM_FEATURE > 0) +/** + * @brief Initializes UART MSP. + * @param huart UART handle + * @retval BSP status + */ +static void COM1_MspInit(UART_HandleTypeDef *huart) +{ + GPIO_InitTypeDef gpio_init_structure; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* Enable GPIO clock */ + COM1_TX_GPIO_CLK_ENABLE(); + COM1_RX_GPIO_CLK_ENABLE(); + + /* Enable USART clock */ + COM1_CLK_ENABLE(); + + /* Configure USART Tx as alternate function */ + gpio_init_structure.Pin = COM1_TX_PIN; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH; + gpio_init_structure.Pull = GPIO_PULLUP; + gpio_init_structure.Alternate = COM1_TX_AF; + HAL_GPIO_Init(COM1_TX_GPIO_PORT, &gpio_init_structure); + + /* Configure USART Rx as alternate function */ + gpio_init_structure.Pin = COM1_RX_PIN; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Alternate = COM1_RX_AF; + HAL_GPIO_Init(COM1_RX_GPIO_PORT, &gpio_init_structure); +} + +/** + * @brief Initialize USART Msp part + * @param huart UART handle + * @retval BSP status + */ +static void COM1_MspDeInit(UART_HandleTypeDef *huart) +{ + GPIO_InitTypeDef gpio_init_structure; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* COM GPIO pin configuration */ + gpio_init_structure.Pin = COM1_TX_PIN; + HAL_GPIO_DeInit(COM1_TX_GPIO_PORT, gpio_init_structure.Pin); + + gpio_init_structure.Pin = COM1_RX_PIN; + HAL_GPIO_DeInit(COM1_RX_GPIO_PORT, gpio_init_structure.Pin); + + /* Disable USART clock */ + COM1_CLK_DISABLE(); +} +#endif /* USE_BSP_COM_FEATURE */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.h b/embedded-software/firmware/gimbal_test_stand/Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.h new file mode 100644 index 00000000..d1acbad7 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.h @@ -0,0 +1,420 @@ +/** + ****************************************************************************** + * @file stm32h5xx_nucleo.h + * @author MCD Application Team + * @brief This file contains definitions for: + * - LEDs and push-button available on STM32H5xx-Nucleo Kit + * from STMicroelectronics + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5XX_NUCLEO_H +#define STM32H5XX_NUCLEO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_nucleo_conf.h" +#include "stm32h5xx_nucleo_errno.h" + +#if (USE_BSP_COM_FEATURE > 0) +#include +#endif /* USE_BSP_COM_FEATURE */ + +/** @addtogroup BSP + * @{ + */ + +/** @defgroup STM32H5XX_NUCLEO STM32H5XX_NUCLEO + * @{ + */ + +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL LOW LEVEL + * @{ + */ + +/** + * @brief Define for STM32H5XX_NUCLEO board + */ +#if !defined (USE_STM32H5XX_NUCLEO) +#define USE_STM32H5XX_NUCLEO +#endif /* !defined (USE_STM32H5XX_NUCLEO) */ + +#if !defined (USE_NUCLEO_144) && !defined (USE_NUCLEO_64) && !defined (USE_NUCLEO_H533RE)&& !defined (USE_NUCLEO_H5E5ZJ) +#error "Board Pin number not defined!! Add USE_NUCLEO_144 or USE_NUCLEO_64 or USE_NUCLEO_H533RE or \ + USE_NUCLEO_H5E5ZJ define in conf.h file" +#endif /* (!defined (USE_NUCLEO_144) && !defined (USE_NUCLEO_64) && !defined (USE_NUCLEO_H533RE) && \ + !defined (USE_NUCLEO_H5E5ZJ)) */ + + +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL_Exported_Types LOW LEVEL Exported Types + * @{ + */ +typedef enum +{ +#if defined (USE_NUCLEO_144) +#if defined (USE_NUCLEO_H5E5ZJ) || defined(USE_NUCLEO_H553ZG) + LED1 = 0, + LED_GREEN = LED1, + LED2 = 1, + LED_RED = LED2, + LED3 = 2, + LED_BLUE = LED3, +#else + LED1 = 0, + LED_GREEN = LED1, + LED2 = 1, + LED_YELLOW = LED2, + LED3 = 2, + LED_RED = LED3, +#endif /* USE_NUCLEO_H5E5ZJ || USE_NUCLEO_H553ZG */ +#else + LED2 = 0, + LED_GREEN = LED2, +#endif /* defined (USE_NUCLEO_144) */ + LED_NBR +} Led_TypeDef; + +typedef enum +{ + BUTTON_USER = 0U, + BUTTON_NBR +} Button_TypeDef; + +typedef enum +{ + BUTTON_MODE_GPIO = 0, + BUTTON_MODE_EXTI = 1 +} ButtonMode_TypeDef; + +#if (USE_BSP_COM_FEATURE > 0) +typedef enum +{ + COM1 = 0U, + COM_NBR +} COM_TypeDef; + +typedef enum +{ + COM_STOPBITS_1 = UART_STOPBITS_1, + COM_STOPBITS_2 = UART_STOPBITS_2, +} COM_StopBitsTypeDef; + +typedef enum +{ + COM_PARITY_NONE = UART_PARITY_NONE, + COM_PARITY_EVEN = UART_PARITY_EVEN, + COM_PARITY_ODD = UART_PARITY_ODD, +} COM_ParityTypeDef; + +typedef enum +{ + COM_HWCONTROL_NONE = UART_HWCONTROL_NONE, + COM_HWCONTROL_RTS = UART_HWCONTROL_RTS, + COM_HWCONTROL_CTS = UART_HWCONTROL_CTS, + COM_HWCONTROL_RTS_CTS = UART_HWCONTROL_RTS_CTS, +} COM_HwFlowCtlTypeDef; + +typedef enum +{ + COM_WORDLENGTH_7B = UART_WORDLENGTH_7B, + COM_WORDLENGTH_8B = UART_WORDLENGTH_8B, + COM_WORDLENGTH_9B = UART_WORDLENGTH_9B, +} COM_WordLengthTypeDef; + +typedef struct +{ + uint32_t BaudRate; + COM_WordLengthTypeDef WordLength; + COM_StopBitsTypeDef StopBits; + COM_ParityTypeDef Parity; + COM_HwFlowCtlTypeDef HwFlowCtl; +} COM_InitTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +typedef struct +{ + void (* pMspInitCb)(UART_HandleTypeDef *); + void (* pMspDeInitCb)(UART_HandleTypeDef *); +} BSP_COM_Cb_t; +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 1) */ + +#define MX_UART_InitTypeDef COM_InitTypeDef + +#endif /* USE_BSP_COM_FEATURE */ + +/** + * @} + */ + +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL_Exported_Constants LOW LEVEL Exported Constants + * @{ + */ + +/** + * @brief STM32H5XX NUCLEO BSP Driver version number V1.1.0 + */ +#define STM32H5XX_NUCLEO_BSP_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define STM32H5XX_NUCLEO_BSP_VERSION_SUB1 (0x01UL) /*!< [23:16] sub1 version */ +#define STM32H5XX_NUCLEO_BSP_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ +#define STM32H5XX_NUCLEO_BSP_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ +#define STM32H5XX_NUCLEO_BSP_VERSION ((STM32H5XX_NUCLEO_BSP_VERSION_MAIN << 24)\ + |(STM32H5XX_NUCLEO_BSP_VERSION_SUB1 << 16)\ + |(STM32H5XX_NUCLEO_BSP_VERSION_SUB2 << 8 )\ + |(STM32H5XX_NUCLEO_BSP_VERSION_RC)) +#if defined (USE_NUCLEO_144) +#if defined (USE_NUCLEO_H5E5ZJ) +#define STM32H5XX_NUCLEO_BSP_BOARD_NAME "NUCLEO-H5E5ZJ"; +#define STM32H5XX_NUCLEO_BSP_BOARD_ID "MB2129"; +#elif defined(USE_NUCLEO_H553ZG) +#define STM32H5XX_NUCLEO_BSP_BOARD_NAME "NUCLEO-H553ZG"; +#define STM32H5XX_NUCLEO_BSP_BOARD_ID "MB2321"; +#else +#define STM32H5XX_NUCLEO_BSP_BOARD_NAME "NUCLEO-H563ZI"; +#define STM32H5XX_NUCLEO_BSP_BOARD_ID "MB1404A"; +#endif /* USE_NUCLEO_H5E5ZJ */ +#else +#if defined (USE_NUCLEO_H533RE) +#define STM32H5XX_NUCLEO_BSP_BOARD_NAME "NUCLEO-H533RE"; +#define STM32H5XX_NUCLEO_BSP_BOARD_ID "MB1814C"; +#else +#define STM32H5XX_NUCLEO_BSP_BOARD_NAME "NUCLEO-H503RB"; +#define STM32H5XX_NUCLEO_BSP_BOARD_ID "MB1814B"; +#endif /* USE_NUCLEO_H533RE */ +#endif /* USE_NUCLEO_144 */ + +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL_LED LOW LEVEL LED + * @{ + */ +#if defined (USE_NUCLEO_144) +#if defined (USE_NUCLEO_H5E5ZJ) + +#define LED1_PIN GPIO_PIN_3 +#define LED1_GPIO_PORT GPIOA +#define LED1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define LED1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() + +#define LED2_PIN GPIO_PIN_0 +#define LED2_GPIO_PORT GPIOF +#define LED2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() +#define LED2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOF_CLK_DISABLE() + +#define LED3_PIN GPIO_PIN_5 +#define LED3_GPIO_PORT GPIOE +#define LED3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE() +#define LED3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOE_CLK_DISABLE() + +#elif defined(USE_NUCLEO_H553ZG) + +#define LED1_PIN GPIO_PIN_15 +#define LED1_GPIO_PORT GPIOD +#define LED1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() +#define LED1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() + +#define LED2_PIN GPIO_PIN_6 +#define LED2_GPIO_PORT GPIOC +#define LED2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define LED2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() + +#define LED3_PIN GPIO_PIN_0 +#define LED3_GPIO_PORT GPIOA +#define LED3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define LED3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() + +#else + +#define LED1_PIN GPIO_PIN_0 +#define LED1_GPIO_PORT GPIOB +#define LED1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define LED1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() + +#define LED2_PIN GPIO_PIN_4 +#define LED2_GPIO_PORT GPIOF +#define LED2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() +#define LED2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOF_CLK_DISABLE() + +#define LED3_PIN GPIO_PIN_4 +#define LED3_GPIO_PORT GPIOG +#define LED3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE() +#define LED3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOG_CLK_DISABLE() +#endif /* USE_NUCLEO_H5E5ZJ */ +#else /* defined (USE_NUCLEO_64) */ +#define LED2_PIN GPIO_PIN_5 +#define LED2_GPIO_PORT GPIOA +#define LED2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define LED2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#endif /* defined (USE_NUCLEO_144) */ +/** + * @} + */ + +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL_BUTTON LOW LEVEL BUTTON + * @{ + */ +/* Button state */ +#define BUTTON_RELEASED 0U +#define BUTTON_PRESSED 1U + +/** + * @brief Key push-button + */ +#define BUTTON_USER_PIN GPIO_PIN_13 +#define BUTTON_USER_GPIO_PORT GPIOC +#define BUTTON_USER_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define BUTTON_USER_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() +#define BUTTON_USER_EXTI_IRQ EXTI13_IRQn +#define BUTTON_USER_EXTI_LINE EXTI_LINE_13 + +/** + * @} + */ + +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL_COM LOW LEVEL COM + * @{ + */ +/** + * @brief Definition for COM port1, connected to USART3 + */ +#if (USE_BSP_COM_FEATURE > 0) +#if defined (USE_NUCLEO_144) +#define COM1_UART USART3 +#define COM1_CLK_ENABLE() __HAL_RCC_USART3_CLK_ENABLE() +#define COM1_CLK_DISABLE() __HAL_RCC_USART3_CLK_DISABLE() + +#define COM1_TX_PIN GPIO_PIN_8 +#define COM1_TX_GPIO_PORT GPIOD +#define COM1_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() +#define COM1_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() +#define COM1_TX_AF GPIO_AF7_USART3 + +#define COM1_RX_PIN GPIO_PIN_9 +#define COM1_RX_GPIO_PORT GPIOD +#define COM1_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE() +#define COM1_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE() +#define COM1_RX_AF GPIO_AF7_USART3 +#else /* defined (USE_NUCLEO_64) */ +#if defined (USE_NUCLEO_H533RE) +#define COM1_UART USART2 +#define COM1_CLK_ENABLE() __HAL_RCC_USART2_CLK_ENABLE() +#define COM1_CLK_DISABLE() __HAL_RCC_USART2_CLK_DISABLE() + +#define COM1_TX_PIN GPIO_PIN_2 +#define COM1_TX_GPIO_PORT GPIOA +#define COM1_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define COM1_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define COM1_TX_AF GPIO_AF7_USART2 + +#define COM1_RX_PIN GPIO_PIN_3 +#define COM1_RX_GPIO_PORT GPIOA +#define COM1_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define COM1_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define COM1_RX_AF GPIO_AF7_USART2 +#else +#define COM1_UART USART3 +#define COM1_CLK_ENABLE() __HAL_RCC_USART3_CLK_ENABLE() +#define COM1_CLK_DISABLE() __HAL_RCC_USART3_CLK_DISABLE() + +#define COM1_TX_PIN GPIO_PIN_4 +#define COM1_TX_GPIO_PORT GPIOA +#define COM1_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define COM1_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define COM1_TX_AF GPIO_AF13_USART3 + +#define COM1_RX_PIN GPIO_PIN_3 +#define COM1_RX_GPIO_PORT GPIOA +#define COM1_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define COM1_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define COM1_RX_AF GPIO_AF13_USART3 +#endif /* defined (USE_NUCLEO_64) */ +#endif /* defined (USE_NUCLEO_H533RE) */ +#define COM_POLL_TIMEOUT 1000 +#endif /* USE_BSP_COM_FEATURE */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup STM32H5XX_NUCLEO_LOW_LEVEL_Exported_Variables + * @{ + */ +extern EXTI_HandleTypeDef hpb_exti[]; +#if (USE_BSP_COM_FEATURE > 0) +extern UART_HandleTypeDef hcom_uart[]; +extern USART_TypeDef *COM_USART[]; +#endif /* USE_BSP_COM_FEATURE */ + +/** + * @} + */ + +/** @defgroup STM32H5XX_NUCLEO_LOW_LEVEL_Exported_FunctionsPrototypes LOW LEVEL Exported Functions Prototypes + * @{ + */ +int32_t BSP_GetVersion(void); +const uint8_t *BSP_GetBoardName(void); +const uint8_t *BSP_GetBoardID(void); +int32_t BSP_LED_Init(Led_TypeDef Led); +int32_t BSP_LED_DeInit(Led_TypeDef Led); +int32_t BSP_LED_On(Led_TypeDef Led); +int32_t BSP_LED_Off(Led_TypeDef Led); +int32_t BSP_LED_Toggle(Led_TypeDef Led); +int32_t BSP_LED_GetState(Led_TypeDef Led); +int32_t BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode); +int32_t BSP_PB_DeInit(Button_TypeDef Button); +int32_t BSP_PB_GetState(Button_TypeDef Button); +void BSP_PB_IRQHandler(Button_TypeDef Button); +void BSP_PB_Callback(Button_TypeDef Button); + +#if (USE_BSP_COM_FEATURE > 0) +int32_t BSP_COM_Init(COM_TypeDef COM, COM_InitTypeDef *COM_Init); +int32_t BSP_COM_DeInit(COM_TypeDef COM); +#if (USE_COM_LOG > 0) +int32_t BSP_COM_SelectLogPort(COM_TypeDef COM); +#endif /* USE_COM_LOG */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +int32_t BSP_COM_RegisterDefaultMspCallbacks(COM_TypeDef COM); +int32_t BSP_COM_RegisterMspCallbacks(COM_TypeDef COM, BSP_COM_Cb_t *Callback); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef MX_USART_Init(UART_HandleTypeDef *huart, MX_UART_InitTypeDef *COM_Init); +#endif /* USE_BSP_COM_FEATURE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5XX_NUCLEO_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo_errno.h b/embedded-software/firmware/gimbal_test_stand/Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo_errno.h new file mode 100644 index 00000000..7807b04e --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo_errno.h @@ -0,0 +1,45 @@ +/** + ****************************************************************************** + * @file stm32h5xx_nucleo_errno.h + * @author MCD Application Team + * @brief Error Code. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5XX_NUCLEO_ERRNO_H +#define STM32H5XX_NUCLEO_ERRNO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Common Error codes */ +#define BSP_ERROR_NONE 0 +#define BSP_ERROR_NO_INIT -1 +#define BSP_ERROR_WRONG_PARAM -2 +#define BSP_ERROR_BUSY -3 +#define BSP_ERROR_PERIPH_FAILURE -4 +#define BSP_ERROR_COMPONENT_FAILURE -5 +#define BSP_ERROR_UNKNOWN_FAILURE -6 +#define BSP_ERROR_UNKNOWN_COMPONENT -7 +#define BSP_ERROR_BUS_FAILURE -8 +#define BSP_ERROR_CLOCK_FAILURE -9 +#define BSP_ERROR_MSP_FAILURE -10 +#define BSP_ERROR_FEATURE_NOT_SUPPORTED -11 + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5XX_NUCLEO_ERRNO_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h new file mode 100644 index 00000000..0c843a0c --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h @@ -0,0 +1,20685 @@ +/** + ****************************************************************************** + * @file stm32h533xx.h + * @author MCD Application Team + * @brief CMSIS STM32H533xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32H533xx_H +#define STM32H533xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32H533xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32H533xx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + GPDMA1_Channel0_IRQn = 27, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 28, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 29, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 30, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 31, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 32, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 33, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 34, /*!< GPDMA1 Channel 7 global interrupt */ + IWDG_IRQn = 35, /*!< IWDG global interrupt */ + SAES_IRQn = 36, /*!< Secure AES global interrupt */ + ADC1_IRQn = 37, /*!< ADC1 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + I2C1_EV_IRQn = 51, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 52, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 53, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 54, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 55, /*!< SPI1 global interrupt */ + SPI2_IRQn = 56, /*!< SPI2 global interrupt */ + SPI3_IRQn = 57, /*!< SPI3 global interrupt */ + USART1_IRQn = 58, /*!< USART1 global interrupt */ + USART2_IRQn = 59, /*!< USART2 global interrupt */ + USART3_IRQn = 60, /*!< USART3 global interrupt */ + UART4_IRQn = 61, /*!< UART4 global interrupt */ + UART5_IRQn = 62, /*!< UART5 global interrupt */ + LPUART1_IRQn = 63, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 64, /*!< LPTIM1 global interrupt */ + TIM8_BRK_IRQn = 65, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 66, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 67, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 68, /*!< TIM8 Capture Compare interrupt */ + ADC2_IRQn = 69, /*!< ADC2 global interrupt */ + LPTIM2_IRQn = 70, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 71, /*!< TIM15 global interrupt */ + USB_DRD_FS_IRQn = 74, /*!< USB FS global interrupt */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + UCPD1_IRQn = 76, /*!< UCPD1 global interrupt */ + FMC_IRQn = 77, /*!< FMC global interrupt */ + OCTOSPI1_IRQn = 78, /*!< OctoSPI1 global interrupt */ + SDMMC1_IRQn = 79, /*!< SDMMC1 global interrupt */ + I2C3_EV_IRQn = 80, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 81, /*!< I2C3 error interrupt */ + SPI4_IRQn = 82, /*!< SPI4 global interrupt */ + USART6_IRQn = 85, /*!< USART6 global interrupt */ + GPDMA2_Channel0_IRQn = 90, /*!< GPDMA2 Channel 0 global interrupt */ + GPDMA2_Channel1_IRQn = 91, /*!< GPDMA2 Channel 1 global interrupt */ + GPDMA2_Channel2_IRQn = 92, /*!< GPDMA2 Channel 2 global interrupt */ + GPDMA2_Channel3_IRQn = 93, /*!< GPDMA2 Channel 3 global interrupt */ + GPDMA2_Channel4_IRQn = 94, /*!< GPDMA2 Channel 4 global interrupt */ + GPDMA2_Channel5_IRQn = 95, /*!< GPDMA2 Channel 5 global interrupt */ + GPDMA2_Channel6_IRQn = 96, /*!< GPDMA2 Channel 6 global interrupt */ + GPDMA2_Channel7_IRQn = 97, /*!< GPDMA2 Channel 7 global interrupt */ + FPU_IRQn = 103, /*!< FPU global interrupt */ + ICACHE_IRQn = 104, /*!< Instruction cache global interrupt */ + DCACHE1_IRQn = 105, /*!< Data cache global interrupt */ + DCMI_PSSI_IRQn = 108, /*!< DCMI/PSSI global interrupt */ + FDCAN2_IT0_IRQn = 109, /*!< FDCAN2 interrupt 0 */ + FDCAN2_IT1_IRQn = 110, /*!< FDCAN2 interrupt 1 */ + DTS_IRQn = 113, /*!< DTS global interrupt */ + RNG_IRQn = 114, /*!< RNG global interrupt */ + OTFDEC1_IRQn = 115, /*!< OTFDEC1 global interrupt */ + AES_IRQn = 116, /*!< AES global interrupt */ + HASH_IRQn = 117, /*!< HASH global interrupt */ + PKA_IRQn = 118, /*!< PKA global interrupt */ + CEC_IRQn = 119, /*!< CEC-HDMI global interrupt */ + TIM12_IRQn = 120, /*!< TIM12 global interrupt */ + I3C1_EV_IRQn = 123, /*!< I3C1 event interrupt */ + I3C1_ER_IRQn = 124, /*!< I3C1 error interrupt */ + I3C2_EV_IRQn = 131, /*!< I3C2 Event interrupt */ + I3C2_ER_IRQn = 132, /*!< I3C2 Error interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HRA[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */ + __IO uint32_t SR; /*!< Debug MCU SR register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug DBG_AUTH_DEV register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug DBG_AUTH_ACK register, Address offset: 0x108 */ + uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU Peripheral ID register 4, Address offset: 0xFD0 */ + __IO uint32_t PIDR5; /*!< Debug MCU Peripheral ID register 5, Address offset: 0xFD4 */ + __IO uint32_t PIDR6; /*!< Debug MCU Peripheral ID register 6, Address offset: 0xFD8 */ + __IO uint32_t PIDR7; /*!< Debug MCU Peripheral ID register 7, Address offset: 0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU Peripheral ID register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU Peripheral ID register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU Peripheral ID register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU Peripheral ID register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU Component ID register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU Component ID register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU Component ID register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU Component ID register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ + __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ + __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ + uint32_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x04 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, Address offset: 0x10 */ + __IO uint32_t SECOBKKEYR; /*!< FLASH secure option bytes keys key register, Address offset: 0x14 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x18 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, Address offset: 0x30 */ + __IO uint32_t SECCCR; /*!< FLASH secure clear control register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x38 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x3C */ + __IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, Address offset: 0x40 */ + __IO uint32_t SECOBKCFGR; /*!< FLASH secure option byte key configuration register, Address offset: 0x44 */ + __IO uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x4C */ + __IO uint32_t OPTSR_CUR; /*!< FLASH option status current register, Address offset: 0x50 */ + __IO uint32_t OPTSR_PRG; /*!< FLASH option status to program register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x58-0x5C */ + __IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, Address offset: 0x60 */ + __IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, Address offset: 0x64 */ + __IO uint32_t SECEPOCHR_CUR; /*!< FLASH secure epoch current register, Address offset: 0x68 */ + __IO uint32_t SECEPOCHR_PRG; /*!< FLASH secure epoch to program register, Address offset: 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< FLASH option status current register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< FLASH option status to program register 2, Address offset: 0x74 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x78-0x7C */ + __IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, Address offset: 0x80 */ + __IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, Address offset: 0x84 */ + __IO uint32_t SECBOOTR_CUR; /*!< FLASH secure unique boot entry current register, Address offset: 0x88 */ + __IO uint32_t SECBOOTR_PRG; /*!< FLASH secure unique boot entry to program register, Address offset: 0x8C */ + __IO uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock current register, Address offset: 0x90 */ + __IO uint32_t OTPBLR_PRG; /*!< FLASH OTP block Lock to program register, Address offset: 0x94 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x98-0x9C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0xA0 */ + uint32_t RESERVED6[7]; /*!< Reserved6, Address offset: 0xA4-0xBF */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xC0 */ + uint32_t RESERVED7[7]; /*!< Reserved7, Address offset: 0xC4-0xDC */ + __IO uint32_t SECWM1R_CUR; /*!< FLASH secure watermark 1 current register, Address offset: 0xE0 */ + __IO uint32_t SECWM1R_PRG; /*!< FLASH secure watermark 1 to program register, Address offset: 0xE4 */ + __IO uint32_t WRP1R_CUR; /*!< FLASH write sector group protection current register for bank1, Address offset: 0xE8 */ + __IO uint32_t WRP1R_PRG; /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */ + __IO uint32_t EDATA1R_CUR; /*!< FLASH data sectors configuration current register for bank1, Address offset: 0xF0 */ + __IO uint32_t EDATA1R_PRG; /*!< FLASH data sectors configuration to program register for bank1, Address offset: 0xF4 */ + __IO uint32_t HDP1R_CUR; /*!< FLASH HDP configuration current register for bank1, Address offset: 0xF8 */ + __IO uint32_t HDP1R_PRG; /*!< FLASH HDP configuration to program register for bank1, Address offset: 0xFC */ + __IO uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IO uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IO uint32_t ECCDR; /*!< FLASH ECC data register, Address offset: 0x108 */ + uint32_t RESERVED8[37]; /*!< Reserved8, Address offset: 0x10C-0x19C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0x1A0 */ + uint32_t RESERVED9[7]; /*!< Reserved9, Address offset: 0x1A4-0x1BF */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0x1C0 */ + uint32_t RESERVED10[7]; /*!< Reserved10, Address offset: 0x1C4-0x1DC */ + __IO uint32_t SECWM2R_CUR; /*!< FLASH secure watermark 2 current register, Address offset: 0x1E0 */ + __IO uint32_t SECWM2R_PRG; /*!< FLASH secure watermark 2 to program register, Address offset: 0x1E4 */ + __IO uint32_t WRP2R_CUR; /*!< FLASH write sector group protection current register for bank2, Address offset: 0x1E8 */ + __IO uint32_t WRP2R_PRG; /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */ + __IO uint32_t EDATA2R_CUR; /*!< FLASH data sectors configuration current register for bank2, Address offset: 0x1F0 */ + __IO uint32_t EDATA2R_PRG; /*!< FLASH data sectors configuration to program register for bank2, Address offset: 0x1F4 */ + __IO uint32_t HDP2R_CUR; /*!< FLASH HDP configuration current register for bank2, Address offset: 0x1F8 */ + __IO uint32_t HDP2R_PRG; /*!< FLASH HDP configuration to program register for bank2, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + __IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, Address offset: 0x68 */ + __IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, Address offset: 0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + __IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, Address offset: 0x78 */ + __IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, Address offset: 0x7c */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t PMCR; /*!< Power mode control register , Address offset: 0x00 */ + __IO uint32_t PMSR; /*!< Power mode status register , Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t VOSCR; /*!< Voltage scaling control register , Address offset: 0x10 */ + __IO uint32_t VOSSR; /*!< Voltage sacling status register , Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t BDCR; /*!< BacKup domain control register , Address offset: 0x20 */ + __IO uint32_t DBPCR; /*!< DBP control register, Address offset: 0x24 */ + __IO uint32_t BDSR; /*!< BacKup domain status register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Usb typeC and Power Delivery Register, Address offset: 0x2C */ + __IO uint32_t SCCR; /*!< Supply configuration control register, Address offset: 0x30 */ + __IO uint32_t VMCR; /*!< Voltage Monitor Control Register, Address offset: 0x34 */ + __IO uint32_t USBSCR; /*!< USB Supply Control Register Address offset: 0x38 */ + __IO uint32_t VMSR; /*!< Status Register Voltage Monitoring, Address offset: 0x3C */ + __IO uint32_t WUSCR; /*!< WakeUP status clear register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< WakeUP status Register, Address offset: 0x44 */ + __IO uint32_t WUCR; /*!< WakeUP configuration register, Address offset: 0x48 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t IORETR; /*!< IO RETention Register, Address offset: 0x50 */ + uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */ + __IO uint32_t SECCFGR; /*!< Security configuration register, Address offset: 0x100 */ + __IO uint32_t PRIVCFGR; /*!< Privilege configuration register, Address offset: 0x104 */ +}PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + __IO uint32_t WPR3; /*!< SRAM Write Protection Register 3, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t HSICFGR; /*!< RCC HSI Clock Calibration Register, Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x14 */ + __IO uint32_t CSICFGR; /*!< RCC CSI Clock Calibration Register, Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< RCC PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 Peripherals Reset Register Address offset: 0x64 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x68 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 Peripherals reset Low Word register Address offset: 0x74 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 Peripherals reset High Word register Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED10; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 Peripherals Clock Enable Register Address offset: 0x8C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x90 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 Peripherals clock Enable Low Word register Address offset: 0x9C */ + __IO uint32_t APB1HENR; /*!< RCC APB1 Peripherals clock Enable High Word register Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 Peripheral sleep clock Register Address offset: 0xB0 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 Peripheral sleep clock Register Address offset: 0xB4 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0xB8 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 Peripherals sleep clock Register Address offset: 0xBC */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 Peripherals sleep clock Low Word Register Address offset: 0xC4 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 Peripherals sleep clock High Word Register Address offset: 0xC8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 Peripherals sleep clock Register Address offset: 0xCC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 Peripherals Clock Low Power Enable Register Address offset: 0xD0 */ + uint32_t RESERVED18; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t CCIPR1; /*!< RCC IPs Clocks Configuration Register 1 Address offset: 0xD8 */ + __IO uint32_t CCIPR2; /*!< RCC IPs Clocks Configuration Register 2 Address offset: 0xDC */ + __IO uint32_t CCIPR3; /*!< RCC IPs Clocks Configuration Register 3 Address offset: 0xE0 */ + __IO uint32_t CCIPR4; /*!< RCC IPs Clocks Configuration Register 4 Address offset: 0xE4 */ + __IO uint32_t CCIPR5; /*!< RCC IPs Clocks Configuration Register 5 Address offset: 0xE8 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< RCC VSW Backup Domain & V33 Domain Control Register Address offset: 0xF0 */ + __IO uint32_t RSR; /*!< RCC Reset status Register Address offset: 0xF4 */ + uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC Secure mode configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x64 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief System configuration, Boot and Security + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */ + __IO uint32_t HDPLCR; /*!< SBS HDPL Control Register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS HDPL Status Register, Address offset: 0x14 */ + __IO uint32_t NEXTHDPLCR; /*!< NEXT HDPL Control Register, Address offset: 0x18 */ + __IO uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control Register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock Register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command Register, Address offset: 0x34 */ + uint32_t RESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */ + __IO uint32_t EPOCHSELCR; /*!< EPOCH Selection Register, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */ + __IO uint32_t SECCFGR; /*!< SBS Security Mode Configuration, Address offset: 0xC0 */ + uint32_t RESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config Register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask Register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status Register, Address offset: 0x108 */ + uint32_t RESERVED7; /*!< RESERVED7, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS Compensation Cell Value Register, Address offset: 0x114 */ + __IO uint32_t CCSWCR; /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */ + __IO uint32_t RESERVED8; /*!< RESERVED8, Address offset: 0x11C */ + __IO uint32_t CFGR2; /*!< SBS Class B Register, Address offset: 0x120 */ + uint32_t RESERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */ + __IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset: 0x144 */ + __IO uint32_t CSLCKR; /*!< SBS CPU Secure Lock Register, Address offset: 0x148 */ + __IO uint32_t ECCNMIR; /*!< SBS FLITF ECC NMI MASK Register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ + +#define SRAM1_SIZE (0x20000UL) /*!< SRAM1=128k */ +#define SRAM2_SIZE (0x14000UL) /*!< SRAM2=80k */ +#define SRAM3_SIZE (0x10000UL) /*!< SRAM3=64k */ +#define BKPSRAM_SIZE (0x00800UL) /*!< BKPSRAM=2k */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 512 KB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (128 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20020000UL) /*!< SRAM2 (80 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x20034000UL) /*!< SRAM3 (64 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) /*!< FMC Memory Bank1 for SRAM, NOR and PSRAM */ +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< FMC Memory Bank3 for NAND */ +#define FMC_SDRAM_BANK_1 (FMC_BASE + 0x60000000UL) /*!< FMC Memory SDRAM Bank1 */ +#define FMC_SDRAM_BANK_2 (FMC_BASE + 0x70000000UL) /*!< FMC Memory SDRAM Bank2 */ + + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define CEC_BASE_NS (APB1PERIPH_BASE_NS + 0x7000UL) +#define DTS_BASE_NS (APB1PERIPH_BASE_NS + 0x8C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x6400UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define GPDMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA2_Channel0_BASE_NS (GPDMA2_BASE_NS + 0x0050UL) +#define GPDMA2_Channel1_BASE_NS (GPDMA2_BASE_NS + 0x00D0UL) +#define GPDMA2_Channel2_BASE_NS (GPDMA2_BASE_NS + 0x0150UL) +#define GPDMA2_Channel3_BASE_NS (GPDMA2_BASE_NS + 0x01D0UL) +#define GPDMA2_Channel4_BASE_NS (GPDMA2_BASE_NS + 0x0250UL) +#define GPDMA2_Channel5_BASE_NS (GPDMA2_BASE_NS + 0x02D0UL) +#define GPDMA2_Channel6_BASE_NS (GPDMA2_BASE_NS + 0x0350UL) +#define GPDMA2_Channel7_BASE_NS (GPDMA2_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + +/*!< APB3 Non secure peripherals */ +#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define I3C2_BASE_NS (APB3PERIPH_BASE_NS + 0x3000UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB3 Non secure peripherals */ +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) + +/*!< AHB4 Non secure peripherals */ +#define OTFDEC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL) +#define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 512 KB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (128 KB) secure base address */ +#define SRAM2_BASE_S (0x30020000UL) /*!< SRAM2 (80 KB) secure base address */ +#define SRAM3_BASE_S (0x30034000UL) /*!< SRAM3 (64 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) + +/*!< APB1 secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define CEC_BASE_S (APB1PERIPH_BASE_S + 0x7000UL) +#define DTS_BASE_S (APB1PERIPH_BASE_S + 0x8C00UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x6000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x6400UL) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define GPDMA2_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA2_Channel0_BASE_S (GPDMA2_BASE_S + 0x0050UL) +#define GPDMA2_Channel1_BASE_S (GPDMA2_BASE_S + 0x00D0UL) +#define GPDMA2_Channel2_BASE_S (GPDMA2_BASE_S + 0x0150UL) +#define GPDMA2_Channel3_BASE_S (GPDMA2_BASE_S + 0x01D0UL) +#define GPDMA2_Channel4_BASE_S (GPDMA2_BASE_S + 0x0250UL) +#define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL) +#define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL) +#define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) + +/*!< AHB2 secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x08400UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB3 secure peripherals */ +#define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define I3C2_BASE_S (APB3PERIPH_BASE_S + 0x3000UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB3 secure peripherals */ +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define DEBUG_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) + +/*!< AHB4 secure peripherals */ +#define OTFDEC1_BASE_S (AHB4PERIPH_BASE_S + 0x5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) +#define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL) +#define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x44024000UL) +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ +#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */ + +/* Flash system Area */ +#define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */ +#define FLASH_SYSTEM_BASE_S (0x0FF80000UL) /*!< FLASH System secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes system Flash */ + +/* Internal Flash EDATA Area */ +#define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */ +#define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */ +#define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */ + +/* Internal Flash OBK Area */ +#define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base address */ +#define FLASH_OBK_BASE_S (0x0FFD0000UL) /*!< FLASH OBK (option byte keys) secure base address */ +#define FLASH_OBK_SIZE (0x2000U) /*!< 8 KB of option byte keys */ +#define FLASH_OBK_HDPL0_SIZE (0x100U) /*!< 256 Bytes of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL1_BASE_NS (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address */ +#define FLASH_OBK_HDPL1_BASE_S (FLASH_OBK_BASE_S + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 secure base address */ +#define FLASH_OBK_HDPL1_SIZE (0x800U) /*!< 2 KB of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL2_BASE_NS (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address */ +#define FLASH_OBK_HDPL2_BASE_S (FLASH_OBK_HDPL1_BASE_S + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 secure base address */ +#define FLASH_OBK_HDPL2_SIZE (0x300U) /*!< 768 Bytes of HDPL2 option byte keys */ + +#define FLASH_OBK_HDPL3_BASE_NS (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3_BASE_S (FLASH_OBK_HDPL2_BASE_S + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3_SIZE (0x13F0U) /*!< 5104 Bytes HDPL3 option byte keys */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_OBK_HDPL3S_BASE_NS (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3S_BASE_S (FLASH_OBK_HDPL3_BASE_S) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3S_SIZE (0x0C00U) /*!< 3072 Bytes of secure HDPL3 option byte keys */ + +#define FLASH_OBK_HDPL3NS_BASE_NS (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3NS_BASE_S (FLASH_OBK_HDPL3_BASE_S + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ +#endif /* CMSE */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB84UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0xBF9FB68UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it jumps to the non-secure reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3NS_TypeDef)(uint32_t VectorTableAddr); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t *pDestination; /*!< Address in OBKeys sections where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_NSC_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_S_JumpHDPlvl3NS_TypeDef JumpHDPLvl3NS; +} S_pFuncTypeDef; + +/** + * @brief RSSLib Non-secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_NSC_DataProvisioning_TypeDef DataProvisioning; +} NSC_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + uint32_t RESERVED1[3]; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/*!< Non Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define NSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB6CUL) +#define NSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB74UL) + +/************ RSSLIB function return constants ********************************/ +#define NSSLIB_ERROR (0xF5F5F5F5UL) +#define NSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define NSSLIB_PFUNC_BASE (0xBF9FB6CUL) +#define NSSLIB_PFUNC ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; +} NSSLIB_pFunc_TypeDef; + +/* + * Certificate address description + */ +#define CERT_CHIP_PACK1_ADDR (0x0BF9FE00U) +#define CERT_CHIP_PACK1_SIZE (0x200U) +#define CERT_CHIP_PACK2_ADDR (0x0BF9FC00U) +#define CERT_CHIP_PACK2_SIZE (0x200U) + +#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR) +#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE) + +#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET (152U) +#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET) +#define CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET (216U) +#define CERT_ST_DUA_INIT_ATTEST_SIGN_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET) +#define CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET (484U) +#define CERT_ST_DUA_INIT_ATTEST_SERIAL_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET) + +#define CERT_ST_DUA_USER_PUB_KEY_OFFSET (12U) +#define CERT_ST_DUA_USER_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_PUB_KEY_OFFSET) +#define CERT_ST_DUA_USER_SIGN_OFFSET (76U) +#define CERT_ST_DUA_USER_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SIGN_OFFSET) +#define CERT_ST_DUA_USER_SERIAL_OFFSET (140U) +#define CERT_ST_DUA_USER_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SERIAL_OFFSET) + +/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *)TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *)TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *)TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *)TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *)TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *)TIM7_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *)TIM12_BASE_NS) +#define TIM13_NS ((TIM_TypeDef *)TIM13_BASE_NS) +#define TIM14_NS ((TIM_TypeDef *)TIM14_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *)WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *)IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *)SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *)SPI3_BASE_NS) +#define USART2_NS ((USART_TypeDef *)USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *)USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *)UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *)UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *)I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *)I2C2_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *)I3C1_BASE_NS) +#define CRS_NS ((CRS_TypeDef *)CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *)USART6_BASE_NS) +#define CEC_NS ((CEC_TypeDef *)CEC_BASE_NS) +#define DTS_NS ((DTS_TypeDef *)DTS_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *)LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *)UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA2_NS ((DMA_TypeDef *) GPDMA2_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA2_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS) +#define GPDMA2_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS) +#define GPDMA2_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS) +#define GPDMA2_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS) +#define GPDMA2_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS) +#define GPDMA2_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS) +#define GPDMA2_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS) +#define GPDMA2_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) + + +/*!< APB3 Non secure peripherals */ +#define SBS_NS ((SBS_TypeDef *) SBS_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) + +/*!< AHB4 Non secure peripherals */ +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) + +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *)TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *)TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *)TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *)TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *)TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *)TIM7_BASE_S) +#define TIM12_S ((TIM_TypeDef *)TIM12_BASE_S) +#define WWDG_S ((WWDG_TypeDef *)WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *)IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *)SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *)SPI3_BASE_S) +#define USART2_S ((USART_TypeDef *)USART2_BASE_S) +#define USART3_S ((USART_TypeDef *)USART3_BASE_S) +#define UART4_S ((USART_TypeDef *)UART4_BASE_S) +#define UART5_S ((USART_TypeDef *)UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *)I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *)I2C2_BASE_S) +#define I3C1_S ((I3C_TypeDef *)I3C1_BASE_S) +#define CRS_S ((CRS_TypeDef *)CRS_BASE_S) +#define USART6_S ((USART_TypeDef *)USART6_BASE_S) +#define CEC_S ((CEC_TypeDef *)CEC_BASE_S) +#define DTS_S ((DTS_TypeDef *)DTS_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *)LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *)UCPD1_BASE_S) + +/*!< APB2 secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *)USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA2_S ((DMA_TypeDef *) GPDMA2_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA2_Channel0_S ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_S) +#define GPDMA2_Channel1_S ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_S) +#define GPDMA2_Channel2_S ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_S) +#define GPDMA2_Channel3_S ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_S) +#define GPDMA2_Channel4_S ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_S) +#define GPDMA2_Channel5_S ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_S) +#define GPDMA2_Channel6_S ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_S) +#define GPDMA2_Channel7_S ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_S) + + +/*!< AHB2 secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) + +/*!< APB3 secure peripherals */ +#define SBS_S ((SBS_TypeDef *) SBS_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) + +/*!< AHB4 secure peripherals */ +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) + +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) + +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define FLASH_OBK_BASE FLASH_OBK_BASE_S +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_S +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define APB3PERIPH_BASE APB3PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_S +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA2 GPDMA2_S +#define GPDMA2_BASE GPDMA2_BASE_S + +#define GPDMA2_Channel0 GPDMA2_Channel0_S +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_S + +#define GPDMA2_Channel1 GPDMA2_Channel1_S +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_S + +#define GPDMA2_Channel2 GPDMA2_Channel2_S +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_S + +#define GPDMA2_Channel3 GPDMA2_Channel3_S +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_S + +#define GPDMA2_Channel4 GPDMA2_Channel4_S +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_S + +#define GPDMA2_Channel5 GPDMA2_Channel5_S +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_S + +#define GPDMA2_Channel6 GPDMA2_Channel6_S +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_S + +#define GPDMA2_Channel7 GPDMA2_Channel7_S +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define CEC CEC_S +#define CEC_BASE CEC_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SBS SBS_S +#define SBS_BASE SBS_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + + + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#else + +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define FLASH_OBK_BASE FLASH_OBK_BASE_NS +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_NS +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_NS + +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS + +#define SRAM3_BASE SRAM3_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS + +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define APB3PERIPH_BASE APB3PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA2 GPDMA2_NS +#define GPDMA2_BASE GPDMA2_BASE_NS + +#define GPDMA2_Channel0 GPDMA2_Channel0_NS +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_NS + +#define GPDMA2_Channel1 GPDMA2_Channel1_NS +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_NS + +#define GPDMA2_Channel2 GPDMA2_Channel2_NS +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_NS + +#define GPDMA2_Channel3 GPDMA2_Channel3_NS +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_NS + +#define GPDMA2_Channel4 GPDMA2_Channel4_NS +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_NS + +#define GPDMA2_Channel5 GPDMA2_Channel5_NS +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_NS + +#define GPDMA2_Channel6 GPDMA2_Channel6_NS +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_NS + +#define GPDMA2_Channel7 GPDMA2_Channel7_NS +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define CEC CEC_NS +#define CEC_BASE CEC_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SBS SBS_NS +#define SBS_BASE SBS_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + + + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#endif + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register *****************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x01UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC Option bit 0 */ +#define ADC_OR_OP1_Pos (1U) +#define ADC_OR_OP1_Msk (0x01UL << ADC_OR_OP1_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC Option bit 1 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************** RNG Nist Compliance Values ******************************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) /*!< FLASH Bank Size */ +#define FLASH_SECTOR_SIZE 0x2000U /*!< Flash Sector Size: 8 KB */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area interrupted */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (23U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00800000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< Operation in OTP area interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< Data buffer not empty flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OBKERR_Pos (21U) +#define FLASH_SR_OBKERR_Msk (0x1UL << FLASH_SR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_OBKERR FLASH_SR_OBKERR_Msk /*!< OBK general error flag */ +#define FLASH_SR_OBKWERR_Pos (22U) +#define FLASH_SR_OBKWERR_Msk (0x1UL << FLASH_SR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OBKWERR FLASH_SR_OBKWERR_Msk /*!< OBK write error flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ + +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (5U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (6U) +#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x000007C0 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ +#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ +#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ +#define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-operation interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OBKERRIE_Pos (21U) +#define FLASH_CR_OBKERRIE_Msk (0x1UL << FLASH_CR_OBKERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_OBKERRIE FLASH_CR_OBKERRIE_Msk /*!< OBK general error interrupt enable bitt */ +#define FLASH_CR_OBKWERRIE_Pos (22U) +#define FLASH_CR_OBKWERRIE_Msk (0x1UL << FLASH_CR_OBKWERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OBKWERRIE FLASH_CR_OBKWERRIE_Msk /*!< OBK write error interrupt enable bit */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_CR_INV_Pos (29U) +#define FLASH_CR_INV_Msk (0x1UL << FLASH_CR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_CR_INV FLASH_CR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x10000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OBKERR_Pos (21U) +#define FLASH_CCR_CLR_OBKERR_Msk (0x1UL << FLASH_CCR_CLR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_OBKERR FLASH_CCR_CLR_OBKERR_Msk /*!< OBKERR flag clear bit */ +#define FLASH_CCR_CLR_OBKWERR_Pos (22U) +#define FLASH_CCR_CLR_OBKWERR_Msk (0x1UL << FLASH_CCR_CLR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OBKWERR FLASH_CCR_CLR_OBKWERR_Msk /*!< OBKWERR flag clear bit */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Option byte change error clear bit */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/****************** Bits definition for FLASH_OBKCFGR register *****************/ +#define FLASH_OBKCFGR_LOCK_Pos (0U) +#define FLASH_OBKCFGR_LOCK_Msk (0x1UL << FLASH_OBKCFGR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OBKCFGR_LOCK FLASH_OBKCFGR_LOCK_Msk /*!< OBKCFGR lock */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Pos (1U) +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Msk (0x1UL << FLASH_OBKCFGR_SWAP_SECT_REQ_Pos) /*!< 0x00000002 */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ FLASH_OBKCFGR_SWAP_SECT_REQ_Msk /*!< OBK swap sector request */ +#define FLASH_OBKCFGR_ALT_SECT_Pos (2U) +#define FLASH_OBKCFGR_ALT_SECT_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_Pos) /*!< 0x00000004 */ +#define FLASH_OBKCFGR_ALT_SECT FLASH_OBKCFGR_ALT_SECT_Msk /*!< Alternate sector */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Pos (3U) +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_ERASE_Pos) /*!< 0x00000008 */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE FLASH_OBKCFGR_ALT_SECT_ERASE_Msk /*!< Alternate sector erase */ +#define FLASH_OBKCFGR_SWAP_OFFSET_Pos (16U) +#define FLASH_OBKCFGR_SWAP_OFFSET_Msk (0x1FFUL << FLASH_OBKCFGR_SWAP_OFFSET_Pos) /*!< 0x01FF0000 */ +#define FLASH_OBKCFGR_SWAP_OFFSET FLASH_OBKCFGR_SWAP_OFFSET_Msk /*!< Swap offset */ + +/****************** Bits definition for FLASH_HDPEXTR register *****************/ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x1FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000001F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x1FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x001F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_BOR_LEV_Pos (0U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000003 */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR_BORH_EN_Pos (2U) +#define FLASH_OPTSR_BORH_EN_Msk (0x1UL << FLASH_OPTSR_BORH_EN_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BORH_EN FLASH_OPTSR_BORH_EN_Msk /*!< Brownout high enable configuration bit */ +#define FLASH_OPTSR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG_SW FLASH_OPTSR_IWDG_SW_Msk /*!< IWDG control mode option bit */ +#define FLASH_OPTSR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_WWDG_SW FLASH_OPTSR_WWDG_SW_Msk /*!< WWDG control mode option bit */ +#define FLASH_OPTSR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP FLASH_OPTSR_NRST_STOP_Msk /*!< Stop mode entry reset option bit */ +#define FLASH_OPTSR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STDBY FLASH_OPTSR_NRST_STDBY_Msk /*!< Standby mode entry reset option bit */ +#define FLASH_OPTSR_PRODUCT_STATE_Pos (8U) +#define FLASH_OPTSR_PRODUCT_STATE_Msk (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRODUCT_STATE FLASH_OPTSR_PRODUCT_STATE_Msk /*!< Life state code option byte */ +#define FLASH_OPTSR_IO_VDD_HSLV_Pos (16U) +#define FLASH_OPTSR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos) /*!< 0x00010000 */ +#define FLASH_OPTSR_IO_VDD_HSLV FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos (17U) +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_IWDG_STOP FLASH_OPTSR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTSR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_IWDG_STDBY FLASH_OPTSR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTSR_BOOT_UBE_Pos (22U) +#define FLASH_OPTSR_BOOT_UBE_Msk (0xFFUL << FLASH_OPTSR_BOOT_UBE_Pos) /*!< 0x3FC00000 */ +#define FLASH_OPTSR_BOOT_UBE FLASH_OPTSR_BOOT_UBE_Msk /*!< Unique boot entry option byte */ +#define FLASH_OPTSR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK FLASH_OPTSR_SWAP_BANK_Msk /*!< Bank swapping option bit */ + +/******************* Bits definition for FLASH_EPOCHR register ***************/ +#define FLASH_EPOCHR_EPOCH_Pos (0U) +#define FLASH_EPOCHR_EPOCH_Msk (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos) /*!< 0x00FFFFFF */ +#define FLASH_EPOCHR_EPOCH FLASH_EPOCHR_EPOCH_Msk /*!< EPOCH counter */ + +/******************* Bits definition for FLASH_OPTSR2 register ***************/ +#define FLASH_OPTSR2_SRAM1_3_RST_Pos (2U) +#define FLASH_OPTSR2_SRAM1_3_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM1_3_RST_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR2_SRAM1_3_RST FLASH_OPTSR2_SRAM1_3_RST_Msk /*!< SRAM1 and SRAM3 erased when a system reset occurs */ +#define FLASH_OPTSR2_SRAM2_RST_Pos (3U) +#define FLASH_OPTSR2_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR2_SRAM2_RST FLASH_OPTSR2_SRAM2_RST_Msk /*!< SRAM2 erased when a system reset occurs*/ +#define FLASH_OPTSR2_BKPRAM_ECC_Pos (4U) +#define FLASH_OPTSR2_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_BKPRAM_ECC FLASH_OPTSR2_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) +#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_USBPD_DIS_Pos (8U) +#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ +#define FLASH_OPTSR2_TZEN_Pos (24U) +#define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ +#define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ + +/**************** Bits definition for FLASH_BOOTR register **********************/ +#define FLASH_BOOTR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_BOOT_LOCK FLASH_BOOTR_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_BOOTR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_BOOTADD FLASH_BOOTR_BOOTADD_Msk /*!< Boot address */ + +/**************** Bits definition for FLASH_PRIVBBR register *******************/ +#define FLASH_PRIVBBR_PRIVBB_Pos (0U) +#define FLASH_PRIVBBR_PRIVBB_Msk (0xFFFFFFFFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRIVBBR_PRIVBB FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */ + +/***************** Bits definition for FLASH_SECWMR register ********************/ +#define FLASH_SECWMR_SECWM_STRT_Pos (0U) +#define FLASH_SECWMR_SECWM_STRT_Msk (0x1FUL << FLASH_SECWMR_SECWM_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWMR_SECWM_STRT FLASH_SECWMR_SECWM_STRT_Msk /*!< Start sector of secure area */ +#define FLASH_SECWMR_SECWM_END_Pos (16U) +#define FLASH_SECWMR_SECWM_END_Msk (0x1FUL << FLASH_SECWMR_SECWM_END_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWMR_SECWM_END FLASH_SECWMR_SECWM_END_Msk /*!< End sector of secure area */ + +/***************** Bits definition for FLASH_WRPR register *********************/ +#define FLASH_WRPR_WRPSG_Pos (0U) +#define FLASH_WRPR_WRPSG_Msk (0x000000FFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0x000000FF */ +#define FLASH_WRPR_WRPSG FLASH_WRPR_WRPSG_Msk /*!< Sector group protection option status */ + +/***************** Bits definition for FLASH_EDATA register ********************/ +#define FLASH_EDATAR_EDATA_STRT_Pos (0U) +#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ +#define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ +#define FLASH_EDATAR_EDATA_EN_Pos (15U) +#define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ +#define FLASH_EDATAR_EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */ + +/***************** Bits definition for FLASH_HDPR register ********************/ +#define FLASH_HDPR_HDP_STRT_Pos (0U) +#define FLASH_HDPR_HDP_STRT_Msk (0x1FUL << FLASH_HDPR_HDP_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_HDPR_HDP_STRT FLASH_HDPR_HDP_STRT_Msk /*!< Start sector of hide protection area */ +#define FLASH_HDPR_HDP_END_Pos (16U) +#define FLASH_HDPR_HDP_END_Msk (0x1FUL << FLASH_HDPR_HDP_END_Pos) /*!< 0x001F0000 */ +#define FLASH_HDPR_HDP_END FLASH_HDPR_HDP_END_Msk /*!< End sector of hide protection area */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_OBK_ECC_Pos (20U) +#define FLASH_ECCR_OBK_ECC_Msk (0x1UL << FLASH_ECCR_OBK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_OBK_ECC FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */ +#define FLASH_ECCR_DATA_ECC_Pos (21U) +#define FLASH_ECCR_DATA_ECC_Msk (0x1UL << FLASH_ECCR_DATA_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_DATA_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */ +#define FLASH_ECCR_BK_ECC_Pos (22U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (23U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_OTP_ECC_Pos (24U) +#define FLASH_ECCR_OTP_ECC_Msk (0x1UL << FLASH_ECCR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (25U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_ECCDR register ***************/ +#define FLASH_ECCDR_FAIL_DATA_Pos (0U) +#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_OR register ******************/ +#define RTC_OR_OUT2_RMP_Pos (0U) +#define RTC_OR_OUT2_RMP_Msk (0x1UL << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x08000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk +#define TAMP_CR1_ITAMP15E_Pos (30U) +#define TAMP_CR1_ITAMP15E_Msk (0x1UL << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ +#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP4NOER_Pos (3U) +#define TAMP_CR3_ITAMP4NOER_Msk (0x1UL << TAMP_CR3_ITAMP4NOER_Pos) /*!< 0x00000008 */ +#define TAMP_CR3_ITAMP4NOER TAMP_CR3_ITAMP4NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000080 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000400 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00001000 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk +#define TAMP_CR3_ITAMP15NOER_Pos (14U) +#define TAMP_CR3_ITAMP15NOER_Msk (0x1UL << TAMP_CR3_ITAMP15NOER_Pos) /*!< 0x00004000 */ +#define TAMP_CR3_ITAMP15NOER TAMP_CR3_ITAMP15NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk +#define TAMP_IER_ITAMP15IE_Pos (30U) +#define TAMP_IER_ITAMP15IE_Msk (0x1UL << TAMP_IER_ITAMP15IE_Pos) /*!< 0x40000000 */ +#define TAMP_IER_ITAMP15IE TAMP_IER_ITAMP15IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk +#define TAMP_SR_ITAMP15F_Pos (30U) +#define TAMP_SR_ITAMP15F_Msk (0x1UL << TAMP_SR_ITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SR_ITAMP15F TAMP_SR_ITAMP15F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk +#define TAMP_MISR_ITAMP15MF_Pos (30U) +#define TAMP_MISR_ITAMP15MF_Msk (0x1UL << TAMP_MISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_MISR_ITAMP15MF TAMP_MISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP4MF_Pos (19U) +#define TAMP_SMISR_ITAMP4MF_Msk (0x1UL << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk +#define TAMP_SMISR_ITAMP15MF_Pos (30U) +#define TAMP_SMISR_ITAMP15MF_Msk (0x1UL << TAMP_SMISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_SMISR_ITAMP15MF TAMP_SMISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk +#define TAMP_SCR_CITAMP15F_Pos (30U) +#define TAMP_SCR_CITAMP15F_Msk (0x1UL << TAMP_SCR_CITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SCR_CITAMP15F TAMP_SCR_CITAMP15F_Msk +/******************** Bits definition for TAMP_COUNT1R register ***************/ +#define TAMP_COUNT1R_COUNT_Pos (0U) +#define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */ +#define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk + +/******************** Bits definition for TAMP_OR register ***************/ +#define TAMP_OR_OUT3_RMP_Pos (1U) +#define TAMP_OR_OUT3_RMP_Msk (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00000006 */ +#define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk +#define TAMP_OR_OUT3_RMP_0 (0x1UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00100000 */ +#define TAMP_OR_OUT3_RMP_1 (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00200000 */ +#define TAMP_OR_OUT5_RMP_Pos (3U) +#define TAMP_OR_OUT5_RMP_Msk (0x1UL << TAMP_OR_OUT5_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_OUT5_RMP TAMP_OR_OUT5_RMP_Msk +#define TAMP_OR_IN2_RMP_Pos (8U) +#define TAMP_OR_IN2_RMP_Msk (0x1UL << TAMP_OR_IN2_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN2_RMP TAMP_OR_IN2_RMP_Msk +#define TAMP_OR_IN3_RMP_Pos (9U) +#define TAMP_OR_IN3_RMP_Msk (0x1UL << TAMP_OR_IN3_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN3_RMP TAMP_OR_IN3_RMP_Msk +#define TAMP_OR_IN4_RMP_Pos (10U) +#define TAMP_OR_IN4_RMP_Msk (0x1UL << TAMP_OR_IN4_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN4_RMP TAMP_OR_IN4_RMP_Msk + +/******************** Bits definition for TAMP_ERCFG register ***************/ +#define TAMP_ERCFGR_ERCFG0_Pos (0U) +#define TAMP_ERCFGR_ERCFG0_Msk (0x1UL << TAMP_ERCFGR_ERCFG0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR_ERCFG0 TAMP_ERCFGR_ERCFG0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* SBS */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SBS_HDPLCR register *****************/ +#define SBS_HDPLCR_INCR_HDPL_Pos (0U) +#define SBS_HDPLCR_INCR_HDPL_Msk (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLCR_INCR_HDPL SBS_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL value. */ + +/******************** Bit definition for SBS_HDPLSR register *****************/ +#define SBS_HDPLSR_HDPL_Pos (0U) +#define SBS_HDPLSR_HDPL_Msk (0xFFUL << SBS_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLSR_HDPL SBS_HDPLSR_HDPL_Msk /*!< HDPL value. */ + +/******************** Bit definition for SBS_NEXTHDPLCR register *****************/ +#define SBS_NEXTHDPLCR_NEXTHDPL_Pos (0U) +#define SBS_NEXTHDPLCR_NEXTHDPL_Msk (0x3UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000003 */ +#define SBS_NEXTHDPLCR_NEXTHDPL SBS_NEXTHDPLCR_NEXTHDPL_Msk /*!< NEXTHDPL value. */ +#define SBS_NEXTHDPLCR_NEXTHDPL_0 (0x1UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000001 */ +#define SBS_NEXTHDPLCR_NEXTHDPL_1 (0x2UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000002 */ + +/******************** Bit definition for SBS_DBGCR register *****************/ +#define SBS_DBGCR_AP_UNLOCK_Pos (0U) +#define SBS_DBGCR_AP_UNLOCK_Msk (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGCR_AP_UNLOCK SBS_DBGCR_AP_UNLOCK_Msk /*!< Open the Access Port. */ + +#define SBS_DBGCR_DBG_UNLOCK_Pos (8U) +#define SBS_DBGCR_DBG_UNLOCK_Msk (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< 0x0000FF00 */ +#define SBS_DBGCR_DBG_UNLOCK SBS_DBGCR_DBG_UNLOCK_Msk /*!< Open the debug when DBG_AUTH_HDPL is reached. */ + +#define SBS_DBGCR_DBG_AUTH_HDPL_Pos (16U) +#define SBS_DBGCR_DBG_AUTH_HDPL_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ +#define SBS_DBGCR_DBG_AUTH_HDPL SBS_DBGCR_DBG_AUTH_HDPL_Msk /*!< HDPL value when the debug should be effectively opened. */ + +#define SBS_DBGCR_DBG_AUTH_SEC_Pos (24U) +#define SBS_DBGCR_DBG_AUTH_SEC_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_SEC_Pos) /*!< 0xFF000000 */ +#define SBS_DBGCR_DBG_AUTH_SEC SBS_DBGCR_DBG_AUTH_SEC_Msk /*!< Open the non-secured and secured debugs. */ + +/******************** Bit definition for SBS_DBGLCKR register *****************/ +#define SBS_DBGLOCKR_DBGCFG_LOCK_Pos (0U) +#define SBS_DBGLOCKR_DBGCFG_LOCK_Msk (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGLOCKR_DBGCFG_LOCK SBS_DBGLOCKR_DBGCFG_LOCK_Msk /*!< SBS_DBGLOCKR_DBGCFG_LOCK value. */ + +/******************** Bit definition for SBS_RSSCMDR register ***************/ +#define SBS_RSSCMDR_RSSCMD_Pos (0U) +#define SBS_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SBS_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */ +#define SBS_RSSCMDR_RSSCMD SBS_RSSCMDR_RSSCMD_Msk /*!< command to be executed by the RSS. */ + +/******************** Bit definition for SBS_EPOCHSELCR register ************/ +#define SBS_EPOCHSELCR_EPOCH_SEL_Pos (0U) +#define SBS_EPOCHSELCR_EPOCH_SEL_Msk (0x3UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000003 */ +#define SBS_EPOCHSELCR_EPOCH_SEL SBS_EPOCHSELCR_EPOCH_SEL_Msk /*!< Select EPOCH sent to SAES IP to encrypt/decrypt keys */ +#define SBS_EPOCHSELCR_EPOCH_SEL_0 (0x1UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000001 */ +#define SBS_EPOCHSELCR_EPOCH_SEL_1 (0x2UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000002 */ + +/****************** Bit definition for SBS_PMCR register ****************/ +#define SBS_PMCR_PB6_FMP_Pos (16U) +#define SBS_PMCR_PB6_FMP_Msk (0x1UL << SBS_PMCR_PB6_FMP_Pos) /*!< 0x00010000 */ +#define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode Plus command on PB(6) */ +#define SBS_PMCR_PB7_FMP_Pos (17U) +#define SBS_PMCR_PB7_FMP_Msk (0x1UL << SBS_PMCR_PB7_FMP_Pos) /*!< 0x00020000 */ +#define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode Plus command on PB(7) */ +#define SBS_PMCR_PB8_FMP_Pos (18U) +#define SBS_PMCR_PB8_FMP_Msk (0x1UL << SBS_PMCR_PB8_FMP_Pos) /*!< 0x00040000 */ +#define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode Plus command on PB(8) */ +#define SBS_PMCR_PB9_FMP_Pos (19U) +#define SBS_PMCR_PB9_FMP_Msk (0x1UL << SBS_PMCR_PB9_FMP_Pos) /*!< 0x00080000 */ +#define SBS_PMCR_PB9_FMP SBS_PMCR_PB9_FMP_Msk /*!< Fast-mode Plus command on PB(9) */ + +/****************** Bit definition for SBS_FPUIMR register ***************/ +#define SBS_FPUIMR_FPU_IE_Pos (0U) +#define SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */ +#define SBS_FPUIMR_FPU_IE SBS_FPUIMR_FPU_IE_Msk /*!< All FPU interrupts enable */ +#define SBS_FPUIMR_FPU_IE_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_1 (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */ + +/****************** Bit definition for SBS_MESR register ****************/ +#define SBS_MESR_MCLR_Pos (0U) +#define SBS_MESR_MCLR_Msk (0x1UL << SBS_MESR_MCLR_Pos) /*!< 0x00000001 */ +#define SBS_MESR_MCLR SBS_MESR_MCLR_Msk /*!< Status of Erase after Reset */ +#define SBS_MESR_IPMEE_Pos (16U) +#define SBS_MESR_IPMEE_Msk (0x1UL << SBS_MESR_IPMEE_Pos) /*!< 0x00010000 */ +#define SBS_MESR_IPMEE SBS_MESR_IPMEE_Msk /*!< Status of End of Erase for ICache and PKA RAMs */ + +/****************** Bit definition for SBS_CCCSR register ****************/ +#define SBS_CCCSR_EN1_Pos (0U) +#define SBS_CCCSR_EN1_Msk (0x1UL << SBS_CCCSR_EN1_Pos) /*!< 0x00000001 */ +#define SBS_CCCSR_EN1 SBS_CCCSR_EN1_Msk /*!< Enable compensation cell for VDD power rail */ +#define SBS_CCCSR_CS1_Pos (1U) +#define SBS_CCCSR_CS1_Msk (0x1UL << SBS_CCCSR_CS1_Pos) /*!< 0x00000002 */ +#define SBS_CCCSR_CS1 SBS_CCCSR_CS1_Msk /*!< Code selection for VDD power rail */ +#define SBS_CCCSR_EN2_Pos (2U) +#define SBS_CCCSR_EN2_Msk (0x1UL << SBS_CCCSR_EN2_Pos) /*!< 0x00000004 */ +#define SBS_CCCSR_EN2 SBS_CCCSR_EN2_Msk /*!< Enable compensation cell for VDDIO power rail */ +#define SBS_CCCSR_CS2_Pos (3U) +#define SBS_CCCSR_CS2_Msk (0x1UL << SBS_CCCSR_CS2_Pos) /*!< 0x00000008 */ +#define SBS_CCCSR_CS2 SBS_CCCSR_CS2_Msk /*!< Code selection for VDDIO power rail */ +#define SBS_CCCSR_RDY1_Pos (8U) +#define SBS_CCCSR_RDY1_Msk (0x1UL << SBS_CCCSR_RDY1_Pos) /*!< 0x00000100 */ +#define SBS_CCCSR_RDY1 SBS_CCCSR_RDY1_Msk /*!< VDD compensation cell ready flag */ +#define SBS_CCCSR_RDY2_Pos (9U) +#define SBS_CCCSR_RDY2_Msk (0x1UL << SBS_CCCSR_RDY2_Pos) /*!< 0x00000200 */ +#define SBS_CCCSR_RDY2 SBS_CCCSR_RDY2_Msk /*!< VDDIO compensation cell ready flag */ + +/****************** Bit definition for SBS_CCVALR register ****************/ +#define SBS_CCVALR_ANSRC1_Pos (0U) +#define SBS_CCVALR_ANSRC1_Msk (0xFUL << SBS_CCVALR_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCVALR_ANSRC1 SBS_CCVALR_ANSRC1_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC1_Pos (4U) +#define SBS_CCVALR_APSRC1_Msk (0xFUL << SBS_CCVALR_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCVALR_APSRC1 SBS_CCVALR_APSRC1_Msk /*!< PMOS compensation value */ +#define SBS_CCVALR_ANSRC2_Pos (8U) +#define SBS_CCVALR_ANSRC2_Msk (0xFUL << SBS_CCVALR_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCVALR_ANSRC2 SBS_CCVALR_ANSRC2_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC2_Pos (12U) +#define SBS_CCVALR_APSRC2_Msk (0xFUL << SBS_CCVALR_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCVALR_APSRC2 SBS_CCVALR_APSRC2_Msk /*!< PMOS compensation value */ + +/****************** Bit definition for SBS_CCSWCR register ****************/ +#define SBS_CCSWCR_SW_ANSRC1_Pos (0U) +#define SBS_CCSWCR_SW_ANSRC1_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCSWCR_SW_ANSRC1 SBS_CCSWCR_SW_ANSRC1_Msk /*!< NMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_APSRC1_Pos (4U) +#define SBS_CCSWCR_SW_APSRC1_Msk (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCSWCR_SW_APSRC1 SBS_CCSWCR_SW_APSRC1_Msk /*!< PMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_ANSRC2_Pos (8U) +#define SBS_CCSWCR_SW_ANSRC2_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCSWCR_SW_ANSRC2 SBS_CCSWCR_SW_ANSRC2_Msk /*!< NMOS compensation code for VDDIO Power Rail */ +#define SBS_CCSWCR_SW_APSRC2_Pos (12U) +#define SBS_CCSWCR_SW_APSRC2_Msk (0xFUL << SBS_CCSWCR_SW_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCSWCR_SW_APSRC2 SBS_CCSWCR_SW_APSRC2_Msk /*!< PMOS compensation code for VDDIO Power Rail */ + +/****************** Bit definition for SBS_CFGR2 register ****************/ +#define SBS_CFGR2_CLL_Pos (0U) +#define SBS_CFGR2_CLL_Msk (0x1UL << SBS_CFGR2_CLL_Pos) /*!< 0x00000001 */ +#define SBS_CFGR2_CLL SBS_CFGR2_CLL_Msk /*!< Core Lockup Lock */ +#define SBS_CFGR2_SEL_Pos (1U) +#define SBS_CFGR2_SEL_Msk (0x1UL << SBS_CFGR2_SEL_Pos) /*!< 0x00000002 */ +#define SBS_CFGR2_SEL SBS_CFGR2_SEL_Msk /*!< SRAM ECC Lock */ +#define SBS_CFGR2_PVDL_Pos (2U) +#define SBS_CFGR2_PVDL_Msk (0x1UL << SBS_CFGR2_PVDL_Pos) /*!< 0x00000004 */ +#define SBS_CFGR2_PVDL SBS_CFGR2_PVDL_Msk /*!< PVD Lock */ +#define SBS_CFGR2_ECCL_Pos (3U) +#define SBS_CFGR2_ECCL_Msk (0x1UL << SBS_CFGR2_ECCL_Pos) /*!< 0x00000008 */ +#define SBS_CFGR2_ECCL SBS_CFGR2_ECCL_Msk /*!< Flash ECC Lock*/ + +/******************** Bit definition for SBS_SECCFGR register ***************/ +#define SBS_SECCFGR_SBSSEC_Pos (0U) +#define SBS_SECCFGR_SBSSEC_Msk (0x1UL << SBS_SECCFGR_SBSSEC_Pos) /*!< 0x00000001 */ +#define SBS_SECCFGR_SBSSEC SBS_SECCFGR_SBSSEC_Msk /*!< SBS clock control security enable */ +#define SBS_SECCFGR_CLASSBSEC_Pos (1U) +#define SBS_SECCFGR_CLASSBSEC_Msk (0x1UL << SBS_SECCFGR_CLASSBSEC_Pos) /*!< 0x00000002 */ +#define SBS_SECCFGR_CLASSBSEC SBS_SECCFGR_CLASSBSEC_Msk /*!< ClassB SBS security enable */ +#define SBS_SECCFGR_FPUSEC_Pos (3U) +#define SBS_SECCFGR_FPUSEC_Msk (0x1UL << SBS_SECCFGR_FPUSEC_Pos) /*!< 0x00000008 */ +#define SBS_SECCFGR_FPUSEC SBS_SECCFGR_FPUSEC_Msk /*!< FPU SBS security enable */ + +/****************** Bit definition for SBS_CNSLCKR register **************/ +#define SBS_CNSLCKR_LOCKNSVTOR_Pos (0U) +#define SBS_CNSLCKR_LOCKNSVTOR_Msk (0x1UL << SBS_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */ +#define SBS_CNSLCKR_LOCKNSVTOR SBS_CNSLCKR_LOCKNSVTOR_Msk /*!< Disable VTOR_NS register writes by SW or debug agent */ +#define SBS_CNSLCKR_LOCKNSMPU_Pos (1U) +#define SBS_CNSLCKR_LOCKNSMPU_Msk (0x1UL << SBS_CNSLCKR_LOCKNSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Secure MPU registers writes by SW or debug agent */ + +/****************** Bit definition for SBS_CSLCKR register ***************/ +#define SBS_CSLCKR_LOCKSVTAIRCR_Pos (0U) +#define SBS_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SBS_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */ +#define SBS_CSLCKR_LOCKSVTAIRCR SBS_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vector table address, handling of system faults */ +#define SBS_CSLCKR_LOCKSMPU_Pos (1U) +#define SBS_CSLCKR_LOCKSMPU_Msk (0x1UL << SBS_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CSLCKR_LOCKSMPU SBS_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */ +#define SBS_CSLCKR_LOCKSAU_Pos (2U) +#define SBS_CSLCKR_LOCKSAU_Msk (0x1UL << SBS_CSLCKR_LOCKSAU_Pos) /*!< 0x00000004 */ +#define SBS_CSLCKR_LOCKSAU SBS_CSLCKR_LOCKSAU_Msk /*!< Disable changes to SAU registers */ + +/****************** Bit definition for SBS_ECCNMIR register ***************/ +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos (0U) +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos) /*!< 0x00000001 */ +#define SBS_ECCNMIR_ECCNMI_MASK_EN SBS_ECCNMIR_ECCNMI_MASK_EN_Msk /*!< Disable NMI in case of double ECC error in flash interface */ + +/*****************************************************************************/ +/* */ +/* Global TrustZone Control */ +/* */ +/*****************************************************************************/ +/******************* Bits definition for GTZC_TZSC_CR register ******************/ +#define GTZC_TZSC_CR_LCK_Pos (0U) +#define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */ + +/******************* Bits definition for GTZC_TZSC_MPCWM_CFGR register **********/ +#define GTZC_TZSC_MPCWM_CFGR_SREN_Pos (0U) +#define GTZC_TZSC_MPCWM_CFGR_SREN_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SREN GTZC_TZSC_MPCWM_CFGR_SREN_Msk +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos (1U) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk +#define GTZC_TZSC_MPCWM_CFGR_SEC_Pos (8U) +#define GTZC_TZSC_MPCWM_CFGR_SEC_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SEC GTZC_TZSC_MPCWM_CFGR_SEC_Msk +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos (9U) +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos) +#define GTZC_TZSC_MPCWM_CFGR_PRIV GTZC_TZSC_MPCWM_CFGR_PRIV_Msk + +/******************* Bits definition for GTZC_TZSC_MPCWMR register **************/ +#define GTZC_TZSC_MPCWMR_SUBZ_START_Pos (0U) +#define GTZC_TZSC_MPCWMR_SUBZ_START_Msk (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_START GTZC_TZSC_MPCWMR_SUBZ_START_Msk +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos (16U) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk + +/******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/ +/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers *****/ + +/*************** Bits definition for register x=1 (TZSC1) *************/ +#define GTZC_CFGR1_TIM2_Pos (0U) +#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) +#define GTZC_CFGR1_TIM3_Pos (1U) +#define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) +#define GTZC_CFGR1_TIM4_Pos (2U) +#define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) +#define GTZC_CFGR1_TIM5_Pos (3U) +#define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos) +#define GTZC_CFGR1_TIM6_Pos (4U) +#define GTZC_CFGR1_TIM6_Msk (0x01UL << GTZC_CFGR1_TIM6_Pos) +#define GTZC_CFGR1_TIM7_Pos (5U) +#define GTZC_CFGR1_TIM7_Msk (0x01UL << GTZC_CFGR1_TIM7_Pos) +#define GTZC_CFGR1_TIM12_Pos (6U) +#define GTZC_CFGR1_TIM12_Msk (0x01UL << GTZC_CFGR1_TIM12_Pos) +#define GTZC_CFGR1_WWDG_Pos (9U) +#define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) +#define GTZC_CFGR1_IWDG_Pos (10U) +#define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) +#define GTZC_CFGR1_SPI2_Pos (11U) +#define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos) +#define GTZC_CFGR1_SPI3_Pos (12U) +#define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos) +#define GTZC_CFGR1_USART2_Pos (13U) +#define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) +#define GTZC_CFGR1_USART3_Pos (14U) +#define GTZC_CFGR1_USART3_Msk (0x01UL << GTZC_CFGR1_USART3_Pos) +#define GTZC_CFGR1_UART4_Pos (15U) +#define GTZC_CFGR1_UART4_Msk (0x01UL << GTZC_CFGR1_UART4_Pos) +#define GTZC_CFGR1_UART5_Pos (16U) +#define GTZC_CFGR1_UART5_Msk (0x01UL << GTZC_CFGR1_UART5_Pos) +#define GTZC_CFGR1_I2C1_Pos (17U) +#define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) +#define GTZC_CFGR1_I2C2_Pos (18U) +#define GTZC_CFGR1_I2C2_Msk (0x01UL << GTZC_CFGR1_I2C2_Pos) +#define GTZC_CFGR1_I3C1_Pos (19U) +#define GTZC_CFGR1_I3C1_Msk (0x01UL << GTZC_CFGR1_I3C1_Pos) +#define GTZC_CFGR1_CRS_Pos (20U) +#define GTZC_CFGR1_CRS_Msk (0x01UL << GTZC_CFGR1_CRS_Pos) +#define GTZC_CFGR1_USART6_Pos (21U) +#define GTZC_CFGR1_USART6_Msk (0x01UL << GTZC_CFGR1_USART6_Pos) +#define GTZC_CFGR1_HDMICEC_Pos (24U) +#define GTZC_CFGR1_HDMICEC_Msk (0x01UL << GTZC_CFGR1_HDMICEC_Pos) +#define GTZC_CFGR1_DAC1_Pos (25U) +#define GTZC_CFGR1_DAC1_Msk (0x01UL << GTZC_CFGR1_DAC1_Pos) +#define GTZC_CFGR1_DTS_Pos (30U) +#define GTZC_CFGR1_DTS_Msk (0x01UL << GTZC_CFGR1_DTS_Pos) +#define GTZC_CFGR1_LPTIM2_Pos (31U) +#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) + +/*************** Bits definition for register x=2 (TZSC1) *************/ +#define GTZC_CFGR2_FDCAN1_Pos (0U) +#define GTZC_CFGR2_FDCAN1_Msk (0x01UL << GTZC_CFGR2_FDCAN1_Pos) +#define GTZC_CFGR2_FDCAN2_Pos (1U) +#define GTZC_CFGR2_FDCAN2_Msk (0x01UL << GTZC_CFGR2_FDCAN2_Pos) +#define GTZC_CFGR2_UCPD1_Pos (2U) +#define GTZC_CFGR2_UCPD1_Msk (0x01UL << GTZC_CFGR2_UCPD1_Pos) +#define GTZC_CFGR2_TIM1_Pos (8U) +#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) +#define GTZC_CFGR2_SPI1_Pos (9U) +#define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) +#define GTZC_CFGR2_TIM8_Pos (10U) +#define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos) +#define GTZC_CFGR2_USART1_Pos (11U) +#define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) +#define GTZC_CFGR2_TIM15_Pos (12U) +#define GTZC_CFGR2_TIM15_Msk (0x01UL << GTZC_CFGR2_TIM15_Pos) +#define GTZC_CFGR2_SPI4_Pos (15U) +#define GTZC_CFGR2_SPI4_Msk (0x01UL << GTZC_CFGR2_SPI4_Pos) +#define GTZC_CFGR2_USB_Pos (19U) +#define GTZC_CFGR2_USB_Msk (0x01UL << GTZC_CFGR2_USB_Pos) +#define GTZC_CFGR2_LPUART1_Pos (25U) +#define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) +#define GTZC_CFGR2_I2C3_Pos (26U) +#define GTZC_CFGR2_I2C3_Msk (0x01UL << GTZC_CFGR2_I2C3_Pos) +#define GTZC_CFGR2_LPTIM1_Pos (28U) +#define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) + +/*************** Bits definition for register x=3 (TZSC1) *************/ +#define GTZC_CFGR3_VREFBUF_Pos (1U) +#define GTZC_CFGR3_VREFBUF_Msk (0x01UL << GTZC_CFGR3_VREFBUF_Pos) +#define GTZC_CFGR3_I3C2_Pos (2U) +#define GTZC_CFGR3_I3C2_Msk (0x01UL << GTZC_CFGR3_I3C2_Pos) +#define GTZC_CFGR3_CRC_Pos (8U) +#define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) +#define GTZC_CFGR3_ICACHE_REG_Pos (12U) +#define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_CFGR3_DCACHE1_REG_Pos (13U) +#define GTZC_CFGR3_DCACHE1_REG_Msk (0x01UL << GTZC_CFGR3_DCACHE1_REG_Pos) +#define GTZC_CFGR3_ADC_Pos (14U) +#define GTZC_CFGR3_ADC_Msk (0x01UL << GTZC_CFGR3_ADC_Pos) +#define GTZC_CFGR3_DCMI_PSSI_Pos (15U) +#define GTZC_CFGR3_DCMI_PSSI_Msk (0x01UL << GTZC_CFGR3_DCMI_PSSI_Pos) +#define GTZC_CFGR3_AES_Pos (16U) +#define GTZC_CFGR3_AES_Msk (0x01UL << GTZC_CFGR3_AES_Pos) +#define GTZC_CFGR3_HASH_Pos (17U) +#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) +#define GTZC_CFGR3_RNG_Pos (18U) +#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) +#define GTZC_CFGR3_SAES_Pos (19U) +#define GTZC_CFGR3_SAES_Msk (0x01UL << GTZC_CFGR3_SAES_Pos) +#define GTZC_CFGR3_PKA_Pos (20U) +#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos) +#define GTZC_CFGR3_SDMMC1_Pos (21U) +#define GTZC_CFGR3_SDMMC1_Msk (0x01UL << GTZC_CFGR3_SDMMC1_Pos) +#define GTZC_CFGR3_FMC_REG_Pos (23U) +#define GTZC_CFGR3_FMC_REG_Msk (0x01UL << GTZC_CFGR3_FMC_REG_Pos) +#define GTZC_CFGR3_OCTOSPI1_Pos (24U) +#define GTZC_CFGR3_OCTOSPI1_Msk (0x01UL << GTZC_CFGR3_OCTOSPI1_Pos) +#define GTZC_CFGR3_RAMCFG_Pos (26U) +#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) + +/*************** Bits definition for register x=4 (TZSC1) *************/ +#define GTZC_CFGR4_GPDMA1_Pos (0U) +#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_CFGR4_GPDMA2_Pos (1U) +#define GTZC_CFGR4_GPDMA2_Msk (0x01UL << GTZC_CFGR4_GPDMA2_Pos) +#define GTZC_CFGR4_FLASH_Pos (2U) +#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) +#define GTZC_CFGR4_FLASH_REG_Pos (3U) +#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) + +#define GTZC_CFGR4_OTFDEC1_Pos (4U) +#define GTZC_CFGR4_OTFDEC1_Msk (0x01UL << GTZC_CFGR4_OTFDEC1_Pos) +#define GTZC_CFGR4_SBS_Pos (6U) +#define GTZC_CFGR4_SBS_Msk (0x01UL << GTZC_CFGR4_SBS_Pos) +#define GTZC_CFGR4_RTC_Pos (7U) +#define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) +#define GTZC_CFGR4_TAMP_Pos (8U) +#define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) +#define GTZC_CFGR4_PWR_Pos (9U) +#define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) +#define GTZC_CFGR4_RCC_Pos (10U) +#define GTZC_CFGR4_RCC_Msk (0x01UL << GTZC_CFGR4_RCC_Pos) +#define GTZC_CFGR4_EXTI_Pos (11U) +#define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) +#define GTZC_CFGR4_TZSC_Pos (16U) +#define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) +#define GTZC_CFGR4_TZIC_Pos (17U) +#define GTZC_CFGR4_TZIC_Msk (0x01UL << GTZC_CFGR4_TZIC_Pos) +#define GTZC_CFGR4_OCTOSPI1_MEM_Pos (18U) +#define GTZC_CFGR4_OCTOSPI1_MEM_Msk (0x01UL << GTZC_CFGR4_OCTOSPI1_MEM_Pos) +#define GTZC_CFGR4_FMC_MEM_Pos (19U) +#define GTZC_CFGR4_FMC_MEM_Msk (0x01UL << GTZC_CFGR4_FMC_MEM_Pos) +#define GTZC_CFGR4_BKPSRAM_Pos (20U) +#define GTZC_CFGR4_BKPSRAM_Msk (0x01UL << GTZC_CFGR4_BKPSRAM_Pos) +#define GTZC_CFGR4_SRAM1_Pos (24U) +#define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) +#define GTZC_CFGR4_MPCBB1_REG_Pos (25U) +#define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_CFGR4_SRAM2_Pos (26U) +#define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) +#define GTZC_CFGR4_MPCBB2_REG_Pos (27U) +#define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) +#define GTZC_CFGR4_SRAM3_Pos (28U) +#define GTZC_CFGR4_SRAM3_Msk (0x01UL << GTZC_CFGR4_SRAM3_Pos) +#define GTZC_CFGR4_MPCBB3_REG_Pos (29U) +#define GTZC_CFGR4_MPCBB3_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos) + +/******************* Bits definition for GTZC_TZSC1_SECCFGR1 register ***************/ +#define GTZC_TZSC1_SECCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_SECCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_SECCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_SECCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_SECCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_SECCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_SECCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_SECCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_SECCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_SECCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_SECCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_SECCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_SECCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_SECCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_SECCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_SECCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_SECCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_SECCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_SECCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_SECCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_SECCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_SECCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_SECCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_SECCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_SECCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_SECCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_SECCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_SECCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_SECCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_SECCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_SECCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_SECCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_SECCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_SECCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_SECCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_SECCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_SECCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_SECCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_SECCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/ +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_SECCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_SECCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_SECCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_SECCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_SECCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_SECCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_SECCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_SECCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_SECCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_SECCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_SECCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_SECCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_SECCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_SECCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_SECCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR3 register ***************/ +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_SECCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_SECCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_SECCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_SECCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_SECCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_SECCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_SECCFGR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZSC1_SECCFGR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZSC1_SECCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_SECCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_SECCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_SECCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_SECCFGR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZSC1_SECCFGR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZSC1_SECCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZSC1_SECCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_PRIVCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_PRIVCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_PRIVCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_PRIVCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_PRIVCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_PRIVCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_PRIVCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_PRIVCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_PRIVCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_PRIVCFGR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZSC1_PRIVCFGR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZSC1_PRIVCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_PRIVCFGR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZSC1_PRIVCFGR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZSC1_PRIVCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZSC1_PRIVCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER1 register ***************/ +#define GTZC_TZIC1_IER1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_IER1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_IER1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_IER1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_IER1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_IER1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_IER1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_IER1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_IER1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_IER1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_IER1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_IER1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_IER1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_IER1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_IER1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_IER1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_IER1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_IER1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_IER1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_IER1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_IER1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_IER1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_IER1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_IER1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_IER1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_IER1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_IER1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_IER1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_IER1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_IER1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_IER1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_IER1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_IER1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_IER1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_IER1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_IER1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_IER1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_IER1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_IER1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_IER1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_IER1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_IER1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_IER2 register ***************/ +#define GTZC_TZIC1_IER2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_IER2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_IER2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_IER2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_IER2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_IER2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_IER2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_IER2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_IER2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_IER2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_IER2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_IER2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_IER2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_IER2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_IER2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_IER2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_IER2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_IER2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_IER2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_IER2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_IER2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_IER2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_IER2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_IER3 register ***************/ +#define GTZC_TZIC1_IER3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_IER3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_IER3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_IER3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_IER3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_IER3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_IER3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_IER3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_IER3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_IER3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_IER3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_IER3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_IER3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_IER3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_IER3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZIC1_IER3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZIC1_IER3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_IER3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_IER3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_IER3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_IER3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZIC1_IER3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZIC1_IER3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_IER3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_IER3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_IER3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_IER3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_IER3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_IER3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_IER3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_IER3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_IER3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_TZIC1_IER4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_IER4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_IER4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_IER4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_IER4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_IER4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_IER4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_IER4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_IER4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos +#define GTZC_TZIC1_IER4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk +#define GTZC_TZIC1_IER4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_IER4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_IER4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_IER4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_IER4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_IER4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_IER4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_IER4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_IER4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_IER4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_IER4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_IER4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_IER4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_IER4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_IER4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_IER4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_IER4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_IER4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_IER4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_IER4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_IER4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_IER4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_IER4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_IER4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_IER4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_IER4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_IER4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_IER4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_TZIC_SR1 register **************/ +#define GTZC_TZIC1_SR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_SR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_SR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_SR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_SR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_SR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_SR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_SR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_SR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_SR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_SR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_SR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_SR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_SR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_SR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_SR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_SR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_SR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_SR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_SR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_SR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_SR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_SR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_SR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_SR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_SR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_SR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_SR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_SR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_SR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_SR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_SR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_SR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_SR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_SR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_SR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_SR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_SR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_SR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_SR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_SR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_SR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_SR2 register **************/ +#define GTZC_TZIC1_SR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_SR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_SR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_SR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_SR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_SR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_SR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_SR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_SR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_SR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_SR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_SR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_SR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_SR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_SR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_SR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_SR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_SR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_SR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_SR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_SR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_SR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_SR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_SR3 register **************/ +#define GTZC_TZIC1_SR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_SR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_SR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_SR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_SR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_SR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_SR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_SR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_SR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_SR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_SR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_SR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_SR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_SR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_SR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZIC1_SR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZIC1_SR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_SR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_SR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_SR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_SR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZIC1_SR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZIC1_SR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_SR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_SR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_SR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_SR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_SR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_SR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_SR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_SR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_SR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_SR4 register ***************/ +#define GTZC_TZIC1_SR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_SR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_SR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_SR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_SR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_SR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_SR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_SR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_SR4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos +#define GTZC_TZIC1_SR4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk +#define GTZC_TZIC1_SR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_SR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_SR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_SR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_SR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_SR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_SR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_SR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_SR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_SR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_SR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_SR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_SR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_SR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_SR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_SR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_SR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_SR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_SR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_SR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_SR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_SR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_SR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_SR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_SR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_SR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_SR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_SR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/****************** Bits definition for GTZC_TZIC_FCR1 register ****************/ +#define GTZC_TZIC1_FCR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_FCR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_FCR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_FCR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_FCR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_FCR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_FCR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_FCR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_FCR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_FCR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_FCR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_FCR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_FCR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_FCR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_FCR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_FCR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_FCR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_FCR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_FCR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_FCR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_FCR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_FCR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_FCR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_FCR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_FCR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_FCR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_FCR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_FCR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_FCR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_FCR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_FCR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_FCR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_FCR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_FCR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_FCR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_FCR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_FCR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_FCR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_FCR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_FCR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_FCR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_FCR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_FCR2 register **************/ +#define GTZC_TZIC1_FCR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_FCR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_FCR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_FCR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_FCR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_FCR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_FCR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_FCR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_FCR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_FCR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_FCR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_FCR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_FCR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_FCR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_FCR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_FCR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_FCR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_FCR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_FCR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_FCR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_FCR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_FCR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_FCR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/****************** Bits definition for GTZC_TZIC_FCR3 register ****************/ +#define GTZC_TZIC1_FCR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_FCR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_FCR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_FCR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_FCR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_FCR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_FCR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_FCR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_FCR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_FCR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_FCR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZIC1_FCR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZIC1_FCR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_FCR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_FCR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_FCR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_FCR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZIC1_FCR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZIC1_FCR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_FCR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_FCR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_FCR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_FCR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_FCR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_FCR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_FCR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_FCR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_FCR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_FCR4 register ***************/ +#define GTZC_TZIC1_FCR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_FCR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_FCR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_FCR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_FCR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_FCR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_FCR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_FCR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_FCR4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos +#define GTZC_TZIC1_FCR4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk +#define GTZC_TZIC1_FCR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_FCR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_FCR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_FCR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_FCR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_FCR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_FCR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_FCR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_FCR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_FCR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_FCR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_FCR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_FCR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_FCR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_FCR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_FCR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_FCR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_FCR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_FCR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_FCR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_FCR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_FCR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_FCR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_FCR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_MPCBB_CR register *****************/ +#define GTZC_MPCBB_CR_GLOCK_Pos (0U) +#define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) +#define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CR_SRWILADIS_Pos (31U) +#define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for GTZC_MPCBB_CFGLOCKR1 register ************/ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos (0U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos (1U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos (2U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos (3U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos (4U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos (5U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos (6U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos (7U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos (8U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos (9U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos (10U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos (11U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos (12U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos (13U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos (14U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos (15U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos (16U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos (17U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos (18U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos (19U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos (20U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos (21U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos (22U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos (23U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos (24U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos (25U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos (26U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos (27U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos (28U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos (29U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos (30U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos (31U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) /*!< 0x80000000 */ + + +/******************************************************************************/ +/* */ +/* UCPD */ +/* */ +/******************************************************************************/ +/******************** Bits definition for UCPD_CFG1 register *******************/ +#define UCPD_CFG1_HBITCLKDIV_Pos (0U) +#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */ +#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */ +#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */ +#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */ +#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */ +#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */ +#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */ +#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */ +#define UCPD_CFG1_IFRGAP_Pos (6U) +#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */ +#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */ +#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */ +#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */ +#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */ +#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */ +#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */ +#define UCPD_CFG1_TRANSWIN_Pos (11U) +#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */ +#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */ +#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */ +#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */ +#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */ +#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */ +#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */ +#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U) +#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */ +#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */ +#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */ +#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */ +#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */ +#define UCPD_CFG1_RXORDSETEN_Pos (20U) +#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x1FF00000 */ +#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */ +#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00100000 */ +#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00200000 */ +#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00400000 */ +#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00800000 */ +#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x01000000 */ +#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x02000000 */ +#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x04000000 */ +#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x08000000 */ +#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x10000000 */ +#define UCPD_CFG1_TXDMAEN_Pos (29U) +#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */ +#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define UCPD_CFG1_RXDMAEN_Pos (30U) +#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */ +#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define UCPD_CFG1_UCPDEN_Pos (31U) +#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */ +#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */ + +/******************** Bits definition for UCPD_CFG2 register *******************/ +#define UCPD_CFG2_RXFILTDIS_Pos (0U) +#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */ +#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */ +#define UCPD_CFG2_RXFILT2N3_Pos (1U) +#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */ +#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */ +#define UCPD_CFG2_FORCECLK_Pos (2U) +#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */ +#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */ +#define UCPD_CFG2_WUPEN_Pos (3U) +#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */ +#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define UCPD_CFG2_RXAFILTEN_Pos (8U) +#define UCPD_CFG2_RXAFILTEN_Msk (0x1UL << UCPD_CFG2_RXAFILTEN_Pos) /*!< 0x00000100 */ +#define UCPD_CFG2_RXAFILTEN UCPD_CFG2_RXAFILTEN_Msk /*!< Rx analog filter enable */ + +/******************** Bits definition for UCPD_CFG3 register *******************/ +#define UCPD_CFG3_TRIM_CC1_RD_Pos (0U) +#define UCPD_CFG3_TRIM_CC1_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos) /*!< 0x0000000F */ +#define UCPD_CFG3_TRIM_CC1_RD UCPD_CFG3_TRIM_CC1_RD_Msk /*!< SW trim value for RD resistor (CC1) */ +#define UCPD_CFG3_TRIM_CC1_RP_Pos (9U) +#define UCPD_CFG3_TRIM_CC1_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos) /*!< 0x00001E00 */ +#define UCPD_CFG3_TRIM_CC1_RP UCPD_CFG3_TRIM_CC1_RP_Msk /*!< SW trim value for RP current sources (CC1) */ +#define UCPD_CFG3_TRIM_CC2_RD_Pos (16U) +#define UCPD_CFG3_TRIM_CC2_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos) /*!< 0x000F0000 */ +#define UCPD_CFG3_TRIM_CC2_RD UCPD_CFG3_TRIM_CC2_RD_Msk /*!< SW trim value for RD resistor (CC2) */ +#define UCPD_CFG3_TRIM_CC2_RP_Pos (25U) +#define UCPD_CFG3_TRIM_CC2_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos) /*!< 0x1E000000 */ +#define UCPD_CFG3_TRIM_CC2_RP UCPD_CFG3_TRIM_CC2_RP_Msk /*!< SW trim value for RP current sources (CC2) */ + +/******************** Bits definition for UCPD_CR register ********************/ +#define UCPD_CR_TXMODE_Pos (0U) +#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */ +#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */ +#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */ +#define UCPD_CR_TXSEND_Pos (2U) +#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */ +#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXHRST_Pos (3U) +#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */ +#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */ +#define UCPD_CR_RXMODE_Pos (4U) +#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */ +#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */ +#define UCPD_CR_PHYRXEN_Pos (5U) +#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */ +#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */ +#define UCPD_CR_PHYCCSEL_Pos (6U) +#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */ +#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */ +#define UCPD_CR_ANASUBMODE_Pos (7U) +#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */ +#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */ +#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */ +#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */ +#define UCPD_CR_ANAMODE_Pos (9U) +#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */ +#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */ +#define UCPD_CR_CCENABLE_Pos (10U) +#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */ +#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */ +#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */ +#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */ +#define UCPD_CR_FRSRXEN_Pos (16U) +#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */ +#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */ +#define UCPD_CR_FRSTX_Pos (17U) +#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */ +#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */ +#define UCPD_CR_RDCH_Pos (18U) +#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */ +#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */ +#define UCPD_CR_CC1TCDIS_Pos (20U) +#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */ +#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */ +#define UCPD_CR_CC2TCDIS_Pos (21U) +#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */ +#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */ + +/******************** Bits definition for UCPD_IMR register *******************/ +#define UCPD_IMR_TXISIE_Pos (0U) +#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */ +#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */ +#define UCPD_IMR_TXMSGDISCIE_Pos (1U) +#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */ +#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */ +#define UCPD_IMR_TXMSGSENTIE_Pos (2U) +#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */ +#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */ +#define UCPD_IMR_TXMSGABTIE_Pos (3U) +#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */ +#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */ +#define UCPD_IMR_HRSTDISCIE_Pos (4U) +#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */ +#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */ +#define UCPD_IMR_HRSTSENTIE_Pos (5U) +#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */ +#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */ +#define UCPD_IMR_TXUNDIE_Pos (6U) +#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */ +#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */ +#define UCPD_IMR_RXNEIE_Pos (8U) +#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */ +#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */ +#define UCPD_IMR_RXORDDETIE_Pos (9U) +#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */ +#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */ +#define UCPD_IMR_RXHRSTDETIE_Pos (10U) +#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */ +#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */ +#define UCPD_IMR_RXOVRIE_Pos (11U) +#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */ +#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */ +#define UCPD_IMR_RXMSGENDIE_Pos (12U) +#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */ +#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */ +#define UCPD_IMR_TYPECEVT1IE_Pos (14U) +#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */ +#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */ +#define UCPD_IMR_TYPECEVT2IE_Pos (15U) +#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */ +#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */ +#define UCPD_IMR_FRSEVTIE_Pos (20U) +#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */ +#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */ + +/******************** Bits definition for UCPD_SR register ********************/ +#define UCPD_SR_TXIS_Pos (0U) +#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */ +#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */ +#define UCPD_SR_TXMSGDISC_Pos (1U) +#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */ +#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */ +#define UCPD_SR_TXMSGSENT_Pos (2U) +#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */ +#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */ +#define UCPD_SR_TXMSGABT_Pos (3U) +#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */ +#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */ +#define UCPD_SR_HRSTDISC_Pos (4U) +#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */ +#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */ +#define UCPD_SR_HRSTSENT_Pos (5U) +#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */ +#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */ +#define UCPD_SR_TXUND_Pos (6U) +#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */ +#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */ +#define UCPD_SR_RXNE_Pos (8U) +#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */ +#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */ +#define UCPD_SR_RXORDDET_Pos (9U) +#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */ +#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */ +#define UCPD_SR_RXHRSTDET_Pos (10U) +#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */ +#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */ +#define UCPD_SR_RXOVR_Pos (11U) +#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */ +#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */ +#define UCPD_SR_RXMSGEND_Pos (12U) +#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */ +#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */ +#define UCPD_SR_RXERR_Pos (13U) +#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */ +#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */ +#define UCPD_SR_TYPECEVT1_Pos (14U) +#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */ +#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */ +#define UCPD_SR_TYPECEVT2_Pos (15U) +#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */ +#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U) +#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00030000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */ +#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00010000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00020000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U) +#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x000C0000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/** @addtogroup STM32H5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)|| \ + ((INSTANCE) == ADC2_NS)|| \ + ((INSTANCE) == ADC2_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S)) +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel1_NS) || ((INSTANCE) == GPDMA2_Channel1_S) || \ + ((INSTANCE) == GPDMA2_Channel2_NS) || ((INSTANCE) == GPDMA2_Channel2_S) || \ + ((INSTANCE) == GPDMA2_Channel3_NS) || ((INSTANCE) == GPDMA2_Channel3_S) || \ + ((INSTANCE) == GPDMA2_Channel4_NS) || ((INSTANCE) == GPDMA2_Channel4_S) || \ + ((INSTANCE) == GPDMA2_Channel5_NS) || ((INSTANCE) == GPDMA2_Channel5_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) IS_DMA_ALL_INSTANCE(INSTANCE) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* DTS Instances *******************************/ +#define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS) || ((__INSTANCE__) == DTS_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On H5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On H5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************** I3C Instances *******************************/ +#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S) || \ + ((INSTANCE) == I3C2_NS) || ((INSTANCE) == I3C2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S)) + +/****************************** FDCAN Instances *******************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S) || \ + ((INSTANCE) == FDCAN2_NS) || ((INSTANCE) == FDCAN2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S) || \ + ((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************************** I2S Instances *******************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** CEC Instance *****************************************/ +#define IS_CEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CEC_NS) || ((INSTANCE) == CEC_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* USB DRD FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* USB DRD FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) +/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32H533xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H533xx_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h new file mode 100644 index 00000000..22750f35 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h @@ -0,0 +1,261 @@ +/** + ****************************************************************************** + * @file stm32h5xx.h + * @author MCD Application Team + * @brief CMSIS STM32H5xx Device Peripheral Access Layer Header File. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The STM32H5xx device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_HAL_DRIVER" + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h5xx + * @{ + */ + +#ifndef STM32H5xx_H +#define STM32H5xx_H +#include "math.h" + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32H5) +#define STM32H5 +#endif /* STM32H5 */ + +/* Uncomment the line below according to the target STM32H5 device used in your + application + */ + +#if !defined (STM32H5F5xx) && !defined (STM32H5F4xx) \ + && !defined (STM32H5F4xx) && !defined (STM32H5E4xx) \ + && !defined (STM32H573xx) && !defined (STM32H563xx) \ + && !defined (STM32H562xx) && !defined (STM32H503xx) \ + && !defined (STM32H533xx) && !defined (STM32H523xx) + /* #define STM32H543xx */ /*!< STM32H543xx Devices */ + /* #define STM32H553xx */ /*!< STM32H553xx Devices */ + /* #define STM32H5F5xx */ /*!< STM32H5F5xx Devices */ + /* #define STM32H5F4xx */ /*!< STM32H5F4xx Devices */ + /* #define STM32H5E5xx */ /*!< STM32H5E5xx Devices */ + /* #define STM32H5E4xx */ /*!< STM32H5E4xx Devices */ + /* #define STM32H573xx */ /*!< STM32H573xx Devices */ + /* #define STM32H563xx */ /*!< STM32H563xx Devices */ + /* #define STM32H562xx */ /*!< STM32H562xx Devices */ + /* #define STM32H503xx */ /*!< STM32H503xx Devices */ + /* #define STM32H533xx */ /*!< STM32H533xx Devices */ + /* #define STM32H523xx */ /*!< STM32H523xx Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number 1.4.0 + */ +#define __STM32H5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32H5_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ +#define __STM32H5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32H5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32H5_CMSIS_VERSION ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\ + |(__STM32H5_CMSIS_VERSION_SUB1 << 16U)\ + |(__STM32H5_CMSIS_VERSION_SUB2 << 8U )\ + |(__STM32H5_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32H5F5xx) + #include "stm32h5f5xx.h" +#elif defined(STM32H5F4xx) + #include "stm32h5f4xx.h" +#elif defined(STM32H5E5xx) + #include "stm32h5e5xx.h" +#elif defined(STM32H5E4xx) + #include "stm32h5e4xx.h" +#elif defined(STM32H573xx) + #include "stm32h573xx.h" +#elif defined(STM32H563xx) + #include "stm32h563xx.h" +#elif defined(STM32H562xx) + #include "stm32h562xx.h" +#elif defined(STM32H503xx) + #include "stm32h503xx.h" +#elif defined(STM32H523xx) + #include "stm32h523xx.h" +#elif defined(STM32H533xx) + #include "stm32h533xx.h" +#else + #error "Please select first the target STM32H5xx device used in your application (in stm32h5xx.h file)" +#endif + + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32h5xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32H5xx_H */ +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h new file mode 100644 index 00000000..a7a5a751 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h @@ -0,0 +1,107 @@ +/** + ****************************************************************************** + * @file system_stm32h5xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device System Source File for STM32H5xx devices. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h5xx_system + * @{ + */ + +#ifndef SYSTEM_STM32H5XX_H +#define SYSTEM_STM32H5XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup STM32H5xx_System_Includes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + + +/** @addtogroup STM32H5xx_System_Exported_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + * @brief Update SystemCoreClock variable. + * + * Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +/** + * @brief Update SystemCoreClock variable from secure application and return its value + * when security is implemented in the system (Non-secure callable function). + * + * Returns the SystemCoreClock value with current core Clock retrieved from cpu registers. + */ +extern uint32_t SECURE_SystemCoreClockUpdate(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_STM32H5XX_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/LICENSE.txt b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/LICENSE.txt new file mode 100644 index 00000000..872e82b4 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Device/ST/STM32H5xx/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the Apache-2.0 license shall apply. +You may obtain a copy of the Apache-2.0 at: +https://opensource.org/licenses/Apache-2.0 diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cachel1_armv7.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cachel1_armv7.h new file mode 100644 index 00000000..efb29d88 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cachel1_armv7.h @@ -0,0 +1,441 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.3 + * @date 17. March 2023 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + struct { + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + } locals + #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) + __ALIGNED(__SCB_DCACHE_LINE_SIZE) + #endif + ; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + #if !defined(__OPTIMIZE__) + /* + * For the endless loop issue with no optimization builds. + * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 + * + * The issue only happens when local variables are in stack. If + * local variables are saved in general purpose register, then the function + * is OK. + * + * When local variables are in stack, after disabling the cache, flush the + * local variables cache line for data consistency. + */ + /* Clean and invalidate the local variable cache. */ + #if defined(__ICCARM__) + /* As we can't align the stack to the cache line size, invalidate each of the variables */ + SCB->DCCIMVAC = (uint32_t)&locals.sets; + SCB->DCCIMVAC = (uint32_t)&locals.ways; + SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; + #else + SCB->DCCIMVAC = (uint32_t)&locals; + #endif + __DSB(); + __ISB(); + #endif + + locals.ccsidr = SCB->CCSIDR; + /* clean & invalidate D-Cache */ + locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); + do { + locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); + do { + SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (locals.ways-- != 0U); + } while(locals.sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_armcc.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 00000000..a955d471 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_armclang.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 00000000..69114177 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 00000000..1e255d59 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_compiler.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 00000000..adbf296f --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_gcc.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 00000000..67bda4ef --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_iccarm.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 00000000..65b824b0 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_version.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 00000000..8b4765f1 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_armv81mml.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_armv81mml.h new file mode 100644 index 00000000..94128a1a --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_armv8mbl.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 00000000..932d3d18 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_armv8mml.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 00000000..c119fbf2 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm0.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 00000000..6441ff34 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm0plus.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 00000000..4e7179a6 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm1.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 00000000..76b45697 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm23.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 00000000..55fff995 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm3.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 00000000..74fb87e5 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm33.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 00000000..18a2e6fb --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm35p.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm35p.h new file mode 100644 index 00000000..3843d954 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm35p.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm4.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 00000000..e21cd149 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm55.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm55.h new file mode 100644 index 00000000..faa30ce3 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm55.h @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm7.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 00000000..010506e9 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm85.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm85.h new file mode 100644 index 00000000..60463111 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_cm85.h @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_sc000.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 00000000..dbc755ff --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_sc300.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 00000000..d6662103 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_starmc1.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_starmc1.h new file mode 100644 index 00000000..d86c8d38 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/core_starmc1.h @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/mpu_armv7.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 00000000..d9eedf81 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/mpu_armv8.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 00000000..3de16efc --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/pac_armv81.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/pac_armv81.h new file mode 100644 index 00000000..854b60a2 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/pac_armv81.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/pmu_armv8.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/pmu_armv8.h new file mode 100644 index 00000000..f8f3d893 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/tz_context.h b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 00000000..0d09749f --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/LICENSE.txt b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/LICENSE.txt new file mode 100644 index 00000000..8dada3ed --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h new file mode 100644 index 00000000..97310298 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,4436 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#endif /* STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) +#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI +#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) +#define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) +#endif /* STM32F3 */ + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS || STM32N6 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +#if defined(STM32F7) || defined(STM32WB) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 || STM32WB */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif +#if defined (STM32H7RS) +#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO PWR_SMPS_1V8_SUPPLIES_EXT_VDD_SUPPLIES_LDO +#endif + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +#if defined(STM32H7RS) || defined(STM32N6) +#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0 +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1 +#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig +#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig +#endif /* STM32H7RS || STM32N6 */ + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32U3) || defined (STM32WBA) || defined (STM32H5) || defined (STM32U0) || \ + defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h new file mode 100644 index 00000000..2663df9e --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h @@ -0,0 +1,1005 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H5xx_HAL_H +#define __STM32H5xx_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_conf.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Types HAL Exported Types + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SBS_Exported_Constants SBS Exported Constants + * @{ + */ + +/** @defgroup SBS_FPU_Interrupts FPU Interrupts + * @{ + */ +#define SBS_IT_FPU_IOC SBS_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ +#define SBS_IT_FPU_DZC SBS_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ +#define SBS_IT_FPU_UFC SBS_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ +#define SBS_IT_FPU_OFC SBS_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ +#define SBS_IT_FPU_IDC SBS_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ +#define SBS_IT_FPU_IXC SBS_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ + +/** + * @} + */ + +/** @defgroup SBS_BREAK_CONFIG SBS Break Config + * @{ + */ +#define SBS_BREAK_FLASH_ECC SBS_CFGR2_ECCL /*!< Enable and lock the FLASH ECC double error with TIM1/8/15/16/17 + Break inputs.*/ +#define SBS_BREAK_PVD SBS_CFGR2_PVDL /*!< Enable and lock the PVD connection with TIM1/8/15/16/17 + Break inputs. */ +#define SBS_BREAK_SRAM_ECC SBS_CFGR2_SEL /*!< Enable and lock the SRAM ECC double error signal with + TIM1/8/15/16/17 Break inputs.*/ +#define SBS_BREAK_LOCKUP SBS_CFGR2_CLL /*!< Enable and lock the connection of Cortex-M33 LOCKUP (hardfault) + output to TIM1/8/15/16/17 Break inputs.*/ + +/** + * @} + */ + +#if defined(VREFBUF) +/** @defgroup VREFBUF_VoltageScale VREFBUF Voltage Scale + * @{ + */ +#define VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ + +/** + * @} + */ + +/** @defgroup VREFBUF_HighImpedance VREFBUF High Impedance + * @{ + */ +#define VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to + Voltage reference buffer output */ +#define VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ + +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SBS_FastModePlus_GPIO Fast-mode Plus on GPIO + * @{ + */ + +/** @brief Fast-mode Plus driving capability on a specific GPIO + */ +#define SBS_FASTMODEPLUS_PB6 SBS_PMCR_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ +#define SBS_FASTMODEPLUS_PB7 SBS_PMCR_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ +#define SBS_FASTMODEPLUS_PB8 SBS_PMCR_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ +#if defined(SBS_PMCR_PB9_FMP) +#define SBS_FASTMODEPLUS_PB9 SBS_PMCR_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ +#endif /* SBS_PMCR_PB9_FMP */ + +/** + * @} + */ + +#if defined(SBS_PMCR_ETH_SEL_PHY) +/** @defgroup SBS_Ethernet_Config Ethernet Config + * @{ + */ +#define SBS_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface (MII) or GMII */ +#define SBS_ETH_RMII SBS_PMCR_ETH_SEL_PHY_2 /*!< Select the Reduced Media Independent Interface (RMII) */ + +#define IS_SBS_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SBS_ETH_MII) || \ + ((CONFIG) == SBS_ETH_RMII)) + + +/** + * @} + */ +#endif /* SBS_PMCR_ETH_SEL_PHY */ + +/** @defgroup SBS_Memories_Erase_Flag_Status Memory Erase Flags Status + * @{ + */ +#define SBS_MEMORIES_ERASE_FLAG_IPMEE SBS_MESR_IPMEE /*!< Select the Status of End Of Erase for ICACHE + and PKA RAMs */ +#define SBS_MEMORIES_ERASE_FLAG_MCLR SBS_MESR_MCLR /*!< Select the Status of Erase after Power-on Reset + (SRAM2, BKPRAM, ICACHE, DCACHE, PKA rams) */ + +#define IS_SBS_MEMORIES_ERASE_FLAG(FLAG) (((FLAG) == SBS_MEMORIES_ERASE_FLAG_IPMEE) || \ + ((FLAG) == SBS_MEMORIES_ERASE_FLAG_MCLR)) + +/** + * @} + */ + +/** @defgroup SBS_IOCompenstionCell_Config IOCompenstionCell Config + * @{ + */ +#define SBS_VDD_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */ +#define SBS_VDD_REGISTER_CODE SBS_CCCSR_CS1 /*!< Code from the SBS compensation cell code register */ + +#define IS_SBS_VDD_CODE_SELECT(SELECT) (((SELECT) == SBS_VDD_CELL_CODE)|| \ + ((SELECT) == SBS_VDD_REGISTER_CODE)) + +#define SBS_VDDIO_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */ +#define SBS_VDDIO_REGISTER_CODE SBS_CCCSR_CS2 /*!< Code from the SBS compensation cell code register */ + +#define IS_SBS_VDDIO_CODE_SELECT(SELECT) (((SELECT) == SBS_VDDIO_CELL_CODE)|| \ + ((SELECT) == SBS_VDDIO_REGISTER_CODE)) + +#define IS_SBS_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL)) + +/** + * @} + */ + +#if defined(SBS_EPOCHSELCR_EPOCH_SEL) +/** @defgroup SBS_EPOCH_Selection EPOCH Selection + * @{ + */ +#define SBS_EPOCH_SEL_NONSECURE 0x0UL /*!< EPOCH non secure selected */ +#define SBS_EPOCH_SEL_SECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH secure selected */ +#define SBS_EPOCH_SEL_PUFCHECK SBS_EPOCHSELCR_EPOCH_SEL_1 /*!< EPOCH all zeros for PUF integrity check */ + +#define IS_SBS_EPOCH_SELECTION(SELECT) (((SELECT) == SBS_EPOCH_SEL_SECURE) || \ + ((SELECT) == SBS_EPOCH_SEL_NONSECURE) || \ + ((SELECT) == SBS_EPOCH_SEL_PUFCHECK)) +/** + * @} + */ +#endif /* SBS_EPOCHSELCR_EPOCH_SEL */ + +#if defined(SBS_NEXTHDPLCR_NEXTHDPL) +/** @defgroup SBS_NextHDPL_Selection Next HDPL Selection + * @{ + */ +#define SBS_OBKHDPL_INCR_0 0x00U /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define SBS_OBKHDPL_INCR_1 SBS_NEXTHDPLCR_NEXTHDPL_0 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define SBS_OBKHDPL_INCR_2 SBS_NEXTHDPLCR_NEXTHDPL_1 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define SBS_OBKHDPL_INCR_3 SBS_NEXTHDPLCR_NEXTHDPL /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +/** + * @} + */ +#endif /* SBS_NEXTHDPLCR_NEXTHDPL */ + +/** @defgroup SBS_HDPL_Value HDPL Value + * @{ + */ +#define SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */ +#define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 1 */ +#define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 2 */ +#define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 3 */ +/** + * @} + */ + +#if defined(SBS_DBGCR_DBG_AUTH_SEC) +/** @defgroup SBS_DEBUG_SEC_Value Debug sec Value + * @{ + */ +#define SBS_DEBUG_SEC_NSEC 0x000000B4U /*!< Debug opening for secure and non-secure */ +#define SBS_DEBUG_NSEC 0x0000003CU /*!< Debug opening for non-secure only */ +/** + * @} + */ +#endif /* SBS_DBGCR_DBG_AUTH_SEC */ + +/** @defgroup SBS_Lock_items SBS Lock items + * @brief SBS items to set lock on + * @{ + */ +#define SBS_MPU_NSEC SBS_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or + non-secure only) */ +#define SBS_VTOR_NSEC SBS_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or + non-secure only) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SBS_SAU (SBS_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ +#define SBS_MPU_SEC (SBS_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) + */ +#define SBS_VTOR_AIRCR_SEC (SBS_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure + code only) */ +#define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC|SBS_SAU|SBS_MPU_SEC|SBS_VTOR_AIRCR_SEC) /*!< All */ +#else +#define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup SBS_Attributes_items SBS Attributes items + * @brief SBS items to configure secure or non-secure attributes on + * @{ + */ +#define SBS_CLK SBS_SECCFGR_SBSSEC /*!< SBS clock control */ +#define SBS_CLASSB SBS_SECCFGR_CLASSBSEC /*!< Class B */ +#define SBS_FPU SBS_SECCFGR_FPUSEC /*!< FPU */ +#define SBS_ALL (SBS_CLK | SBS_CLASSB | SBS_FPU) /*!< All */ +/** + * @} + */ + +/** @defgroup SBS_attributes SBS attributes + * @brief SBS secure or non-secure attributes + * @{ + */ +#define SBS_SEC 0x00000001U /*!< Secure attribute */ +#define SBS_NSEC 0x00000000U /*!< Non-secure attribute */ +/** + * @} + */ + +#if defined(SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE) +/** @defgroup SBS_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current + * @{ + */ + +/** @brief High-speed (HS) transmitter preemphasis current control + */ +#define SBS_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ +#define SBS_OTG_HS_PHY_PREEMP_1X SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ +#define SBS_OTG_HS_PHY_PREEMP_2X SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ +#define SBS_OTG_HS_PHY_PREEMP_3X (SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ + +/** + * @} + */ +#endif /* SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */ + +#if defined(SBS_OTGHSPHYTUNER2_SQRXTUNE) +/** @defgroup SBS_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold + * @{ + */ + +/** @brief Squelch threshold adjustment + */ +#define SBS_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ +#define SBS_OTG_HS_PHY_SQUELCH_0PERCENT (SBS_OTGHSPHYTUNER2_SQRXTUNE_0 | SBS_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ + +/** + * @} + */ +#endif /* SBS_OTGHSPHYTUNER2_SQRXTUNE */ + +#if defined(SBS_OTGHSPHYTUNER2_COMPDISTUNE) +/** @defgroup SBS_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold + * @{ + */ + +/** @brief Disconnect threshold adjustment + */ +#define SBS_OTG_HS_PHY_DISCONNECT_5_9PERCENT SBS_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ +#define SBS_OTG_HS_PHY_DISCONNECT_0PERCENT SBS_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ + +/** + * @} + */ + +#endif /* SBS_OTGHSPHYTUNER2_COMPDISTUNE */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) +#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) +#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) +#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) +#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM12_STOP) +#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM12_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM12_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM12_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM13_STOP) +#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM13_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM13_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM13_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_TIM14_STOP) +#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM14_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM14_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_TIM14_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) +#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) +#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ + +#if defined(DBGMCU_APB1FZR1_DBG_I3C1_STOP) +#define __HAL_DBGMCU_FREEZE_I3C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP) +#define __HAL_DBGMCU_UNFREEZE_I3C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP) +#endif /* DBGMCU_APB1FZR1_DBG_I3C1_STOP */ + +#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) +#endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */ + +#if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) +#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) +#endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */ + +#if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP) +#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) +#endif /* DBGMCU_APB2FZR_DBG_TIM8_STOP */ + +#if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP) +#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) +#endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */ + +#if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) +#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) +#endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */ + +#if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) +#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) +#endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP) +#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) +#endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_I2C4_STOP) +#define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C4_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C4_STOP) +#endif /* DBGMCU_APB3FZR_DBG_I2C4_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_I3C2_STOP) +#define __HAL_DBGMCU_FREEZE_I3C2() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I3C2_STOP) +#define __HAL_DBGMCU_UNFREEZE_I3C2() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I3C2_STOP) +#endif /* DBGMCU_APB3FZR_DBG_I3C2_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) +#endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) +#endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) +#endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_LPTIM5_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM5_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM5_STOP) +#endif /* DBGMCU_APB3FZR_DBG_LPTIM5_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_LPTIM6_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM6() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM6_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM6() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM6_STOP) +#endif /* DBGMCU_APB3FZR_DBG_LPTIM6_STOP */ + +#if defined(DBGMCU_APB3FZR_DBG_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) +#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) +#endif /* DBGMCU_APB3FZR_DBG_RTC_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP */ +/** + * @} + */ + +/** @defgroup SBS_Exported_Macros SBS Exported Macros + * @{ + */ + +/** @brief Floating Point Unit interrupt enable/disable macros + * @param __INTERRUPT__: This parameter can be a value of @ref SBS_FPU_Interrupts + */ +#define __HAL_SBS_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__)));\ + SET_BIT(SBS->FPUIMR, (__INTERRUPT__));\ + }while(0) + +#define __HAL_SBS_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__)));\ + CLEAR_BIT(SBS->FPUIMR, (__INTERRUPT__));\ + }while(0) + +/** @brief SBS Break ECC lock. + * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SBS_BREAK_ECC_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_ECCL) + +/** @brief SBS Break Cortex-M33 Lockup lock. + * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SBS_BREAK_LOCKUP_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_CLL) + +/** @brief SBS Break PVD lock. + * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] + * in the PWR_CR2 register. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SBS_BREAK_PVD_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_PVDL) + +/** @brief SBS Break SRAM double ECC lock. + * Enable and lock the connection of SRAM double ECC error to TIM1/8/15/16/17 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SBS_BREAK_SRAM_ECC_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_SEL) + +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__: This parameter can be a value of : + * @arg @ref SBS_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 + * @arg @ref SBS_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 + * @arg @ref SBS_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 + * @arg @ref SBS_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 + */ +#define __HAL_SBS_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SBS_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SBS->PMCR, (__FASTMODEPLUS__));\ + }while(0) + +#define __HAL_SBS_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SBS_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SBS->PMCR, (__FASTMODEPLUS__));\ + }while(0) + +/** @brief Check SBS Memories Erase Status Flags. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref SBS_MEMORIES_ERASE_FLAG_IPMEE Status of End Of Erase for ICACHE and PKA RAMs + * @arg @ref SBS_MEMORIES_ERASE_FLAG_MCLR Status of Erase after Power-on Reset ((SRAM2, BKPRAM, + * ICACHE, DCACHE, PKA RAMs) + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SBS_GET_MEMORIES_ERASE_STATUS(__FLAG__) ((((SBS->MESR) & (__FLAG__))!= 0) ? 1 : 0) + +/** @brief Clear SBS Memories Erase Status Flags. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref SBS_MEMORIES_ERASE_FLAG_IPMEE Status of End Of Erase for ICACHE and PKA RAMs + * @arg @ref SBS_MEMORIES_ERASE_FLAG_MCLR Status of Erase after Power-on Reset ((SRAM2, BKPRAM, + * ICACHE, DCACHE, PKA RAMs) + */ +#define __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS(__FLAG__) do {assert_param(IS_SBS_MEMORIES_ERASE_FLAG((__FLAG__)));\ + WRITE_REG(SBS->MESR, (__FLAG__));\ + }while(0) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup SBS_Private_Macros SBS Private Macros + * @{ + */ + +#define IS_SBS_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SBS_IT_FPU_IOC) == SBS_IT_FPU_IOC) || \ + (((__INTERRUPT__) & SBS_IT_FPU_DZC) == SBS_IT_FPU_DZC) || \ + (((__INTERRUPT__) & SBS_IT_FPU_UFC) == SBS_IT_FPU_UFC) || \ + (((__INTERRUPT__) & SBS_IT_FPU_OFC) == SBS_IT_FPU_OFC) || \ + (((__INTERRUPT__) & SBS_IT_FPU_IDC) == SBS_IT_FPU_IDC) || \ + (((__INTERRUPT__) & SBS_IT_FPU_IXC) == SBS_IT_FPU_IXC)) + +#define IS_SBS_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SBS_BREAK_FLASH_ECC) || \ + ((__CONFIG__) == SBS_BREAK_PVD) || \ + ((__CONFIG__) == SBS_BREAK_SRAM_ECC) || \ + ((__CONFIG__) == SBS_BREAK_LOCKUP)) + +#if defined(VREFBUF) +#define IS_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == VREFBUF_VOLTAGE_SCALE0) || \ + ((__SCALE__) == VREFBUF_VOLTAGE_SCALE1) || \ + ((__SCALE__) == VREFBUF_VOLTAGE_SCALE2) || \ + ((__SCALE__) == VREFBUF_VOLTAGE_SCALE3)) + +#define IS_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ + ((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_ENABLE)) + +#define IS_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) +#endif /* VREFBUF*/ + +#if defined(SBS_FASTMODEPLUS_PB9) +#define IS_SBS_FASTMODEPLUS(__PIN__) ((((__PIN__) & SBS_FASTMODEPLUS_PB6) == SBS_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SBS_FASTMODEPLUS_PB7) == SBS_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SBS_FASTMODEPLUS_PB9) == SBS_FASTMODEPLUS_PB9)) +#else +#define IS_SBS_FASTMODEPLUS(__PIN__) ((((__PIN__) & SBS_FASTMODEPLUS_PB6) == SBS_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SBS_FASTMODEPLUS_PB7) == SBS_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8)) +#endif /* SBS_FASTMODEPLUS_PB9 */ + +#define IS_SBS_HDPL(__LEVEL__) (((__LEVEL__) == SBS_HDPL_VALUE_0) || ((__LEVEL__) == SBS_HDPL_VALUE_1) || \ + ((__LEVEL__) == SBS_HDPL_VALUE_2) || ((__LEVEL__) == SBS_HDPL_VALUE_3)) + +#define IS_SBS_OBKHDPL_SELECTION(__SELECT__) (((__SELECT__) == SBS_OBKHDPL_INCR_0) || \ + ((__SELECT__) == SBS_OBKHDPL_INCR_1) || \ + ((__SELECT__) == SBS_OBKHDPL_INCR_2) || \ + ((__SELECT__) == SBS_OBKHDPL_INCR_3)) + +#define IS_SBS_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SBS_CLK) == SBS_CLK) || \ + (((__ITEM__) & SBS_CLASSB) == SBS_CLASSB) || \ + (((__ITEM__) & SBS_FPU) == SBS_FPU) || \ + (((__ITEM__) & ~(SBS_ALL)) == 0U)) + +#define IS_SBS_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SBS_SEC) ||\ + ((__ATTRIBUTES__) == SBS_NSEC)) + +#if defined(SBS_OTGHSPHYTUNER2_COMPDISTUNE) +#define IS_SBS_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SBS_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \ + ((__VALUE__) == SBS_OTG_HS_PHY_DISCONNECT_0PERCENT)) +#endif /* SBS_OTGHSPHYTUNER2_COMPDISTUNE*/ +#if defined(SBS_OTGHSPHYTUNER2_SQRXTUNE) +#define IS_SBS_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SBS_OTG_HS_PHY_SQUELCH_0PERCENT) || \ + ((__VALUE__) == SBS_OTG_HS_PHY_SQUELCH_15PERCENT)) +#endif /* SBS_OTGHSPHYTUNER2_SQRXTUNE */ + +#if defined(SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE) +#define IS_SBS_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SBS_OTG_HS_PHY_PREEMP_DISABLED) || \ + ((__VALUE__) == SBS_OTG_HS_PHY_PREEMP_1X) || \ + ((__VALUE__) == SBS_OTG_HS_PHY_PREEMP_2X) || \ + ((__VALUE__) == SBS_OTG_HS_PHY_PREEMP_3X)) +#endif /* SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +#define IS_SBS_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SBS_MPU_NSEC) == SBS_MPU_NSEC) || \ + (((__ITEM__) & SBS_VTOR_NSEC) == SBS_VTOR_NSEC) || \ + (((__ITEM__) & SBS_SAU) == SBS_SAU) || \ + (((__ITEM__) & SBS_MPU_SEC) == SBS_MPU_SEC) || \ + (((__ITEM__) & SBS_VTOR_AIRCR_SEC) == SBS_VTOR_AIRCR_SEC) || \ + (((__ITEM__) & ~(SBS_LOCK_ALL)) == 0U)) + +#else + +#define IS_SBS_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SBS_MPU_NSEC) == SBS_MPU_NSEC) || \ + (((__ITEM__) & SBS_VTOR_NSEC) == SBS_VTOR_NSEC) || \ + (((__ITEM__) & ~(SBS_LOCK_ALL)) == 0U)) + + +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group3 + * @{ + */ + +/* DBGMCU Peripheral Control functions *****************************************/ +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group4 + * @{ + */ + +/* VREFBUF Control functions ****************************************************/ +#if defined(VREFBUF) +void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); +void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode); +void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); +HAL_StatusTypeDef HAL_EnableVREFBUF(void); +void HAL_DisableVREFBUF(void); +#endif /* VREFBUF */ + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group5 + * @{ + */ + +/* SBS System Configuration functions *******************************************/ +void HAL_SBS_ETHInterfaceSelect(uint32_t SBS_ETHInterface); +void HAL_SBS_EnableVddIO1CompensationCell(void); +void HAL_SBS_DisableVddIO1CompensationCell(void); +void HAL_SBS_EnableVddIO2CompensationCell(void); +void HAL_SBS_DisableVddIO2CompensationCell(void); +void HAL_SBS_VDDCompensationCodeSelect(uint32_t SBS_CompCode); +void HAL_SBS_VDDIOCompensationCodeSelect(uint32_t SBS_CompCode); +uint32_t HAL_SBS_GetVddIO1CompensationCellReadyFlag(void); +uint32_t HAL_SBS_GetVddIO2CompensationCellReadyFlag(void); +void HAL_SBS_VDDCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode); +void HAL_SBS_VDDIOCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode); +uint32_t HAL_SBS_GetNMOSVddCompensationValue(void); +uint32_t HAL_SBS_GetPMOSVddCompensationValue(void); +uint32_t HAL_SBS_GetNMOSVddIO2CompensationValue(void); +uint32_t HAL_SBS_GetPMOSVddIO2CompensationValue(void); +void HAL_SBS_FLASH_EnableECCNMI(void); +void HAL_SBS_FLASH_DisableECCNMI(void); +uint32_t HAL_SBS_FLASH_ECCNMI_IsDisabled(void); +void HAL_SBS_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); +uint32_t HAL_SBS_GetOTGPHYDisconnectThreshold(void); +void HAL_SBS_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); +uint32_t HAL_SBS_GetOTGPHYSquelchThreshold(void); +void HAL_SBS_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); +uint32_t HAL_SBS_GetOTGPHYPreemphasisCurrent(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group6 + * @{ + */ + +/* SBS Boot control functions ***************************************************/ +void HAL_SBS_IncrementHDPLValue(void); +uint32_t HAL_SBS_GetHDPLValue(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group7 + * @{ + */ + +/* SBS Hardware secure storage control functions ********************************/ +void HAL_SBS_EPOCHSelection(uint32_t Epoch_Selection); +uint32_t HAL_SBS_GetEPOCHSelection(void); +void HAL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value); +uint32_t HAL_SBS_GetOBKHDPL(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group8 + * @{ + */ + +/* SBS Debug control functions ***************************************************/ +void HAL_SBS_OpenAccessPort(void); +void HAL_SBS_OpenDebug(void); +HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level); +uint32_t HAL_SBS_GetDebugLevel(void); +void HAL_SBS_LockDebugConfig(void); +void HAL_SBS_ConfigDebugSecurity(uint32_t Security); +uint32_t HAL_SBS_GetDebugSecurity(void); + +/** + * @} + */ + + +/** @addtogroup HAL_Exported_Functions_Group9 + * @{ + */ + +/* SBS Lock functions ********************************************/ +void HAL_SBS_Lock(uint32_t Item); +HAL_StatusTypeDef HAL_SBS_GetLock(uint32_t *pItem); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group10 + * @{ + */ + +/* SBS Attributes functions ********************************************/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +void HAL_SBS_ConfigAttributes(uint32_t Item, uint32_t Attributes); +HAL_StatusTypeDef HAL_SBS_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32H5xx_HAL_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h new file mode 100644 index 00000000..152fb210 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h @@ -0,0 +1,429 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H5xx_HAL_CORTEX_H +#define __STM32H5xx_HAL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types CORTEX Exported Types + * @{ + */ + +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the index of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ + uint8_t AttributesIndex; /*!< Specifies the memory attributes index. + This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter + can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ +} MPU_Region_InitTypeDef; +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes + * Initialization Structure Definition + * @{ + */ +typedef struct +{ + uint8_t Number; /*!< Specifies the number of the memory attributes to configure. + This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ + + uint8_t Attributes; /*!< Specifies the memory attributes value. Attributes This parameter + can be a combination of @ref CORTEX_MPU_Attributes */ + +} MPU_Attributes_InitTypeDef; +/** + * @} + */ + + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 0x7U /*!< 0 bit for pre-emption priority, + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x6U /*!< 1 bit for pre-emption priority, + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x5U /*!< 2 bits for pre-emption priority, + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x4U /*!< 3 bits for pre-emption priority, + 1 bit for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x3U /*!< 4 bits for pre-emption priority, + 0 bit for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x0U /*!< AHB clock divided by 8 selected as SysTick clock source */ +#define SYSTICK_CLKSOURCE_LSI 0x1U /*!< LSI clock selected as SysTick clock source */ +#define SYSTICK_CLKSOURCE_LSE 0x2U /*!< LSE clock selected as SysTick clock source */ +#define SYSTICK_CLKSOURCE_HCLK 0x4U /*!< AHB clock selected as SysTick clock source */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE 1U /*!< Enable region */ +#define MPU_REGION_DISABLE 0U /*!< Disable region */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */ +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */ +#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */ +#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */ +#define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */ +#define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */ +#define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 0U /*!< MPU region number 0 */ +#define MPU_REGION_NUMBER1 1U /*!< MPU region number 1 */ +#define MPU_REGION_NUMBER2 2U /*!< MPU region number 2 */ +#define MPU_REGION_NUMBER3 3U /*!< MPU region number 3 */ +#define MPU_REGION_NUMBER4 4U /*!< MPU region number 4 */ +#define MPU_REGION_NUMBER5 5U /*!< MPU region number 5 */ +#define MPU_REGION_NUMBER6 6U /*!< MPU region number 6 */ +#define MPU_REGION_NUMBER7 7U /*!< MPU region number 7 */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define MPU_REGION_NUMBER8 8U /*!< MPU region number 8 */ +#define MPU_REGION_NUMBER9 9U /*!< MPU region number 9 */ +#define MPU_REGION_NUMBER10 10U /*!< MPU region number 10 */ +#define MPU_REGION_NUMBER11 11U /*!< MPU region number 11 */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number + * @{ + */ +#define MPU_ATTRIBUTES_NUMBER0 0U /*!< MPU attribute number 0 */ +#define MPU_ATTRIBUTES_NUMBER1 1U /*!< MPU attribute number 1 */ +#define MPU_ATTRIBUTES_NUMBER2 2U /*!< MPU attribute number 2 */ +#define MPU_ATTRIBUTES_NUMBER3 3U /*!< MPU attribute number 3 */ +#define MPU_ATTRIBUTES_NUMBER4 4U /*!< MPU attribute number 4 */ +#define MPU_ATTRIBUTES_NUMBER5 5U /*!< MPU attribute number 5 */ +#define MPU_ATTRIBUTES_NUMBER6 6U /*!< MPU attribute number 6 */ +#define MPU_ATTRIBUTES_NUMBER7 7U /*!< MPU attribute number 7 */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes + * @{ + */ +/* Device memory attributes */ +#define MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* To set with INNER_OUTER() macro for both inner/outer cache attributes */ + +/* Non-cacheable memory attribute */ +#define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */ +#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */ +/* - transient mode attribute */ +#define MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */ +#define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */ +/* - allocation attribute */ +#define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */ +#define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */ +#define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */ +#define MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate. */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ +#define OUTER(__ATTR__) ((__ATTR__) << 4U) +#define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_Exported_Functions_Group1 NVIC functions + * @brief NVIC functions + * @{ + */ +/* NVIC functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, + uint32_t *const pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 SYSTICK functions + * @brief SYSTICK functions + * @{ + */ +/* SYSTICK functions ***********************************************/ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +uint32_t HAL_SYSTICK_GetCLKSourceConfig(void); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group3 MPU functions + * @brief MPU functions + * @{ + */ +/* MPU functions ***********************************************/ +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit); +void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* MPU_NS Control functions ***********************************************/ +void HAL_MPU_Enable_NS(uint32_t MPU_Control); +void HAL_MPU_Disable_NS(void); +void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber); +void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit); +void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_MPU_INSTANCE(INSTANCE) (((INSTANCE) == MPU) || ((INSTANCE) == MPU_NS)) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_ALL_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_ALL_RO)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7) || \ + ((NUMBER) == MPU_REGION_NUMBER8) || \ + ((NUMBER) == MPU_REGION_NUMBER9) || \ + ((NUMBER) == MPU_REGION_NUMBER10)|| \ + ((NUMBER) == MPU_REGION_NUMBER11)) + +#define IS_MPU_REGION_NUMBER_NS(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) +#else +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H5xx_HAL_CORTEX_H */ + + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h new file mode 100644 index 00000000..f05f54ec --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h @@ -0,0 +1,232 @@ +/** + ********************************************************************************************************************** + * @file stm32h5xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef __STM32H5xx_HAL_DEF +#define __STM32H5xx_HAL_DEF + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#include +#endif /* __ARM_FEATURE_CMSE */ + +#include "stm32h5xx.h" +#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ +#include +#include + +/* Exported types ----------------------------------------------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00, + HAL_LOCKED = 0x01 +} HAL_LockTypeDef; + +/* Exported macros ---------------------------------------------------------------------------------------------------*/ + +#define HAL_MAX_DELAY 0xFFFFFFFFU +#define ARMCC_MIN_VERSION 6010050 + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +#if !defined(UNUSED) +#define UNUSED(x) ((void)(x)) +#endif /* UNUSED */ + +/** @brief Reset the Handle's State field. + * @param __HANDLE__: specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1) +/* Reserved for future use */ +#error " USE_RTOS should be 0 in the current HAL release " +#else +#define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + +#if defined ( __GNUC__ ) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION) +#ifndef __weak +#define __weak __WEAK +#endif /* __weak */ +#ifndef __packed +#define __packed __PACKED +#endif /* __packed */ +#endif + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" + must be used instead */ +#if defined (__GNUC__) /* GNU Compiler */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION) +#ifndef __ALIGN_END +#define __ALIGN_END __ALIGNED(4) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#else +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#if defined (__CC_ARM) /* ARM Compiler */ +#define __ALIGN_BEGIN __align(4) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __ALIGN_BEGIN +#endif /* __CC_ARM */ +#endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ +#if defined (__GNUC__) /* GNU Compiler */ +#define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION) +#define ALIGN_32BYTES(buf) __ALIGNED(32) buf +#elif defined (__CC_ARM) /* ARM Compiler */ +#define ALIGN_32BYTES(buf) __align(32) buf +#endif /* __GNUC__ */ + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) + +/* ARM Compiler + + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC HAL_StatusTypeDef + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc HAL_StatusTypeDef + +#elif defined ( __GNUC__ ) +/* GNU Compiler + + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) + +#endif /* defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) */ + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) || \ + defined ( __GNUC__ ) +/* ARM & GNUCompiler + +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif /* ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) || defined ( __GNUC__ ) */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ___STM32H5xx_HAL_DEF */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h new file mode 100644 index 00000000..804dc0bb --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h @@ -0,0 +1,1223 @@ +/** + ********************************************************************************************************************** + * @file stm32h5xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32H5xx_HAL_DMA_H +#define STM32H5xx_HAL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + + +/* Exported types ----------------------------------------------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Transfer Configuration Structure definition. + */ +typedef struct +{ + uint32_t Request; /*!< Specifies the DMA channel request. + This parameter can be a value of @ref DMA_Request_Selection */ + + uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel. + Block Hardware request feature can be used only with dedicated peripherals. + This parameter can be a value of @ref DMA_Block_Request */ + + uint32_t Direction; /*!< Specifies the transfer direction for DMA channel. + This parameter can be a value of @ref DMA_Transfer_Direction */ + + uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel. + This parameter can be a value of @ref DMA_Source_Increment_Mode */ + + uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel. + This parameter can be a value of @ref DMA_Destination_Increment_Mode */ + + uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel. + This parameter can be a value of @ref DMA_Source_Data_Width */ + + uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel. + This parameter can be a value of @ref DMA_Destination_Data_Width */ + + uint32_t Priority; /*!< Specifies the priority level for the DMA channel. + This parameter can be a value of @ref DMA_Priority_Level */ + + uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA + channel. + This parameter can be a value between 1 and 64 */ + + uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the + DMA channel. + This parameter can be a value between 1 and 64 */ + + uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports. + This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */ + + uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Event_Mode */ + + uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Mode */ + +} DMA_InitTypeDef; + +/** + * @brief DMA Linked-List Configuration Structure Definition. + */ +typedef struct +{ + uint32_t Priority; /*!< Specifies the priority level for the DMA channel. + This parameter can be a value of @ref DMA_Priority_Level */ + + uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel. + This parameter can be a value of @ref DMAEx_Link_Step_Mode */ + + uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel. + This parameter can be a value of @ref DMAEx_Link_Allocated_Port */ + + uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Event_Mode */ + + uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel. + This parameter can be a value of @ref DMAEx_LinkedList_Mode */ + +} DMA_InitLinkedListTypeDef; + +/** + * @brief HAL DMA State Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ + HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */ + +} HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Level Complete Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */ + +} HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callbacks IDs Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */ + HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */ + HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */ + +} HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */ + + DMA_InitTypeDef Init; /*!< DMA channel init parameters */ + + DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + uint32_t Mode; /*!< DMA transfer mode */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + __IO uint32_t ErrorCode; /*!< DMA error code */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */ + + void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ + + void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */ + + struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */ + +} DMA_HandleTypeDef; +/** + * @} + */ + + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Codes DMA Error Codes + * @brief DMA Error Codes + * @{ + */ +#define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */ +#define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */ +#define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */ +#define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */ +#define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */ +#define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */ +#define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */ +#define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */ +#define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition + * @brief DMA Interrupt Enable Definition + * @{ + */ +#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */ +#define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */ +#define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */ +#define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */ +#define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */ +#define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */ +/** + * @} + */ + +/** @defgroup DMA_Flag_Definition DMA Flag Definition + * @brief DMA Flag Definition + * @{ + */ +#define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */ +#define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */ +#define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */ +#define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */ +#define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */ +#define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */ +#define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */ +#define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */ +/** + * @} + */ + +/** @defgroup DMA_Request_Selection DMA Request Selection + * @brief DMA Request Selection + * @{ + */ +/* GPDMA1 requests */ +#define GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */ +#if defined (ADC2) +#define GPDMA1_REQUEST_ADC2 1U /*!< GPDMA1 HW request is ADC2 */ +#endif /* ADC2 */ +#define GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW request is DAC1_CH1 */ +#define GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW request is DAC1_CH2 */ +#define GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW request is TIM6_UP */ +#define GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW request is TIM7_UP */ +#define GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW request is SPI1_RX */ +#define GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW request is SPI1_TX */ +#define GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW request is SPI2_RX */ +#define GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW request is SPI2_TX */ +#define GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW request is SPI3_RX */ +#define GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW request is SPI3_TX */ +#define GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW request is I2C1_RX */ +#define GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW request is I2C1_TX */ +#define GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW request is I2C2_RX */ +#define GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW request is I2C2_TX */ +#if defined (I2C3) +#define GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW request is I2C3_RX */ +#define GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW request is I2C3_TX */ +#endif /* I2C3 */ +#define GPDMA1_REQUEST_USART1_RX 21U /*!< GPDMA1 HW request is USART1_RX */ +#define GPDMA1_REQUEST_USART1_TX 22U /*!< GPDMA1 HW request is USART1_TX */ +#define GPDMA1_REQUEST_USART2_RX 23U /*!< GPDMA1 HW request is USART2_RX */ +#define GPDMA1_REQUEST_USART2_TX 24U /*!< GPDMA1 HW request is USART2_TX */ +#define GPDMA1_REQUEST_USART3_RX 25U /*!< GPDMA1 HW request is USART3_RX */ +#define GPDMA1_REQUEST_USART3_TX 26U /*!< GPDMA1 HW request is USART3_TX */ +#if defined (UART4) +#define GPDMA1_REQUEST_UART4_RX 27U /*!< GPDMA1 HW request is UART4_RX */ +#define GPDMA1_REQUEST_UART4_TX 28U /*!< GPDMA1 HW request is UART4_TX */ +#endif /* UART4 */ +#if defined (UART5) +#define GPDMA1_REQUEST_UART5_RX 29U /*!< GPDMA1 HW request is UART5_RX */ +#define GPDMA1_REQUEST_UART5_TX 30U /*!< GPDMA1 HW request is UART5_TX */ +#endif /* UART5 */ +#if defined (USART6) +#define GPDMA1_REQUEST_USART6_RX 31U /*!< GPDMA1 HW request is USART6_RX */ +#define GPDMA1_REQUEST_USART6_TX 32U /*!< GPDMA1 HW request is USART6_TX */ +#endif /* USART6 */ +#if defined (UART7) +#define GPDMA1_REQUEST_UART7_RX 33U /*!< GPDMA1 HW request is UART7_RX */ +#define GPDMA1_REQUEST_UART7_TX 34U /*!< GPDMA1 HW request is UART7_TX */ +#endif /* UART7 */ +#if defined (UART8) +#define GPDMA1_REQUEST_UART8_RX 35U /*!< GPDMA1 HW request is UART8_RX */ +#define GPDMA1_REQUEST_UART8_TX 36U /*!< GPDMA1 HW request is UART8_TX */ +#endif /* UART8 */ +#if defined (UART9) +#define GPDMA1_REQUEST_UART9_RX 37U /*!< GPDMA1 HW request is UART9_RX */ +#define GPDMA1_REQUEST_UART9_TX 38U /*!< GPDMA1 HW request is UART9_TX */ +#endif /* UART9 */ +#if defined (USART10) +#define GPDMA1_REQUEST_USART10_RX 39U /*!< GPDMA1 HW request is USART10_RX */ +#define GPDMA1_REQUEST_USART10_TX 40U /*!< GPDMA1 HW request is USART10_TX */ +#endif /* USART10 */ +#if defined (USART11) +#define GPDMA1_REQUEST_USART11_RX 41U /*!< GPDMA1 HW request is USART11_RX */ +#define GPDMA1_REQUEST_USART11_TX 42U /*!< GPDMA1 HW request is USART11_TX */ +#endif /* USART11 */ +#if defined (UART12) +#define GPDMA1_REQUEST_UART12_RX 43U /*!< GPDMA1 HW request is UART12_RX */ +#define GPDMA1_REQUEST_UART12_TX 44U /*!< GPDMA1 HW request is UART12_TX */ +#endif /* UART12 */ +#define GPDMA1_REQUEST_LPUART1_RX 45U /*!< GPDMA1 HW request is LPUART1_RX */ +#define GPDMA1_REQUEST_LPUART1_TX 46U /*!< GPDMA1 HW request is LPUART1_TX */ +#if defined (SPI4) +#define GPDMA1_REQUEST_SPI4_RX 47U /*!< GPDMA1 HW request is SPI4_RX */ +#define GPDMA1_REQUEST_SPI4_TX 48U /*!< GPDMA1 HW request is SPI4_TX */ +#endif /* SPI4 */ +#if defined (SPI5) +#define GPDMA1_REQUEST_SPI5_RX 49U /*!< GPDMA1 HW request is SPI5_RX */ +#define GPDMA1_REQUEST_SPI5_TX 50U /*!< GPDMA1 HW request is SPI5_TX */ +#endif /* SPI5 */ +#if defined (SPI6) +#define GPDMA1_REQUEST_SPI6_RX 51U /*!< GPDMA1 HW request is SPI6_RX */ +#define GPDMA1_REQUEST_SPI6_TX 52U /*!< GPDMA1 HW request is SPI6_TX */ +#endif /* SPI6 */ +#if defined (SAI1) +#define GPDMA1_REQUEST_SAI1_A 53U /*!< GPDMA1 HW request is SAI1_A */ +#define GPDMA1_REQUEST_SAI1_B 54U /*!< GPDMA1 HW request is SAI1_B */ +#endif /* SAI1 */ +#if defined (SAI2) +#define GPDMA1_REQUEST_SAI2_A 55U /*!< GPDMA1 HW request is SAI2_A */ +#define GPDMA1_REQUEST_SAI2_B 56U /*!< GPDMA1 HW request is SAI2_B */ +#endif /* SAI2 */ +#if defined (OCTOSPI1) +#define GPDMA1_REQUEST_OCTOSPI1 57U /*!< GPDMA1 HW request is OCTOSPI1 */ +#endif /* OCTOSPI1 */ +#define GPDMA1_REQUEST_TIM1_CH1 58U /*!< GPDMA1 HW request is TIM1_CH1 */ +#define GPDMA1_REQUEST_TIM1_CH2 59U /*!< GPDMA1 HW request is TIM1_CH2 */ +#define GPDMA1_REQUEST_TIM1_CH3 60U /*!< GPDMA1 HW request is TIM1_CH3 */ +#define GPDMA1_REQUEST_TIM1_CH4 61U /*!< GPDMA1 HW request is TIM1_CH4 */ +#define GPDMA1_REQUEST_TIM1_UP 62U /*!< GPDMA1 HW request is TIM1_UP */ +#define GPDMA1_REQUEST_TIM1_TRIG 63U /*!< GPDMA1 HW request is TIM1_TRIG */ +#define GPDMA1_REQUEST_TIM1_COM 64U /*!< GPDMA1 HW request is TIM1_COM */ +#if defined (TIM8) +#define GPDMA1_REQUEST_TIM8_CH1 65U /*!< GPDMA1 HW request is TIM8_CH1 */ +#define GPDMA1_REQUEST_TIM8_CH2 66U /*!< GPDMA1 HW request is TIM8_CH2 */ +#define GPDMA1_REQUEST_TIM8_CH3 67U /*!< GPDMA1 HW request is TIM8_CH3 */ +#define GPDMA1_REQUEST_TIM8_CH4 68U /*!< GPDMA1 HW request is TIM8_CH4 */ +#define GPDMA1_REQUEST_TIM8_UP 69U /*!< GPDMA1 HW request is TIM8_UP */ +#define GPDMA1_REQUEST_TIM8_TRIG 70U /*!< GPDMA1 HW request is TIM8_TRIG */ +#define GPDMA1_REQUEST_TIM8_COM 71U /*!< GPDMA1 HW request is TIM8_COM */ +#endif /* TIM8 */ +#define GPDMA1_REQUEST_TIM2_CH1 72U /*!< GPDMA1 HW request is TIM2_CH1 */ +#define GPDMA1_REQUEST_TIM2_CH2 73U /*!< GPDMA1 HW request is TIM2_CH2 */ +#define GPDMA1_REQUEST_TIM2_CH3 74U /*!< GPDMA1 HW request is TIM2_CH3 */ +#define GPDMA1_REQUEST_TIM2_CH4 75U /*!< GPDMA1 HW request is TIM2_CH4 */ +#define GPDMA1_REQUEST_TIM2_UP 76U /*!< GPDMA1 HW request is TIM2_UP */ +#define GPDMA1_REQUEST_TIM3_CH1 77U /*!< GPDMA1 HW request is TIM3_CH1 */ +#define GPDMA1_REQUEST_TIM3_CH2 78U /*!< GPDMA1 HW request is TIM3_CH2 */ +#define GPDMA1_REQUEST_TIM3_CH3 79U /*!< GPDMA1 HW request is TIM3_CH3 */ +#define GPDMA1_REQUEST_TIM3_CH4 80U /*!< GPDMA1 HW request is TIM3_CH4 */ +#define GPDMA1_REQUEST_TIM3_UP 81U /*!< GPDMA1 HW request is TIM3_UP */ +#define GPDMA1_REQUEST_TIM3_TRIG 82U /*!< GPDMA1 HW request is TIM3_TRIG */ +#if defined (TIM4) +#define GPDMA1_REQUEST_TIM4_CH1 83U /*!< GPDMA1 HW request is TIM4_CH1 */ +#define GPDMA1_REQUEST_TIM4_CH2 84U /*!< GPDMA1 HW request is TIM4_CH2 */ +#define GPDMA1_REQUEST_TIM4_CH3 85U /*!< GPDMA1 HW request is TIM4_CH3 */ +#define GPDMA1_REQUEST_TIM4_CH4 86U /*!< GPDMA1 HW request is TIM4_CH4 */ +#define GPDMA1_REQUEST_TIM4_UP 87U /*!< GPDMA1 HW request is TIM4_UP */ +#endif /* TIM4 */ +#if defined (TIM5) +#define GPDMA1_REQUEST_TIM5_CH1 88U /*!< GPDMA1 HW request is TIM5_CH1 */ +#define GPDMA1_REQUEST_TIM5_CH2 89U /*!< GPDMA1 HW request is TIM5_CH2 */ +#define GPDMA1_REQUEST_TIM5_CH3 90U /*!< GPDMA1 HW request is TIM5_CH3 */ +#define GPDMA1_REQUEST_TIM5_CH4 91U /*!< GPDMA1 HW request is TIM5_CH4 */ +#define GPDMA1_REQUEST_TIM5_UP 92U /*!< GPDMA1 HW request is TIM5_UP */ +#define GPDMA1_REQUEST_TIM5_TRIG 93U /*!< GPDMA1 HW request is TIM5_TRIG */ +#endif /* TIM5 */ +#if defined (TIM15) +#define GPDMA1_REQUEST_TIM15_CH1 94U /*!< GPDMA1 HW request is TIM15_CH1 */ +#define GPDMA1_REQUEST_TIM15_UP 95U /*!< GPDMA1 HW request is TIM15_UP */ +#define GPDMA1_REQUEST_TIM15_TRIG 96U /*!< GPDMA1 HW request is TIM15_TRIG */ +#define GPDMA1_REQUEST_TIM15_COM 97U /*!< GPDMA1 HW request is TIM15_COM */ +#endif /* TIM15 */ +#if defined (TIM16) +#define GPDMA1_REQUEST_TIM16_CH1 98U /*!< GPDMA1 HW request is TIM16_CH1 */ +#define GPDMA1_REQUEST_TIM16_UP 99U /*!< GPDMA1 HW request is TIM16_UP */ +#endif /* TIM16 */ +#if defined (TIM17) +#define GPDMA1_REQUEST_TIM17_CH1 100U /*!< GPDMA1 HW request is TIM17_CH1 */ +#define GPDMA1_REQUEST_TIM17_UP 101U /*!< GPDMA1 HW request is TIM17_UP */ +#endif /* TIM17 */ +#define GPDMA1_REQUEST_LPTIM1_IC1 102U /*!< GPDMA1 HW request is LPTIM1_IC1 */ +#define GPDMA1_REQUEST_LPTIM1_IC2 103U /*!< GPDMA1 HW request is LPTIM1_IC2 */ +#define GPDMA1_REQUEST_LPTIM1_UE 104U /*!< GPDMA1 HW request is LPTIM1_UE */ +#define GPDMA1_REQUEST_LPTIM2_IC1 105U /*!< GPDMA1 HW request is LPTIM2_IC1 */ +#define GPDMA1_REQUEST_LPTIM2_IC2 106U /*!< GPDMA1 HW request is LPTIM2_IC2 */ +#define GPDMA1_REQUEST_LPTIM2_UE 107U /*!< GPDMA1 HW request is LPTIM2_UE */ +#if defined (DCMI) +#define GPDMA1_REQUEST_DCMI 108U /*!< GPDMA1 HW request is DCMI */ +#endif /* DCMI */ +#if defined (AES) +#define GPDMA1_REQUEST_AES_OUT 109U /*!< GPDMA1 HW request is AES_OUT */ +#define GPDMA1_REQUEST_AES_IN 110U /*!< GPDMA1 HW request is AES_IN */ +#endif /* AES */ +#define GPDMA1_REQUEST_HASH_IN 111U /*!< GPDMA1 HW request is HASH_IN */ +#if defined (UCPD1) +#define GPDMA1_REQUEST_UCPD1_RX 112U /*!< GPDMA1 HW request is UCPD1_RX */ +#define GPDMA1_REQUEST_UCPD1_TX 113U /*!< GPDMA1 HW request is UCPD1_TX */ +#endif /* UCPD1 */ +#if defined (CORDIC) +#define GPDMA1_REQUEST_CORDIC_READ 114U /*!< GPDMA1 HW request is CORDIC_READ */ +#define GPDMA1_REQUEST_CORDIC_WRITE 115U /*!< GPDMA1 HW request is CORDIC_WRITE */ +#endif /* CORDIC */ +#if defined (FMAC) +#define GPDMA1_REQUEST_FMAC_READ 116U /*!< GPDMA1 HW request is FMAC_READ */ +#define GPDMA1_REQUEST_FMAC_WRITE 117U /*!< GPDMA1 HW request is FMAC_WRITE */ +#endif /* FMAC */ +#if defined (SAES) +#define GPDMA1_REQUEST_SAES_OUT 118U /*!< GPDMA1 HW request is SAES_OUT */ +#define GPDMA1_REQUEST_SAES_IN 119U /*!< GPDMA1 HW request is SAES_IN */ +#endif /* SAES */ +#define GPDMA1_REQUEST_I3C1_RX 120U /*!< GPDMA1 HW request is I3C1_RX */ +#define GPDMA1_REQUEST_I3C1_TX 121U /*!< GPDMA1 HW request is I3C1_TX */ +#define GPDMA1_REQUEST_I3C1_TC 122U /*!< GPDMA1 HW request is I3C1_TC */ +#define GPDMA1_REQUEST_I3C1_RS 123U /*!< GPDMA1 HW request is I3C1_RS */ +#if defined (I2C4) +#define GPDMA1_REQUEST_I2C4_RX 124U /*!< GPDMA1 HW request is I2C4_RX */ +#define GPDMA1_REQUEST_I2C4_TX 125U /*!< GPDMA1 HW request is I2C4_TX */ +#endif /* I2C4 */ +#if defined (LPTIM3) +#define GPDMA1_REQUEST_LPTIM3_IC1 127U /*!< GPDMA1 HW request is LPTIM3_IC1 */ +#define GPDMA1_REQUEST_LPTIM3_IC2 128U /*!< GPDMA1 HW request is LPTIM3_IC2 */ +#define GPDMA1_REQUEST_LPTIM3_UE 129U /*!< GPDMA1 HW request is LPTIM3_UE */ +#endif /* LPTIM3 */ +#if defined (LPTIM5) +#define GPDMA1_REQUEST_LPTIM5_IC1 130U /*!< GPDMA1 HW request is LPTIM5_IC1 */ +#define GPDMA1_REQUEST_LPTIM5_IC2 131U /*!< GPDMA1 HW request is LPTIM5_IC2 */ +#define GPDMA1_REQUEST_LPTIM5_UE 132U /*!< GPDMA1 HW request is LPTIM5_UE */ +#endif /* LPTIM5 */ +#if defined (LPTIM6) +#define GPDMA1_REQUEST_LPTIM6_IC1 133U /*!< GPDMA1 HW request is LPTIM6_IC1 */ +#define GPDMA1_REQUEST_LPTIM6_IC2 134U /*!< GPDMA1 HW request is LPTIM6_IC2 */ +#define GPDMA1_REQUEST_LPTIM6_UE 135U /*!< GPDMA1 HW request is LPTIM6_UE */ +#endif /* LPTIM6 */ +#if defined (I3C2) +#define GPDMA1_REQUEST_I3C2_RX 136U /*!< GPDMA1 HW request is I3C2_RX */ +#define GPDMA1_REQUEST_I3C2_TX 137U /*!< GPDMA1 HW request is I3C2_TX */ +#define GPDMA1_REQUEST_I3C2_TC 138U /*!< GPDMA1 HW request is I3C2_TC */ +#define GPDMA1_REQUEST_I3C2_RS 139U /*!< GPDMA1 HW request is I3C2_RS */ +#endif /* I3C2 */ +#if defined (JPEG) +#define GPDMA1_REQUEST_JPEG_RX_REQ 140U /*!< GPDMA1 HW request is JPEG_TX_REQ */ +#define GPDMA1_REQUEST_JPEG_TX_REQ 141U /*!< GPDMA1 HW request is JPEG_TX_REQ */ +#endif /* JPEG */ +#if defined (ADC3) +#define GPDMA1_REQUEST_ADC3 142U /*!< GPDMA1 HW request is ADC3 */ +#endif /* ADC3 */ +#if defined (OCTOSPI2) +#define GPDMA1_REQUEST_OCTOSPI2 143U /*!< GPDMA1 HW request is OCTOSPI2 */ +#endif /* OCTOSPI2 */ +#if defined (MDF1) +#define GPDMA1_REQUEST_MDF1_FLT0 144U /*!< GPDMA1 HW request is MDF1_FLT0 */ +#define GPDMA1_REQUEST_MDF1_FLT1 145U /*!< GPDMA1 HW request is MDF1_FLT1 */ +#define GPDMA1_REQUEST_MDF1_FLT2 146U /*!< GPDMA1 HW request is MDF1_FLT2 */ +#define GPDMA1_REQUEST_MDF1_FLT3 147U /*!< GPDMA1 HW request is MDF1_FLT3 */ +#define GPDMA1_REQUEST_MDF1_FLT4 148U /*!< GPDMA1 HW request is MDF1_FLT4 */ +#define GPDMA1_REQUEST_MDF1_FLT5 149U /*!< GPDMA1 HW request is MDF1_FLT5 */ +#endif /* MDF1 */ +#if defined (ADF1) +#define GPDMA1_REQUEST_ADF1_FLT0 150U /*!< GPDMA1 HW request is ADF1_FLT0 */ +#endif /* ADF1 */ + +/* GPDMA2 requests */ +#define GPDMA2_REQUEST_ADC1 0U /*!< GPDMA2 HW request is ADC1 */ +#if defined (ADC2) +#define GPDMA2_REQUEST_ADC2 1U /*!< GPDMA2 HW request is ADC2 */ +#endif /* ADC2 */ +#define GPDMA2_REQUEST_DAC1_CH1 2U /*!< GPDMA2 HW request is DAC1_CH1 */ +#define GPDMA2_REQUEST_DAC1_CH2 3U /*!< GPDMA2 HW request is DAC1_CH2 */ +#define GPDMA2_REQUEST_TIM6_UP 4U /*!< GPDMA2 HW request is TIM6_UP */ +#define GPDMA2_REQUEST_TIM7_UP 5U /*!< GPDMA2 HW request is TIM7_UP */ +#define GPDMA2_REQUEST_SPI1_RX 6U /*!< GPDMA2 HW request is SPI1_RX */ +#define GPDMA2_REQUEST_SPI1_TX 7U /*!< GPDMA2 HW request is SPI1_TX */ +#define GPDMA2_REQUEST_SPI2_RX 8U /*!< GPDMA2 HW request is SPI2_RX */ +#define GPDMA2_REQUEST_SPI2_TX 9U /*!< GPDMA2 HW request is SPI2_TX */ +#define GPDMA2_REQUEST_SPI3_RX 10U /*!< GPDMA2 HW request is SPI3_RX */ +#define GPDMA2_REQUEST_SPI3_TX 11U /*!< GPDMA2 HW request is SPI3_TX */ +#define GPDMA2_REQUEST_I2C1_RX 12U /*!< GPDMA2 HW request is I2C1_RX */ +#define GPDMA2_REQUEST_I2C1_TX 13U /*!< GPDMA2 HW request is I2C1_TX */ +#define GPDMA2_REQUEST_I2C2_RX 15U /*!< GPDMA2 HW request is I2C2_RX */ +#define GPDMA2_REQUEST_I2C2_TX 16U /*!< GPDMA2 HW request is I2C2_TX */ +#if defined (I2C3) +#define GPDMA2_REQUEST_I2C3_RX 18U /*!< GPDMA2 HW request is I2C3_RX */ +#define GPDMA2_REQUEST_I2C3_TX 19U /*!< GPDMA2 HW request is I2C3_TX */ +#endif /* I2C3 */ +#define GPDMA2_REQUEST_USART1_RX 21U /*!< GPDMA2 HW request is USART1_RX */ +#define GPDMA2_REQUEST_USART1_TX 22U /*!< GPDMA2 HW request is USART1_TX */ +#define GPDMA2_REQUEST_USART2_RX 23U /*!< GPDMA2 HW request is USART2_RX */ +#define GPDMA2_REQUEST_USART2_TX 24U /*!< GPDMA2 HW request is USART2_TX */ +#define GPDMA2_REQUEST_USART3_RX 25U /*!< GPDMA2 HW request is USART3_RX */ +#define GPDMA2_REQUEST_USART3_TX 26U /*!< GPDMA2 HW request is USART3_TX */ +#if defined (UART4) +#define GPDMA2_REQUEST_UART4_RX 27U /*!< GPDMA2 HW request is UART4_RX */ +#define GPDMA2_REQUEST_UART4_TX 28U /*!< GPDMA2 HW request is UART4_TX */ +#endif /* UART4 */ +#if defined (UART5) +#define GPDMA2_REQUEST_UART5_RX 29U /*!< GPDMA2 HW request is UART5_RX */ +#define GPDMA2_REQUEST_UART5_TX 30U /*!< GPDMA2 HW request is UART5_TX */ +#endif /* UART5 */ +#if defined (USART6) +#define GPDMA2_REQUEST_USART6_RX 31U /*!< GPDMA2 HW request is USART6_RX */ +#define GPDMA2_REQUEST_USART6_TX 32U /*!< GPDMA2 HW request is USART6_TX */ +#endif /* USART6 */ +#if defined (UART7) +#define GPDMA2_REQUEST_UART7_RX 33U /*!< GPDMA2 HW request is UART7_RX */ +#define GPDMA2_REQUEST_UART7_TX 34U /*!< GPDMA2 HW request is UART7_TX */ +#endif /* UART7 */ +#if defined (UART8) +#define GPDMA2_REQUEST_UART8_RX 35U /*!< GPDMA2 HW request is UART8_RX */ +#define GPDMA2_REQUEST_UART8_TX 36U /*!< GPDMA2 HW request is UART8_TX */ +#endif /* UART8 */ +#if defined (UART9) +#define GPDMA2_REQUEST_UART9_RX 37U /*!< GPDMA2 HW request is UART9_RX */ +#define GPDMA2_REQUEST_UART9_TX 38U /*!< GPDMA2 HW request is UART9_TX */ +#endif /* UART9 */ +#if defined (USART10) +#define GPDMA2_REQUEST_USART10_RX 39U /*!< GPDMA2 HW request is USART10_RX */ +#define GPDMA2_REQUEST_USART10_TX 40U /*!< GPDMA2 HW request is USART10_TX */ +#endif /* USART10 */ +#if defined (USART11) +#define GPDMA2_REQUEST_USART11_RX 41U /*!< GPDMA2 HW request is USART11_RX */ +#define GPDMA2_REQUEST_USART11_TX 42U /*!< GPDMA2 HW request is USART11_TX */ +#endif /* USART11 */ +#if defined (UART12) +#define GPDMA2_REQUEST_UART12_RX 43U /*!< GPDMA2 HW request is UART12_RX */ +#define GPDMA2_REQUEST_UART12_TX 44U /*!< GPDMA2 HW request is UART12_TX */ +#endif /* UART12 */ +#define GPDMA2_REQUEST_LPUART1_RX 45U /*!< GPDMA2 HW request is LPUART1_RX */ +#define GPDMA2_REQUEST_LPUART1_TX 46U /*!< GPDMA2 HW request is LPUART1_TX */ +#if defined (SPI4) +#define GPDMA2_REQUEST_SPI4_RX 47U /*!< GPDMA2 HW request is SPI4_RX */ +#define GPDMA2_REQUEST_SPI4_TX 48U /*!< GPDMA2 HW request is SPI4_TX */ +#endif /* SPI4 */ +#if defined (SPI5) +#define GPDMA2_REQUEST_SPI5_RX 49U /*!< GPDMA2 HW request is SPI5_RX */ +#define GPDMA2_REQUEST_SPI5_TX 50U /*!< GPDMA2 HW request is SPI5_TX */ +#endif /* SPI5 */ +#if defined (SPI6) +#define GPDMA2_REQUEST_SPI6_RX 51U /*!< GPDMA2 HW request is SPI6_RX */ +#define GPDMA2_REQUEST_SPI6_TX 52U /*!< GPDMA2 HW request is SPI6_TX */ +#endif /* SPI6 */ +#if defined (SAI1) +#define GPDMA2_REQUEST_SAI1_A 53U /*!< GPDMA2 HW request is SAI1_A */ +#define GPDMA2_REQUEST_SAI1_B 54U /*!< GPDMA2 HW request is SAI1_B */ +#endif /* SAI1 */ +#if defined (SAI2) +#define GPDMA2_REQUEST_SAI2_A 55U /*!< GPDMA2 HW request is SAI2_A */ +#define GPDMA2_REQUEST_SAI2_B 56U /*!< GPDMA2 HW request is SAI2_B */ +#endif /* SAI2 */ +#if defined (OCTOSPI1) +#define GPDMA2_REQUEST_OCTOSPI1 57U /*!< GPDMA2 HW request is OCTOSPI1 */ +#endif /* OCTOSPI1 */ +#define GPDMA2_REQUEST_TIM1_CH1 58U /*!< GPDMA2 HW request is TIM1_CH1 */ +#define GPDMA2_REQUEST_TIM1_CH2 59U /*!< GPDMA2 HW request is TIM1_CH2 */ +#define GPDMA2_REQUEST_TIM1_CH3 60U /*!< GPDMA2 HW request is TIM1_CH3 */ +#define GPDMA2_REQUEST_TIM1_CH4 61U /*!< GPDMA2 HW request is TIM1_CH4 */ +#define GPDMA2_REQUEST_TIM1_UP 62U /*!< GPDMA2 HW request is TIM1_UP */ +#define GPDMA2_REQUEST_TIM1_TRIG 63U /*!< GPDMA2 HW request is TIM1_TRIG */ +#define GPDMA2_REQUEST_TIM1_COM 64U /*!< GPDMA2 HW request is TIM1_COM */ +#if defined (TIM8) +#define GPDMA2_REQUEST_TIM8_CH1 65U /*!< GPDMA2 HW request is TIM8_CH1 */ +#define GPDMA2_REQUEST_TIM8_CH2 66U /*!< GPDMA2 HW request is TIM8_CH2 */ +#define GPDMA2_REQUEST_TIM8_CH3 67U /*!< GPDMA2 HW request is TIM8_CH3 */ +#define GPDMA2_REQUEST_TIM8_CH4 68U /*!< GPDMA2 HW request is TIM8_CH4 */ +#define GPDMA2_REQUEST_TIM8_UP 69U /*!< GPDMA2 HW request is TIM8_UP */ +#define GPDMA2_REQUEST_TIM8_TRIG 70U /*!< GPDMA2 HW request is TIM8_TRIG */ +#define GPDMA2_REQUEST_TIM8_COM 71U /*!< GPDMA2 HW request is TIM8_COM */ +#endif /* TIM8 */ +#define GPDMA2_REQUEST_TIM2_CH1 72U /*!< GPDMA2 HW request is TIM2_CH1 */ +#define GPDMA2_REQUEST_TIM2_CH2 73U /*!< GPDMA2 HW request is TIM2_CH2 */ +#define GPDMA2_REQUEST_TIM2_CH3 74U /*!< GPDMA2 HW request is TIM2_CH3 */ +#define GPDMA2_REQUEST_TIM2_CH4 75U /*!< GPDMA2 HW request is TIM2_CH4 */ +#define GPDMA2_REQUEST_TIM2_UP 76U /*!< GPDMA2 HW request is TIM2_UP */ +#define GPDMA2_REQUEST_TIM3_CH1 77U /*!< GPDMA2 HW request is TIM3_CH1 */ +#define GPDMA2_REQUEST_TIM3_CH2 78U /*!< GPDMA2 HW request is TIM3_CH2 */ +#define GPDMA2_REQUEST_TIM3_CH3 79U /*!< GPDMA2 HW request is TIM3_CH3 */ +#define GPDMA2_REQUEST_TIM3_CH4 80U /*!< GPDMA2 HW request is TIM3_CH4 */ +#define GPDMA2_REQUEST_TIM3_UP 81U /*!< GPDMA2 HW request is TIM3_UP */ +#define GPDMA2_REQUEST_TIM3_TRIG 82U /*!< GPDMA2 HW request is TIM3_TRIG */ +#if defined (TIM4) +#define GPDMA2_REQUEST_TIM4_CH1 83U /*!< GPDMA2 HW request is TIM4_CH1 */ +#define GPDMA2_REQUEST_TIM4_CH2 84U /*!< GPDMA2 HW request is TIM4_CH2 */ +#define GPDMA2_REQUEST_TIM4_CH3 85U /*!< GPDMA2 HW request is TIM4_CH3 */ +#define GPDMA2_REQUEST_TIM4_CH4 86U /*!< GPDMA2 HW request is TIM4_CH4 */ +#define GPDMA2_REQUEST_TIM4_UP 87U /*!< GPDMA2 HW request is TIM4_UP */ +#endif /* TIM4 */ +#if defined (TIM5) +#define GPDMA2_REQUEST_TIM5_CH1 88U /*!< GPDMA2 HW request is TIM5_CH1 */ +#define GPDMA2_REQUEST_TIM5_CH2 89U /*!< GPDMA2 HW request is TIM5_CH2 */ +#define GPDMA2_REQUEST_TIM5_CH3 90U /*!< GPDMA2 HW request is TIM5_CH3 */ +#define GPDMA2_REQUEST_TIM5_CH4 91U /*!< GPDMA2 HW request is TIM5_CH4 */ +#define GPDMA2_REQUEST_TIM5_UP 92U /*!< GPDMA2 HW request is TIM5_UP */ +#define GPDMA2_REQUEST_TIM5_TRIG 93U /*!< GPDMA2 HW request is TIM5_TRIG */ +#endif /* TIM5 */ +#if defined (TIM15) +#define GPDMA2_REQUEST_TIM15_CH1 94U /*!< GPDMA2 HW request is TIM15_CH1 */ +#define GPDMA2_REQUEST_TIM15_UP 95U /*!< GPDMA2 HW request is TIM15_UP */ +#define GPDMA2_REQUEST_TIM15_TRIG 96U /*!< GPDMA2 HW request is TIM15_TRIG */ +#define GPDMA2_REQUEST_TIM15_COM 97U /*!< GPDMA2 HW request is TIM15_COM */ +#endif /* TIM15 */ +#if defined (TIM16) +#define GPDMA2_REQUEST_TIM16_CH1 98U /*!< GPDMA2 HW request is TIM16_CH1 */ +#define GPDMA2_REQUEST_TIM16_UP 99U /*!< GPDMA2 HW request is TIM16_UP */ +#endif /* TIM16 */ +#if defined (TIM17) +#define GPDMA2_REQUEST_TIM17_CH1 100U /*!< GPDMA2 HW request is TIM17_CH1 */ +#define GPDMA2_REQUEST_TIM17_UP 101U /*!< GPDMA2 HW request is TIM17_UP */ +#endif /* TIM17 */ +#define GPDMA2_REQUEST_LPTIM1_IC1 102U /*!< GPDMA2 HW request is LPTIM1_IC1 */ +#define GPDMA2_REQUEST_LPTIM1_IC2 103U /*!< GPDMA2 HW request is LPTIM1_IC2 */ +#define GPDMA2_REQUEST_LPTIM1_UE 104U /*!< GPDMA2 HW request is LPTIM1_UE */ +#define GPDMA2_REQUEST_LPTIM2_IC1 105U /*!< GPDMA2 HW request is LPTIM2_IC1 */ +#define GPDMA2_REQUEST_LPTIM2_IC2 106U /*!< GPDMA2 HW request is LPTIM2_IC2 */ +#define GPDMA2_REQUEST_LPTIM2_UE 107U /*!< GPDMA2 HW request is LPTIM2_UE */ +#if defined (DCMI) +#define GPDMA2_REQUEST_DCMI 108U /*!< GPDMA2 HW request is DCMI */ +#endif /* DCMI */ +#if defined (AES) +#define GPDMA2_REQUEST_AES_OUT 109U /*!< GPDMA2 HW request is AES_OUT */ +#define GPDMA2_REQUEST_AES_IN 110U /*!< GPDMA2 HW request is AES_IN */ +#endif /* AES */ +#define GPDMA2_REQUEST_HASH_IN 111U /*!< GPDMA2 HW request is HASH_IN */ +#if defined (UCPD1) +#define GPDMA2_REQUEST_UCPD1_RX 112U /*!< GPDMA2 HW request is UCPD1_RX */ +#define GPDMA2_REQUEST_UCPD1_TX 113U /*!< GPDMA2 HW request is UCPD1_TX */ +#endif /* UCPD1 */ +#if defined (CORDIC) +#define GPDMA2_REQUEST_CORDIC_READ 114U /*!< GPDMA2 HW request is CORDIC_READ */ +#define GPDMA2_REQUEST_CORDIC_WRITE 115U /*!< GPDMA2 HW request is CORDIC_WRITE */ +#endif /* CORDIC */ +#if defined (FMAC) +#define GPDMA2_REQUEST_FMAC_READ 116U /*!< GPDMA2 HW request is FMAC_READ */ +#define GPDMA2_REQUEST_FMAC_WRITE 117U /*!< GPDMA2 HW request is FMAC_WRITE */ +#endif /* FMAC */ +#if defined (SAES) +#define GPDMA2_REQUEST_SAES_OUT 118U /*!< GPDMA2 HW request is SAES_OUT */ +#define GPDMA2_REQUEST_SAES_IN 119U /*!< GPDMA2 HW request is SAES_IN */ +#endif /* SAES */ +#define GPDMA2_REQUEST_I3C1_RX 120U /*!< GPDMA2 HW request is I3C1_RX */ +#define GPDMA2_REQUEST_I3C1_TX 121U /*!< GPDMA2 HW request is I3C1_TX */ +#define GPDMA2_REQUEST_I3C1_TC 122U /*!< GPDMA2 HW request is I3C1_TC */ +#define GPDMA2_REQUEST_I3C1_RS 123U /*!< GPDMA2 HW request is I3C1_RS */ +#if defined (I2C4) +#define GPDMA2_REQUEST_I2C4_RX 124U /*!< GPDMA2 HW request is I2C4_RX */ +#define GPDMA2_REQUEST_I2C4_TX 125U /*!< GPDMA2 HW request is I2C4_TX */ +#endif /* I2C4 */ +#if defined (LPTIM3) +#define GPDMA2_REQUEST_LPTIM3_IC1 127U /*!< GPDMA2 HW request is LPTIM3_IC1 */ +#define GPDMA2_REQUEST_LPTIM3_IC2 128U /*!< GPDMA2 HW request is LPTIM3_IC2 */ +#define GPDMA2_REQUEST_LPTIM3_UE 129U /*!< GPDMA2 HW request is LPTIM3_UE */ +#endif /* LPTIM3 */ +#if defined (LPTIM5) +#define GPDMA2_REQUEST_LPTIM5_IC1 130U /*!< GPDMA2 HW request is LPTIM5_IC1 */ +#define GPDMA2_REQUEST_LPTIM5_IC2 131U /*!< GPDMA2 HW request is LPTIM5_IC2 */ +#define GPDMA2_REQUEST_LPTIM5_UE 132U /*!< GPDMA2 HW request is LPTIM5_UE */ +#endif /* LPTIM5 */ +#if defined (LPTIM6) +#define GPDMA2_REQUEST_LPTIM6_IC1 133U /*!< GPDMA2 HW request is LPTIM6_IC1 */ +#define GPDMA2_REQUEST_LPTIM6_IC2 134U /*!< GPDMA2 HW request is LPTIM6_IC2 */ +#define GPDMA2_REQUEST_LPTIM6_UE 135U /*!< GPDMA2 HW request is LPTIM6_UE */ +#endif /* LPTIM6 */ +#if defined (I3C2) +#define GPDMA2_REQUEST_I3C2_RX 136U /*!< GPDMA2 HW request is I3C2_RX */ +#define GPDMA2_REQUEST_I3C2_TX 137U /*!< GPDMA2 HW request is I3C2_TX */ +#define GPDMA2_REQUEST_I3C2_TC 138U /*!< GPDMA2 HW request is I3C2_TC */ +#define GPDMA2_REQUEST_I3C2_RS 139U /*!< GPDMA2 HW request is I3C2_RS */ +#endif /* I3C2 */ +#if defined (JPEG) +#define GPDMA2_REQUEST_JPEG_RX_REQ 140U /*!< GPDMA2 HW request is JPEG_TX_REQ */ +#define GPDMA2_REQUEST_JPEG_TX_REQ 141U /*!< GPDMA2 HW request is JPEG_TX_REQ */ +#endif /* JPEG */ +#if defined (ADC3) +#define GPDMA2_REQUEST_ADC3 142U /*!< GPDMA2 HW request is ADC3 */ +#endif /* ADC3 */ +#if defined (OCTOSPI2) +#define GPDMA2_REQUEST_OCTOSPI2 143U /*!< GPDMA2 HW request is OCTOSPI2 */ +#endif /* OCTOSPI2 */ +#if defined (MDF1) +#define GPDMA2_REQUEST_MDF1_FLT0 144U /*!< GPDMA2 HW request is MDF1_FLT0 */ +#define GPDMA2_REQUEST_MDF1_FLT1 145U /*!< GPDMA2 HW request is MDF1_FLT1 */ +#define GPDMA2_REQUEST_MDF1_FLT2 146U /*!< GPDMA2 HW request is MDF1_FLT2 */ +#define GPDMA2_REQUEST_MDF1_FLT3 147U /*!< GPDMA2 HW request is MDF1_FLT3 */ +#define GPDMA2_REQUEST_MDF1_FLT4 148U /*!< GPDMA2 HW request is MDF1_FLT4 */ +#define GPDMA2_REQUEST_MDF1_FLT5 149U /*!< GPDMA2 HW request is MDF1_FLT5 */ +#endif /* MDF1 */ +#if defined (ADF1) +#define GPDMA2_REQUEST_ADF1_FLT0 150U /*!< GPDMA2 HW request is ADF1_FLT0 */ +#endif /* ADF1 */ + +/* Software request */ +#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ +/** + * @} + */ + +/** @defgroup DMA_Block_Request DMA Block Request + * @brief DMA Block Request + * @{ + */ +#define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */ +#define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Direction DMA Transfer Direction + * @brief DMA transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode + * @brief DMA Source Increment Mode + * @{ + */ +#define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */ +#define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */ +/** + * @} + */ + +/** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode + * @brief DMA Destination Increment Mode + * @{ + */ +#define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */ +#define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */ +/** + * @} + */ + +/** @defgroup DMA_Source_Data_Width DMA Source Data Width + * @brief DMA Source Data Width + * @{ + */ +#define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */ +#define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */ +#define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */ +/** + * @} + */ + +/** @defgroup DMA_Destination_Data_Width DMA destination Data Width + * @brief DMA destination Data Width + * @{ + */ +#define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */ +#define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */ +#define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */ + +/** + * @} + */ + +/** @defgroup DMA_Priority_Level DMA Priority Level + * @brief DMA Priority Level + * @{ + */ +#define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */ +#define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */ +#define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */ +#define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port + * @brief DMA Transfer Allocated Port + * @{ + */ +#define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */ +#define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ +#define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ +#define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode + * @brief DMA Transfer Event Mode + * @{ + */ +#define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the + HT event is generated at the half of each block */ +#define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block + and the HT event is generated at the half of the repeated + block */ +#define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list + item and the HT event is generated at the half of each + linked-list item */ +#define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last + linked-list item and the HT event is generated at the half + of the last linked-list item */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Mode DMA Transfer Mode + * @brief DMA Transfer Mode + * @{ + */ +#define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */ +#define DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_Channel_Attributes DMA Channel Attributes + * @brief DMA Channel Security and Privilege Attributes + * @note Secure and non-secure attributes are only available from the secure world when TZEN = 1 + * @{ + */ +#define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | 0x01U) /*!< Channel is privileged */ +#define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ + +#define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | 0x02U) /*!< Channel is secure */ +#define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */ +#define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | 0x04U) /*!< Channel source is secure */ +#define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */ +#define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | 0x08U) /*!< Channel destination is secure */ +#define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */ + +#define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */ +#define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */ +/** + * @} + */ + + +/** + * @} + */ + + +/* Exported macro ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @brief DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state. + * @param __HANDLE__ : DMA handle. + * @retval None. + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ : DMA handle. + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ : DMA handle. + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET)) + +/** + * @brief Get the DMA channel pending flags. + * @param __HANDLE__ : DMA handle. + * @param __FLAG__ : Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TC : Transfer Complete flag. + * @arg DMA_FLAG_HT : Half Transfer Complete flag. + * @arg DMA_FLAG_DTE : Data Transfer Error flag. + * @arg DMA_FLAG_ULE : Update linked-list Error flag. + * @arg DMA_FLAG_USE : User Setting Error flag. + * @arg DMA_FLAG_TO : Trigger Overrun flag. + * @arg DMA_FLAG_SUSP : Completed Suspension flag. + * @arg DMA_FLAG_IDLEF : Idle flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \ + ((__HANDLE__)->Instance->CSR & (__FLAG__)) + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__ : DMA handle. + * @param __FLAG__ : Specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TC : Transfer Complete flag. + * @arg DMA_FLAG_HT : Half Transfer Complete flag. + * @arg DMA_FLAG_DTE : Data Transfer Error flag. + * @arg DMA_FLAG_ULE : Update Linked-List Error flag. + * @arg DMA_FLAG_USE : User Setting Error flag. + * @arg DMA_FLAG_TO : Trigger Overrun flag. + * @arg DMA_FLAG_SUSP : Completed Suspension flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + ((__HANDLE__)->Instance->CFCR = (__FLAG__)) + +/** + * @brief Enable the specified DMA Channel interrupts. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DMA Channel interrupt is enabled or not. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : specifies the DMA interrupt source to check. + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Writes the block number of bytes to be transferred from the source on the DMA Channel. + * @param __HANDLE__ : DMA handle. + * @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535). + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \ + MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__)) + +/** + * @brief Returns the number of remaining data bytes in the current DMA Channel transfer. + * @param __HANDLE__ : DMA handle. + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) \ + (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT) +/** + * @} + */ + + +/* Include DMA HAL Extension module */ +#include "stm32h5xx_hal_dma_ex.h" + + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and De-Initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions + * @brief I/O Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, + HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID, + void (*const pCallback)(DMA_HandleTypeDef *const _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 State and Error Functions + * @brief State and Error Functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions + * @brief DMA Attributes Functions + * @{ + */ + +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, + uint32_t ChannelAttributes); +HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pChannelAttributes); + +#if defined (DMA_RCFGLOCKR_LOCK0) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pLockState); + +#endif /* DMA_RCFGLOCKR_LOCK0 */ + +/** + * @} + */ + +/** + * @} + */ + + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA Private Constants + * @{ + */ +#define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */ +#define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */ +#define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */ +#define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */ +#define DMA_CHANNEL_ATTR_PRIV_MASK (0x00000010U) /* DMA channel privilege mask */ +#define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */ +#define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */ +#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */ +#define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */ +#define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */ +#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ +#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ +/** + * @} + */ + + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA Private Macros + * @{ + */ +#define GET_DMA_INSTANCE(__HANDLE__) \ + ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK))) + +#define GET_DMA_CHANNEL(__HANDLE__) \ + ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE) + +#define IS_DMA_MODE(MODE) \ + (((MODE) == DMA_NORMAL) || \ + ((MODE) == DMA_PFCTRL)) + +#define IS_DMA_DIRECTION(DIRECTION) \ + (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_LEVEL_COMPLETE(LEVEL) \ + (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \ + ((LEVEL) == HAL_DMA_HALF_TRANSFER)) + +#define IS_DMA_SOURCE_INC(INC) \ + (((INC) == DMA_SINC_FIXED) || \ + ((INC) == DMA_SINC_INCREMENTED)) + +#define IS_DMA_DESTINATION_INC(INC) \ + (((INC) == DMA_DINC_FIXED) || \ + ((INC) == DMA_DINC_INCREMENTED)) + +#define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \ + (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \ + ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \ + ((WIDTH) == DMA_SRC_DATAWIDTH_WORD)) + +#define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \ + (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \ + ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \ + ((WIDTH) == DMA_DEST_DATAWIDTH_WORD)) + +#define IS_DMA_BURST_LENGTH(LENGTH) \ + (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \ + ((LENGTH) <= DMA_CHANNEL_BURST_MAX)) + +#define IS_DMA_PRIORITY(PRIORITY) \ + (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \ + ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \ + ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ + ((PRIORITY) == DMA_HIGH_PRIORITY)) + +#define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ + (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) + +#if defined (ADF1) +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_ADF1_FLT0)) +#elif defined (I3C2) +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_I3C2_RS)) +#else +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_LPTIM6_UE)) +#endif /* I3C2 */ + +#define IS_DMA_BLOCK_HW_REQUEST(MODE) \ + (((MODE) == DMA_BREQ_SINGLE_BURST) || \ + ((MODE) == DMA_BREQ_BLOCK)) + +#define IS_DMA_TCEM_EVENT_MODE(MODE) \ + (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ + ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) + +#define IS_DMA_BLOCK_SIZE(SIZE) \ + (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ + (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \ + (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \ + (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U))) +#else +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ + (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ + ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ + (((INSTANCE)->SMISR & (GLOBAL_FLAG))) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ + (((INSTANCE)->MISR & (GLOBAL_FLAG))) + +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_DMA_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h new file mode 100644 index 00000000..8f73bd0c --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h @@ -0,0 +1,803 @@ +/** + ********************************************************************************************************************** + * @file stm32h5xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32H5xx_HAL_DMA_EX_H +#define STM32H5xx_HAL_DMA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief DMAEx Data Handling Configuration Structure Definition. + */ +typedef struct +{ + uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode. + This parameter can be a value of @ref DMAEx_Data_Exchange */ + + uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode + This parameter can be a value of @ref DMAEx_Data_Alignment */ + +} DMA_DataHandlingConfTypeDef; + +/** + * @brief DMAEx Trigger Configuration Structure Definition. + */ +typedef struct +{ + uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode. + This parameter can be a value of @ref DMAEx_Trigger_Mode */ + + uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity. + This parameter can be a value of @ref DMAEx_Trigger_Polarity */ + + uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection. + This parameter can be a value of @ref DMAEx_Trigger_Selection */ + +} DMA_TriggerConfTypeDef; + +/** + * @brief DMAEx Repeated Block Configuration Structure Definition. + */ +typedef struct +{ + uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block). + This parameter can be a value between 1 and 2048 */ + + int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset : + This parameter can be a value between -8191 and 8191. + * If source address offset > 0 => Increment the source address by offset from where + the last single/burst transfer ends. + * If source address offset < 0 => Decrement the source address by offset from where + the last single/burst transfer ends. + * If source address offset == 0 => The next single/burst source address starts from + where the last transfer ends */ + + int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value : + This parameter can be a value between -8191 and 8191. + * If destination address offset > 0 => Increment the destination address by offset + from where the last single/burst transfer ends. + * If destination address offset < 0 => Decrement the destination address by offset + from where the last single/burst transfer ends. + * If destination address offset == 0 => The next single/burst destination address + starts from where the last transfer ends. */ + + int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value : + This parameter can be a value between -65535 and 65535. + * If block source address offset > 0 => Increment the block source address by offset + from where the last block ends. + * If block source address offset < 0 => Decrement the next block source address by + offset from where the last block ends. + * If block source address offset == 0 => the next block source address starts from + where the last block ends */ + + int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value : + This parameter can be a value between -65535 and 65535. + * If block destination address offset > 0 => Increment the block destination address + by offset from where the last block ends. + * If block destination address offset < 0 => Decrement the next block destination + address by offset from where the last block ends. + * If block destination address offset == 0 => the next block destination address + starts from where the last block ends */ + +} DMA_RepeatBlockConfTypeDef; + +/** + * @brief DMAEx Queue State Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */ + HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */ + HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */ + +} HAL_DMA_QStateTypeDef; + +/** + * @brief DMAEx Linked-List Node Configuration Structure Definition. + */ +typedef struct +{ + uint32_t NodeType; /*!< Specifies the DMA channel node type. + This parameter can be a value of @ref DMAEx_Node_Type */ + + DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */ + + DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */ + + DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */ + + DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */ + + uint32_t SrcAddress; /*!< Specifies the source memory address */ + uint32_t DstAddress; /*!< Specifies the destination memory address */ + uint32_t DataSize; /*!< Specifies the source data size in bytes */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t SrcSecure; /*!< Specifies the source security attribute */ + uint32_t DestSecure; /*!< Specifies the destination security attribute */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +} DMA_NodeConfTypeDef; + +/** + * @brief DMAEx Linked-List Node Structure Definition. + */ +typedef struct +{ + uint32_t LinkRegisters[8U]; /*!< Physical Node register description */ + uint32_t NodeInfo; /*!< Node information */ + +} DMA_NodeTypeDef; + +/** + * @brief DMAEx Linked-List Queue Structure Definition. + */ +typedef struct __DMA_QListTypeDef +{ + DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */ + + DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */ + + uint32_t NodeNumber; /*!< Specifies the queue node number */ + + __IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */ + + __IO uint32_t ErrorCode; /*!< Specifies the queue error code */ + + __IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */ + +} DMA_QListTypeDef; +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @brief DMAEx Exported Constants + * @{ + */ + +/** @defgroup Queue_Error_Codes Queue Error Codes + * @brief Queue Error Codes + * @{ + */ +#define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */ +#define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */ +#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */ +#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization + and queue circular types are incompatible */ +#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */ +#define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */ +/** + * @} + */ + +/** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode + * @brief DMAEx LinkedList Mode + * @{ + */ +#define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */ +#define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */ +/** + * @} + */ + +/** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment + * @brief DMAEx Data Alignment + * @{ + */ +#define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width + => Right aligned padded with 0 up to destination data + width */ +#define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width + => Right aligned left Truncated down to destination + data width */ +#define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width + => Right Aligned padded with sign extended up to + destination data width */ +#define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width + => Left Aligned Right Truncated down to the + destination data width */ +#define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width + => Packed at the destination data width */ +#define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width + => Unpacked at the destination data width */ +/** + * @} + */ + +/** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange + * @brief DMAEx Data Exchange + * @{ + */ +#define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */ +#define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */ +#define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */ +#define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity + * @brief DMAEx Trigger Polarity + * @{ + */ +#define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */ +#define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */ +#define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode + * @brief DMAEx Trigger Mode + * @{ + */ +#define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection + * @brief DMAEx Trigger Selection + * @{ + */ +/* GPDMA1 triggers */ +#define GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ +#define GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ +#define GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */ +#define GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */ +#define GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */ +#define GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */ +#define GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */ +#define GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */ +#define GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */ +#define GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */ +#if defined (TAMP_CR1_TAMP3E) +#define GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */ +#endif /* TAMP_CR1_TAMP3E */ +#define GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#define GPDMA1_TRIGGER_RTC_ALRA_TRG 15U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ +#define GPDMA1_TRIGGER_RTC_ALRB_TRG 16U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ +#define GPDMA1_TRIGGER_RTC_WUT_TRG 17U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ +#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 18U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 19U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 20U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 21U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define GPDMA1_TRIGGER_GPDMA2_CH0_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH0_TCF */ +#define GPDMA1_TRIGGER_GPDMA2_CH1_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH1_TCF */ +#define GPDMA1_TRIGGER_GPDMA2_CH2_TCF 28U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH2_TCF */ +#define GPDMA1_TRIGGER_GPDMA2_CH3_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH3_TCF */ +#define GPDMA1_TRIGGER_GPDMA2_CH4_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH4_TCF */ +#define GPDMA1_TRIGGER_GPDMA2_CH5_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH5_TCF */ +#define GPDMA1_TRIGGER_GPDMA2_CH6_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH6_TCF */ +#define GPDMA1_TRIGGER_GPDMA2_CH7_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH7_TCF */ +#define GPDMA1_TRIGGER_TIM2_TRGO 34U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ +#if defined (TIM15) +#define GPDMA1_TRIGGER_TIM15_TRGO 35U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ +#endif /* TIM15 */ +#if defined (TIM12) +#define GPDMA1_TRIGGER_TIM12_TRGO 36U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */ +#endif /* TIM12 */ +#if defined (LPTIM3) +#define GPDMA1_TRIGGER_LPTIM3_CH1 37U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */ +#define GPDMA1_TRIGGER_LPTIM3_CH2 38U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */ +#endif /* LPTIM3 */ +#if defined (LPTIM4) +#define GPDMA1_TRIGGER_LPTIM4_AIT 39U /*!< GPDMA1 HW Trigger signal is LPTIM4_AIT */ +#endif /* LPTIM4 */ +#if defined (LPTIM5) +#define GPDMA1_TRIGGER_LPTIM5_CH1 40U /*!< GPDMA1 HW Trigger signal is LPTIM5_CH1 */ +#define GPDMA1_TRIGGER_LPTIM5_CH2 41U /*!< GPDMA1 HW Trigger signal is LPTIM5_CH2 */ +#endif /* LPTIM5 */ +#if defined (LPTIM6) +#define GPDMA1_TRIGGER_LPTIM6_CH1 42U /*!< GPDMA1 HW Trigger signal is LPTIM6_CH1 */ +#define GPDMA1_TRIGGER_LPTIM6_CH2 43U /*!< GPDMA1 HW Trigger signal is LPTIM6_CH2 */ +#endif /* LPTIM6 */ +#if defined (COMP1) +#define GPDMA1_TRIGGER_COMP1_OUT 44U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ +#endif /* COMP1 */ +#if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) \ + || defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx) +#define GPDMA1_TRIGGER_EVENTOUT 45U /*!< GPDMA1 HW Trigger signal is EVENTOUT */ +#endif /* STM32H503xx || STM32H523xx || STM32H533xx || STM32H5F5xx || STM32H5F4xx || + STM32H5E5xx || STM32H5E4xx || STM32H553xx || STM32H543xx */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx) +#define GPDMA1_TRIGGER_COMP2_OUT 46U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPDMA1_TRIGGER_DMA2D_TC_FLAG 47U /*!< GPDMA1 HW Trigger signal is TC_FLAG */ +#define GPDMA1_TRIGGER_DMA2D_CTC_FLAG 48U /*!< GPDMA1 HW Trigger signal is CTC_FLAG */ +#define GPDMA1_TRIGGER_DMA2D_TW_FLAG 49U /*!< GPDMA1 HW Trigger signal is TW_FLAG */ +#define GPDMA1_TRIGGER_DMA2D_GPFLAGS0 50U /*!< GPDMA1 HW Trigger signal is GPFLAGS[0] */ +#define GPDMA1_TRIGGER_DMA2D_GPFLAGS1 51U /*!< GPDMA1 HW Trigger signal is GPFLAGS[1] */ +#define GPDMA1_TRIGGER_DMA2D_GPFLAGS2 52U /*!< GPDMA1 HW Trigger signal is GPFLAGS[2] */ +#define GPDMA1_TRIGGER_DMA2D_GPFLAGS3 53U /*!< GPDMA1 HW Trigger signal is GPFLAGS[3] */ +#define GPDMA1_TRIGGER_JPEG_IFT_FLAG 54U /*!< GPDMA1 HW Trigger signal is JPEG_IFT_FLAG */ +#define GPDMA1_TRIGGER_JPEG_IFNF_FLAG 55U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF_FLAG */ +#define GPDMA1_TRIGGER_JPEG_OFT_FLAG 56U /*!< GPDMA1 HW Trigger signal is JPEG_OFT_FLAG */ +#define GPDMA1_TRIGGER_JPEG_OFNE_FLAG 57U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE_FLAG */ +#define GPDMA1_TRIGGER_JPEG_EOC_FLAG 58U /*!< GPDMA1 HW Trigger signal is JPEG_EOC_FLAG */ +#define GPDMA1_TRIGGER_GFXTIM_EVT1 59U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT[1] */ +#define GPDMA1_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT[2] */ +#define GPDMA1_TRIGGER_GFXTIM_EVT3 61U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT[2+4] */ +#define GPDMA1_TRIGGER_GFXTIM_EVT4 62U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT[4] */ +#define GPDMA1_TRIGGER_LCD_CTRL_SCANLINE 63U /*!< GPDMA1 HW Trigger signal is LCD_CTRL_SCANLINE */ +#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF 64U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TC */ +#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF 65U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TC */ +#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF 66U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TC */ +#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF 67U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TC */ +#define GPDMA1_TRIGGER_GPDMA2_CH8_TCF 68U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH8_TC */ +#define GPDMA1_TRIGGER_GPDMA2_CH9_TCF 69U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH9_TC */ +#define GPDMA1_TRIGGER_GPDMA2_CH10_TCF 70U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH10_TC */ +#define GPDMA1_TRIGGER_GPDMA2_CH11_TCF 71U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH11_TC */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#define GPDMA1_TRIGGER_PLAY1_OUT15 72U /*!< GPDMA1 HW Trigger signal is PLAY1_OUT15 */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx || STM32H553xx || STM32H543xx*/ + +/* GPDMA2 triggers */ +#define GPDMA2_TRIGGER_EXTI_LINE0 0U /*!< GPDMA2 HW Trigger signal is EXTI_LINE0 */ +#define GPDMA2_TRIGGER_EXTI_LINE1 1U /*!< GPDMA2 HW Trigger signal is EXTI_LINE1 */ +#define GPDMA2_TRIGGER_EXTI_LINE2 2U /*!< GPDMA2 HW Trigger signal is EXTI_LINE2 */ +#define GPDMA2_TRIGGER_EXTI_LINE3 3U /*!< GPDMA2 HW Trigger signal is EXTI_LINE3 */ +#define GPDMA2_TRIGGER_EXTI_LINE4 4U /*!< GPDMA2 HW Trigger signal is EXTI_LINE4 */ +#define GPDMA2_TRIGGER_EXTI_LINE5 5U /*!< GPDMA2 HW Trigger signal is EXTI_LINE5 */ +#define GPDMA2_TRIGGER_EXTI_LINE6 6U /*!< GPDMA2 HW Trigger signal is EXTI_LINE6 */ +#define GPDMA2_TRIGGER_EXTI_LINE7 7U /*!< GPDMA2 HW Trigger signal is EXTI_LINE7 */ +#define GPDMA2_TRIGGER_TAMP_TRG1 8U /*!< GPDMA2 HW Trigger signal is TAMP_TRG1 */ +#define GPDMA2_TRIGGER_TAMP_TRG2 9U /*!< GPDMA2 HW Trigger signal is TAMP_TRG2 */ +#define GPDMA2_TRIGGER_TAMP_TRG3 10U /*!< GPDMA2 HW Trigger signal is TAMP_TRG3 */ +#define GPDMA2_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA2 HW Trigger signal is LPTIM1_CH1 */ +#define GPDMA2_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA2 HW Trigger signal is LPTIM1_CH2 */ +#define GPDMA2_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA2 HW Trigger signal is LPTIM2_CH1 */ +#define GPDMA2_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA2 HW Trigger signal is LPTIM2_CH2 */ +#define GPDMA2_TRIGGER_RTC_ALRA_TRG 15U /*!< GPDMA2 HW Trigger signal is RTC_ALRA_TRG */ +#define GPDMA2_TRIGGER_RTC_ALRB_TRG 16U /*!< GPDMA2 HW Trigger signal is RTC_ALRB_TRG */ +#define GPDMA2_TRIGGER_RTC_WUT_TRG 17U /*!< GPDMA2 HW Trigger signal is RTC_WUT_TRG */ +#define GPDMA2_TRIGGER_GPDMA1_CH0_TCF 18U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH0_TCF */ +#define GPDMA2_TRIGGER_GPDMA1_CH1_TCF 19U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH1_TCF */ +#define GPDMA2_TRIGGER_GPDMA1_CH2_TCF 20U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH2_TCF */ +#define GPDMA2_TRIGGER_GPDMA1_CH3_TCF 21U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH3_TCF */ +#define GPDMA2_TRIGGER_GPDMA1_CH4_TCF 22U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH4_TCF */ +#define GPDMA2_TRIGGER_GPDMA1_CH5_TCF 23U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH5_TCF */ +#define GPDMA2_TRIGGER_GPDMA1_CH6_TCF 24U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH6_TCF */ +#define GPDMA2_TRIGGER_GPDMA1_CH7_TCF 25U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH7_TCF */ +#define GPDMA2_TRIGGER_GPDMA2_CH0_TCF 26U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH0_TCF */ +#define GPDMA2_TRIGGER_GPDMA2_CH1_TCF 27U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH1_TCF */ +#define GPDMA2_TRIGGER_GPDMA2_CH2_TCF 28U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH2_TCF */ +#define GPDMA2_TRIGGER_GPDMA2_CH3_TCF 29U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH3_TCF */ +#define GPDMA2_TRIGGER_GPDMA2_CH4_TCF 30U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH4_TCF */ +#define GPDMA2_TRIGGER_GPDMA2_CH5_TCF 31U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH5_TCF */ +#define GPDMA2_TRIGGER_GPDMA2_CH6_TCF 32U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH6_TCF */ +#define GPDMA2_TRIGGER_GPDMA2_CH7_TCF 33U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH7_TCF */ +#define GPDMA2_TRIGGER_TIM2_TRGO 34U /*!< GPDMA2 HW Trigger signal is TIM2_TRGO */ +#if defined (TIM15) +#define GPDMA2_TRIGGER_TIM15_TRGO 35U /*!< GPDMA2 HW Trigger signal is TIM15_TRGO */ +#endif /* TIM15 */ +#if defined (TIM12) +#define GPDMA2_TRIGGER_TIM12_TRGO 36U /*!< GPDMA2 HW Trigger signal is TIM12_TRGO */ +#endif /* TIM12 */ +#if defined (LPTIM3) +#define GPDMA2_TRIGGER_LPTIM3_CH1 37U /*!< GPDMA2 HW Trigger signal is LPTIM3_CH1 */ +#define GPDMA2_TRIGGER_LPTIM3_CH2 38U /*!< GPDMA2 HW Trigger signal is LPTIM3_CH2 */ +#endif /* LPTIM3 */ +#if defined (LPTIM4) +#define GPDMA2_TRIGGER_LPTIM4_AIT 39U /*!< GPDMA2 HW Trigger signal is LPTIM4_AIT */ +#endif /* LPTIM4 */ +#if defined (LPTIM5) +#define GPDMA2_TRIGGER_LPTIM5_CH1 40U /*!< GPDMA2 HW Trigger signal is LPTIM5_CH1 */ +#define GPDMA2_TRIGGER_LPTIM5_CH2 41U /*!< GPDMA2 HW Trigger signal is LPTIM5_CH2 */ +#endif /* LPTIM5 */ +#if defined (LPTIM6) +#define GPDMA2_TRIGGER_LPTIM6_CH1 42U /*!< GPDMA2 HW Trigger signal is LPTIM6_CH1 */ +#define GPDMA2_TRIGGER_LPTIM6_CH2 43U /*!< GPDMA2 HW Trigger signal is LPTIM6_CH2 */ +#endif /* LPTIM6 */ +#if defined (COMP1) +#define GPDMA2_TRIGGER_COMP1_OUT 44U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */ +#endif /* COMP1 */ +#if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) \ + || defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx) +#define GPDMA2_TRIGGER_EVENTOUT 45U /*!< GPDMA2 HW Trigger signal is EVENTOUT */ +#endif /* STM32H503xx || STM32H523xx || STM32H533xx || STM32H5F5xx || STM32H5F4xx || + STM32H5E5xx || STM32H5E4xx || STM32H553xx || STM32H543xx */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx) +#define GPDMA2_TRIGGER_COMP2_OUT 46U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPDMA2_TRIGGER_DMA2D_TC_FLAG 47U /*!< GPDMA2 HW Trigger signal is TC_FLAG */ +#define GPDMA2_TRIGGER_DMA2D_CTC_FLAG 48U /*!< GPDMA2 HW Trigger signal is CTC_FLAG */ +#define GPDMA2_TRIGGER_DMA2D_TW_FLAG 49U /*!< GPDMA2 HW Trigger signal is TW_FLAG */ +#define GPDMA2_TRIGGER_DMA2D_GPFLAGS0 50U /*!< GPDMA2 HW Trigger signal is GPFLAGS[0] */ +#define GPDMA2_TRIGGER_DMA2D_GPFLAGS1 51U /*!< GPDMA2 HW Trigger signal is GPFLAGS[1] */ +#define GPDMA2_TRIGGER_DMA2D_GPFLAGS2 52U /*!< GPDMA2 HW Trigger signal is GPFLAGS[2] */ +#define GPDMA2_TRIGGER_DMA2D_GPFLAGS3 53U /*!< GPDMA2 HW Trigger signal is GPFLAGS[3] */ +#define GPDMA2_TRIGGER_JPEG_IFT_FLAG 54U /*!< GPDMA2 HW Trigger signal is JPEG_IFT_FLAG */ +#define GPDMA2_TRIGGER_JPEG_IFNF_FLAG 55U /*!< GPDMA2 HW Trigger signal is JPEG_IFNF_FLAG */ +#define GPDMA2_TRIGGER_JPEG_OFT_FLAG 56U /*!< GPDMA2 HW Trigger signal is JPEG_OFT_FLAG */ +#define GPDMA2_TRIGGER_JPEG_OFNE_FLAG 57U /*!< GPDMA2 HW Trigger signal is JPEG_OFNE_FLAG */ +#define GPDMA2_TRIGGER_JPEG_EOC_FLAG 58U /*!< GPDMA2 HW Trigger signal is JPEG_EOC_FLAG */ +#define GPDMA2_TRIGGER_GFXTIM_EVT1 59U /*!< GPDMA2 HW Trigger signal is GFXTIM_EVT[1] */ +#define GPDMA2_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA2 HW Trigger signal is GFXTIM_EVT[2] */ +#define GPDMA2_TRIGGER_GFXTIM_EVT3 61U /*!< GPDMA2 HW Trigger signal is GFXTIM_EVT[2+4] */ +#define GPDMA2_TRIGGER_GFXTIM_EVT4 62U /*!< GPDMA2 HW Trigger signal is GFXTIM_EVT[4] */ +#define GPDMA2_TRIGGER_LCD_CTRL_SCANLINE 63U /*!< GPDMA2 HW Trigger signal is LCD_CTRL_SCANLINE */ +#define GPDMA2_TRIGGER_GPDMA1_CH8_TCF 64U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH8_TC */ +#define GPDMA2_TRIGGER_GPDMA1_CH9_TCF 65U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH9_TC */ +#define GPDMA2_TRIGGER_GPDMA1_CH10_TCF 66U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH10_TC */ +#define GPDMA2_TRIGGER_GPDMA1_CH11_TCF 67U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH11_TC */ +#define GPDMA2_TRIGGER_GPDMA2_CH8_TCF 68U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH8_TC */ +#define GPDMA2_TRIGGER_GPDMA2_CH9_TCF 69U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH9_TC */ +#define GPDMA2_TRIGGER_GPDMA2_CH10_TCF 70U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH10_TC */ +#define GPDMA2_TRIGGER_GPDMA2_CH11_TCF 71U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH11_TC */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#define GPDMA2_TRIGGER_PLAY1_OUT15 72U /*!< GPDMA2 HW Trigger signal is PLAY1_OUT15 */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx || STM32H553xx || STM32H543xx*/ +/** + * @} + */ + +/** @defgroup DMAEx_Node_Type DMAEx Node Type + * @brief DMAEx Node Type + * @{ + */ +#define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */ +#define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */ +/** + * @} + */ + +/** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port + * @brief DMAEx Linked-List Allocated Port + * @{ + */ +#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */ +#define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */ +/** + * @} + */ + +/** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode + * @brief DMAEx Link Step Mode + * @{ + */ +#define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */ +#define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions + * @brief Linked-List Initialization and De-Initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions + * @brief Linked-List IO Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions + * @brief Linked-List Management Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode); +HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode); + +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pPrevNode, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); + +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNode); +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pOldNode, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); + +HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, + DMA_NodeTypeDef const *const pPrevNode, + DMA_QListTypeDef *const pDestQList); +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList); +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList); + +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pFirstCircularNode); +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, + DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions + * @brief Data Handling, Repeated Block and Trigger Configuration Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, + DMA_DataHandlingConfTypeDef const *const pConfigDataHandling); +HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, + DMA_TriggerConfTypeDef const *const pConfigTrigger); +HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, + DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions + * @brief Suspend and Resume Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function + * @brief FIFO Status Function + * @{ + */ +uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Types DMAEx Private Types + * @brief DMAEx Private Types + * @{ + */ + +/** + * @brief DMA Node in Queue Information Structure Definition. + */ +typedef struct +{ + uint32_t cllr_offset; /* CLLR register offset */ + + uint32_t previousnode_addr; /* Previous node address */ + + uint32_t currentnode_pos; /* Current node position */ + + uint32_t currentnode_addr; /* Current node address */ + + uint32_t nextnode_addr; /* Next node address */ + +} DMA_NodeInQInfoTypeDef; +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Constants DMAEx Private Constants + * @brief DMAEx Private Constants + * @{ + */ +#define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */ + +#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */ +#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */ +#define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */ + +#define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */ +#define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */ +#define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */ + +#define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */ + +#define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */ +#define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */ + +#define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */ +#define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */ + +#define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */ +#define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */ + +#define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */ +#define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */ + +#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ +#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */ +#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */ +#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */ +#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */ +#define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */ +#define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */ +#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007UL) /* CLLR 2D addressing default offset */ +#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005UL) /* CLLR linear addressing default offset */ + +#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ +#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ +#define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */ +#define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMAEx Private Macros + * @brief DMAEx Private Macros + * @{ + */ +#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \ + (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \ + ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \ + ((ALIGNMENT) == DMA_DATA_PACK)) + +#define IS_DMA_DATA_EXCHANGE(EXCHANGE) \ + (((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD))) == 0U) + +#define IS_DMA_REPEAT_COUNT(COUNT) \ + (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos))) + +#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \ + (((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \ + ((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX)) + +#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \ + (((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \ + ((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX)) + +#define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \ + (((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U) + +#define IS_DMA_LINK_STEP_MODE(MODE) \ + (((MODE) == DMA_LSM_FULL_EXECUTION) || \ + ((MODE) == DMA_LSM_1LINK_EXECUTION)) + +#define IS_DMA_TRIGGER_MODE(MODE) \ + (((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER)) + +#define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \ + (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ + ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) + +#define IS_DMA_LINKEDLIST_MODE(MODE) \ + (((MODE) == DMA_LINKEDLIST_NORMAL) || \ + ((MODE) == DMA_LINKEDLIST_CIRCULAR)) + +#define IS_DMA_TRIGGER_POLARITY(POLARITY) \ + (((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \ + ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \ + ((POLARITY) == DMA_TRIG_POLARITY_FALLING)) + +#if defined (PLAY1) +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_PLAY1_OUT15) +#elif defined (I3C2) +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_EVENTOUT) +#else +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_LPTIM6_CH2) +#endif /* I3C2 */ + +#define IS_DMA_NODE_TYPE(TYPE) \ + (((TYPE) == DMA_GPDMA_LINEAR_NODE) || \ + ((TYPE) == DMA_GPDMA_2D_NODE)) +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32H5xx_HAL_DMA_EX_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h new file mode 100644 index 00000000..5278a336 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h @@ -0,0 +1,534 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_EXTI_H +#define STM32H5xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, + HAL_EXTI_RISING_CB_ID = 0x01U, + HAL_EXTI_FALLING_CB_ID = 0x02U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* RisingCallback)(void); /*!< Exti rising callback */ + void (* FallingCallback)(void); /*!< Exti falling callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00U) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01U) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02U) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03U) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04U) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05U) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06U) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07U) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08U) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09U) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0AU) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0BU) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0CU) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0DU) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0EU) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0FU) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10U) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | 0x11U) +#if defined(EXTI_IMR1_IM18) +#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12U) +#endif /* EXTI_IMR1_IM18 */ +#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13U) +#if defined(EXTI_IMR1_IM20) +#define EXTI_LINE_20 (EXTI_DIRECT | EXTI_REG1 | 0x14U) +#endif /* EXTI_IMR1_IM20 */ +#define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15U) +#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16U) +#if defined(EXTI_IMR1_IM23) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17U) +#endif /* EXTI_IMR1_IM23 */ +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18U) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19U) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1AU) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1BU) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1CU) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1DU) +#if defined(EXTI_IMR1_IM30) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1EU) +#endif /* EXTI_IMR1_IM30 */ +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1FU) +#if defined(EXTI_IMR2_IM32) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00U) +#endif /* EXTI_IMR2_IM32 */ +#if defined(EXTI_IMR2_IM33) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01U) +#endif /* EXTI_IMR2_IM33 */ +#if defined(EXTI_IMR2_IM34) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02U) +#endif /* EXTI_IMR2_IM34 */ +#if defined(EXTI_IMR2_IM35) +#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03U) +#endif /* EXTI_IMR2_IM35 */ +#if defined(EXTI_IMR2_IM36) +#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04U) +#endif /* EXTI_IMR2_IM36 */ +#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05U) +#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06U) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07U) +#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | 0x08U) +#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_REG2 | 0x09U) +#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0AU) +#if defined(EXTI_IMR2_IM43) +#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0BU) +#endif /* EXTI_IMR2_IM43 */ +#if defined(EXTI_IMR2_IM44) +#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0CU) +#endif /* EXTI_IMR2_IM44 */ +#if defined(EXTI_IMR2_IM45) +#endif /* EXTI_IMR2_IM45 */ +#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0DU) +#if defined(ETH) +#define EXTI_LINE_46 (EXTI_CONFIG | EXTI_REG2 | 0x0EU) +#endif /* ETH */ +#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_REG2 | 0x0FU) +#if defined(EXTI_IMR2_IM48) +#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10U) +#endif /* EXTI_IMR2_IM48 */ +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) +#define EXTI_LINE_49 (EXTI_CONFIG | EXTI_REG2 | 0x11U) +#else +#define EXTI_LINE_49 (EXTI_DIRECT | EXTI_REG2 | 0x11U) +#endif /* STM32H5E5xx || STM32H5E4xx || STM32H5F5xx || STM32H5F4xx */ +#define EXTI_LINE_50 (EXTI_CONFIG | EXTI_REG2 | 0x12U) +#if defined(EXTI_IMR2_IM51) +#define EXTI_LINE_51 (EXTI_DIRECT | EXTI_REG2 | 0x13U) +#endif /* EXTI_IMR2_IM51 */ +#if defined(EXTI_IMR2_IM52) +#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_REG2 | 0x14U) +#endif /* EXTI_IMR2_IM52 */ +#define EXTI_LINE_53 (EXTI_CONFIG | EXTI_REG2 | 0x15U) +#if defined(EXTI_IMR2_IM54) +#define EXTI_LINE_54 (EXTI_DIRECT | EXTI_REG2 | 0x16U) +#endif /* EXTI_IMR2_IM54 */ +#if defined(EXTI_IMR2_IM55) +#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_REG2 | 0x17U) +#endif /* EXTI_IMR2_IM55 */ +#if defined(EXTI_IMR2_IM56) +#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_REG2 | 0x18U) +#endif /* EXTI_IMR2_IM56 */ +#if defined(EXTI_IMR2_IM57) +#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_REG2 | 0x19U) +#endif /* EXTI_IMR2_IM57 */ +#if defined(EXTI_IMR2_IM58) +#if defined(I3C2) +#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_REG2 | 0x1AU) +#elif defined(COMP1) +#define EXTI_LINE_58 (EXTI_CONFIG | EXTI_REG2 | 0x1AU) +#endif /* I3C2 */ +#endif /* EXTI_IMR2_IM58 */ +#if defined(EXTI_IMR2_IM59) +#define EXTI_LINE_59 (EXTI_CONFIG | EXTI_REG2 | 0x1BU) +#endif /* EXTI_IMR2_IM59 */ +#if defined(EXTI_IMR2_IM60) +#define EXTI_LINE_60 (EXTI_DIRECT | EXTI_REG2 | 0x1CU) +#endif /* EXTI_IMR2_IM60 */ +#if defined(EXTI_IMR2_IM61) +#define EXTI_LINE_61 (EXTI_DIRECT | EXTI_REG2 | 0x1DU) +#endif /* EXTI_IMR2_IM61 */ +#if defined(EXTI_IMR2_IM62) +#define EXTI_LINE_62 (EXTI_DIRECT | EXTI_REG2 | 0x1EU) +#endif /* EXTI_IMR2_IM62 */ +#if defined(EXTI_IMR2_IM63) +#define EXTI_LINE_63 (EXTI_DIRECT | EXTI_REG2 | 0x1FU) +#endif /* EXTI_IMR2_IM63 */ +#if defined(EXTI_IMR3_IM64) +#define EXTI_LINE_64 (EXTI_CONFIG | EXTI_REG3 | 0x20U) +#endif /* EXTI_IMR3_IM64 */ +#if defined(EXTI_IMR3_IM65) +#define EXTI_LINE_65 (EXTI_DIRECT | EXTI_REG3 | 0x21U) +#endif /* EXTI_IMR3_IM65 */ +#if defined(EXTI_IMR3_IM66) +#define EXTI_LINE_66 (EXTI_CONFIG | EXTI_REG3 | 0x22U) +#endif /* EXTI_IMR3_IM66 */ +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000U +#define EXTI_MODE_INTERRUPT 0x00000001U +#define EXTI_MODE_EVENT 0x00000002U +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000U +#define EXTI_TRIGGER_RISING 0x00000001U +#define EXTI_TRIGGER_FALLING 0x00000002U +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000U +#define EXTI_GPIOB 0x00000001U +#define EXTI_GPIOC 0x00000002U +#define EXTI_GPIOD 0x00000003U +#if defined(GPIOE) +#define EXTI_GPIOE 0x00000004U +#endif /* GPIOE */ +#if defined(GPIOF) +#define EXTI_GPIOF 0x00000005U +#endif /* GPIOF */ +#if defined(GPIOG) +#define EXTI_GPIOG 0x00000006U +#endif /* GPIOG */ +#define EXTI_GPIOH 0x00000007U +#if defined(GPIOI) +#define EXTI_GPIOI 0x00000008U +#endif /* GPIOI */ +#if defined(GPIOJ) +#define EXTI_GPIOJ 0x00000009U +#endif /* GPIOJ */ +#if defined(GPIOK) +#define EXTI_GPIOK 0x0000000AU +#endif /* GPIOK */ +/** + * @} + */ + +/** @defgroup EXTI_Line_attributes EXTI line attributes + * @brief EXTI line secure or non-secure and privileged or non-privileged attributes + * @note secure and non-secure attributes are only available from secure state when the system + * implement the security (TZEN=1) + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/*!< Secure line attribute */ +#define EXTI_LINE_SEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000001U) +/*!< Non-secure line attribute */ +#define EXTI_LINE_NSEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000000U) +#endif /* __ARM_FEATURE_CMSE */ +/*!< Privileged line attribute */ +#define EXTI_LINE_PRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000002U) +/*!< Non-privileged line attribute */ +#define EXTI_LINE_NPRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000000U) +/** + * @} + */ +/** @defgroup EXTI_Security_Privilege_Configuration EXTI Security Privilege Configuration + * @brief EXTI security and privilege configurations + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Security and privilege configuration open, can be modified */ +#define EXTI_ATTRIBUTES_UNLOCKED 0x00000000U +/* Security and privilege configuration locked, can no longer be modified */ +#define EXTI_ATTRIBUTES_LOCKED 0x00000001U +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24UL +#define EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16U +#define EXTI_REG1 (0x00UL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01UL << EXTI_REG_SHIFT) +#define EXTI_REG3 (0x02UL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3) +#define EXTI_PIN_MASK 0x0000001FU + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(EXTI_IMR3_IM66) +#define EXTI_LINE_NB 67U +#elif defined(EXTI_IMR2_IM58) +#define EXTI_LINE_NB 59U +#elif defined(EXTI_IMR2_IM57) +#define EXTI_LINE_NB 58U +#else +#define EXTI_LINE_NB 54U +#endif /* EXTI_IMR3_IM66 */ + +/** + * @brief EXTI Mask for secure & privilege attributes + */ +#define EXTI_LINE_ATTR_SEC_MASK 0x100U +#define EXTI_LINE_ATTR_PRIV_MASK 0x200U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | \ + EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) \ + &&((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U)))) + +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \ + ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING)) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U) + +#if defined(GPIOK) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#elif defined(GPIOI) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI)) +#elif defined(GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOH)) +#endif /* GPIOI */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_SEC) == EXTI_LINE_SEC) || \ + (((__ATTRIBUTES__) & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) || \ + (((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \ + (((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \ + (((__ATTRIBUTES__) & ~(EXTI_LINE_SEC|EXTI_LINE_NSEC|EXTI_LINE_PRIV| \ + EXTI_LINE_NPRIV)) == 0U)) + +#else + +#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \ + (((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \ + (((__ATTRIBUTES__) & ~(EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U)) + +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, const EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, + void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions + * @{ + */ + +/* EXTI line attributes management functions **********************************/ +void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes); +HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +HAL_StatusTypeDef HAL_EXTI_LockConfigAttributes(void); +HAL_StatusTypeDef HAL_EXTI_GetLockConfigAttributes(uint32_t *const pLockState); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_EXTI_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h new file mode 100644 index 00000000..929d61d9 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h @@ -0,0 +1,960 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_FLASH_H +#define STM32H5xx_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + HAL_LockTypeDef Lock; /*!< FLASH locking object */ + + uint32_t ErrorCode; /*!< FLASH error code */ + + uint32_t ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not + in IT context */ + + uint32_t Address; /*!< Internal variable to save address selected for program */ + + uint32_t Bank; /*!< Internal variable to save current bank selected during erase in + IT context */ + + uint32_t Sector; /*!< Internal variable to define the current sector which is erasing */ + + uint32_t NbSectorsToErase; /*!< Internal variable to save the remaining sectors to erase in + IT context */ + +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Flag_definition FLASH Flag definition + * @brief Flag definition + * @{ + */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_WBNE FLASH_SR_WBNE /*!< FLASH Write Buffer Not Empty flag */ +#define FLASH_FLAG_DBNE FLASH_SR_DBNE /*!< FLASH data Buffer Not Empty flag */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End Of operation flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write Protection Error flag */ +#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Program Sequence Error flag */ +#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< FLASH Strobe Error flag */ +#define FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< FLASH Inconsistency Error flag */ +#if defined (FLASH_SR_OBKERR) +#define FLASH_FLAG_OBKERR FLASH_SR_OBKERR /*!< FLASH OBK Error flag */ +#define FLASH_FLAG_OBKWERR FLASH_SR_OBKWERR /*!< FLASH OBK Write Error flag */ +#endif /* FLASH_SR_OBKERR */ +#define FLASH_FLAG_OPTCHANGEERR FLASH_SR_OPTCHANGEERR /*!< FLASH Option Byte change Error flag */ +#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC Correction flag */ +#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC Detection flag */ + +#if defined (FLASH_SR_OBKERR) +#define FLASH_FLAG_SR_ERRORS (FLASH_SR_WRPERR | FLASH_SR_PGSERR | \ + FLASH_SR_STRBERR | FLASH_SR_INCERR | \ + FLASH_SR_OBKERR | FLASH_SR_OBKWERR | \ + FLASH_SR_OPTCHANGEERR) +#else +#define FLASH_FLAG_SR_ERRORS (FLASH_SR_WRPERR | FLASH_SR_PGSERR | \ + FLASH_SR_STRBERR | FLASH_SR_INCERR | \ + FLASH_SR_OPTCHANGEERR) +#endif /* FLASH_SR_OBKERR */ +#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) /*!< All FLASH error flags */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupts definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation interrupt enable */ +#define FLASH_IT_WRPERR FLASH_CR_WRPERRIE /*!< Write Protection Error interrupt enable */ +#define FLASH_IT_PGSERR FLASH_CR_PGSERRIE /*!< Program Sequence Error interrupt enable */ +#define FLASH_IT_STRBERR FLASH_CR_STRBERRIE /*!< Strobe Error interrupt enable */ +#define FLASH_IT_INCERR FLASH_CR_INCERRIE /*!< Inconsistency Error interrupt enable */ +#if defined (FLASH_SR_OBKERR) +#define FLASH_IT_OBKERR FLASH_CR_OBKERRIE /*!< OBK Error interrupt enable */ +#define FLASH_IT_OBKWERR FLASH_CR_OBKWERRIE /*!< OBK Write Error interrupt enable */ +#endif /* FLASH_SR_OBKERR */ +#define FLASH_IT_OPTCHANGEERR FLASH_CR_OPTCHANGEERRIE /*!< Option Byte change Error interrupt enable */ +#define FLASH_IT_ECCC FLASH_ECCR_ECCIE /*!< Single ECC Error Correction interrupt enable */ + +#if defined (FLASH_SR_OBKERR) +#define FLASH_IT_ALL (FLASH_IT_EOP | FLASH_IT_WRPERR | \ + FLASH_IT_PGSERR | FLASH_IT_STRBERR | \ + FLASH_IT_INCERR | FLASH_IT_OBKERR | \ + FLASH_IT_OBKWERR | FLASH_IT_OPTCHANGEERR | \ + FLASH_IT_ECCC) /*!< All Flash interrupt sources */ +#else +#define FLASH_IT_ALL (FLASH_IT_EOP | FLASH_IT_WRPERR | \ + FLASH_IT_PGSERR | FLASH_IT_STRBERR | \ + FLASH_IT_INCERR | FLASH_IT_OPTCHANGEERR | \ + FLASH_IT_ECCC) /*!< All Flash interrupt sources */ +#endif /* FLASH_SR_OBKERR */ + +/** + * @} + */ + +/** @defgroup FLASH_Error_Code FLASH Error Code + * @brief FLASH Error Code + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */ +#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */ +#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */ +#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */ +#if defined (FLASH_SR_OBKERR) +#define HAL_FLASH_ERROR_OBK FLASH_FLAG_OBKERR /*!< OBK Error */ +#define HAL_FLASH_ERROR_OBKW FLASH_FLAG_OBKWERR /*!< OBK Write Error */ +#endif /* FLASH_SR_OBKERR */ +#define HAL_FLASH_ERROR_OB_CHANGE FLASH_FLAG_OPTCHANGEERR /*!< Option Byte Change Error */ +#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC /*!< ECC Single Correction Error */ +#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD /*!< ECC Double Detection Error */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Program Type + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_TYPEPROGRAM_QUADWORD FLASH_CR_PG /*!< Program a quad-word + (128-bit) at a specified secure address */ +#define FLASH_TYPEPROGRAM_QUADWORD_NS (FLASH_CR_PG | FLASH_NON_SECURE_MASK) /*!< Program a quad-word + (128-bit) at a specified non-secure address */ +#if defined (FLASH_SR_OBKERR) +#define FLASH_TYPEPROGRAM_QUADWORD_OBK (FLASH_CR_PG | FLASH_OBK) /*!< Program a quad-word + (128-bit) of OBK to current sector */ +#define FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT (FLASH_CR_PG | FLASH_OBK | FLASH_OBKCFGR_ALT_SECT) /*!< Program a quad-word + (128-bit) of OBK to alternate sector */ +#endif /* FLASH_SR_OBKERR */ +#if defined (FLASH_EDATAR_EDATA_EN) +#define FLASH_TYPEPROGRAM_HALFWORD_EDATA (FLASH_CR_PG | FLASH_EDATA_HALFWORD) /*!< Program a flash + high-cycle data half-word (16-bit)at a specified secure address */ +#define FLASH_TYPEPROGRAM_HALFWORD_EDATA_NS (FLASH_CR_PG | FLASH_EDATA_HALFWORD | FLASH_NON_SECURE_MASK) /*!< Program a flash + high-cycle data half-word (16-bit)at a specified non-secure address */ +#define FLASH_TYPEPROGRAM_WORD_EDATA (FLASH_CR_PG | FLASH_EDATA_WORD) /*!< Program a flash + high-cycle data word (32-bit)at a specified secure address */ +#define FLASH_TYPEPROGRAM_WORD_EDATA_NS (FLASH_CR_PG | FLASH_EDATA_WORD | FLASH_NON_SECURE_MASK) /*!< Program a flash + high-cycle data word (32-bit)at a specified non-secure address */ +#endif /* FLASH_EDATAR_EDATA_EN */ +#else +#define FLASH_TYPEPROGRAM_QUADWORD FLASH_CR_PG /*!< Program a quad-word + (128-bit) at a specified address */ +#if defined (FLASH_SR_OBKERR) +#define FLASH_TYPEPROGRAM_QUADWORD_OBK (FLASH_CR_PG | FLASH_OBK) /*!< Program a quad-word + (128-bit) of OBK to current sector */ +#define FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT (FLASH_CR_PG | FLASH_OBK | FLASH_OBKCFGR_ALT_SECT) /*!< Program a quad-word + (128-bit) of OBK to alternate sector */ +#endif /* FLASH_SR_OBKERR */ +#if defined (FLASH_EDATAR_EDATA_EN) +#define FLASH_TYPEPROGRAM_HALFWORD_EDATA (FLASH_CR_PG | FLASH_EDATA_HALFWORD) /*!< Program a flash + high-cycle data half-word (16-bit)at a specified address */ +#define FLASH_TYPEPROGRAM_WORD_EDATA (FLASH_CR_PG | FLASH_EDATA_WORD) /*!< Program a flash + high-cycle data half-word (32-bit)at a specified address */ +#endif /* FLASH_EDATAR_EDATA_EN */ +#endif /* __ARM_FEATURE_CMSE */ +#define FLASH_TYPEPROGRAM_HALFWORD_OTP (FLASH_CR_PG | FLASH_OTP | FLASH_NON_SECURE_MASK) /*!< Program an OTP + half-word (16-bit)at a specified address */ +/** + * @} + */ + +/** @defgroup FLASH_Latency FLASH Latency + * @{ + */ +#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait cycle */ +#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait cycle */ +#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait cycles */ +#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait cycles */ +#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait cycles */ +#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait cycles */ +#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait cycles */ +#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait cycles */ +#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait cycle */ +#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait cycle */ +#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait cycles */ +#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait cycles */ +#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait cycles */ +#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait cycles */ +#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait cycles */ +#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait cycles */ +/** + * @} + */ + +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define FLASH_KEY1 0x45670123U +#define FLASH_KEY2 0xCDEF89ABU +#define FLASH_OPT_KEY1 0x08192A3BU +#define FLASH_OPT_KEY2 0x4C5D6E7FU +#if defined (FLASH_SR_OBKERR) +#define FLASH_OBK_KEY1 0x192A083BU +#define FLASH_OBK_KEY2 0x6E7F4C5DU +#endif /* FLASH_SR_OBKERR */ +/** + * @} + */ + +/** @defgroup FLASH_Sectors FLASH Sectors + * @{ + */ +#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */ +#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */ +#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */ +#if (FLASH_SECTOR_NB >= 32) +#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */ +#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */ +#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */ +#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */ +#define FLASH_SECTOR_12 12U /*!< Sector Number 12 */ +#define FLASH_SECTOR_13 13U /*!< Sector Number 13 */ +#define FLASH_SECTOR_14 14U /*!< Sector Number 14 */ +#define FLASH_SECTOR_15 15U /*!< Sector Number 15 */ +#define FLASH_SECTOR_16 16U /*!< Sector Number 16 */ +#define FLASH_SECTOR_17 17U /*!< Sector Number 17 */ +#define FLASH_SECTOR_18 18U /*!< Sector Number 18 */ +#define FLASH_SECTOR_19 19U /*!< Sector Number 19 */ +#define FLASH_SECTOR_20 20U /*!< Sector Number 20 */ +#define FLASH_SECTOR_21 21U /*!< Sector Number 21 */ +#define FLASH_SECTOR_22 22U /*!< Sector Number 22 */ +#define FLASH_SECTOR_23 23U /*!< Sector Number 23 */ +#define FLASH_SECTOR_24 24U /*!< Sector Number 24 */ +#define FLASH_SECTOR_25 25U /*!< Sector Number 25 */ +#define FLASH_SECTOR_26 26U /*!< Sector Number 26 */ +#define FLASH_SECTOR_27 27U /*!< Sector Number 27 */ +#define FLASH_SECTOR_28 28U /*!< Sector Number 28 */ +#define FLASH_SECTOR_29 29U /*!< Sector Number 29 */ +#define FLASH_SECTOR_30 30U /*!< Sector Number 30 */ +#define FLASH_SECTOR_31 31U /*!< Sector Number 31 */ +#endif /* (FLASH_SECTOR_NB >= 32) */ +#if (FLASH_SECTOR_NB >= 64) +#define FLASH_SECTOR_32 32U /*!< Sector Number 32 */ +#define FLASH_SECTOR_33 33U /*!< Sector Number 33 */ +#define FLASH_SECTOR_34 34U /*!< Sector Number 34 */ +#define FLASH_SECTOR_35 35U /*!< Sector Number 35 */ +#define FLASH_SECTOR_36 36U /*!< Sector Number 36 */ +#define FLASH_SECTOR_37 37U /*!< Sector Number 37 */ +#define FLASH_SECTOR_38 38U /*!< Sector Number 38 */ +#define FLASH_SECTOR_39 39U /*!< Sector Number 39 */ +#define FLASH_SECTOR_40 40U /*!< Sector Number 40 */ +#define FLASH_SECTOR_41 41U /*!< Sector Number 41 */ +#define FLASH_SECTOR_42 42U /*!< Sector Number 42 */ +#define FLASH_SECTOR_43 43U /*!< Sector Number 43 */ +#define FLASH_SECTOR_44 44U /*!< Sector Number 44 */ +#define FLASH_SECTOR_45 45U /*!< Sector Number 45 */ +#define FLASH_SECTOR_46 46U /*!< Sector Number 46 */ +#define FLASH_SECTOR_47 47U /*!< Sector Number 47 */ +#define FLASH_SECTOR_48 48U /*!< Sector Number 48 */ +#define FLASH_SECTOR_49 49U /*!< Sector Number 49 */ +#define FLASH_SECTOR_50 50U /*!< Sector Number 50 */ +#define FLASH_SECTOR_51 51U /*!< Sector Number 51 */ +#define FLASH_SECTOR_52 52U /*!< Sector Number 52 */ +#define FLASH_SECTOR_53 53U /*!< Sector Number 53 */ +#define FLASH_SECTOR_54 54U /*!< Sector Number 54 */ +#define FLASH_SECTOR_55 55U /*!< Sector Number 55 */ +#define FLASH_SECTOR_56 56U /*!< Sector Number 56 */ +#define FLASH_SECTOR_57 57U /*!< Sector Number 57 */ +#define FLASH_SECTOR_58 58U /*!< Sector Number 58 */ +#define FLASH_SECTOR_59 59U /*!< Sector Number 59 */ +#define FLASH_SECTOR_60 60U /*!< Sector Number 60 */ +#define FLASH_SECTOR_61 61U /*!< Sector Number 61 */ +#define FLASH_SECTOR_62 62U /*!< Sector Number 62 */ +#define FLASH_SECTOR_63 63U /*!< Sector Number 63 */ +#endif /* (FLASH_SECTOR_NB >= 64) */ +#if (FLASH_SECTOR_NB >= 128) +#define FLASH_SECTOR_64 64U /*!< Sector Number 64 */ +#define FLASH_SECTOR_65 65U /*!< Sector Number 65 */ +#define FLASH_SECTOR_66 66U /*!< Sector Number 66 */ +#define FLASH_SECTOR_67 67U /*!< Sector Number 67 */ +#define FLASH_SECTOR_68 68U /*!< Sector Number 68 */ +#define FLASH_SECTOR_69 69U /*!< Sector Number 69 */ +#define FLASH_SECTOR_70 70U /*!< Sector Number 70 */ +#define FLASH_SECTOR_71 71U /*!< Sector Number 71 */ +#define FLASH_SECTOR_72 72U /*!< Sector Number 72 */ +#define FLASH_SECTOR_73 73U /*!< Sector Number 73 */ +#define FLASH_SECTOR_74 74U /*!< Sector Number 74 */ +#define FLASH_SECTOR_75 75U /*!< Sector Number 75 */ +#define FLASH_SECTOR_76 76U /*!< Sector Number 76 */ +#define FLASH_SECTOR_77 77U /*!< Sector Number 77 */ +#define FLASH_SECTOR_78 78U /*!< Sector Number 78 */ +#define FLASH_SECTOR_79 79U /*!< Sector Number 79 */ +#define FLASH_SECTOR_80 80U /*!< Sector Number 80 */ +#define FLASH_SECTOR_81 81U /*!< Sector Number 81 */ +#define FLASH_SECTOR_82 82U /*!< Sector Number 82 */ +#define FLASH_SECTOR_83 83U /*!< Sector Number 83 */ +#define FLASH_SECTOR_84 84U /*!< Sector Number 84 */ +#define FLASH_SECTOR_85 85U /*!< Sector Number 85 */ +#define FLASH_SECTOR_86 86U /*!< Sector Number 86 */ +#define FLASH_SECTOR_87 87U /*!< Sector Number 87 */ +#define FLASH_SECTOR_88 88U /*!< Sector Number 88 */ +#define FLASH_SECTOR_89 89U /*!< Sector Number 89 */ +#define FLASH_SECTOR_90 90U /*!< Sector Number 90 */ +#define FLASH_SECTOR_91 91U /*!< Sector Number 91 */ +#define FLASH_SECTOR_92 92U /*!< Sector Number 92 */ +#define FLASH_SECTOR_93 93U /*!< Sector Number 93 */ +#define FLASH_SECTOR_94 94U /*!< Sector Number 94 */ +#define FLASH_SECTOR_95 95U /*!< Sector Number 95 */ +#define FLASH_SECTOR_96 96U /*!< Sector Number 96 */ +#define FLASH_SECTOR_97 97U /*!< Sector Number 97 */ +#define FLASH_SECTOR_98 98U /*!< Sector Number 98 */ +#define FLASH_SECTOR_99 99U /*!< Sector Number 99 */ +#define FLASH_SECTOR_100 100U /*!< Sector Number 100 */ +#define FLASH_SECTOR_101 101U /*!< Sector Number 101 */ +#define FLASH_SECTOR_102 102U /*!< Sector Number 102 */ +#define FLASH_SECTOR_103 103U /*!< Sector Number 103 */ +#define FLASH_SECTOR_104 104U /*!< Sector Number 104 */ +#define FLASH_SECTOR_105 105U /*!< Sector Number 105 */ +#define FLASH_SECTOR_106 106U /*!< Sector Number 106 */ +#define FLASH_SECTOR_107 107U /*!< Sector Number 107 */ +#define FLASH_SECTOR_108 108U /*!< Sector Number 108 */ +#define FLASH_SECTOR_109 109U /*!< Sector Number 109 */ +#define FLASH_SECTOR_110 110U /*!< Sector Number 110 */ +#define FLASH_SECTOR_111 111U /*!< Sector Number 111 */ +#define FLASH_SECTOR_112 112U /*!< Sector Number 112 */ +#define FLASH_SECTOR_113 113U /*!< Sector Number 113 */ +#define FLASH_SECTOR_114 114U /*!< Sector Number 114 */ +#define FLASH_SECTOR_115 115U /*!< Sector Number 115 */ +#define FLASH_SECTOR_116 116U /*!< Sector Number 116 */ +#define FLASH_SECTOR_117 117U /*!< Sector Number 117 */ +#define FLASH_SECTOR_118 118U /*!< Sector Number 118 */ +#define FLASH_SECTOR_119 119U /*!< Sector Number 119 */ +#define FLASH_SECTOR_120 120U /*!< Sector Number 120 */ +#define FLASH_SECTOR_121 121U /*!< Sector Number 121 */ +#define FLASH_SECTOR_122 122U /*!< Sector Number 122 */ +#define FLASH_SECTOR_123 123U /*!< Sector Number 123 */ +#define FLASH_SECTOR_124 124U /*!< Sector Number 124 */ +#define FLASH_SECTOR_125 125U /*!< Sector Number 125 */ +#define FLASH_SECTOR_126 126U /*!< Sector Number 126 */ +#define FLASH_SECTOR_127 127U /*!< Sector Number 127 */ +#endif /* (FLASH_SECTOR_NB >= 128) */ +#if (FLASH_SECTOR_NB >= 256) +#define FLASH_SECTOR_128 128U /*!< Sector Number 128 */ +#define FLASH_SECTOR_129 129U /*!< Sector Number 129 */ +#define FLASH_SECTOR_130 130U /*!< Sector Number 130 */ +#define FLASH_SECTOR_131 131U /*!< Sector Number 131 */ +#define FLASH_SECTOR_132 132U /*!< Sector Number 132 */ +#define FLASH_SECTOR_133 133U /*!< Sector Number 133 */ +#define FLASH_SECTOR_134 134U /*!< Sector Number 134 */ +#define FLASH_SECTOR_135 135U /*!< Sector Number 135 */ +#define FLASH_SECTOR_136 136U /*!< Sector Number 136 */ +#define FLASH_SECTOR_137 137U /*!< Sector Number 137 */ +#define FLASH_SECTOR_138 138U /*!< Sector Number 138 */ +#define FLASH_SECTOR_139 139U /*!< Sector Number 139 */ +#define FLASH_SECTOR_140 140U /*!< Sector Number 140 */ +#define FLASH_SECTOR_141 141U /*!< Sector Number 141 */ +#define FLASH_SECTOR_142 142U /*!< Sector Number 142 */ +#define FLASH_SECTOR_143 143U /*!< Sector Number 143 */ +#define FLASH_SECTOR_144 144U /*!< Sector Number 144 */ +#define FLASH_SECTOR_145 145U /*!< Sector Number 145 */ +#define FLASH_SECTOR_146 146U /*!< Sector Number 146 */ +#define FLASH_SECTOR_147 147U /*!< Sector Number 147 */ +#define FLASH_SECTOR_148 148U /*!< Sector Number 148 */ +#define FLASH_SECTOR_149 149U /*!< Sector Number 149 */ +#define FLASH_SECTOR_150 150U /*!< Sector Number 150 */ +#define FLASH_SECTOR_151 151U /*!< Sector Number 151 */ +#define FLASH_SECTOR_152 152U /*!< Sector Number 152 */ +#define FLASH_SECTOR_153 153U /*!< Sector Number 153 */ +#define FLASH_SECTOR_154 154U /*!< Sector Number 154 */ +#define FLASH_SECTOR_155 155U /*!< Sector Number 155 */ +#define FLASH_SECTOR_156 156U /*!< Sector Number 156 */ +#define FLASH_SECTOR_157 157U /*!< Sector Number 157 */ +#define FLASH_SECTOR_158 158U /*!< Sector Number 158 */ +#define FLASH_SECTOR_159 159U /*!< Sector Number 159 */ +#define FLASH_SECTOR_160 160U /*!< Sector Number 160 */ +#define FLASH_SECTOR_161 161U /*!< Sector Number 161 */ +#define FLASH_SECTOR_162 162U /*!< Sector Number 162 */ +#define FLASH_SECTOR_163 163U /*!< Sector Number 163 */ +#define FLASH_SECTOR_164 164U /*!< Sector Number 164 */ +#define FLASH_SECTOR_165 165U /*!< Sector Number 165 */ +#define FLASH_SECTOR_166 166U /*!< Sector Number 166 */ +#define FLASH_SECTOR_167 167U /*!< Sector Number 167 */ +#define FLASH_SECTOR_168 168U /*!< Sector Number 168 */ +#define FLASH_SECTOR_169 169U /*!< Sector Number 169 */ +#define FLASH_SECTOR_170 170U /*!< Sector Number 170 */ +#define FLASH_SECTOR_171 171U /*!< Sector Number 171 */ +#define FLASH_SECTOR_172 172U /*!< Sector Number 172 */ +#define FLASH_SECTOR_173 173U /*!< Sector Number 173 */ +#define FLASH_SECTOR_174 174U /*!< Sector Number 174 */ +#define FLASH_SECTOR_175 175U /*!< Sector Number 175 */ +#define FLASH_SECTOR_176 176U /*!< Sector Number 176 */ +#define FLASH_SECTOR_177 177U /*!< Sector Number 177 */ +#define FLASH_SECTOR_178 178U /*!< Sector Number 178 */ +#define FLASH_SECTOR_179 179U /*!< Sector Number 179 */ +#define FLASH_SECTOR_180 180U /*!< Sector Number 180 */ +#define FLASH_SECTOR_181 181U /*!< Sector Number 181 */ +#define FLASH_SECTOR_182 182U /*!< Sector Number 182 */ +#define FLASH_SECTOR_183 183U /*!< Sector Number 183 */ +#define FLASH_SECTOR_184 184U /*!< Sector Number 184 */ +#define FLASH_SECTOR_185 185U /*!< Sector Number 185 */ +#define FLASH_SECTOR_186 186U /*!< Sector Number 186 */ +#define FLASH_SECTOR_187 187U /*!< Sector Number 187 */ +#define FLASH_SECTOR_188 188U /*!< Sector Number 188 */ +#define FLASH_SECTOR_189 189U /*!< Sector Number 189 */ +#define FLASH_SECTOR_190 190U /*!< Sector Number 190 */ +#define FLASH_SECTOR_191 191U /*!< Sector Number 191 */ +#define FLASH_SECTOR_192 192U /*!< Sector Number 192 */ +#define FLASH_SECTOR_193 193U /*!< Sector Number 193 */ +#define FLASH_SECTOR_194 194U /*!< Sector Number 194 */ +#define FLASH_SECTOR_195 195U /*!< Sector Number 195 */ +#define FLASH_SECTOR_196 196U /*!< Sector Number 196 */ +#define FLASH_SECTOR_197 197U /*!< Sector Number 197 */ +#define FLASH_SECTOR_198 198U /*!< Sector Number 198 */ +#define FLASH_SECTOR_199 199U /*!< Sector Number 199 */ +#define FLASH_SECTOR_200 200U /*!< Sector Number 200 */ +#define FLASH_SECTOR_201 201U /*!< Sector Number 201 */ +#define FLASH_SECTOR_202 202U /*!< Sector Number 202 */ +#define FLASH_SECTOR_203 203U /*!< Sector Number 203 */ +#define FLASH_SECTOR_204 204U /*!< Sector Number 204 */ +#define FLASH_SECTOR_205 205U /*!< Sector Number 205 */ +#define FLASH_SECTOR_206 206U /*!< Sector Number 206 */ +#define FLASH_SECTOR_207 207U /*!< Sector Number 207 */ +#define FLASH_SECTOR_208 208U /*!< Sector Number 208 */ +#define FLASH_SECTOR_209 209U /*!< Sector Number 209 */ +#define FLASH_SECTOR_210 210U /*!< Sector Number 210 */ +#define FLASH_SECTOR_211 211U /*!< Sector Number 211 */ +#define FLASH_SECTOR_212 212U /*!< Sector Number 212 */ +#define FLASH_SECTOR_213 213U /*!< Sector Number 213 */ +#define FLASH_SECTOR_214 214U /*!< Sector Number 214 */ +#define FLASH_SECTOR_215 215U /*!< Sector Number 215 */ +#define FLASH_SECTOR_216 216U /*!< Sector Number 216 */ +#define FLASH_SECTOR_217 217U /*!< Sector Number 217 */ +#define FLASH_SECTOR_218 218U /*!< Sector Number 218 */ +#define FLASH_SECTOR_219 219U /*!< Sector Number 219 */ +#define FLASH_SECTOR_220 220U /*!< Sector Number 220 */ +#define FLASH_SECTOR_221 221U /*!< Sector Number 221 */ +#define FLASH_SECTOR_222 222U /*!< Sector Number 222 */ +#define FLASH_SECTOR_223 223U /*!< Sector Number 223 */ +#define FLASH_SECTOR_224 224U /*!< Sector Number 224 */ +#define FLASH_SECTOR_225 225U /*!< Sector Number 225 */ +#define FLASH_SECTOR_226 226U /*!< Sector Number 226 */ +#define FLASH_SECTOR_227 227U /*!< Sector Number 227 */ +#define FLASH_SECTOR_228 228U /*!< Sector Number 228 */ +#define FLASH_SECTOR_229 229U /*!< Sector Number 229 */ +#define FLASH_SECTOR_230 230U /*!< Sector Number 230 */ +#define FLASH_SECTOR_231 231U /*!< Sector Number 231 */ +#define FLASH_SECTOR_232 232U /*!< Sector Number 232 */ +#define FLASH_SECTOR_233 233U /*!< Sector Number 233 */ +#define FLASH_SECTOR_234 234U /*!< Sector Number 234 */ +#define FLASH_SECTOR_235 235U /*!< Sector Number 235 */ +#define FLASH_SECTOR_236 236U /*!< Sector Number 236 */ +#define FLASH_SECTOR_237 237U /*!< Sector Number 237 */ +#define FLASH_SECTOR_238 238U /*!< Sector Number 238 */ +#define FLASH_SECTOR_239 239U /*!< Sector Number 239 */ +#define FLASH_SECTOR_240 240U /*!< Sector Number 240 */ +#define FLASH_SECTOR_241 241U /*!< Sector Number 241 */ +#define FLASH_SECTOR_242 242U /*!< Sector Number 242 */ +#define FLASH_SECTOR_243 243U /*!< Sector Number 243 */ +#define FLASH_SECTOR_244 244U /*!< Sector Number 244 */ +#define FLASH_SECTOR_245 245U /*!< Sector Number 245 */ +#define FLASH_SECTOR_246 246U /*!< Sector Number 246 */ +#define FLASH_SECTOR_247 247U /*!< Sector Number 247 */ +#define FLASH_SECTOR_248 248U /*!< Sector Number 248 */ +#define FLASH_SECTOR_249 249U /*!< Sector Number 249 */ +#define FLASH_SECTOR_250 251U /*!< Sector Number 251 */ +#define FLASH_SECTOR_251 251U /*!< Sector Number 251 */ +#define FLASH_SECTOR_252 252U /*!< Sector Number 252 */ +#define FLASH_SECTOR_253 253U /*!< Sector Number 253 */ +#define FLASH_SECTOR_254 254U /*!< Sector Number 254 */ +#define FLASH_SECTOR_255 255U /*!< Sector Number 255 */ +#endif /* (FLASH_SECTOR_NB >= 256) */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__: FLASH Latency + * This parameter can be one of the following values : + * @arg FLASH_LATENCY_0: FLASH Zero wait state + * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_2: FLASH Two wait states + * @arg FLASH_LATENCY_3: FLASH Three wait states + * @arg FLASH_LATENCY_4: FLASH Four wait states + * @arg FLASH_LATENCY_5: FLASH Five wait states + * @arg FLASH_LATENCY_6: FLASH Six wait states + * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_8: FLASH Eight wait states + * @arg FLASH_LATENCY_9: FLASH Nine wait states + * @arg FLASH_LATENCY_10: FLASH Ten wait states + * @arg FLASH_LATENCY_11: FLASH Eleven wait states + * @arg FLASH_LATENCY_12: FLASH Twelve wait states + * @arg FLASH_LATENCY_13: FLASH Thirteen wait states + * @arg FLASH_LATENCY_14: FLASH Fourteen wait states + * @arg FLASH_LATENCY_15: FLASH Fifteen wait states + * @retval none + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * This return value can be one of the following values : + * @arg FLASH_LATENCY_0: FLASH Zero wait state + * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_2: FLASH Two wait states + * @arg FLASH_LATENCY_3: FLASH Three wait states + * @arg FLASH_LATENCY_4: FLASH Four wait states + * @arg FLASH_LATENCY_5: FLASH Five wait states + * @arg FLASH_LATENCY_6: FLASH Six wait states + * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_8: FLASH Eight wait states + * @arg FLASH_LATENCY_9: FLASH Nine wait states + * @arg FLASH_LATENCY_10: FLASH Ten wait states + * @arg FLASH_LATENCY_11: FLASH Eleven wait states + * @arg FLASH_LATENCY_12: FLASH Twelve wait states + * @arg FLASH_LATENCY_13: FLASH Thirteen wait states + * @arg FLASH_LATENCY_14: FLASH Fourteen wait states + * @arg FLASH_LATENCY_15: FLASH Fifteen wait states + */ +#define __HAL_FLASH_GET_LATENCY() READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY) + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ : FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP : End of FLASH Operation Interrupt + * @arg FLASH_IT_WRPERR : Write Protection Error Interrupt + * @arg FLASH_IT_PGSERR : Program Sequence Error Interrupt + * @arg FLASH_IT_STRBERR : Strobe Error Interrupt + * @arg FLASH_IT_INCERR : Inconsistency Error Interrupt + * @arg FLASH_IT_OBKERR : OBK Error Interrupt + * @arg FLASH_IT_OBKWERR : OBK Write Error Interrupt + * @arg FLASH_IT_OPTCHANGEERR : Option Byte Change Error Interrupt + * @arg FLASH_IT_ECCC : Single ECC Error Correction Interrupt + * @retval none + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Enable secure FLASH interrupts from the secure world */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ + { SET_BIT(FLASH->ECCCORR, FLASH_IT_ECCC); } \ + if(((__INTERRUPT__) & FLASH_IT_OPTCHANGEERR) != 0U) \ + { SET_BIT(FLASH->NSCR, FLASH_IT_OPTCHANGEERR); } \ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ + { SET_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~(FLASH_IT_ECCC | \ + FLASH_IT_OPTCHANGEERR)))); }\ + } while(0) +/* Enable non-secure FLASH interrupts from the secure world */ +#define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ + { SET_BIT(FLASH->ECCCORR, FLASH_IT_ECCC); } \ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ + { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); } \ + } while(0) +#else +/* Enable non-secure FLASH interrupts from the non-secure world */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ + { SET_BIT(FLASH->ECCCORR, FLASH_IT_ECCC); } \ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ + { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); } \ + } while(0) +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ : FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP : End of FLASH Operation Interrupt + * @arg FLASH_IT_WRPERR : Write Protection Error Interrupt + * @arg FLASH_IT_PGSERR : Program Sequence Error Interrupt + * @arg FLASH_IT_STRBERR : Strobe Error Interrupt + * @arg FLASH_IT_INCERR : Inconsistency Error Interrupt + * @arg FLASH_IT_OBKERR : OBK Error Interrupt + * @arg FLASH_IT_OBKWERR : OBK Write Error Interrupt + * @arg FLASH_IT_OPTCHANGEERR : Option Byte Change Error Interrupt + * @arg FLASH_IT_ECCC : Single ECC Error Correction Interrupt + * @retval none + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Disable secure FLASH interrupts from the secure world */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ + { CLEAR_BIT(FLASH->ECCCORR, FLASH_IT_ECCC); } \ + if(((__INTERRUPT__) & FLASH_IT_OPTCHANGEERR) != 0U) \ + { CLEAR_BIT(FLASH->NSCR, FLASH_IT_OPTCHANGEERR); } \ + if(((__INTERRUPT__) & (~(FLASH_IT_ECCC | FLASH_IT_OPTCHANGEERR))) \ + != 0U){ CLEAR_BIT(FLASH->SECCR, ((__INTERRUPT__) & \ + (~(FLASH_IT_ECCC | FLASH_IT_OPTCHANGEERR)))); }\ + } while(0) +/* Disable non-secure FLASH interrupts from the secure world */ +#define __HAL_FLASH_DISABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT \ + (FLASH->ECCCORR, FLASH_IT_ECCC); } \ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ + { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC)));\ + } \ + } while(0) +#else +/* Disable non-secure FLASH interrupts from the non-secure world */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT \ + (FLASH->ECCCORR, FLASH_IT_ECCC); } \ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT \ + (FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); } \ + } while(0) +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @param __FLAG__: specifies the FLASH flag to check. + * This parameter can be one of the following values : + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * @arg FLASH_FLAG_WBNE : Write Buffer Not Empty flag + * @arg FLASH_FLAG_EOP : End Of Operation flag + * @arg FLASH_FLAG_WRPERR : Write Protection Error flag + * @arg FLASH_FLAG_PGSERR : Program Sequence Error flag + * @arg FLASH_FLAG_STRBERR : Strobe Error flag + * @arg FLASH_FLAG_INCERR : Inconsistency Error flag + * @arg FLASH_FLAG_OBKERR : OBK Error flag + * @arg FLASH_FLAG_OBKWERR : OBK Write Error flag + * @arg FLASH_FLAG_OPTCHANGEERR : Option Byte Change Error flag + * @arg FLASH_FLAG_ECCC : Single ECC Error Correction flag + * @arg FLASH_FLAG_ECCD : Double Detection ECC Error flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Get secure FLASH flags from the secure world */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC)) != 0U) ? \ + (READ_BIT(FLASH->ECCCORR, (__FLAG__)) == (__FLAG__)) : \ + (((__FLAG__) & (FLASH_FLAG_ECCD)) != 0U) ? \ + (READ_BIT(FLASH->ECCDETR, (__FLAG__)) == (__FLAG__)) : \ + ((((__FLAG__) & (FLASH_FLAG_OPTCHANGEERR)) != 0U) ? \ + (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)) : \ + (READ_BIT(FLASH->SECSR, (__FLAG__)) == (__FLAG__)))) +/* Get non-secure FLASH flags from the secure world */ +#define __HAL_FLASH_GET_FLAG_NS(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC)) != 0U) ? \ + (READ_BIT(FLASH->ECCCORR, (__FLAG__)) == (__FLAG__)) : \ + (((__FLAG__) & (FLASH_FLAG_ECCD)) != 0U) ? \ + (READ_BIT(FLASH->ECCDETR, (__FLAG__)) == (__FLAG__)) : \ + (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)))) +#else +/* Get non-secure FLASH flags from the non-secure world */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC)) != 0U) ? \ + (READ_BIT(FLASH->ECCCORR, (__FLAG__)) == (__FLAG__)) : \ + (((__FLAG__) & (FLASH_FLAG_ECCD)) != 0U) ? \ + (READ_BIT(FLASH->ECCDETR, (__FLAG__)) == (__FLAG__)) : \ + (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__: specifies the FLASH flags to clear. + * This parameter can be one of the following values : + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * @arg FLASH_FLAG_WBNE : Write Buffer Not Empty flag + * @arg FLASH_FLAG_EOP : End Of Operation flag + * @arg FLASH_FLAG_WRPERR : Write Protection Error flag + * @arg FLASH_FLAG_PGSERR : Program Sequence Error flag + * @arg FLASH_FLAG_STRBERR : Strobe Error flag + * @arg FLASH_FLAG_INCERR : Inconsistency Error flag + * @arg FLASH_FLAG_OBKERR : OBK Error flag + * @arg FLASH_FLAG_OBKWERR : OBK Write Error flag + * @arg FLASH_FLAG_OPTCHANGEERR : Option Byte Change Error flag + * @arg FLASH_FLAG_ECCC : Single ECC Error Correction flag + * @arg FLASH_FLAG_ECCD : Double Detection ECC Error flag + * @arg FLASH_FLAG_ALL_ERRORS: All errors flags + * @retval none + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Clear secure FLASH flags from the secure world */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCC) != 0U) { SET_BIT(FLASH->ECCCORR,\ + ((__FLAG__) & FLASH_FLAG_ECCC)); } \ + if(((__FLAG__) & FLASH_FLAG_ECCD) != 0U) { SET_BIT(FLASH->ECCDETR,\ + ((__FLAG__) & FLASH_FLAG_ECCD)); } \ + if(((__FLAG__) & FLASH_FLAG_OPTCHANGEERR) != 0U) { SET_BIT \ + (FLASH->NSCCR, ((__FLAG__) & (FLASH_FLAG_OPTCHANGEERR))); } \ + if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | \ + FLASH_FLAG_OPTCHANGEERR)) != 0U) { WRITE_REG(FLASH->SECCCR, \ + ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | \ + FLASH_FLAG_OPTCHANGEERR))); } \ + } while(0) +/* Clear non-secure FLASH flags from the secure world */ +#define __HAL_FLASH_CLEAR_FLAG_NS(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCC) != 0U) { SET_BIT(FLASH->ECCCORR,\ + ((__FLAG__) & FLASH_FLAG_ECCC)); } \ + if(((__FLAG__) & FLASH_FLAG_ECCD) != 0U) { SET_BIT(FLASH->ECCDETR,\ + ((__FLAG__) & FLASH_FLAG_ECCD)); } \ + if(((__FLAG__) & (~FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG \ + (FLASH->NSCCR, ((__FLAG__) & (~FLASH_FLAG_ECCR_ERRORS))); } \ + } while(0) +#else +/* Clear non-secure FLASH flags from the non-secure world */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCC) != 0U) { SET_BIT(FLASH->ECCCORR,\ + ((__FLAG__) & FLASH_FLAG_ECCC)); } \ + if(((__FLAG__) & FLASH_FLAG_ECCD) != 0U) { SET_BIT(FLASH->ECCDETR,\ + ((__FLAG__) & FLASH_FLAG_ECCD)); } \ + if(((__FLAG__) & (~FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG \ + (FLASH->NSCCR, ((__FLAG__) & (~FLASH_FLAG_ECCR_ERRORS))); } \ + } while(0) +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/* Include FLASH HAL Extension module */ +#include "stm32h5xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* Program operation functions */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +HAL_StatusTypeDef HAL_FLASHEx_PUF_Launch(void); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions */ +uint32_t HAL_FLASH_GetError(void); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 1000U /*!< 1 s */ + +#if defined (FLASH_SR_OBKERR) +#define FLASH_OBK 0x10000000U +#endif /* FLASH_SR_OBKERR */ + +#define FLASH_OTP 0x20000000U + +#if defined (FLASH_EDATAR_EDATA_EN) +#define FLASH_EDATA_HALFWORD 0x40000000U +#define FLASH_EDATA_WORD 0x60000000U +#endif /* FLASH_EDATAR_EDATA_EN */ + +#define FLASH_NON_SECURE_MASK 0x80000000U + +#if !defined(STM32H5F5xx) +#define FLASH_EDATA_SECTOR_NB 8U /*!< Maximum number of FLASH high-cycle data sectors */ +#else +#define FLASH_EDATA_SECTOR_NB 16U /*!< Maximum number of FLASH high-cycle data sectors */ +#endif /* STM32H5F5xx */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined (FLASH_SR_OBKERR) && defined (FLASH_EDATAR_EDATA_EN) +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_OTP) || \ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_EDATA) || \ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_EDATA_NS) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD_EDATA) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD_EDATA_NS) || \ + ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_OBK) || \ + ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT)) +#else +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_OTP)) +#endif /* FLASH_SR_OBKERR && FLASH_EDATAR_EDATA_EN */ +#else +#if defined (FLASH_SR_OBKERR) && defined (FLASH_EDATAR_EDATA_EN) +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_OTP) || \ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_EDATA) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD_EDATA) || \ + ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_OBK) || \ + ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT)) +#else +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_OTP)) +#endif /* FLASH_SR_OBKERR && FLASH_EDATAR_EDATA_EN */ +#endif /* __ARM_FEATURE_CMSE */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_USER_MEM_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) || \ + (((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE)))) +#if defined (FLASH_SR_OBKERR) +#define IS_FLASH_OBK_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_OBK_BASE) && \ + ((ADDRESS) < (FLASH_OBK_BASE+FLASH_OBK_SIZE))) || \ + (((ADDRESS) >= FLASH_OBK_BASE_NS) && \ + ((ADDRESS) < (FLASH_OBK_BASE_NS+FLASH_OBK_SIZE)))) +#endif /* FLASH_SR_OBKERR */ +#if defined (FLASH_EDATAR_EDATA_EN) +#define IS_FLASH_EDATA_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_EDATA_BASE_S) && \ + ((ADDRESS) < (FLASH_EDATA_BASE_S+FLASH_EDATA_SIZE))) || \ + (((ADDRESS) >= FLASH_EDATA_BASE_NS) && \ + ((ADDRESS) < (FLASH_EDATA_BASE_NS+FLASH_EDATA_SIZE)))) +#endif /* FLASH_EDATAR_EDATA_EN */ +#else +#define IS_FLASH_USER_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && \ + ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) +#if defined (FLASH_SR_OBKERR) +#define IS_FLASH_OBK_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OBK_BASE) && \ + ((ADDRESS) < (FLASH_OBK_BASE + FLASH_OBK_SIZE))) +#endif /* FLASH_SR_OBKERR */ +#if defined (FLASH_EDATAR_EDATA_EN) +#define IS_FLASH_EDATA_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_EDATA_BASE_NS) && \ + ((ADDRESS) < (FLASH_EDATA_BASE_NS + FLASH_EDATA_SIZE))) +#endif /* FLASH_EDATAR_EDATA_EN */ +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OTP_BASE) && \ + ((ADDRESS) < (FLASH_OTP_BASE + FLASH_OTP_SIZE))) + +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) + +#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2)) + +#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_NB) + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ + ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || \ + ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || \ + ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || \ + ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || \ + ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || \ + ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || \ + ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || \ + ((LATENCY) == FLASH_LATENCY_15)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_SECURE_OPERATION() ((pFlash.ProcedureOnGoing & FLASH_NON_SECURE_MASK) == 0U) +#else +#define IS_FLASH_SECURE_OPERATION() (1U == 0U) +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_FLASH_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h new file mode 100644 index 00000000..fe46174f --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h @@ -0,0 +1,1178 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_FLASH_EX_H +#define STM32H5xx_HAL_FLASH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or sector Erase. + This parameter can be a value of @ref FLASH_Type_Erase */ + + uint32_t Banks; /*!< Select bank to erase. + This parameter can be a value of @ref FLASH_Banks + (FLASH_BANK_BOTH should be used only for mass erase) */ + + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled + This parameter can be a value of @ref FLASH_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be erased. + This parameter can be a value between 1 and (max number of sectors in the bank - + value of initial sector)*/ +} FLASH_EraseInitTypeDef; + + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a value of @ref FLASH_Option_Type */ + + uint32_t ProductState; /*!< Set the product state. + This parameter can be a value of @ref FLASH_OB_Product_State */ + + uint32_t USERType; /*!< Select the User Option Byte(s) to be configured (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_Type */ + + uint32_t USERConfig; /*!< Value of the User Option Byte (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, + @ref FLASH_OB_USER_BORH_EN, @ref FLASH_OB_USER_IWDG_SW, + @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nRST_STOP, + @ref FLASH_OB_USER_nRST_STANDBY, @ref FLASH_OB_USER_IO_VDD_HSLV, + @ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_IWDG_STOP, + @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_BOOT_UBE, + @ref FLASH_OB_USER_SWAP_BANK */ + + uint32_t USERConfig2; /*!< Value of the User Option Byte (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_SRAM1_3_RST, + @ref FLASH_OB_USER_SRAM2_RST, @ref FLASH_OB_USER_BKPRAM_ECC, + @ref FLASH_OB_USER_SRAM3_ECC, @ref FLASH_OB_USER_SRAM2_ECC, + @ref FLASH_OB_USER_SRAM1_RST, @ref FLASH_OB_USER_SRAM1_ECC, + @ref FLASH_OB_USER_USBPD_DIS, @ref FLASH_OB_USER_TZEN */ + + uint32_t Banks; /*!< Select banks for WRP , HDP and secure area configuration. + This parameter must be a value of @ref FLASH_Banks */ + + uint32_t WRPState; /*!< Write protection activation or deactivation. + This parameter can be a value of @ref FLASH_WRP_State */ + + uint64_t WRPSector; /*!< Specifies the sector(s) to be write protected. + The value of this parameter depend on device used within the same series */ + + uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured: secure or non-secure. + This parameter must be a value of @ref FLASH_OB_BOOT_CONFIG enumeration */ + + uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR). + This parameter must be a value between 0x0 and 0xFFFFFF00 */ + + uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK). + This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */ + + uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked. + This parameter must be a value of @ref FLASH_OTP_Blocks */ + + uint32_t HDPStartSector; /*!< Start sector of HDP area (used for OPTIONBYTE_HDP). + This parameter must be a value between 0 and (max number of sectors in the bank - 1) */ + + uint32_t HDPEndSector; /*!< End sector of HDP area (used for OPTIONBYTE_HDP). + This parameter must be a value between 0 and (max number of sectors in the bank - 1) */ + + uint32_t EDATASize; /*!< Specifies the number of Flash high-cycle sectors. + This parameter must be a value between 0 and 8 (sectors) */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t WMSecStartSector; /*!< Start sector of secure area (used for OPTIONBYTE_WMSEC). + This parameter must be a value between 0 and (max number of sectors in the bank - 1)*/ + uint32_t WMSecEndSector; /*!< End sector of secure area (used for OPTIONBYTE_WMSEC). + This parameter must be a value between 0 and (max number of sectors in the bank - 1)*/ +#endif /* __ARM_FEATURE_CMSE */ + +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASHEx Block-based attributes structure definition + */ +typedef struct +{ + uint32_t Bank; /*!< Selection of the associated bank of Block-based Area. + This parameter must be a value of @ref FLASH_Banks */ + uint32_t BBAttributesType; /*!< Block-Based Attributes type. + This parameter must be a value of @ref FLASH_BB_Attributes + */ + uint32_t BBAttributes_array[FLASH_BLOCKBASED_NB_REG]; /*!< Each bit specifies the block-based attribute configuration + of a sector: + 0 means sector non-protected, 1 means sector protected. + Protection (secure or privilege) depends on + BBAttributesType value */ +} FLASH_BBAttributesTypeDef; + +/** + * @brief FLASHEx Operation structure definition + */ +typedef struct +{ + uint32_t OperationType; /*!< Flash operation Type. + This parameter must be a value of @ref FLASH_Operation_Type */ + uint32_t FlashArea; /*!< Flash operation memory area. + This parameter must be a value of @ref FLASH_Operation_Area */ + uint32_t Address; /*!< Flash operation Address offset. + This parameter is given by bank, and must be a value between 0x0 and 0xFFFF0 */ +} FLASH_OperationTypeDef; + +/** + * @brief FLASH HDP Extension structure definition + */ +typedef struct +{ + uint32_t Banks; /*!< Selection of the associated bank of HDP Area. + This parameter must be a value of @ref FLASH_Banks */ + uint32_t NbSectors; /*!< Number of sectors to be HDP extended. + This parameter can be a value between 1 and max number of sectors in the bank */ +} FLASH_HDPExtensionTypeDef; + +/** + * @brief ECC Info Structure definition + */ +typedef struct +{ + uint32_t Area; /*!< Area from which an ECC was detected. + This parameter can be a value of @ref FLASH_ECC_Area */ + + uint32_t Address; /*!< ECC error address */ + + uint32_t Data; /*!< ECC failing data */ +} FLASH_EccInfoTypeDef; + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants + * @{ + */ + +/** @defgroup FLASH_Type_Erase FLASH Type Erase + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_TYPEERASE_SECTORS FLASH_CR_SER /*!< Secure flash sectors + erase activation */ +#define FLASH_TYPEERASE_SECTORS_NS (FLASH_CR_SER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash + sectors erase activation */ +#define FLASH_TYPEERASE_MASSERASE (FLASH_CR_BER | FLASH_CR_MER) /*!< Secure flash mass erase + activation */ +#define FLASH_TYPEERASE_MASSERASE_NS (FLASH_CR_BER | FLASH_CR_MER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash mass + erase activation */ +#if defined (FLASH_SR_OBKERR) +#define FLASH_TYPEERASE_OBK_ALT FLASH_OBKCFGR_ALT_SECT_ERASE /*!< Flash OBK erase + activation */ +#endif /* FLASH_SR_OBKERR */ +#else +#define FLASH_TYPEERASE_SECTORS FLASH_CR_SER /*!< Flash sectors erase + activation */ +#define FLASH_TYPEERASE_MASSERASE (FLASH_CR_BER | FLASH_CR_MER) /*!< Flash mass erase + activation */ +#if defined (FLASH_SR_OBKERR) +#define FLASH_TYPEERASE_OBK_ALT (FLASH_OBKCFGR_ALT_SECT_ERASE | FLASH_NON_SECURE_MASK) /*!< Flash OBK erase + activation */ +#endif /* FLASH_SR_OBKERR */ +#endif /* __ARM_FEATURE_CMSE */ + +/** @defgroup FLASH_ECC_Area FLASH ECC Area + * @brief FLASH ECC Area + * @{ + */ +#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */ +#define FLASH_ECC_AREA_USER_BANK2 FLASH_ECCR_BK_ECC /*!< FLASH bank 2 area */ +#define FLASH_ECC_AREA_SYSTEM FLASH_ECCR_SYSF_ECC /*!< System FLASH area */ +#if defined (FLASH_SR_OBKERR) +#define FLASH_ECC_AREA_OBK FLASH_ECCR_OBK_ECC /*!< FLASH OBK area */ +#endif /* FLASH_SR_OBKERR */ +#define FLASH_ECC_AREA_OTP FLASH_ECCR_OTP_ECC /*!< FLASH OTP area */ +#if defined (FLASH_EDATAR_EDATA_EN) +#define FLASH_ECC_AREA_EDATA_BANK1 FLASH_ECCR_DATA_ECC /*!< FLASH high-cycle data area */ +#define FLASH_ECC_AREA_EDATA_BANK2 (FLASH_ECCR_DATA_ECC | FLASH_ECCR_BK_ECC) /*!< FLASH high-cycle data area */ +#endif /* FLASH_EDATAR_EDATA_EN */ +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASH_Option_Type FLASH Option Type + * @{ + */ +#define OPTIONBYTE_WRP 0x0001U /*!< WRP option byte configuration */ +#define OPTIONBYTE_PROD_STATE 0x0002U /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER 0x0004U /*!< USER option byte configuration */ +#define OPTIONBYTE_BOOTADDR 0x0008U /*!< BOOT address option byte configuration */ +#define OPTIONBYTE_BOOT_LOCK 0x0010U /*!< Boot lock option byte configuration */ +#define OPTIONBYTE_OTP_LOCK 0x0020U /*!< OTP Lock option byte configuration */ +#define OPTIONBYTE_HDP 0x0040U /*!< Hide Protection area option byte configuration */ +#if defined (FLASH_EDATAR_EDATA_EN) +#define OPTIONBYTE_EDATA 0x0080U /*!< Flash high-cycle data area option byte configuration */ +#endif /* FLASH_EDATAR_EDATA_EN */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define OPTIONBYTE_WMSEC 0x0200U /*!< Watermark-based secure area option byte configuration */ +#endif /* __ARM_FEATURE_CMSE */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\ + OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\ + OPTIONBYTE_HDP | OPTIONBYTE_EDATA | OPTIONBYTE_WMSEC) /*!< All option +byte configuration */ +#else +#if defined (FLASH_EDATAR_EDATA_EN) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\ + OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\ + OPTIONBYTE_HDP | OPTIONBYTE_EDATA) /*!< All option byte configuration */ +#else +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\ + OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\ + OPTIONBYTE_HDP) /*!< All option byte configuration */ +#endif /* FLASH_EDATAR_EDATA_EN */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_Type FLASH OB USER Type + * @{ + */ +#define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */ +#define OB_USER_BORH_EN 0x00000002U /*!< BOR high enable status */ +#define OB_USER_IWDG_SW 0x00000004U /*!< Independent watchdog selection */ +#define OB_USER_WWDG_SW 0x00000008U /*!< Window watchdog selection */ +#define OB_USER_NRST_STOP 0x00000010U /*!< Reset generated when entering the stop mode */ +#define OB_USER_NRST_STDBY 0x00000020U /*!< Reset generated when entering the standby mode */ +#define OB_USER_IO_VDD_HSLV 0x00000040U /*!< High speed IO at low voltage configuration bit */ +#define OB_USER_IO_VDDIO2_HSLV 0x00000080U /*!< High speed IO2 at low voltage configuration bit */ +#define OB_USER_IWDG_STOP 0x00000100U /*!< Independent watchdog counter freeze in stop mode */ +#define OB_USER_IWDG_STDBY 0x00000200U /*!< Independent watchdog counter freeze in standby mode */ +#if defined (FLASH_OPTSR_BOOT_UBE) +#define OB_USER_BOOT_UBE 0x00000400U /*!< Unique Boot entry */ +#endif /* FLASH_OPTSR_BOOT_UBE */ +#define OB_USER_SWAP_BANK 0x00000800U /*!< Swap banks */ + +#if defined (FLASH_OPTSR2_SRAM1_3_RST) +#define OB_USER_SRAM1_3_RST 0x00001000U /*!< SRAM1 and SRAM3 erase upon system reset */ +#elif defined (FLASH_OPTSR2_SRAM1_3_4_5_RST) +#define OB_USER_SRAM1_3_4_5_RST 0x00001000U /*!< SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset */ +#endif /* FLASH_OPTSR2_SRAM1_3_RST */ +#if defined (FLASH_OPTSR2_SRAM1_RST) +#define OB_USER_SRAM1_RST 0x00001000U /*!< SRAM1 Erase when system reset */ +#endif /* FLASH_OPTSR2_SRAM1_RST */ +#define OB_USER_SRAM2_RST 0x00002000U /*!< SRAM2 Erase when system reset */ +#define OB_USER_BKPRAM_ECC 0x00004000U /*!< Backup RAM ECC detection and correction enable */ +#define OB_USER_SRAM3_ECC 0x00008000U /*!< SRAM3 ECC detection and correction enable */ +#define OB_USER_SRAM2_ECC 0x00010000U /*!< SRAM2 ECC detection and correction enable */ +#define OB_USER_SRAM1_ECC 0x00020000U /*!< SRAM1 ECC detection and correction enable */ +#if defined (FLASH_OPTSR2_USBPD_DIS) +#define OB_USER_USBPD_DIS 0x00040000U /*!< USB power delivery configuration enable */ +#endif /*FLASH_OPTSR2_USBPD_DIS*/ +#if defined (FLASH_OPTSR2_TZEN) +#define OB_USER_TZEN 0x00080000U /*!< Global TrustZone security enable */ +#endif /* FLASH_OPTSR2_TZEN */ +#if defined (FLASH_OPTSR2_HUK_PUF) +#define OB_USER_HUK_PUF 0x00100000U /*!< HUK source sent to the SAES is RHUK/PUF */ +#endif /* FLASH_OPTSR2_HUK_PUF */ + +#if defined (FLASH_OPTSR2_SRAM1_3_RST) && defined (FLASH_OPTSR_BOOT_UBE) && defined (FLASH_OPTSR2_USBPD_DIS) +#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\ + OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\ + OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\ + OB_USER_IWDG_STDBY | OB_USER_BOOT_UBE | OB_USER_SWAP_BANK |\ + OB_USER_SRAM1_3_RST | OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC |\ + OB_USER_SRAM3_ECC | OB_USER_SRAM2_ECC | OB_USER_USBPD_DIS |\ + OB_USER_TZEN) +#elif defined (FLASH_OPTSR2_SRAM1_3_4_5_RST) && defined (FLASH_OPTSR_BOOT_UBE) && defined (FLASH_OPTSR2_USBPD_DIS) +#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\ + OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\ + OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\ + OB_USER_IWDG_STDBY | OB_USER_BOOT_UBE | OB_USER_SWAP_BANK |\ + OB_USER_SRAM1_3_4_5_RST | OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC |\ + OB_USER_SRAM3_ECC | OB_USER_SRAM2_ECC | OB_USER_USBPD_DIS |\ + OB_USER_TZEN | OB_USER_HUK_PUF) +#else +#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\ + OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\ + OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\ + OB_USER_IWDG_STDBY | OB_USER_SWAP_BANK | OB_USER_SRAM1_RST |\ + OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC | OB_USER_SRAM3_ECC |\ + OB_USER_SRAM2_ECC | OB_USER_SRAM1_ECC) +#endif /* FLASH_OPTSR2_SRAM1_3_RST && FLASH_OPTSR_BOOT_UBE */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH BOR Reset Level + * @{ + */ +#define OB_BOR_LEVEL_1 0U /*!< Reset level 1 threshold */ +#define OB_BOR_LEVEL_2 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level 2 threshold */ +#define OB_BOR_LEVEL_3 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level 3 threshold */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_BORH_EN FLASH BOR High Enable Status + * @{ + */ +#define OB_BORH_DISABLE 0x00000000U /*!< BOR high status bit disabled */ +#define OB_BORH_ENABLE FLASH_OPTSR_BORH_EN /*!< BOR high status bit enabled */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type + * @{ + */ +#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ +#define OB_IWDG_SW FLASH_OPTSR_IWDG_SW /*!< Software independent watchdog */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type + * @{ + */ +#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ +#define OB_WWDG_SW FLASH_OPTSR_WWDG_SW /*!< Software window watchdog */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes nRST_STOP + * @{ + */ +#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering in stop mode */ +#define OB_STOP_NORST FLASH_OPTSR_NRST_STOP /*!< No reset generated when entering in stop mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes nRST_STDBY + * @{ + */ +#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering in standby mode */ +#define OB_STANDBY_NORST FLASH_OPTSR_NRST_STDBY /*!< No reset generated when entering in standby mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Product_State FLASH Product State + * @{ + */ +#define OB_PROD_STATE_OPEN (0xEDUL << FLASH_OPTSR_PRODUCT_STATE_Pos) +#define OB_PROD_STATE_PROVISIONING (0x17UL << FLASH_OPTSR_PRODUCT_STATE_Pos) +#define OB_PROD_STATE_IROT_PROVISIONED (0x2EUL << FLASH_OPTSR_PRODUCT_STATE_Pos) +#define OB_PROD_STATE_TZ_CLOSED (0xC6UL << FLASH_OPTSR_PRODUCT_STATE_Pos) +#define OB_PROD_STATE_CLOSED (0x72UL << FLASH_OPTSR_PRODUCT_STATE_Pos) +#define OB_PROD_STATE_LOCKED (0x5CUL << FLASH_OPTSR_PRODUCT_STATE_Pos) +#define OB_PROD_STATE_REGRESSION (0x9AUL << FLASH_OPTSR_PRODUCT_STATE_Pos) +#define OB_PROD_STATE_NS_REGRESSION (0xA3UL << FLASH_OPTSR_PRODUCT_STATE_Pos) +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IO_VDD_HSLV FLASH Option Bytes VDD IO HSLV + * @{ + */ +#define OB_IO_VDD_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDD voltage feature disabled */ +#define OB_IO_VDD_HSLV_ENABLE FLASH_OPTSR_IO_VDD_HSLV /*!< High-speed IO at low VDD voltage feature enabled */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IO_VDDIO2_HSLV FLASH Option Bytes VDDIO2 IO HSLV + * @{ + */ +#define OB_IO_VDDIO2_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDDIO2 voltage feature + disabled */ +#define OB_IO_VDDIO2_HSLV_ENABLE FLASH_OPTSR_IO_VDDIO2_HSLV /*!< High-speed IO at low VDDIO2 voltage feature + enabled */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH IWDG Counter Freeze in STOP + * @{ + */ +#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< IWDG counter frozen in STOP mode */ +#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_IWDG_STOP /*!< IWDG counter active in STOP mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH IWDG Counter Freeze in STANDBY + * @{ + */ +#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< IWDG counter frozen in STANDBY mode */ +#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_IWDG_STDBY /*!< IWDG counter active in STANDBY mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_BOOT_UBE FLASH OB Boot UBE + * @{ + */ +#if defined (FLASH_OPTSR_BOOT_UBE) +#define OB_UBE_OEM_IROT (0xB4UL << FLASH_OPTSR_BOOT_UBE_Pos) /*!< OEM-iRoT (user flash) selected */ +#define OB_UBE_ST_IROT (0xC3UL << FLASH_OPTSR_BOOT_UBE_Pos) /*!< ST-iRoT (system flash) selected */ +#endif /* FLASH_OPTSR_BOOT_UBE */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_SWAP_BANK FLASH OB SWAP BANK + * @{ + */ +#define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */ +#define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK /*!< Bank swap enabled */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_SRAM1_3_RST FLASH Option Bytes SRAM1_3 Erase On Reset + * @{ + */ +#if defined (FLASH_OPTSR2_SRAM1_3_RST) +#define OB_SRAM1_3_RST_ERASE 0x00000000U /*!< SRAM1 and SRAM3 erased when a system reset occurs */ +#define OB_SRAM1_3_RST_NOT_ERASE FLASH_OPTSR2_SRAM1_3_RST /*!< SRAM1 and SRAM3 are not erased when a system reset + occurs */ +#endif /* FLASH_OPTSR2_SRAM1_3_RST */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_SRAM1_3_4_5_RST FLASH Option Bytes SRAM1_3 Erase On Reset + * @{ + */ +#if defined (FLASH_OPTSR2_SRAM1_3_4_5_RST) +#define OB_SRAM1_3_4_5_RST_ERASE 0x00000000U /*!< SRAM1, SRAM3, SRAM4, and SRAM5 erased when a system reset occurs */ +#define OB_SRAM1_3_4_5_RST_NOT_ERASE FLASH_OPTSR2_SRAM1_3_4_5_RST /*!< SRAM1, SRAM3, SRAM4, and SRAM5 when a system reset occurs */ +#endif /* FLASH_OPTSR2_SRAM1_3_4_5_RST */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_SRAM1_RST FLASH Option Bytes SRAM1 Erase On Reset + * @{ + */ +#if defined (FLASH_OPTSR2_SRAM1_RST) +#define OB_SRAM1_RST_ERASE 0x00000000U /*!< SRAM1 erased when a system reset occurs */ +#define OB_SRAM1_RST_NOT_ERASE FLASH_OPTSR2_SRAM1_RST /*!< SRAM1 is not erased when a system reset occurs */ +#endif /* FLASH_OPTSR2_SRAM1_RST */ +/** + * @} + */ + + +/** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes SRAM2 Erase On Reset + * @{ + */ +#define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset occurs */ +#define OB_SRAM2_RST_NOT_ERASE FLASH_OPTSR2_SRAM2_RST /*!< SRAM2 is not erased when a system reset occurs */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_BKPRAM_ECC FLASH Option Bytes User BKPRAM ECC check + * @{ + */ +#define OB_BKPRAM_ECC_ENABLE 0x00000000U /*!< BKPRAM ECC check enable */ +#define OB_BKPRAM_ECC_DISABLE FLASH_OPTSR2_BKPRAM_ECC /*!< BKPRAM ECC check disable */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_SRAM3_ECC FLASH Option Bytes User SRAM3 ECC check + * @{ + */ +#if defined (FLASH_OPTSR2_SRAM3_ECC) +#define OB_SRAM3_ECC_ENABLE 0x00000000U /*!< SRAM3 ECC check enable */ +#define OB_SRAM3_ECC_DISABLE FLASH_OPTSR2_SRAM3_ECC /*!< SRAM3 ECC check disable */ +#endif /* FLASH_OPTSR2_SRAM3_ECC */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_SRAM2_ECC FLASH Option Bytes User SRAM2 ECC check + * @{ + */ +#define OB_SRAM2_ECC_ENABLE 0x00000000U /*!< SRAM2 ECC check enable */ +#define OB_SRAM2_ECC_DISABLE FLASH_OPTSR2_SRAM2_ECC /*!< SRAM2 ECC check disable */ +/** + * @} + */ + +/** @defgroup FLASH_OB_HUK_PUF FLASH Option Bytes User PUF STATE check + * @{ + */ +#if defined (FLASH_SR_PUF_STATE) +#define FLASH_FLAG_PUF_NOT_READY 0x00000000U /*!< PUF is not ready. Retry PUF_LAUNCH */ +#define FLASH_FLAG_PUF_READY FLASH_SR_PUF_STATE /*!< PUF is ready for use */ +#endif /* FLASH_SR_PUF_STATE */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_SRAM1_ECC FLASH Option Bytes User SRAM1 ECC check + * @{ + */ +#if defined (FLASH_OPTSR2_SRAM1_ECC) +#define OB_SRAM1_ECC_ENABLE 0x00000000U /*!< SRAM1 ECC check enable */ +#define OB_SRAM1_ECC_DISABLE FLASH_OPTSR2_SRAM1_ECC /*!< SRAM1 ECC check disable */ +#endif /* FLASH_OPTSR2_SRAM1_ECC */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_USBPD_DIS FLASH Option Bytes USB power delivery configuration + * @{ + */ +#if defined (FLASH_OPTSR2_USBPD_DIS) +#define OB_USBPD_DIS_ENABLE 0x00000000U /*!< USB power delivery check enable */ +#define OB_USBPD_DIS_DISABLE FLASH_OPTSR2_USBPD_DIS /*!< USB power delivery check disable */ +#endif /* FLASH_OPTSR2_USBPD_DIS */ +/** + * @} + */ +/** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes Global TrustZone + * @{ + */ +#if defined (FLASH_OPTSR2_TZEN) +#define OB_TZEN_DISABLE (0xC3UL << FLASH_OPTSR2_TZEN_Pos) /*!< Global TrustZone security disabled */ +#define OB_TZEN_ENABLE (0xB4UL << FLASH_OPTSR2_TZEN_Pos) /*!< Global TrustZone security enabled */ +#endif /* FLASH_OPTSR2_TZEN */ +/** + * @} + */ + +/** @defgroup FLASH_OPTSR2_HUK_PUF FLASH Option Bytes Global TrustZone + * @{ + */ +#if defined (FLASH_OPTSR2_HUK_PUF) +#define OB_UNIQUE_KEY_HUK 0x00000000U /*!< HUK source is RHUK */ +#define OB_UNIQUE_KEY_PUF FLASH_OPTSR2_HUK_PUF /*!< HUK source is PUF */ +#endif /* FLASH_OPTSR2_TZEN */ +/** + * @} + */ + +/** @defgroup FLASH_Banks FLASH Banks + * @{ + */ +#define FLASH_BANK_1 0x00000001U /*!< Bank 1 */ +#define FLASH_BANK_2 0x00000002U /*!< Bank 2 */ +#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Write_Protection_Sectors FLASH Option Bytes Write Protection Sectors + * @{ + */ +#if (FLASH_SECTOR_NB == 8) +#define OB_WRP_SECTOR_0 0x0000000000000001U /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 0x0000000000000002U /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 0x0000000000000004U /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 0x0000000000000008U /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_4 0x0000000000000010U /*!< Write protection of Sector4 */ +#define OB_WRP_SECTOR_5 0x0000000000000020U /*!< Write protection of Sector5 */ +#define OB_WRP_SECTOR_6 0x0000000000000040U /*!< Write protection of Sector6 */ +#define OB_WRP_SECTOR_7 0x0000000000000080U /*!< Write protection of Sector7 */ +#define OB_WRP_SECTOR_ALL 0x00000000000000FFU /*!< Write protection of all Sectors */ +#else +#define OB_WRP_SECTOR_0TO3 0x0000000000000001U /*!< Write protection of Sector0 to Sector3 */ +#define OB_WRP_SECTOR_4TO7 0x0000000000000002U /*!< Write protection of Sector4 to Sector7 */ +#define OB_WRP_SECTOR_8TO11 0x0000000000000004U /*!< Write protection of Sector8 to Sector11 */ +#define OB_WRP_SECTOR_12TO15 0x0000000000000008U /*!< Write protection of Sector12 to Sector15 */ +#define OB_WRP_SECTOR_16TO19 0x0000000000000010U /*!< Write protection of Sector16 to Sector19 */ +#define OB_WRP_SECTOR_20TO23 0x0000000000000020U /*!< Write protection of Sector20 to Sector23 */ +#define OB_WRP_SECTOR_24TO27 0x0000000000000040U /*!< Write protection of Sector24 to Sector27 */ +#define OB_WRP_SECTOR_28TO31 0x0000000000000080U /*!< Write protection of Sector28 to Sector31 */ +#if (FLASH_SECTOR_NB == 64) || (FLASH_SECTOR_NB == 128) || (FLASH_SECTOR_NB == 256) +#define OB_WRP_SECTOR_32TO35 0x0000000000000100U /*!< Write protection of Sector32 to Sector35 */ +#define OB_WRP_SECTOR_36TO39 0x0000000000000200U /*!< Write protection of Sector36 to Sector39 */ +#define OB_WRP_SECTOR_40TO43 0x0000000000000400U /*!< Write protection of Sector40 to Sector43 */ +#define OB_WRP_SECTOR_44TO47 0x0000000000000800U /*!< Write protection of Sector44 to Sector47 */ +#define OB_WRP_SECTOR_48TO51 0x0000000000001000U /*!< Write protection of Sector48 to Sector51 */ +#define OB_WRP_SECTOR_52TO55 0x0000000000002000U /*!< Write protection of Sector52 to Sector55 */ +#define OB_WRP_SECTOR_56TO59 0x0000000000004000U /*!< Write protection of Sector56 to Sector59 */ +#define OB_WRP_SECTOR_60TO63 0x0000000000008000U /*!< Write protection of Sector60 to Sector63 */ +#endif /* (FLASH_SECTOR_NB == 64) || (FLASH_SECTOR_NB == 128) || (FLASH_SECTOR_NB == 256) */ +#if (FLASH_SECTOR_NB == 128) || (FLASH_SECTOR_NB == 256) +#define OB_WRP_SECTOR_64TO67 0x0000000000010000U /*!< Write protection of Sector64 to Sector67 */ +#define OB_WRP_SECTOR_68TO71 0x0000000000020000U /*!< Write protection of Sector68 to Sector71 */ +#define OB_WRP_SECTOR_72TO75 0x0000000000040000U /*!< Write protection of Sector72 to Sector75 */ +#define OB_WRP_SECTOR_76TO79 0x0000000000080000U /*!< Write protection of Sector76 to Sector79 */ +#define OB_WRP_SECTOR_80TO83 0x0000000000100000U /*!< Write protection of Sector80 to Sector83 */ +#define OB_WRP_SECTOR_84TO87 0x0000000000200000U /*!< Write protection of Sector84 to Sector87 */ +#define OB_WRP_SECTOR_88TO91 0x0000000000400000U /*!< Write protection of Sector88 to Sector91 */ +#define OB_WRP_SECTOR_92TO95 0x0000000000800000U /*!< Write protection of Sector92 to Sector95 */ +#define OB_WRP_SECTOR_96TO99 0x0000000001000000U /*!< Write protection of Sector96 to Sector99 */ +#define OB_WRP_SECTOR_100TO103 0x0000000002000000U /*!< Write protection of Sector100 to Sector103 */ +#define OB_WRP_SECTOR_104TO107 0x0000000004000000U /*!< Write protection of Sector104 to Sector107 */ +#define OB_WRP_SECTOR_108TO111 0x0000000008000000U /*!< Write protection of Sector108 to Sector111 */ +#define OB_WRP_SECTOR_112TO115 0x0000000010000000U /*!< Write protection of Sector112 to Sector115 */ +#define OB_WRP_SECTOR_116TO119 0x0000000020000000U /*!< Write protection of Sector116 to Sector119 */ +#define OB_WRP_SECTOR_120TO123 0x0000000040000000U /*!< Write protection of Sector120 to Sector123 */ +#define OB_WRP_SECTOR_124TO127 0x0000000080000000U /*!< Write protection of Sector124 to Sector127 */ +#endif /* (FLASH_SECTOR_NB == 128) || (FLASH_SECTOR_NB == 256) */ +#if (FLASH_SECTOR_NB == 256) +#define OB_WRP_SECTOR_128TO131 0x0000000100000000U /*!< Write protection of Sector128 to Sector131 */ +#define OB_WRP_SECTOR_132TO135 0x0000000200000000U /*!< Write protection of Sector132 to Sector135 */ +#define OB_WRP_SECTOR_136TO139 0x0000000400000000U /*!< Write protection of Sector136 to Sector139 */ +#define OB_WRP_SECTOR_140TO143 0x0000000800000000U /*!< Write protection of Sector140 to Sector143 */ +#define OB_WRP_SECTOR_144TO147 0x0000001000000000U /*!< Write protection of Sector144 to Sector147 */ +#define OB_WRP_SECTOR_148TO151 0x0000002000000000U /*!< Write protection of Sector148 to Sector151 */ +#define OB_WRP_SECTOR_152TO155 0x0000004000000000U /*!< Write protection of Sector152 to Sector155 */ +#define OB_WRP_SECTOR_156TO159 0x0000008000000000U /*!< Write protection of Sector156 to Sector159 */ +#define OB_WRP_SECTOR_160TO163 0x0000010000000000U /*!< Write protection of Sector160 to Sector163 */ +#define OB_WRP_SECTOR_164TO167 0x0000020000000000U /*!< Write protection of Sector164 to Sector167 */ +#define OB_WRP_SECTOR_168TO171 0x0000040000000000U /*!< Write protection of Sector168 to Sector171 */ +#define OB_WRP_SECTOR_172TO175 0x0000080000000000U /*!< Write protection of Sector172 to Sector175 */ +#define OB_WRP_SECTOR_176TO179 0x0000100000000000U /*!< Write protection of Sector176 to Sector179 */ +#define OB_WRP_SECTOR_180TO183 0x0000200000000000U /*!< Write protection of Sector180 to Sector183 */ +#define OB_WRP_SECTOR_184TO187 0x0000400000000000U /*!< Write protection of Sector184 to Sector187 */ +#define OB_WRP_SECTOR_188TO191 0x0000800000000000U /*!< Write protection of Sector188 to Sector191 */ +#define OB_WRP_SECTOR_192TO195 0x0001000000000000U /*!< Write protection of Sector192 to Sector195 */ +#define OB_WRP_SECTOR_196TO199 0x0002000000000000U /*!< Write protection of Sector196 to Sector199 */ +#define OB_WRP_SECTOR_200TO203 0x0004000000000000U /*!< Write protection of Sector200 to Sector203 */ +#define OB_WRP_SECTOR_204TO207 0x0008000000000000U /*!< Write protection of Sector204 to Sector207 */ +#define OB_WRP_SECTOR_208TO211 0x0010000000000000U /*!< Write protection of Sector208 to Sector211 */ +#define OB_WRP_SECTOR_212TO215 0x0020000000000000U /*!< Write protection of Sector212 to Sector215 */ +#define OB_WRP_SECTOR_216TO219 0x0040000000000000U /*!< Write protection of Sector216 to Sector219 */ +#define OB_WRP_SECTOR_220TO223 0x0080000000000000U /*!< Write protection of Sector220 to Sector223 */ +#define OB_WRP_SECTOR_224TO227 0x0100000000000000U /*!< Write protection of Sector224 to Sector227 */ +#define OB_WRP_SECTOR_228TO231 0x0200000000000000U /*!< Write protection of Sector228 to Sector231 */ +#define OB_WRP_SECTOR_232TO235 0x0400000000000000U /*!< Write protection of Sector232 to Sector235 */ +#define OB_WRP_SECTOR_236TO239 0x0800000000000000U /*!< Write protection of Sector236 to Sector239 */ +#define OB_WRP_SECTOR_240TO243 0x1000000000000000U /*!< Write protection of Sector240 to Sector243 */ +#define OB_WRP_SECTOR_244TO247 0x2000000000000000U /*!< Write protection of Sector244 to Sector247 */ +#define OB_WRP_SECTOR_248TO251 0x4000000000000000U /*!< Write protection of Sector248 to Sector251 */ +#define OB_WRP_SECTOR_252TO255 0x8000000000000000U /*!< Write protection of Sector252 to Sector255 */ +#endif /* (FLASH_SECTOR_NB == 256) */ +#endif /* (FLASH_SECTOR_NB == 8) */ +#if (FLASH_SECTOR_NB == 32) +#define OB_WRP_SECTOR_ALL 0x00000000000000FFU /*!< Write protection of all Sectors */ +#elif (FLASH_SECTOR_NB == 64) +#define OB_WRP_SECTOR_ALL 0x000000000000FFFFU /*!< Write protection of all Sectors */ +#elif (FLASH_SECTOR_NB == 128) +#define OB_WRP_SECTOR_ALL 0x00000000FFFFFFFFU /*!< Write protection of all Sectors */ +#elif (FLASH_SECTOR_NB == 256) +#define OB_WRP_SECTOR_ALL 0xFFFFFFFFFFFFFFFFU /*!< Write protection of all Sectors */ +#endif /* FLASH_SECTOR_NB == 32 */ + +/** + * @} + */ + +/** @defgroup FLASH_Programming_Delay FLASH Programming Delay + * @{ + */ +#define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 84 MHz or + below */ +#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 84 MHz + and 168 MHz */ +#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 168 MHz + and 250 MHz */ +/** + * @} + */ + +/** @defgroup FLASH_OTP_Blocks FLASH OTP blocks + * @{ + */ +#define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */ +#define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */ +#define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */ +#define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */ +#define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */ +#define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */ +#define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */ +#define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */ +#define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */ +#define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */ +#define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */ +#define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */ +#define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */ +#define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */ +#define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */ +#define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */ +#define FLASH_OTP_BLOCK_16 0x00010000U /*!< OTP Block16 */ +#define FLASH_OTP_BLOCK_17 0x00020000U /*!< OTP Block17 */ +#define FLASH_OTP_BLOCK_18 0x00040000U /*!< OTP Block18 */ +#define FLASH_OTP_BLOCK_19 0x00080000U /*!< OTP Block19 */ +#define FLASH_OTP_BLOCK_20 0x00100000U /*!< OTP Block20 */ +#define FLASH_OTP_BLOCK_21 0x00200000U /*!< OTP Block21 */ +#define FLASH_OTP_BLOCK_22 0x00400000U /*!< OTP Block22 */ +#define FLASH_OTP_BLOCK_23 0x00800000U /*!< OTP Block23 */ +#define FLASH_OTP_BLOCK_24 0x01000000U /*!< OTP Block24 */ +#define FLASH_OTP_BLOCK_25 0x02000000U /*!< OTP Block25 */ +#define FLASH_OTP_BLOCK_26 0x04000000U /*!< OTP Block26 */ +#define FLASH_OTP_BLOCK_27 0x08000000U /*!< OTP Block27 */ +#define FLASH_OTP_BLOCK_28 0x10000000U /*!< OTP Block28 */ +#define FLASH_OTP_BLOCK_29 0x20000000U /*!< OTP Block29 */ +#define FLASH_OTP_BLOCK_30 0x40000000U /*!< OTP Block30 */ +#define FLASH_OTP_BLOCK_31 0x80000000U /*!< OTP Block31 */ +#define FLASH_OTP_BLOCK_ALL 0xFFFFFFFFU /*!< OTP All Blocks */ +/** + * @} + */ + +/** @defgroup FLASH_WRP_State FLASH WRP State + * @{ + */ +#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired flash sectors */ +#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired flash sectors */ +/** + * @} + */ + +/** @defgroup FLASH_OB_BOOT_CONFIG FLASH Option Bytes Boot configuration + * @{ + */ +#define OB_BOOT_NS 0x00000001U /*!< Non-secure boot address */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define OB_BOOT_SEC 0x00000002U /*!< Secure boot address */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup FLASH_OB_BOOT_LOCK FLASH Option Bytes Boot Lock + * @{ + */ +#define OB_BOOT_LOCK_DISABLE 0xC3U /*!< Boot lock disable */ +#define OB_BOOT_LOCK_ENABLE 0xB4U /*!< Boot lock enable */ +/** + * @} + */ + +/** @defgroup FLASH_BB_Attributes FLASH Block-Base Attributes + * @{ + */ +#define FLASH_BB_SEC 0x01U /*!< Flash Block-Based Security Attributes */ +#define FLASH_BB_PRIV 0x02U /*!< Flash Block-Based Privilege Attributes */ +/** + * @} + */ + +/** @defgroup FLASH_PRIV_MODE FLASH privilege mode + * @{ + */ +#define FLASH_NSPRIV_GRANTED 0x00000000U /*!< access to non-secure Flash registers is granted to privileged + or unprivileged access */ +#define FLASH_NSPRIV_DENIED FLASH_PRIVCFGR_NSPRIV /*!< access to non-secure Flash registers is denied to + non-privilege access */ + +#define FLASH_SPRIV_GRANTED 0x00000000U /*!< access to secure Flash registers is granted to privileged or + unprivileged access */ +#if defined (FLASH_PRIVCFGR_SPRIV) +#define FLASH_SPRIV_DENIED FLASH_PRIVCFGR_SPRIV /*!< access to secure Flash registers is denied to non-privilege + access */ +#endif /* FLASH_PRIVCFGR_SPRIV */ +/** + * @} + */ + +#if defined (FLASH_SR_OBKERR) +/** @defgroup FLASH_OBK_SWAP_Offset FLASH OBK Swap Offset + * @{ + */ +#define FLASH_OBK_SWAP_OFFSET_NO_DATA 0x000U /*!< No data will be copied from current to alternate OBK */ +#define FLASH_OBK_SWAP_OFFSET_HDPL0 0x010U /*!< HDPL0 data will be copied from current to alternate OBK */ +#define FLASH_OBK_SWAP_OFFSET_HDPL1 0x090U /*!< HDPL0/1 data will be copied from current to alternate OBK */ +#define FLASH_OBK_SWAP_OFFSET_HDPL2 0x0C0U /*!< HDPL0/1/2 data will be copied from current to alternate OBK */ +#define FLASH_OBK_SWAP_OFFSET_HDPL3_S 0x180U /*!< HDPL0/1/2/3_S data will be copied from current to alternate + OBK */ +#define FLASH_OBK_SWAP_OFFSET_ALL 0x1FFU /*!< All OBK data (511) will be copied from current to alternate + OBK */ +/** + * @} + */ +#endif /* FLASH_SR_OBKERR */ + +/** @defgroup FLASH_Operation_Type FLASH Operation Type + * @{ + */ +#define FLASH_OPERATION_TYPE_NONE 00000000U /*!< No Flash operation */ +#define FLASH_OPERATION_TYPE_QUADWORD FLASH_OPSR_CODE_OP_0 /*!< Single write operation */ +#if defined (FLASH_SR_OBKERR) +#define FLASH_OPERATION_TYPE_OBKALTERASE FLASH_OPSR_CODE_OP_1 /*!< OBK alternate sector erase + operation */ +#endif /* FLASH_SR_OBKERR */ +#define FLASH_OPERATION_TYPE_SECTORERASE (FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< Sector erase operation */ +#define FLASH_OPERATION_TYPE_BANKERASE FLASH_OPSR_CODE_OP_2 /*!< Bank erase operation */ +#define FLASH_OPERATION_TYPE_MASSERASE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_0) /*!< Mass erase operation */ +#define FLASH_OPERATION_TYPE_OPTIONCHANGE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1) /*!< Option change operation */ +#if defined (FLASH_SR_OBKERR) +#define FLASH_OPERATION_TYPE_OBKSWAP (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< OBK + swap operation */ +#endif /* FLASH_SR_OBKERR */ +/** + * @} + */ + +/** @defgroup FLASH_Operation_Area FLASH Operation Area + * @{ + */ +#define FLASH_OPERATION_AREA_BANK_1 00000000U /*!< Operation in Flash Bank 1 */ +#define FLASH_OPERATION_AREA_BANK_2 FLASH_OPSR_BK_OP /*!< Operation in Flash Bank 2 */ +#define FLASH_OPERATION_AREA_SYSF FLASH_OPSR_SYSF_OP /*!< Operation in System Flash memory */ +#if defined (FLASH_EDATAR_EDATA_EN) +#define FLASH_OPERATION_AREA_DATA FLASH_OPSR_DATA_OP /*!< Operation in Flash high-cycle data area */ +#endif /* FLASH_EDATAR_EDATA_EN */ +#define FLASH_OPERATION_AREA_OTP FLASH_OPSR_OTP_OP /*!< Operation in Flash OTP area */ +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** @defgroup SEC_INVERSION_CFG FLASH security inversion configuration + * @{ + */ +#define FLASH_INV_DISABLE 0x00000000U /*!< Security state of Flash is not inverted */ +#define FLASH_INV_ENABLE FLASH_CR_INV /*!< Security state of Flash is inverted */ +/** + * @} + */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros + * @{ + */ + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Enable the FLASH smart prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_SMART_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_S_PRFTEN) + +/** + * @brief Disable the FLASH smart prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_SMART_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_S_PRFTEN) + +/** + * @brief Set the FLASH Programming Delay. + * @param __DELAY__ FLASH Programming Delay + * This parameter can be a value of @ref FLASH_Programming_Delay + * @retval none + */ +#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__)) + +/** + * @brief Get the FLASH Programming Delay. + * @retval FLASH Programming Delay + * This return value can be a value of @ref FLASH_Programming_Delay + */ +#define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ) + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +/* Extension Erase and OB Program operation functions ******************************/ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +#if defined (FLASH_SR_OBKERR) +HAL_StatusTypeDef HAL_FLASHEx_OBK_Unlock(void); +HAL_StatusTypeDef HAL_FLASHEx_OBK_Lock(void); +HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap(uint32_t SwapOffset); +HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap_IT(uint32_t SwapOffset); +#endif /* FLASH_SR_OBKERR */ +void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation); +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group2 + * @{ + */ +/* Extension Protection configuration functions *************************************/ +HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(const FLASH_BBAttributesTypeDef *pBBAttributes); +void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); +void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode); +uint32_t HAL_FLASHEx_GetPrivMode(void); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState); +uint32_t HAL_FLASHEx_GetSecInversion(void); +#endif /* __ARM_FEATURE_CMSE */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(const FLASH_HDPExtensionTypeDef *pHDPExtension); +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group3 + * @{ + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt(void); +void HAL_FLASHEx_DisableEccCorrectionInterrupt(void); +void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData); +void HAL_FLASHEx_ECCD_IRQHandler(void); +__weak void HAL_FLASHEx_EccDetectionCallback(void); +__weak void HAL_FLASHEx_EccCorrectionCallback(void); +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +#define FLASH_TYPEPROGRAM_OB (0x00008000U | FLASH_NON_SECURE_MASK) /*!< Program Option Bytes operation type */ +#define FLASH_ADDRESS_OFFSET_OTP (0x00000600U) /*!< Flash address offset of OTP area */ +#if defined(STM32H5F5xx) +#define FLASH_ADDRESS_OFFSET_EDATA (0x0001E000U) /*!< Flash address offset of EDATA area */ +#elif defined(STM32H533xx) || defined(STM32H523xx) +#define FLASH_ADDRESS_OFFSET_EDATA (0x00003000U) /*!< Flash address offset of EDATA area */ +#elif defined(STM32H553xx) || defined(STM32H543xx) +#define FLASH_ADDRESS_OFFSET_EDATA (0x00007000U) /*!< Flash address offset of EDATA area */ +#else +#define FLASH_ADDRESS_OFFSET_EDATA (0x0000F000U) /*!< Flash address offset of EDATA area */ +#endif /* STM32H533xx || STM32H523xx */ +#if defined(STM32H5F5xx) +#define FLASH_EDATA_BANK_SIZE (0x00018000U) /*!< FLASH EDATA Bank Size */ +#else +#define FLASH_EDATA_BANK_SIZE (0x0000C000U) /*!< FLASH EDATA Bank Size */ +#endif /* STM32H5F5xx */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ + +/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ + ((VALUE) == FLASH_TYPEERASE_SECTORS_NS) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE_NS) || \ + ((VALUE) == FLASH_TYPEERASE_OBK_ALT)) +#else +#if defined (FLASH_SR_OBKERR) +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ + ((VALUE) == FLASH_TYPEERASE_OBK_ALT)) +#else +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) +#endif /* FLASH_SR_OBKERR */ +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ + ((VALUE) == OB_WRPSTATE_ENABLE)) + +#define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \ + (((VALUE) & ~OPTIONBYTE_ALL) == 0U)) + +#define IS_OB_PRODUCT_STATE(STATE) (((STATE) == OB_PROD_STATE_OPEN) || \ + ((STATE) == OB_PROD_STATE_PROVISIONING) || \ + ((STATE) == OB_PROD_STATE_IROT_PROVISIONED) || \ + ((STATE) == OB_PROD_STATE_TZ_CLOSED) || \ + ((STATE) == OB_PROD_STATE_CLOSED) || \ + ((STATE) == OB_PROD_STATE_LOCKED) || \ + ((STATE) == OB_PROD_STATE_REGRESSION) || \ + ((STATE) == OB_PROD_STATE_NS_REGRESSION)) + +#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_1) || ((LEVEL) == OB_BOR_LEVEL_2) || \ + ((LEVEL) == OB_BOR_LEVEL_3)) + +#define IS_OB_USER_BORH_EN(VALUE) (((VALUE) == OB_BORH_DISABLE) || ((VALUE) == OB_BORH_ENABLE)) + +#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) + +#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) + +#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) + +#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) + +#define IS_OB_USER_IO_VDD_HSLV(VALUE) (((VALUE) == OB_IO_VDD_HSLV_DISABLE) || \ + ((VALUE) == OB_IO_VDD_HSLV_ENABLE)) + +#define IS_OB_USER_IO_VDDIO2_HSLV(VALUE) (((VALUE) == OB_IO_VDDIO2_HSLV_DISABLE) || \ + ((VALUE) == OB_IO_VDDIO2_HSLV_ENABLE)) + +#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE)) + +#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE)) + +#define IS_OB_USER_BOOT_UBE(VALUE) (((VALUE) == OB_UBE_OEM_IROT) || ((VALUE) == OB_UBE_ST_IROT)) + +#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) + +#if defined (FLASH_OPTSR2_SRAM1_3_RST) +#define IS_OB_USER_SRAM1_3_RST(VALUE) (((VALUE) == OB_SRAM1_3_RST_ERASE) || ((VALUE) == OB_SRAM1_3_RST_NOT_ERASE)) +#endif /* FLASH_OPTSR2_SRAM1_3_RST */ + +#if defined (FLASH_OPTSR2_SRAM1_3_4_5_RST) +#define IS_OB_USER_SRAM1_3_4_5_RST(VALUE) (((VALUE) == OB_SRAM1_3_4_5_RST_ERASE) || \ + ((VALUE) == OB_SRAM1_3_4_5_RST_NOT_ERASE)) +#endif /* FLASH_OPTSR2_SRAM1_3_4_5_RST */ + +#if defined (FLASH_OPTSR2_SRAM1_RST) +#define IS_OB_USER_SRAM1_RST(VALUE) (((VALUE) == OB_SRAM1_RST_ERASE) || ((VALUE) == OB_SRAM1_RST_NOT_ERASE)) +#endif /* FLASH_OPTSR2_SRAM1_RST */ + +#define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) + +#define IS_OB_USER_BKPRAM_ECC(VALUE) (((VALUE) == OB_BKPRAM_ECC_ENABLE) || ((VALUE) == OB_BKPRAM_ECC_DISABLE)) + +#if defined (FLASH_OPTSR2_SRAM3_ECC) +#define IS_OB_USER_SRAM3_ECC(VALUE) (((VALUE) == OB_SRAM3_ECC_ENABLE) || ((VALUE) == OB_SRAM3_ECC_DISABLE)) +#endif /* FLASH_OPTSR2_SRAM3_ECC */ + +#if defined (FLASH_OPTSR2_SRAM1_ECC) +#define IS_OB_USER_SRAM1_ECC(VALUE) (((VALUE) == OB_SRAM1_ECC_ENABLE) || ((VALUE) == OB_SRAM1_ECC_DISABLE)) +#endif /* FLASH_OPTSR2_SRAM1_ECC */ + +#define IS_OB_USER_SRAM2_ECC(VALUE) (((VALUE) == OB_SRAM2_ECC_ENABLE) || ((VALUE) == OB_SRAM2_ECC_DISABLE)) + +#if defined (FLASH_OPTSR2_HUK_PUF) +#define IS_OB_USER_HUK_PUF(VALUE) (((VALUE) == OB_UNIQUE_KEY_PUF) || ((VALUE) == OB_UNIQUE_KEY_HUK)) +#endif /* FLASH_OPTSR2_HUK_PUF */ + +#if defined(FLASH_OPTSR2_USBPD_DIS) +#define IS_OB_USER_USBPD_DIS(VALUE) (((VALUE) == OB_USBPD_DIS_ENABLE) || ((VALUE) == OB_USBPD_DIS_DISABLE)) +#endif /* FLASH_OPTSR2_USBPD_DIS */ +#define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) + +#define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \ + (((TYPE) & ~OB_USER_ALL) == 0U)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_OB_BOOT_CONFIG(CFG) (((CFG) == OB_BOOT_NS) || ((CFG) == OB_BOOT_SEC)) +#else +#define IS_OB_BOOT_CONFIG(CFG) ((CFG) == OB_BOOT_NS) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_BB_EXCLUSIVE(CFG) (((CFG) == FLASH_BB_SEC) || ((CFG) == FLASH_BB_PRIV)) +#else +#define IS_FLASH_BB_EXCLUSIVE(CFG) ((CFG) == FLASH_BB_PRIV) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_FLASH_CFGPRIVMODE(CFG) (((CFG) & 0xFFFFFFFCU) == 0U) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_CFGSECINV(CFG) (((CFG) == FLASH_INV_DISABLE) || ((CFG) == FLASH_INV_ENABLE)) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_FLASH_EDATA_SIZE(SECTOR) ((SECTOR) <= FLASH_EDATA_SECTOR_NB) +/** + * @} + */ + +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_FLASH_EX_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h new file mode 100644 index 00000000..b41cccfa --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h @@ -0,0 +1,410 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_GPIO_H +#define STM32H5xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be a value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, (Alternate or Analog)) + * @{ + */ +/*!< Input Floating Mode */ +#define GPIO_MODE_INPUT (0x00000000U) +/*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_PP (0x00000001U) +/*!< Output Open Drain Mode */ +#define GPIO_MODE_OUTPUT_OD (0x00000011U) +/*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_PP (0x00000002U) +/*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_AF_OD (0x00000012U) +/*!< Analog Mode */ +#define GPIO_MODE_ANALOG (0x00000003U) +/*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_RISING (0x10110000U) +/*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_FALLING (0x10210000U) +/*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) +/*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_RISING (0x10120000U) +/*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (0x10220000U) +/*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< High speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< Very-high speed */ +/** + * @} + */ + +/** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @defgroup GPIO_attributes GPIO attributes + * @brief GPIO pin secure or non-secure attributes + * @{ + */ +#define GPIO_PIN_SEC (0x00000001U) /*!< Secure pin attribute */ +#define GPIO_PIN_NSEC (0x00000000U) /*!< Non-secure pin attribute */ +/** + * @} + */ + +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line is rising edge asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line rising pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is falling edge asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line falling pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \ + __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) \ + do { \ + __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__); \ + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__); \ + } while(0) + + +/** + * @brief Generate a Software interrupt on selected EXTI line(s). + * @param __EXTI_LINE__: specifies the EXTI line to set. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) + +/** + * @brief Clear the EXTI line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) + +#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0) ||\ + ((__PIN__) == GPIO_PIN_1) ||\ + ((__PIN__) == GPIO_PIN_2) ||\ + ((__PIN__) == GPIO_PIN_3) ||\ + ((__PIN__) == GPIO_PIN_4) ||\ + ((__PIN__) == GPIO_PIN_5) ||\ + ((__PIN__) == GPIO_PIN_6) ||\ + ((__PIN__) == GPIO_PIN_7) ||\ + ((__PIN__) == GPIO_PIN_8) ||\ + ((__PIN__) == GPIO_PIN_9) ||\ + ((__PIN__) == GPIO_PIN_10) ||\ + ((__PIN__) == GPIO_PIN_11) ||\ + ((__PIN__) == GPIO_PIN_12) ||\ + ((__PIN__) == GPIO_PIN_13) ||\ + ((__PIN__) == GPIO_PIN_14) ||\ + ((__PIN__) == GPIO_PIN_15)) + +#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ + (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +#define IS_GPIO_PIN_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == GPIO_PIN_SEC) ||\ + ((__ATTRIBUTES__) == GPIO_PIN_NSEC)) + +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/* Include GPIO HAL Extended module */ +#include "stm32h5xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions + * @brief GPIO Exported Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @addtogroup GPIO_Exported_Functions_Group3 IO attributes management functions + * @{ + */ + +/* IO attributes management functions *****************************************/ +void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes); +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, + uint32_t *pPinAttributes); + +/** + * @} + */ + +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_GPIO_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h new file mode 100644 index 00000000..a745de1f --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h @@ -0,0 +1,612 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_GPIO_EX_H +#define STM32H5xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @brief GPIO Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50HZ ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ +#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */ +#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */ +#if defined(DMA2D) +#define GPIO_AF0_DMA2D ((uint8_t)0x00) /* DMA2D Alternate Function mapping */ +#endif /* DMA2D */ +#if defined(GFXTIM) +#define GPIO_AF0_GFXTIM ((uint8_t)0x00) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#if defined(TIM16) +#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */ +#endif /* TIM16 */ +#if defined(TIM17) +#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */ +#endif /* TIM17 */ +#if !defined(STM32H503xx) +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#endif /* STM32H503xx */ +#if defined(ADF1) +#define GPIO_AF1_ADF1 ((uint8_t)0x01) /* ADF1 Alternate Function mapping */ +#endif /* ADF1 */ + +/** + * @brief AF 2 selection + */ +#if defined(STM32H503xx) +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ +#endif /* STM32H503xx */ +#if defined(LPTIM3) +#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */ +#endif /* LPTIM3 */ +#if defined(SAI1) +#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */ +#endif /* SAI1 */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#if defined(TIM4) +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#endif /* TIM4 */ +#if defined(TIM5) +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ +#endif /* TIM5 */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ +#if defined(TIM12) +#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */ +#endif /* TIM12 */ +#if defined(TIM15) +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */ +#endif /* TIM15 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM13 ((uint8_t)0x02) /* TIM13 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /* TIM14 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_I3C1 ((uint8_t)0x03) /* I3C1 Alternate Function mapping */ +#if defined(I3C2) +#define GPIO_AF3_I3C2 ((uint8_t)0x03) /* I3C2 Alternate Function mapping */ +#endif /* I3C2 */ +#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */ +#if defined(LPTIM3) +#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */ +#endif /* LPTIM3 */ +#define GPIO_AF3_LPUART1 ((uint8_t)0x03) /* LPUART1 Alternate Function mapping */ +#if defined(OCTOSPI1) +#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */ +#endif /* OCTOSPI1 */ +#if !defined(STM32H503xx) +#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */ +#endif /* STM32H503xx */ +#if defined(TIM8) +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#endif /* TIM8 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF3_COMP1 ((uint8_t)0x03) /* COMP1 Alternate Function mapping */ +#define GPIO_AF3_COMP2 ((uint8_t)0x03) /* COMP2 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#if defined(ADF1) +#define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */ +#endif /* ADF1 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ + +/** + * @brief AF 4 selection + */ +#if defined(CEC) +#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ +#endif /* CEC */ +#if !defined(STM32H5F5xx) || !defined(STM32H5F4xx) || !defined(STM32H5E5xx) || !defined(STM32H5E4xx) +#if defined(DCMI) +#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ +#endif /* DCMI */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#if defined(PSSI) +#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */ +#endif /* PSSI */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#if defined(I2C3) +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#endif /* I2C3 */ +#if defined(I2C4) +#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ +#endif /* I2C4 */ +#define GPIO_AF4_LPTIM1 ((uint8_t)0x04) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF4_SPI1 ((uint8_t)0x04) /* SPI1 Alternate Function mapping */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF4_SPI3 ((uint8_t)0x04) /* SPI3 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ +#if defined(TIM15) +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */ +#endif /* TIM15 */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#if defined(STM32H503xx) +#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ +#endif /* STM32H503xx */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF4_SAI1 ((uint8_t)0x04) /* SAI1 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#if defined(MDF1) +#define GPIO_AF4_MDF1 ((uint8_t)0x04) /* MDF1 Alternate Function mapping */ +#endif /* MDF1 */ +#if defined(ADF1) +#define GPIO_AF4_ADF1 ((uint8_t)0x04) /* ADF1 Alternate Function mapping */ +#endif /* ADF1 */ + +/** + * @brief AF 5 selection + */ +#if defined(CEC) +#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */ +#endif /* CEC */ +#if !defined(STM32H503xx) +#define GPIO_AF5_I3C1 ((uint8_t)0x05) /* I3C1 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ +#endif /* STM32H503xx */ +#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#if defined(SPI4) +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#endif /* SPI4 */ +#if defined(SPI5) +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#endif /* SPI5 */ +#if defined(SPI6) +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +#endif /* SPI6 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF5_I3C2 ((uint8_t)0x05) /* I3C2 Alternate Function mapping */ +#if defined(GFXTIM) +#define GPIO_AF5_GFXTIM ((uint8_t)0x05) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ +#define GPIO_AF5_AUDIOCLK ((uint8_t)0x05) /* AUDIOCLK Alternate Function mapping */ +#define GPIO_AF5_USART2 ((uint8_t)0x05) /* USART2 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ + +/** + * @brief AF 6 selection + */ +#if defined(I2C4) +#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */ +#endif /* I2C4 */ +#if defined(OCTOSPI1) +#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */ +#endif /* OCTOSPI1 */ +#if defined(SAI1) +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ +#endif /* SAI1 */ +#if (defined(STM32H503xx) || defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */ +#endif /* STM32H503xx || STM32H533xx || STM32H523xx */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ +#if defined(SPI4) +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */ +#endif /* SPI4 */ +#if defined(UART4) +#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */ +#endif /* UART4 */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF6_USART6 ((uint8_t)0x06) /* USART6 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ +#if defined(UART12) +#define GPIO_AF6_UART12 ((uint8_t)0x06) /* UART12 Alternate Function mapping */ +#endif /* UART12 */ +#if defined(USART10) +#define GPIO_AF6_USART10 ((uint8_t)0x06) /* USART10 Alternate Function mapping */ +#endif /* USART10 */ +#if defined(UCPD1) +#define GPIO_AF6_UCPD1 ((uint8_t)0x06) /* UCPD1 Alternate Function mapping */ +#endif /* UCPD1 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_ETH ((uint8_t)0x06) /* ETH Alternate Function mapping */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /* I2C1 Alternate Function mapping */ +#define GPIO_AF6_USART12 ((uint8_t)0x06) /* USART12 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ + +/** + * @brief AF 7 selection + */ +#if defined(SDMMC1) +#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */ +#endif /* SDMMC1 */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */ +#if defined(SPI6) +#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */ +#endif /* SPI6 */ +#if defined(UART7) +#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */ +#endif /* UART7 */ +#if defined(UART8) +#define GPIO_AF7_UART8 ((uint8_t)0x07) /* UART8 Alternate Function mapping */ +#endif /* UART8 */ +#if !defined(STM32H5F5xx) || !defined(STM32H5F4xx) || !defined(STM32H5E5xx) || !defined(STM32H5E4xx) +#if defined(UART12) +#define GPIO_AF7_UART12 ((uint8_t)0x07) /* UART12 Alternate Function mapping */ +#endif /* UART12 */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#if defined(USART6) +#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */ +#endif /* USART6 */ +#if defined(USART10) +#define GPIO_AF7_USART10 ((uint8_t)0x07) /* USART10 Alternate Function mapping */ +#endif /* USART10 */ +#if defined(USART11) +#define GPIO_AF7_USART11 ((uint8_t)0x07) /* USART11 Alternate Function mapping */ +#endif /* USART11 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF7_ETH ((uint8_t)0x07) /* ETH Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +/** + * @brief AF 8 selection + */ +#if defined(STM32H503xx) +#define GPIO_AF8_I2C2 ((uint8_t)0x08) /* I2C2 Alternate Function mapping */ +#define GPIO_AF8_I3C1 ((uint8_t)0x08) /* I3C1 Alternate Function mapping */ +#define GPIO_AF8_USART1 ((uint8_t)0x08) /* USART1 Alternate Function mapping */ +#endif /* STM32H503xx */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ +#if defined(SAI2) +#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ +#endif /* SAI2 */ +#if defined(SDMMC1) +#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ +#endif /* SDMMC1 */ +#if defined(SPI6) +#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */ +#endif /* SPI6 */ +#if defined(UART4) +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#endif /* UART4 */ +#if defined(UART5) +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#endif /* UART5 */ +#if defined(UART8) +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#endif /* UART8 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF8_ETH ((uint8_t)0x08) /* ETH Alternate Function mapping */ +#define GPIO_AF8_FMC ((uint8_t)0x08) /* FMC Alternate Function mapping */ +#define GPIO_AF8_I3C2 ((uint8_t)0x08) /* I3C2 Alternate Function mapping */ +#define GPIO_AF8_OCTOSPI1 ((uint8_t)0x08) /* OCTOSPI1 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#if defined(OCTOSPI2) +#define GPIO_AF8_OCTOSPI2 ((uint8_t)0x08) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOSPI2 */ +#if defined(MDF1) +#define GPIO_AF8_MDF1 ((uint8_t)0x08) /* MDF1 Alternate Function mapping */ +#endif /* MDF1 */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ +#if defined(FDCAN2) +#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */ +#endif /* FDCAN2 */ +#if defined(FMC_BANK1) +#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */ +#endif /* FMC_BANK1 */ +#if defined(OCTOSPI1) +#define GPIO_AF9_OCTOSPI1 ((uint8_t)0x09) /* OCTOSPI1 Alternate Function mapping */ +#endif /* OCTOSPI1 */ +#if defined(SDMMC2) +#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */ +#endif /* SDMMC2 */ +#if defined(TIM13) +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#endif /* TIM13 */ +#if defined(TIM14) +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#endif /* TIM14 */ +#if defined(STM32H503xx) +#define GPIO_AF9_USART2 ((uint8_t)0x09) /* USART2 Alternate Function mapping */ +#define GPIO_AF9_USART3 ((uint8_t)0x09) /* USART3 Alternate Function mapping */ +#endif /* STM32H503xx */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ +#define GPIO_AF9_I3C2 ((uint8_t)0x09) /* I3C2 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ +#if defined(OCTOSPI2) +#define GPIO_AF9_OCTOSPI2 ((uint8_t)0x09) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOSPI2 */ +#if defined(FDCAN3) +#define GPIO_AF9_FDCAN3 ((uint8_t)0x09) /* FDCAN3 Alternate Function mapping */ +#endif /* FDCAN3 */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF9_SDMMC1 ((uint8_t)0x09) /* SDMMC1 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */ +#if defined(STM32H503xx) +#define GPIO_AF10_I3C1 ((uint8_t)0x0A) /* I3C1 Alternate Function mapping */ +#define GPIO_AF10_SPI3 ((uint8_t)0x0A) /* SPI3 Alternate Function mapping */ +#endif /* STM32H503xx */ +#if (defined(STM32H503xx) || defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF10_I3C2 ((uint8_t)0x0A) /* I3C2 Alternate Function mapping */ +#endif /* STM32H503xx || STM32H533xx || STM32H523xx */ +#if defined(FMC_BANK1) +#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping */ +#endif /* FMC_BANK1 */ +#if defined(OCTOSPI1) +#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */ +#endif /* OCTOSPI1 */ +#if defined(SAI2) +#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ +#endif /* SAI2 */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF10_SDMMC1 ((uint8_t)0x0A) /* SDMMC1 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ +#if defined(SDMMC2) +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */ +#endif /* SDMMC2 */ +#if defined(TIM8) +#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */ +#endif /* TIM8 */ +#if defined(USB_DRD_FS) +#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */ +#endif /* USB_DRD_FS */ +#if defined(LTDC) +#define GPIO_AF10_LTDC ((uint8_t)0x0A) /* LTDC Alternate Function mapping */ +#endif /* LTDC */ +#if defined(ETH) +#define GPIO_AF10_ETH ((uint8_t)0x0A) /* ETH Alternate Function mapping */ +#endif /* ETH */ +#if defined(OCTOSPI2) +#define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOSPI2 */ +#if defined(USB_OTG_FS) +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* USB OTG FS Alternate Function mapping */ +#endif /* USB_OTG_FS */ +#if defined(USB_OTG_HS) +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* USB OTG HS Alternate Function mapping */ +#endif /* USB_OTG_HS */ + +/** + * @brief AF 11 selection + */ +#if defined(ETH) +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */ +#endif /* ETH */ +#if defined(FMC_BANK1) +#define GPIO_AF11_FMC ((uint8_t)0x0B) /* FMC Alternate Function mapping */ +#endif /* FMC_BANK1 */ +#if defined(OCTOSPI1) +#define GPIO_AF11_OCTOSPI1 ((uint8_t)0x0B) /* OCTOSPI1 Alternate Function mapping */ +#endif /* OCTOSPI1 */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF11_SDMMC1 ((uint8_t)0x0B) /* SDMMC1 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ +#if defined(SDMMC2) +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */ +#endif /* SDMMC2 */ +#if defined(UART7) +#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */ +#endif /* UART7 */ +#if defined(UART9) +#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */ +#endif /* UART9 */ +#if defined(UCPD1) +#define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /* UCPD1 Alternate Function mapping */ +#endif /* UCPD1 */ +#if defined(STM32H503xx) +#define GPIO_AF11_I2C1 ((uint8_t)0x0B) /* I2C1 Alternate Function mapping */ +#define GPIO_AF11_I2C2 ((uint8_t)0x0B) /* I2C2 Alternate Function mapping */ +#define GPIO_AF11_SPI2 ((uint8_t)0x0B) /* SPI2 Alternate Function mapping */ +#define GPIO_AF11_USART2 ((uint8_t)0x0B) /* USART2 Alternate Function mapping */ +#endif /* STM32H503xx */ +#if defined(LTDC) +#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping */ +#endif /* LTDC */ + +/** + * @brief AF 12 selection + */ +#if defined(FMC_BANK1) +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#endif /* FMC_BANK1 */ +#if defined(SDMMC1) +#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ +#endif /* SDMMC1 */ +#if defined(STM32H503xx) +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ +#define GPIO_AF12_SPI1 ((uint8_t)0x0C) /* SPI1 Alternate Function mapping */ +#endif /* STM32H503xx */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF12_ETH ((uint8_t)0x0C) /* ETH Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#if defined(LTDC) +#define GPIO_AF12_LTDC ((uint8_t)0x0C) /* LTDC Alternate Function mapping */ +#endif /* LTDC */ + +/** + * @brief AF 13 selection + */ +#if defined(DCMI) +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ +#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */ +#endif /* DCMI */ +#if defined(FMC_BANK1) +#define GPIO_AF13_FMC ((uint8_t)0x0D) /* FMC Alternate Function mapping */ +#endif /* FMC_BANK1 */ +#if defined(LPTIM5) +#define GPIO_AF13_LPTIM5 ((uint8_t)0x0D) /* LPTIM5 Alternate Function mapping */ +#endif /* LPTIM5 */ +#if defined(STM32H503xx) +#define GPIO_AF13_USART2 ((uint8_t)0x0D) /* USART2 Alternate Function mapping */ +#define GPIO_AF13_USART3 ((uint8_t)0x0D) /* USART3 Alternate Function mapping */ +#endif /* STM32H503xx */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define GPIO_AF13_LPTIM6 ((uint8_t)0x0D) /* LPTIM6 Alternate Function mapping */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#if defined(LTDC) +#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */ +#endif /* LTDC */ + +/** + * @brief AF 14 selection + */ +#if defined(STM32H503xx) +#define GPIO_AF14_LPTIM1 ((uint8_t)0x0E) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM1 ((uint8_t)0x0E) /* TIM1 Alternate Function mapping */ +#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM3 ((uint8_t)0x0E) /* TIM3 Alternate Function mapping */ +#endif /* STM32H503xx */ +#if defined(LPTIM3) +#define GPIO_AF14_LPTIM3 ((uint8_t)0x0E) /* LPTIM3 Alternate Function mapping */ +#endif /* LPTIM3 */ +#if defined(LPTIM4) +#define GPIO_AF14_LPTIM4 ((uint8_t)0x0E) /* LPTIM4 Alternate Function mapping */ +#endif /* LPTIM4 */ +#if defined(LPTIM5) +#define GPIO_AF14_LPTIM5 ((uint8_t)0x0E) /* LPTIM5 Alternate Function mapping */ +#endif /* LPTIM5 */ +#if defined(LPTIM6) +#define GPIO_AF14_LPTIM6 ((uint8_t)0x0E) /* LPTIM6 Alternate Function mapping */ +#endif /* LPTIM6 */ +#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || defined(STM32H523xx) +#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ +#endif /* STM32H573xx || STM32H563xx || STM32H562xx || STM32H533xx || STM32H523xx */ +#if defined(UART5) +#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */ +#endif /* UART5 */ +#if (defined(STM32H533xx) || defined(STM32H523xx)) +#define GPIO_AF14_USART6 ((uint8_t)0x0E) /* USART6 Alternate Function mapping */ +#endif /* STM32H533xx || STM32H523xx */ +#if defined(LTDC) +#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */ +#endif /* LTDC */ +#if defined(PLAY1) +#define GPIO_AF14_PLAY1_IN ((uint8_t)0x0E) /* PLAY1_IN Alternate Function mapping */ +#define GPIO_AF14_PLAY1_OUT ((uint8_t)0x0E) /* PLAY1_OUT Alternate Function mapping */ +#endif /* PLAY1 */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index + * @{ + */ + + +/* GPIO_Peripheral_Memory_Mapping Peripheral Memory Mapping */ + +#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || \ + defined(STM32H523xx) || defined(STM32H503xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || \ + defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx) +#define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10) +#endif /* (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || \ + defined(STM32H523xx) || defined(STM32H503xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || \ + defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx)*/ + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_GPIO_EX_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h new file mode 100644 index 00000000..6ecd4419 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h @@ -0,0 +1,300 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_icache.h + * @author MCD Application Team + * @brief Header file of ICACHE HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion ------------------------------------*/ +#ifndef STM32H5xx_HAL_ICACHE_H +#define STM32H5xx_HAL_ICACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -----------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +#if defined(ICACHE) +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup ICACHE + * @{ + */ + +/* Exported types -----------------------------------------------------------*/ +#if defined(ICACHE_CRRx_REN) +/** @defgroup ICACHE_Exported_Types ICACHE Exported Types + * @{ + */ + +/** + * @brief HAL ICACHE region configuration structure definition + */ +typedef struct +{ + uint32_t BaseAddress; /*!< Configures the Base address of Region i to be remapped */ + + uint32_t RemapAddress; /*!< Configures the Remap address of Region i to be remapped */ + + uint32_t Size; /*!< Configures the Region size. + This parameter can be a value of @ref ICACHE_Region_Size */ + + uint32_t TrafficRoute; /*!< Selects the traffic route. + This parameter can be a value of @ref ICACHE_Traffic_Route */ + + uint32_t OutputBurstType; /*!< Selects the output burst type. + This parameter can be a value of @ref ICACHE_Output_Burst_Type */ +} ICACHE_RegionConfigTypeDef; +/** + * @} + */ +#endif /* ICACHE_CRRx_REN */ + +/* Exported constants -------------------------------------------------------*/ +/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants + * @{ + */ + +/** @defgroup ICACHE_WaysSelection Ways selection + * @{ + */ +#define ICACHE_1WAY 0UL /*!< 1-way cache (direct mapped cache) */ +#define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ +/** + * @} + */ + +/** @defgroup ICACHE_Monitor_Type Monitor type + * @{ + */ +#define ICACHE_MONITOR_HIT_MISS (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */ +#define ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitoring */ +#define ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitoring */ +/** + * @} + */ + +#if defined(ICACHE_CRRx_REN) +/** @defgroup ICACHE_Region Remapped Region number + * @{ + */ +#define ICACHE_REGION_0 0UL /*!< Region 0 */ +#define ICACHE_REGION_1 1UL /*!< Region 1 */ +#define ICACHE_REGION_2 2UL /*!< Region 2 */ +#define ICACHE_REGION_3 3UL /*!< Region 3 */ +/** + * @} + */ + +/** @defgroup ICACHE_Region_Size Remapped Region size + * @{ + */ +#define ICACHE_REGIONSIZE_2MB 1UL /*!< Region size 2MB */ +#define ICACHE_REGIONSIZE_4MB 2UL /*!< Region size 4MB */ +#define ICACHE_REGIONSIZE_8MB 3UL /*!< Region size 8MB */ +#define ICACHE_REGIONSIZE_16MB 4UL /*!< Region size 16MB */ +#define ICACHE_REGIONSIZE_32MB 5UL /*!< Region size 32MB */ +#define ICACHE_REGIONSIZE_64MB 6UL /*!< Region size 64MB */ +#define ICACHE_REGIONSIZE_128MB 7UL /*!< Region size 128MB */ +/** + * @} + */ + +/** @defgroup ICACHE_Traffic_Route Remapped Traffic route + * @{ + */ +#define ICACHE_MASTER1_PORT 0UL /*!< Master1 port */ +#define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ +/** + * @} + */ + +/** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type + * @{ + */ +#define ICACHE_OUTPUT_BURST_WRAP 0UL /*!< WRAP */ +#define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ +/** + * @} + */ +#endif /* ICACHE_CRRx_REN */ + +/** @defgroup ICACHE_Interrupts Interrupts + * @{ + */ +#define ICACHE_IT_BUSYEND ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ +#define ICACHE_IT_ERROR ICACHE_IER_ERRIE /*!< Cache error interrupt */ +/** + * @} + */ + +/** @defgroup ICACHE_Flags Flags + * @{ + */ +#define ICACHE_FLAG_BUSY ICACHE_SR_BUSYF /*!< Busy flag */ +#define ICACHE_FLAG_BUSYEND ICACHE_SR_BSYENDF /*!< Busy end flag */ +#define ICACHE_FLAG_ERROR ICACHE_SR_ERRF /*!< Cache error flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ----------------------------------------------------------*/ +/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros + * @{ + */ + +/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management + * @brief macros to manage the specified ICACHE flags and interrupts. + * @{ + */ + +/** @brief Enable ICACHE interrupts. + * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt + * @arg @ref ICACHE_IT_ERROR Cache error interrupt + */ +#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__)) + +/** @brief Disable ICACHE interrupts. + * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt + * @arg @ref ICACHE_IT_ERROR Cache error interrupt + */ +#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__)) + +/** @brief Check whether the specified ICACHE interrupt source is enabled or not. + * @param __INTERRUPT__ specifies the ICACHE interrupt source to check. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt + * @arg @ref ICACHE_IT_ERROR Cache error interrupt + * @retval The state of __INTERRUPT__ (0 or 1). + */ +#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \ + ((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U) + +/** @brief Check whether the selected ICACHE flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref ICACHE_FLAG_BUSY Busy flag + * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag + * @arg @ref ICACHE_FLAG_ERROR Cache error flag + * @retval The state of __FLAG__ (0 or 1). + */ +#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U) + +/** @brief Clear the selected ICACHE flags. + * @param __FLAG__ specifies the ICACHE flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag + * @arg @ref ICACHE_FLAG_ERROR Cache error flag + */ +#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions -------------------------------------------------------*/ +/** @addtogroup ICACHE_Exported_Functions + * @{ + */ + +/** @addtogroup ICACHE_Exported_Functions_Group1 + * @brief Initialization and control functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_ICACHE_Enable(void); +HAL_StatusTypeDef HAL_ICACHE_Disable(void); +uint32_t HAL_ICACHE_IsEnabled(void); +HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode); +HAL_StatusTypeDef HAL_ICACHE_DeInit(void); + +/******* Invalidate in blocking mode (Polling) */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate(void); +/******* Invalidate in non-blocking mode (Interrupt) */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void); +/******* Wait for Invalidate complete in blocking mode (Polling) */ +HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void); + +/******* Performance instruction cache monitoring functions */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType); +HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType); +HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType); +uint32_t HAL_ICACHE_Monitor_GetHitValue(void); +uint32_t HAL_ICACHE_Monitor_GetMissValue(void); + +/** + * @} + */ + +/** @addtogroup ICACHE_Exported_Functions_Group2 + * @brief IRQ and callback functions + * @{ + */ +/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */ +void HAL_ICACHE_IRQHandler(void); +void HAL_ICACHE_InvalidateCompleteCallback(void); +void HAL_ICACHE_ErrorCallback(void); + +/** + * @} + */ + +#if defined(ICACHE_CRRx_REN) +/** @addtogroup ICACHE_Exported_Functions_Group3 + * @brief Memory remapped regions functions + * @{ + */ +/******* Memory remapped regions functions */ +HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig); +HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region); + +/** + * @} + */ +#endif /* ICACHE_CRRx_REN */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* ICACHE */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_ICACHE_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h new file mode 100644 index 00000000..fb477049 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h @@ -0,0 +1,695 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_PWR_H +#define STM32H5xx_HAL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< Specifies the PVD detection level. + This parameter can be a value of + @ref PWR_PVD_Detection_Level. */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode. */ +} PWR_PVDTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_Detection_Level Programmable Voltage Detection Level + * @{ + */ +#define PWR_PVDLEVEL_0 0x00000000UL /*!< PVD threshold around 1.95 V */ +#define PWR_PVDLEVEL_1 (PWR_VMCR_PLS_0) /*!< PVD threshold around 2.1 V */ +#define PWR_PVDLEVEL_2 (PWR_VMCR_PLS_1) /*!< PVD threshold around 2.25 V */ +#define PWR_PVDLEVEL_3 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_1) /*!< PVD threshold around 2.4 V */ +#define PWR_PVDLEVEL_4 (PWR_VMCR_PLS_2) /*!< PVD threshold around 2.55 V */ +#define PWR_PVDLEVEL_5 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_2) /*!< PVD threshold around 2.7 V */ +#define PWR_PVDLEVEL_6 (PWR_VMCR_PLS_1 | PWR_VMCR_PLS_2) /*!< PVD threshold around 2.85 V */ +#define PWR_PVDLEVEL_7 (PWR_VMCR_PLS) /*!< External input analog voltage + (compared internally to VREFINT) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00U) /*!< Basic Mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling + edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling + edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_In_LowPower_Mode PWR Regulator State in SLEEP/STOP Mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0x00U) /*!< Main Regulator ON in Run Mode */ +#define PWR_LOWPOWERREGULATOR_ON (0x00U) /*!< Main Regulator ON in Low Power Mode */ +/** + * @} + */ + +/** @defgroup PWR_SLEEP_Mode_Entry PWR SLEEP Mode Entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Sleep mode */ +/** + * @} + */ + +/** @defgroup PWR_STOP_Mode_Entry PWR STOP Mode Entry + * @{ + */ +#define PWR_STOPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Stop mode */ +/** + * @} + */ + +/** @defgroup PWR_Flags PWR Flags + * @{ + */ +#define PWR_FLAG_STOPF (0x01U) /*!< STOP flag */ +#define PWR_FLAG_SBF (0x02U) /*!< STANDBY flag */ +#define PWR_FLAG_VOSRDY (0x03U) /*!< Voltage scaling ready flag */ +#define PWR_FLAG_ACTVOSRDY (0x04U) /*!< Currently applied VOS ready flag */ +#define PWR_FLAG_BRR (0x05U) /*!< Backup regulator ready flag */ +#define PWR_FLAG_VBATL (0x06U) /*!< Backup domain voltage level flag (versus low threshold) */ +#define PWR_FLAG_VBATH (0x07U) /*!< Backup domain voltage level flag (versus high threshold) */ +#define PWR_FLAG_TEMPL (0x08U) /*!< Temperature level flag (versus low threshold) */ +#define PWR_FLAG_TEMPH (0x09U) /*!< Temperature level flag (versus high threshold) */ +#define PWR_FLAG_AVDO (0x0AU) /*!< VDDA voltage detector output flag */ +#define PWR_FLAG_VDDIO2RDY (0x0BU) /*!< VDDIO2 voltage detector output flag */ +#define PWR_FLAG_PVDO (0x0CU) /*!< VDD voltage detector output flag */ +#define PWR_FLAG_USB33RDY (0x0DU) /*!< VDDUSB33 ready flag */ + +#define PWR_WAKEUP_FLAG1 (0x10U) /*!< Wake up line 1 flag */ +#define PWR_WAKEUP_FLAG2 (0x20U) /*!< Wake up line 2 flag */ +#define PWR_WAKEUP_FLAG3 (0x30U) /*!< Wake up line 3 flag */ +#define PWR_WAKEUP_FLAG4 (0x40U) /*!< Wake up line 4 flag */ +#define PWR_WAKEUP_FLAG5 (0x50U) /*!< Wake up line 5 flag */ +#define PWR_WAKEUP_FLAG6 (0x60U) /*!< Wake up line 6 flag */ +#define PWR_WAKEUP_FLAG7 (0x70U) /*!< Wake up line 7 flag */ +#define PWR_WAKEUP_FLAG8 (0x80U) /*!< Wake up line 8 flag */ +#define PWR_WAKEUP_ALL_FLAG (0x90U) /*!< Wakeup flag all */ + +/** + * @} + */ + +/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins + * @{ + */ +/* High level and No pull (default configuration) */ +#define PWR_WAKEUP_PIN1 PWR_WUCR_WUPEN1 +#define PWR_WAKEUP_PIN2 PWR_WUCR_WUPEN2 +#define PWR_WAKEUP_PIN3 PWR_WUCR_WUPEN3 +#define PWR_WAKEUP_PIN4 PWR_WUCR_WUPEN4 +#define PWR_WAKEUP_PIN5 PWR_WUCR_WUPEN5 +#if defined (PWR_WUCR_WUPEN6) +#define PWR_WAKEUP_PIN6 PWR_WUCR_WUPEN6 +#define PWR_WAKEUP_PIN7 PWR_WUCR_WUPEN7 +#define PWR_WAKEUP_PIN8 PWR_WUCR_WUPEN8 +#endif /* PWR_WUCR_WUPEN6 */ + +/* High level and No pull */ +#define PWR_WAKEUP_PIN1_HIGH PWR_WUCR_WUPEN1 +#define PWR_WAKEUP_PIN2_HIGH PWR_WUCR_WUPEN2 +#define PWR_WAKEUP_PIN3_HIGH PWR_WUCR_WUPEN3 +#define PWR_WAKEUP_PIN4_HIGH PWR_WUCR_WUPEN4 +#define PWR_WAKEUP_PIN5_HIGH PWR_WUCR_WUPEN5 +#if defined (PWR_WUCR_WUPEN6) +#define PWR_WAKEUP_PIN6_HIGH PWR_WUCR_WUPEN6 +#define PWR_WAKEUP_PIN7_HIGH PWR_WUCR_WUPEN7 +#define PWR_WAKEUP_PIN8_HIGH PWR_WUCR_WUPEN8 +#endif /* PWR_WUCR_WUPEN6 */ + +/* Low level and No pull */ +#define PWR_WAKEUP_PIN1_LOW (PWR_WUCR_WUPP1 | PWR_WUCR_WUPEN1) +#define PWR_WAKEUP_PIN2_LOW (PWR_WUCR_WUPP2 | PWR_WUCR_WUPEN2) +#define PWR_WAKEUP_PIN3_LOW (PWR_WUCR_WUPP3 | PWR_WUCR_WUPEN3) +#define PWR_WAKEUP_PIN4_LOW (PWR_WUCR_WUPP4 | PWR_WUCR_WUPEN4) +#define PWR_WAKEUP_PIN5_LOW (PWR_WUCR_WUPP5 | PWR_WUCR_WUPEN5) +#if defined (PWR_WUCR_WUPEN6) +#define PWR_WAKEUP_PIN6_LOW (PWR_WUCR_WUPP6 | PWR_WUCR_WUPEN6) +#define PWR_WAKEUP_PIN7_LOW (PWR_WUCR_WUPP7 | PWR_WUCR_WUPEN7) +#define PWR_WAKEUP_PIN8_LOW (PWR_WUCR_WUPP8 | PWR_WUCR_WUPEN8) +#endif /* PWR_WUCR_WUPEN6 */ + +/** + * @} + */ + +/** @defgroup PWR_Items PWR Items + * @{ + */ +#if defined(PWR_SECCFGR_WUP1SEC) +#define PWR_WKUP1 (PWR_SECCFGR_WUP1SEC) /*!< WUP1 secure protection */ +#define PWR_WKUP2 (PWR_SECCFGR_WUP2SEC) /*!< WUP2 secure protection */ +#define PWR_WKUP3 (PWR_SECCFGR_WUP3SEC) /*!< WUP3 secure protection */ +#define PWR_WKUP4 (PWR_SECCFGR_WUP4SEC) /*!< WUP4 secure protection */ +#define PWR_WKUP5 (PWR_SECCFGR_WUP5SEC) /*!< WUP5 secure protection */ +#define PWR_WKUP6 (PWR_SECCFGR_WUP6SEC) /*!< WUP6 secure protection */ +#define PWR_WKUP7 (PWR_SECCFGR_WUP7SEC) /*!< WUP7 secure protection */ +#define PWR_WKUP8 (PWR_SECCFGR_WUP8SEC) /*!< WUP8 secure protection */ +#define PWR_RET (PWR_SECCFGR_RETSEC) /*!< IO Retention secure protection */ +#define PWR_LPM (PWR_SECCFGR_LPMSEC) /*!< Low power modes secure protection */ +#define PWR_SCM (PWR_SECCFGR_SCMSEC) /*!< Voltage detection and monitoring secure protection */ +#define PWR_VB (PWR_SECCFGR_VBSEC) /*!< Backup domain secure protection */ +#define PWR_VUSB (PWR_SECCFGR_VUSBSEC) /*!< Voltage USB secure protection */ +#define PWR_ALL (PWR_WKUP1 | PWR_WKUP2 | PWR_WKUP3 | PWR_WKUP4 | \ + PWR_WKUP5 | PWR_WKUP6 | PWR_WKUP7 | PWR_WKUP8 | \ + PWR_LPM | PWR_SCM | PWR_VB | PWR_VUSB | \ + PWR_RET) +#else +#define PWR_ALL 0xFF /*!< Dummy Value */ +#endif /* PWR_SECCFGR_WUP1SEC */ + +/** + * @} + */ + +/** @defgroup PWR_Attributes PWR Attributes + * @brief PWR Privilege/NPrivilege and Secure/NSecure Attributes + * @{ + */ +#if defined(PWR_PRIVCFGR_NSPRIV) +#define PWR_NSEC_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< NSecure and Privileged attribute */ +#define PWR_NSEC_NPRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK) /*!< NSecure and NPrivileged attribute */ +#else +#define PWR_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< Privileged attribute */ +#define PWR_NPRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK) /*!< NPrivileged attribute */ +#endif /* PWR_PRIVCFGR_NSPRIV */ +#define PWR_SEC_PRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK | 0x02U) /*!< Secure and Privileged attribute */ +#define PWR_SEC_NPRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK) /*!< Secure and NPrivileged attribute */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @brief Check PWR flags are set or not. + * @param __FLAG__ : Specifies the flag to check. + * This parameter can be one of the following values : + * @arg @ref PWR_FLAG_STOPF : Stop flag. + * Indicates that the device was resumed from Stop mode. + * @arg @ref PWR_FLAG_SBF : Standby flag. + * Indicates that the device was resumed from Standby mode. + * @arg @ref PWR_FLAG_VOSRDY : Voltage scaling ready flag. + * Indicates that the Vcore level at or above VOS selected level. + * @arg @ref PWR_FLAG_ACTVOSRDY : Currently applied VOS ready flag. + * Indicates that Vcore is equal to the current + * voltage scaling provided by ACTVOS. + * @arg @ref PWR_FLAG_BRR : Backup regulator ready flag. This bit is not + * reset when the device wakes up from STANDBY + * mode or by a system reset or power-on reset. + * @arg @ref PWR_FLAG_VBATL : Backup domain voltage level flag (versus low threshold). + * Indicates the backup domain voltage + * level is equal or above low threshold. + * @arg @ref PWR_FLAG_VBATH : Backup domain voltage level flag (versus high threshold). + * Indicates the backup domain voltage + * level is equal or above high threshold. + * @arg @ref PWR_FLAG_TEMPL : Temperature level flag (versus low threshold). + * Indicates the temperature is equal or above low threshold. + * @arg @ref PWR_FLAG_TEMPH : Temperature level flag (versus high threshold). + * Indicates the temperature is equal or above high threshold. + * @arg @ref PWR_FLAG_AVDO : Regulator selection flag. + * Indicates the regulator selected. + * @arg @ref PWR_FLAG_VDDIO2RDY : VDDIO2 ready flag (versus 0.9 V threshold). + * Indicates that VDDIO2 is equal or above the threshold + * of the VDDIO2 voltage monitor (around 0.9 V). + * @arg @ref PWR_FLAG_PVDO : Voltage detector output flag. + * Indicates that Vdd is equal or above + * the PVD threshold selected by PVDLS. + * @arg @ref PWR_FLAG_USB33RDY : VDDUSB ready flag (versus 1.2 V threshold). + * Indicates that VDDUSB is equal or above the threshold + * of the VDDUSB voltage monitor (around 1.2 V). + * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1. + * Indicates that a wakeup event was received from the WKUP line 1. + * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2. + * Indicates that a wakeup event was received from the WKUP line 2. + * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3. + * Indicates that a wakeup event was received from the WKUP line 3. + * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4. + * Indicates that a wakeup event was received from the WKUP line 4. + * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5. + * Indicates that a wakeup event was received from the WKUP line 5. + * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6. + * Indicates that a wakeup event was received from the WKUP line 6. + * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7. + * Indicates that a wakeup event was received from the WKUP line 7. + * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8. + * Indicates that a wakeup event was received from the WKUP line 8. + * @note The PWR_WAKEUP_FLAG6, PWR_WAKEUP_FLAG7 AND PWR_WAKEUP_FLAG8 are not available for STM32H503xx devices. + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#if defined (PWR_WUSR_WUF6) +#define __HAL_PWR_GET_FLAG(__FLAG__) \ + (((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_STOPF) == PWR_PMSR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_SBF) == PWR_PMSR_SBF) : \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_VOSRDY) == PWR_VOSSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOSRDY) == PWR_VOSSR_ACTVOSRDY) : \ + ((__FLAG__) == PWR_FLAG_BRR) ? (READ_BIT(PWR->BDSR, PWR_BDSR_BRRDY) == PWR_BDSR_BRRDY) : \ + ((__FLAG__) == PWR_FLAG_VBATL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATL) == PWR_BDSR_VBATL) : \ + ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \ + ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \ + ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \ + ((__FLAG__) == PWR_FLAG_AVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_AVDO) == PWR_VMSR_AVDO) : \ + ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->VMSR, PWR_VMSR_VDDIO2RDY) == PWR_VMSR_VDDIO2RDY) : \ + ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == PWR_VMSR_PVDO) : \ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? (READ_BIT(PWR->VMSR, PWR_VMSR_USB33RDY) == PWR_VMSR_USB33RDY) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#else +#define __HAL_PWR_GET_FLAG(__FLAG__) \ + (((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_STOPF) == PWR_PMSR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_SBF) == PWR_PMSR_SBF) : \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_VOSRDY) == PWR_VOSSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOSRDY) == PWR_VOSSR_ACTVOSRDY) : \ + ((__FLAG__) == PWR_FLAG_BRR) ? (READ_BIT(PWR->BDSR, PWR_BDSR_BRRDY) == PWR_BDSR_BRRDY) : \ + ((__FLAG__) == PWR_FLAG_VBATL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATL) == PWR_BDSR_VBATL) : \ + ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \ + ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \ + ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \ + ((__FLAG__) == PWR_FLAG_AVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_AVDO) == PWR_VMSR_AVDO) : \ + ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->VMSR, PWR_VMSR_VDDIO2RDY) == PWR_VMSR_VDDIO2RDY) : \ + ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == PWR_VMSR_PVDO) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5)) +#endif /* PWR_WUSR_WUF6 */ + +/** @brief Clear PWR flags. + * @param __FLAG__ : Specifies the flag to clear. + * This parameter can be one of the following values : + * @arg @ref PWR_FLAG_STOPF : STOP flag. + * Indicates that the device was resumed from STOP mode. + * @arg @ref PWR_FLAG_SBF : STANDBY flag. + * Indicates that the device was resumed from STANDBY mode. + * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1. + * Indicates that a wakeup event was received from the WKUP line 1. + * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2. + * Indicates that a wakeup event was received from the WKUP line 2. + * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3. + * Indicates that a wakeup event was received from the WKUP line 3. + * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4. + * Indicates that a wakeup event was received from the WKUP line 4. + * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5. + * Indicates that a wakeup event was received from the WKUP line 5. + * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6. + * Indicates that a wakeup event was received from the WKUP line 6. + * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7. + * Indicates that a wakeup event was received from the WKUP line 7. + * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8. + * Indicates that a wakeup event was received from the WKUP line 8. + * @note The PWR_WAKEUP_FLAG6, PWR_WAKEUP_FLAG7 AND PWR_WAKEUP_FLAG8 are not available for STM32H503xx devices. + * @retval None. + */ +#if defined (PWR_WUSCR_CWUF6) +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \ + (((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \ + (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) +#else +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \ + (((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \ + (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) +#endif /* PWR_WUSCR_CWUF6 */ + +/** + * @brief Enable the PVD Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Event Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Event Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) + +/** + * @brief Check whether the specified PVD EXTI Rising interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_RISING_FLAG() \ + ((READ_BIT(EXTI->RPR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) + +/** + * @brief Check whether the specified PVD EXTI Falling interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG()\ + ((READ_BIT(EXTI->FPR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) + +/** + * @brief Clear the PVD EXTI Interrupt Rising flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); + +/** + * @brief Clear the PVD EXTI Interrupt Falling flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); + +/** + * @brief Clear the PVD EXTI Interrupt flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() \ + do \ + { \ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); \ + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); \ + } while(0) +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ +/* Define PVD extended interrupts and event line */ +#define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16 /*!< PVD EXTI Line */ + +/* Defines wake up lines shift */ +#define PWR_EWUP_MASK (0x0FFF3F3FU) + +/* Defines attribute */ +#define PWR_ITEM_ATTR_NSEC_PRIV_MASK (0x10U) /*!< NSecure Privilege / NPrivilege attribute item mask */ +#define PWR_ITEM_ATTR_SEC_PRIV_MASK (0x20U) /*!< Secure Privilege / NPrivilege attribute item mask */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ +#if defined(PWR_WUCR_WUPEN6) +/* Check wake up pin parameter */ +#define IS_PWR_WAKEUP_PIN(PIN) \ + (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN3) || ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN5) || ((PIN) == PWR_WAKEUP_PIN6) ||\ + ((PIN) == PWR_WAKEUP_PIN7) || ((PIN) == PWR_WAKEUP_PIN8) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH) || ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH) || ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN5_HIGH) || ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN7_HIGH) || ((PIN) == PWR_WAKEUP_PIN8_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW) || ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW) || ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN5_LOW) || ((PIN) == PWR_WAKEUP_PIN6_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN7_LOW) || ((PIN) == PWR_WAKEUP_PIN8_LOW)) +#else +/* Check wake up pin parameter */ +#define IS_PWR_WAKEUP_PIN(PIN) \ + (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN3) || ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN5) || ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH) || ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH) || ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW) || ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW) || ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN5_LOW)) +#endif /* PWR_WUCR_WUPEN6 */ + +/* PVD level check macro */ +#define IS_PWR_PVD_LEVEL(LEVEL) \ + (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) ||\ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) ||\ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) ||\ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) + +/* PVD mode check macro */ +#define IS_PWR_PVD_MODE(MODE) \ + (((MODE) == PWR_PVD_MODE_NORMAL) ||\ + ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) + +/* SLEEP mode entry check macro */ +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +/* STOP mode entry check macro */ +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) + +#if defined (PWR_SECCFGR_WUP1SEC) +/* PWR items check macro */ +#define IS_PWR_ITEMS_ATTRIBUTES(ITEM) ((((ITEM) & (~PWR_ALL)) == 0U) && ((ITEM) != 0U)) +#endif /* PWR_SECCFGR_WUP1SEC */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* PWR attribute check macro (Secure) */ +#define IS_PWR_ATTRIBUTES(ATTRIBUTES) \ + ((((~(((ATTRIBUTES) & 0xF0U) >> 4U)) &((ATTRIBUTES) & 0x0FU)) == 0U) && (((ATTRIBUTES) & 0xFFFFFFCCU) == 0U)) +#elif defined(PWR_PRIVCFGR_NSPRIV) +/* PWR attribute check macro (NSecure) */ +#define IS_PWR_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == PWR_NSEC_NPRIV) || ((ATTRIBUTES) == PWR_NSEC_PRIV)) +#else +/* PWR attribute check macro (NSecure) */ +#define IS_PWR_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == PWR_NPRIV) || ((ATTRIBUTES) == PWR_PRIV)) +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/* Include PWR HAL Extended module */ +#include "stm32h5xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 + * @{ + */ +/* Programmable voltage detector functions ************************************/ +HAL_StatusTypeDef HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* Wake up pins configuration functions ***************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low power modes configuration functions ************************************/ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +/* Sleep on exit and sev on pending configuration functions *******************/ +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + +/* Interrupt handler functions ************************************************/ +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group3 + * @{ + */ +/* Privileges and security configuration functions ****************************/ +void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes); +HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32H5xx_HAL_PWR_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h new file mode 100644 index 00000000..33ef4126 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h @@ -0,0 +1,605 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_PWR_EX_H +#define STM32H5xx_HAL_PWR_EX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Types PWR Extended Exported Types + * @{ + */ + +/** + * @brief PWREx AVD configuration structure definition + */ +typedef struct +{ + uint32_t AVDLevel; /*!< AVDLevel: Specifies the AVD detection level. This + parameter can be a value of @ref + PWREx_AVD_detection_level + */ + + uint32_t Mode; /*!< Mode: Specifies the EXTI operating mode for the AVD + event. This parameter can be a value of @ref + PWREx_AVD_Mode. + */ +} PWREx_AVDTypeDef; + +/** + * @brief PWREx Wakeup pin configuration structure definition + */ +typedef struct +{ + uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled. + This parameter can be a value of @ref + PWREx_WakeUp_Pins + */ + + uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity. + This parameter can be a value of @ref + PWREx_PIN_Polarity + */ + + uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull. This + parameter can be a value of @ref + PWREx_PIN_Pull + */ +} PWREx_WakeupPinTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants + * @{ + */ + +/** @defgroup PWREx_Supply_configuration PWREx Supply configuration + * @{ + */ +#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_SCCR_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains + are supplied from an external source */ + +#if defined (SMPS) +#define PWR_SUPPLY_CONFIG_MASK (PWR_SCCR_SMPSEN | PWR_SCCR_LDOEN | PWR_SCCR_BYPASS) +#else +#define PWR_SUPPLY_CONFIG_MASK (PWR_SCCR_LDOEN | PWR_SCCR_BYPASS) +#endif /* defined (SMPS) */ +/** + * @} + */ + +/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration + * @{ + */ +#define PWR_PIN_POLARITY_HIGH (0x00000000U) +#define PWR_PIN_POLARITY_LOW (0x00000001U) +/** + * @} + */ + +/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration + * @{ + */ +#define PWR_PIN_NO_PULL (0x00000000U) +#define PWR_PIN_PULL_UP (0x00000001U) +#define PWR_PIN_PULL_DOWN (0x00000002U) +/** + * @} + */ + +/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level + * @{ + */ +#define PWR_AVDLEVEL_0 (0x00000000U) /*!< Analog voltage detector level 0 selection : 1V7 */ +#define PWR_AVDLEVEL_1 PWR_VMCR_ALS_0 /*!< Analog voltage detector level 1 selection : 2V1 */ +#define PWR_AVDLEVEL_2 PWR_VMCR_ALS_1 /*!< Analog voltage detector level 2 selection : 2V5 */ +#define PWR_AVDLEVEL_3 PWR_VMCR_ALS /*!< Analog voltage detector level 3 selection : 2V8 */ +/** + * @} + */ + +/** @defgroup PWREx_AVD_Mode PWREx AVD Mode + * @{ + */ +#define PWR_AVD_MODE_NORMAL (0x00000000U)/*!< Basic mode is used */ +#define PWR_AVD_MODE_IT_RISING (0x00010001U)/*!< External Interrupt Mode with Rising edge trigger detection*/ +#define PWR_AVD_MODE_IT_FALLING (0x00010002U)/*!< External Interrupt Mode with + Falling edge trigger detection */ +#define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U)/*!< External Interrupt Mode with + Rising/Falling edge trigger detection */ +#define PWR_AVD_MODE_EVENT_RISING (0x00020001U)/*!< Event Mode with Rising edge trigger detection */ +#define PWR_AVD_MODE_EVENT_FALLING (0x00020002U)/*!< Event Mode with Falling edge trigger detection */ +#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)/*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale + * @{ + */ +#define PWR_REGULATOR_VOLTAGE_SCALE0 PWR_VOSCR_VOS /*!< Voltage scaling range 0 */ +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_VOSCR_VOS_1 /*!< Voltage scaling range 1 */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_VOSCR_VOS_0 /*!< Voltage scaling range 2 */ +#define PWR_REGULATOR_VOLTAGE_SCALE3 (0U) /*!< Voltage scaling range 3 */ +/** + * @} + */ + +/** @defgroup PWREx_System_Stop_Mode_Voltage_Scale PWREx System Stop Mode Voltage Scale + * @{ + */ +#define PWR_REGULATOR_SVOS_SCALE5 (PWR_PMCR_SVOS_0) +#define PWR_REGULATOR_SVOS_SCALE4 (PWR_PMCR_SVOS_1) +#define PWR_REGULATOR_SVOS_SCALE3 (PWR_PMCR_SVOS_0 | PWR_PMCR_SVOS_1) +/** + * @} + */ + +/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR Extended Battery Charging Resistor Selection + * @{ + */ +#define PWR_BATTERY_CHARGING_RESISTOR_5 (0U) /*!< VBAT charging through a 5 kOhms resistor */ +#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_BDCR_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ +/** + * @} + */ + +/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection + * @{ + */ +#define PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO /*!< RAM1 shut-off control in Stop mode */ +#if defined (PWR_PMCR_SRAM2_16SO) +#define PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO /*!< RAM2 16k byte shut-off control in Stop mode */ +#define PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO /*!< RAM2 48k byte shut-off control in Stop mode */ +#elif defined (PWR_PMCR_SRAM2_16LSO) +#define PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO /*!< RAM2 low 16k byte shut-off control in Stop mode */ +#define PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO /*!< RAM2 High 16k byte shut-off control in Stop mode */ +#if defined (PWR_PMCR_SRAM2_48LSO) +#define PWR_RAM2_LOW_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48LSO /*!< RAM2 low 48k byte shut-off control in Stop mode */ +#define PWR_RAM2_HIGH_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48HSO /*!< RAM2 High 48k byte shut-off control in Stop mode */ +#else +#define PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO /*!< RAM2 48k byte shut-off control in Stop mode */ +#endif /* PWR_PMCR_SRAM2_48LSO */ +#else +#define PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO /*!< RAM2 shut-off control in Stop mode */ +#endif /* PWR_PMCR_SRAM2_16SO */ +#if defined (PWR_PMCR_SRAM3SO) +#define PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO /*!< RAM3 shut-off control in Stop mode */ +#endif /* PWR_PMCR_SRAM3SO */ +#if defined (PWR_PMCR_SRAM4SO) +#define PWR_RAM4_MEMORY_BLOCK PWR_PMCR_SRAM4SO /*!< RAM4 shut-off control in Stop mode */ +#endif /* PWR_PMCR_SRAM4SO */ +#if defined (PWR_PMCR_SRAM5SO) +#define PWR_RAM5_MEMORY_BLOCK PWR_PMCR_SRAM5SO /*!< RAM5 shut-off control in Stop mode */ +#endif /* PWR_PMCR_SRAM5SO */ +#if defined (PWR_PMCR_ETHERNETSO) +#define PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO /*!< Ethernet shut-off control in Stop mode */ +#endif /* PWR_PMCR_ETHERNETSO */ +#if defined (PWR_PMCR_LTDCSO) +#define PWR_LTDC_MEMORY_BLOCK PWR_PMCR_LTDCSO /*!< LTDC shut-off control in Stop mode */ +#endif /* PWR_PMCR_LTDCSO */ + +/** + * @} + */ + +/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16 + * @{ + */ +#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16 + Connected to the AVD EXTI Line */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros + * @{ + */ + +/** + * @brief Enable the AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable the AVD EXTI Line 16 + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable event on AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable event on AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable the AVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable the AVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable the AVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable the AVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0); + +/** + * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0); + +/** + * @brief Check whether the specified AVD EXTI Rising interrupt flag is set or not. + * @retval EXTI AVD Line Status. + */ + +#define __HAL_PWR_PVD_AVD_EXTI_GET_RISING_FLAG() ((READ_BIT(EXTI->RPR1, PWR_EXTI_LINE_AVD)\ + == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) + +/** + * @brief Check whether the specified AVD EXTI Falling interrupt flag is set or not. + * @retval EXTI AVD Line Status. + */ + +#define __HAL_PWR_PVD_AVD_EXTI_GET_FALLING_FLAG() ((READ_BIT(EXTI->FPR1, PWR_EXTI_LINE_AVD)\ + == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) + +/** + * @brief Clear the AVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_AVD_EXTI_CLEAR_FLAG() \ + do \ + { \ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVD); \ + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVD); \ + } while(0) + +/** + * @brief Generates a Software interrupt on AVD EXTI line. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD) + +/** + * @brief Configure the main internal regulator output voltage. + * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but + * doesn't check whether or not VOSREADY flag is set. User may resort + * to __HAL_PWR_GET_FLAG() macro to check VOSF bit state. + * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a + * tradeoff between performance and power consumption. + * This parameter can be one of the following values : + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output scale 0. + * Provides a typical output voltage at 1.2 V. + * Used when system clock frequency is up to 160 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1. + * Provides a typical output voltage at 1.1 V. + * Used when system clock frequency is up to 100 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2. + * Provides a typical output voltage at 1.0 V. + * Used when system clock frequency is up to 50 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output scale 3. + * Provides a typical output voltage at 0.9 V. + * Used when system clock frequency is up to 24 MHz. + * @retval None. + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ + do \ + { \ + __IO uint32_t tmpreg; \ + MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->VOSCR, PWR_VOSCR_VOS); \ + UNUSED(tmpreg); \ + } while(0) +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @defgroup PWREx_Private_Constants PWR Extended Private Constants + * @{ + */ + +/** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask + * @{ + */ +#define AVD_MODE_IT (0x00010000U) +#define AVD_MODE_EVT (0x00020000U) +#define AVD_RISING_EDGE (0x00000001U) +#define AVD_FALLING_EDGE (0x00000002U) +#define AVD_RISING_FALLING_EDGE (0x00000003U) +/** + * @} + */ + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ + +/** @defgroup PWREx_Private_Macros PWR Extended Private Macros + * @{ + */ +/* Check PWR regulator configuration parameter */ +#define IS_PWR_SUPPLY(PWR_SOURCE) ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY) + +/* Check wake up pin polarity parameter */ +#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\ + ((POLARITY) == PWR_PIN_POLARITY_LOW)) + +/* Check wake up pin pull configuration parameter */ +#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\ + ((PULL) == PWR_PIN_PULL_UP) ||\ + ((PULL) == PWR_PIN_PULL_DOWN)) + +/* Check wake up flag parameter */ +#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ + ((FLAG) == PWR_WAKEUP_FLAG2) ||\ + ((FLAG) == PWR_WAKEUP_FLAG3) ||\ + ((FLAG) == PWR_WAKEUP_FLAG4) ||\ + ((FLAG) == PWR_WAKEUP_FLAG5) ||\ + ((FLAG) == PWR_WAKEUP_FLAG6) ||\ + ((FLAG) == PWR_WAKEUP_FLAG_ALL)) + +/* Voltage scaling range check macro */ +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE0) ||\ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) ||\ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) ||\ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) + +/* Check PWR regulator configuration in STOP mode parameter */ +#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) ||\ + ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) ||\ + ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5)) + +/* Battery charging resistor selection check macro */ +#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ + ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) + +/* Check memory block parameter */ +#if defined (PWR_PMCR_SRAM2_16SO) +#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_ETHERNET_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM3_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_16_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_48_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_MEMORY_BLOCK)) + +#elif defined (PWR_PMCR_SRAM2_48SO) +#if defined (PWR_PMCR_ETHERNETSO) +#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_ETHERNET_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM3_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_LOW_16_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_HIGH_16_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_48_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_MEMORY_BLOCK)) +#else +#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_RAM3_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_LOW_16_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_HIGH_16_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_48_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_MEMORY_BLOCK)) +#endif /* PWR_PMCR_ETHERNETSO */ +#elif defined (PWR_PMCR_SRAM2_48LSO) +#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_ETHERNET_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_LTDC_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM5_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM4_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM3_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_LOW_16_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_HIGH_16_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_LOW_48_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_HIGH_48_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_MEMORY_BLOCK)) +#elif defined (PWR_PMCR_SRAM2_16LSO) +#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_RAM3_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_LOW_16_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_HIGH_16_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_48_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_MEMORY_BLOCK)) +#else +#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_RAM2_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_MEMORY_BLOCK)) +#endif /* PWR_PMCR_SRAM2_16SO */ + +/* Check wake up flag parameter */ +#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\ + ((LEVEL) == PWR_AVDLEVEL_1) ||\ + ((LEVEL) == PWR_AVDLEVEL_2) ||\ + ((LEVEL) == PWR_AVDLEVEL_3)) + +/* Check AVD mode parameter */ +#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_AVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_NORMAL) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING)) +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource); +uint32_t HAL_PWREx_GetSupplyConfig(void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetStopModeVoltageRange(void); + +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group2 + * @{ + */ +void HAL_PWREx_ConfigAVD(const PWREx_AVDTypeDef *sConfigAVD); +void HAL_PWREx_EnableAVD(void); +void HAL_PWREx_DisableAVD(void); +#if defined (PWR_USBSCR_USB33DEN) +void HAL_PWREx_EnableUSBVoltageDetector(void); +void HAL_PWREx_DisableUSBVoltageDetector(void); +void HAL_PWREx_EnableVddUSB(void); +void HAL_PWREx_DisableVddUSB(void); +void HAL_PWREx_EnableUSBOTGHSPhy(void); +void HAL_PWREx_DisableUSBOTGHSPhy(void); +#endif /* PWR_USBSCR_USB33DEN */ +void HAL_PWREx_EnableMonitoring(void); +void HAL_PWREx_DisableMonitoring(void); +void HAL_PWREx_EnableUCPDStandbyMode(void); +void HAL_PWREx_DisableUCPDStandbyMode(void); +void HAL_PWREx_EnableUCPDDeadBattery(void); +void HAL_PWREx_DisableUCPDDeadBattery(void); +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue); +void HAL_PWREx_DisableBatteryCharging(void); +void HAL_PWREx_EnableAnalogBooster(void); +void HAL_PWREx_DisableAnalogBooster(void); +void HAL_PWREx_PVD_AVD_IRQHandler(void); +void HAL_PWREx_PVD_AVD_Rising_Callback(void); +void HAL_PWREx_PVD_AVD_Falling_Callback(void); + +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group3 + * @{ + */ + +void HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef *sPinParams); +void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPinx); + +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group4 + * @{ + */ +void HAL_PWREx_EnableFlashPowerDown(void); +void HAL_PWREx_DisableFlashPowerDown(void); +void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock); +void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock); +HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void); +void HAL_PWREx_DisableBkupRAMRetention(void); + +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group5 + * @{ + */ +void HAL_PWREx_EnableStandbyIORetention(void); +void HAL_PWREx_DisableStandbyIORetention(void); +void HAL_PWREx_EnableStandbyJTAGIORetention(void); +void HAL_PWREx_DisableStandbyJTAGIORetention(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32H5xx_HAL_PWR_EX_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h new file mode 100644 index 00000000..a8ed92eb --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h @@ -0,0 +1,5953 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H5xx_HAL_RCC_H +#define __STM32H5xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL1 configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< PLLState: The new state of the PLL1. + This parameter can be a value of @ref RCC_PLL1_Config */ + + uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL1_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL1 VCO input clock. + This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL1 VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ + + uint32_t PLLP; /*!< PLLP: Division factor for system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + odd division factors are not allowed */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range + This parameter must be a value of @ref RCC_PLL1_VCI_Range */ + + uint32_t PLLVCOSEL; /*!< PLLVCOSEL: PLL1 clock Output range + This parameter must be a value of @ref RCC_PLL1_VCO_Range */ + + uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for + PLL1 VCO It should be a value between 0 and 8191 */ + +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSIDiv; /*!< The division factor of the HSI. + This parameter can be a value of @ref RCC_HSI_Div */ + + uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F + on the other devices */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + uint32_t CSIState; /*!< The new state of the CSI. + This parameter can be a value of @ref RCC_CSI_Config */ + + uint32_t CSICalibrationValue; /*!< The calibration trimming value (default is RCC_CSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F */ + + uint32_t HSI48State; /*!< The new state of the HSI48. + This parameter can be a value of @ref RCC_HSI48_Config */ + + RCC_PLLInitTypeDef PLL; /*!< PLL1 structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ + + uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Peripheral_Memory_Mapping Peripheral Memory Mapping + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE (0x00000000U) /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE (0x00000001U) /*!< HSE to configure */ +#define RCC_OSCILLATORTYPE_HSI (0x00000002U) /*!< HSI to configure */ +#define RCC_OSCILLATORTYPE_LSE (0x00000004U) /*!< LSE to configure */ +#define RCC_OSCILLATORTYPE_LSI (0x00000008U) /*!< LSI to configure */ +#define RCC_OSCILLATORTYPE_CSI (0x00000010U) /*!< CSI to configure */ +#define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) /*!< HSI48 to configure */ +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External Analog clock source for HSE clock */ +#define RCC_HSE_BYPASS_DIGITAL ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External Digital clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External Analog clock source for LSE clock Bypassed*/ +#define RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External Digital clock source for LSE clock Bypassed */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ + +#define RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Div HSI Div + * @{ + */ +#define RCC_HSI_DIV1 0x00000000U /*!< HSI clock is not divided */ +#define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock is divided by 2 */ +#define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock is divided by 4 */ +#define RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_BDCR_LSION /*!< LSI clock activation */ +/** + * @} + */ + +/** @defgroup RCC_CSI_Config CSI Config + * @{ + */ +#define RCC_CSI_OFF (0x00000000U) /*!< CSI clock deactivation */ +#define RCC_CSI_ON RCC_CR_CSION /*!< CSI clock activation */ + +#define RCC_CSICALIBRATION_DEFAULT (0x20U) /*!< Default CSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_HSI48_Config HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF (0x00000000U) /*!< HSI48 clock deactivation */ +#define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ +/** + * @} + */ + +/** @defgroup RCC_PLL1_Config RCC PLL1 Config + * @{ + */ +#define RCC_PLL_NONE (0x00000000U) +#define RCC_PLL_OFF (0x00000001U) +#define RCC_PLL_ON (0x00000002U) +/** + * @} + */ + +/** @defgroup RCC_PLL1_Clock_Output RCC PLL1 Clock Output + * @{ + */ +#define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN +#define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN +#define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN +/** + * @} + */ + +/** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range + * @{ + */ +#define RCC_PLL1_VCIRANGE_0 (0x00000000U) /*!< Clock range frequency between 1 and 2 MHz */ +#define RCC_PLL1_VCIRANGE_1 RCC_PLL1CFGR_PLL1RGE_0 /*!< Clock range frequency between 2 and 4 MHz */ +#define RCC_PLL1_VCIRANGE_2 RCC_PLL1CFGR_PLL1RGE_1 /*!< Clock range frequency between 4 and 8 MHz */ +#define RCC_PLL1_VCIRANGE_3 (RCC_PLL1CFGR_PLL1RGE_0 | RCC_PLL1CFGR_PLL1RGE_1) /*!< Clock range frequency between 8 and 16 MHz */ +/** + * @} + */ + +/** @defgroup RCC_PLL1_VCO_Range RCC PLL1 VCO Range + * @{ + */ +#define RCC_PLL1_VCORANGE_WIDE (0x00000000U) /*!< Clock range frequency between 192 and 836 MHz */ +#define RCC_PLL1_VCORANGE_MEDIUM RCC_PLL1CFGR_PLL1VCOSEL /*!< Clock range frequency between 150 and 420 MHz */ + +/** + * @} + */ + +/** @defgroup RCC_PLL1_Clock_Source RCC PLL1 Clock Source + * @{ + */ +#define RCC_PLL1_SOURCE_NONE (0x00000000U) +#define RCC_PLL1_SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_0 +#define RCC_PLL1_SOURCE_CSI RCC_PLL1CFGR_PLL1SRC_1 +#define RCC_PLL1_SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) +/** + * @} + */ + + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */ +#define RCC_CLOCKTYPE_PCLK3 (0x00000010U) /*!< PCLK3 to configure */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI (0x00000000U) /*!< HSI selection as system clock */ +#define RCC_SYSCLKSOURCE_CSI RCC_CFGR1_SW_0 /*!< CSI selection as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR1_SW_0 | RCC_CFGR1_SW_1) /*!< PLL1 selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI (0x00000000U) /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR1_SWS_0 /*!< CSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1) /*!< PLL1 used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 (0x00000000U) /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_APB3_Clock_Source APB1 APB2 APB3 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler + * @{ + */ +#define RCC_RTC_HSE_NOCLOCK (0x00000000U) +#define RCC_RTC_HSE_DIV2 (0x00000200U) +#define RCC_RTC_HSE_DIV3 (0x00000300U) +#define RCC_RTC_HSE_DIV4 (0x00000400U) +#define RCC_RTC_HSE_DIV5 (0x00000500U) +#define RCC_RTC_HSE_DIV6 (0x00000600U) +#define RCC_RTC_HSE_DIV7 (0x00000700U) +#define RCC_RTC_HSE_DIV8 (0x00000800U) +#define RCC_RTC_HSE_DIV9 (0x00000900U) +#define RCC_RTC_HSE_DIV10 (0x00000A00U) +#define RCC_RTC_HSE_DIV11 (0x00000B00U) +#define RCC_RTC_HSE_DIV12 (0x00000C00U) +#define RCC_RTC_HSE_DIV13 (0x00000D00U) +#define RCC_RTC_HSE_DIV14 (0x00000E00U) +#define RCC_RTC_HSE_DIV15 (0x00000F00U) +#define RCC_RTC_HSE_DIV16 (0x00001000U) +#define RCC_RTC_HSE_DIV17 (0x00001100U) +#define RCC_RTC_HSE_DIV18 (0x00001200U) +#define RCC_RTC_HSE_DIV19 (0x00001300U) +#define RCC_RTC_HSE_DIV20 (0x00001400U) +#define RCC_RTC_HSE_DIV21 (0x00001500U) +#define RCC_RTC_HSE_DIV22 (0x00001600U) +#define RCC_RTC_HSE_DIV23 (0x00001700U) +#define RCC_RTC_HSE_DIV24 (0x00001800U) +#define RCC_RTC_HSE_DIV25 (0x00001900U) +#define RCC_RTC_HSE_DIV26 (0x00001A00U) +#define RCC_RTC_HSE_DIV27 (0x00001B00U) +#define RCC_RTC_HSE_DIV28 (0x00001C00U) +#define RCC_RTC_HSE_DIV29 (0x00001D00U) +#define RCC_RTC_HSE_DIV30 (0x00001E00U) +#define RCC_RTC_HSE_DIV31 (0x00001F00U) +#define RCC_RTC_HSE_DIV32 (0x00002000U) +#define RCC_RTC_HSE_DIV33 (0x00002100U) +#define RCC_RTC_HSE_DIV34 (0x00002200U) +#define RCC_RTC_HSE_DIV35 (0x00002300U) +#define RCC_RTC_HSE_DIV36 (0x00002400U) +#define RCC_RTC_HSE_DIV37 (0x00002500U) +#define RCC_RTC_HSE_DIV38 (0x00002600U) +#define RCC_RTC_HSE_DIV39 (0x00002700U) +#define RCC_RTC_HSE_DIV40 (0x00002800U) +#define RCC_RTC_HSE_DIV41 (0x00002900U) +#define RCC_RTC_HSE_DIV42 (0x00002A00U) +#define RCC_RTC_HSE_DIV43 (0x00002B00U) +#define RCC_RTC_HSE_DIV44 (0x00002C00U) +#define RCC_RTC_HSE_DIV45 (0x00002D00U) +#define RCC_RTC_HSE_DIV46 (0x00002E00U) +#define RCC_RTC_HSE_DIV47 (0x00002F00U) +#define RCC_RTC_HSE_DIV48 (0x00003000U) +#define RCC_RTC_HSE_DIV49 (0x00003100U) +#define RCC_RTC_HSE_DIV50 (0x00003200U) +#define RCC_RTC_HSE_DIV51 (0x00003300U) +#define RCC_RTC_HSE_DIV52 (0x00003400U) +#define RCC_RTC_HSE_DIV53 (0x00003500U) +#define RCC_RTC_HSE_DIV54 (0x00003600U) +#define RCC_RTC_HSE_DIV55 (0x00003700U) +#define RCC_RTC_HSE_DIV56 (0x00003800U) +#define RCC_RTC_HSE_DIV57 (0x00003900U) +#define RCC_RTC_HSE_DIV58 (0x00003A00U) +#define RCC_RTC_HSE_DIV59 (0x00003B00U) +#define RCC_RTC_HSE_DIV60 (0x00003C00U) +#define RCC_RTC_HSE_DIV61 (0x00003D00U) +#define RCC_RTC_HSE_DIV62 (0x00003E00U) +#define RCC_RTC_HSE_DIV63 (0x00003F00U) +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock used as RTC clock source */ +#define RCC_RTCCLKSOURCE_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock source */ +#define RCC_RTCCLKSOURCE_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock source */ +#define RCC_RTCCLKSOURCE_HSE_DIVx (0x00000300U) /*!< HSE oscillator clock divided by X used as RTC clock source */ +#define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U) +#define RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U) +#define RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U) +#define RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U) +#define RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U) +#define RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U) +#define RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U) +#define RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U) +#define RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U) +#define RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U) +#define RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U) +#define RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U) +#define RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U) +#define RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U) +#define RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U) +#define RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U) +#define RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U) +#define RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U) +#define RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U) +#define RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U) +#define RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U) +#define RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U) +#define RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U) +#define RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U) +#define RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U) +#define RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U) +#define RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U) +#define RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U) +#define RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U) +#define RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U) +#define RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U) +#define RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U) +#define RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U) +#define RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U) +#define RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U) +#define RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U) +#define RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U) +#define RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U) +#define RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U) +#define RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U) +#define RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U) +#define RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U) +#define RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U) +#define RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U) +#define RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U) +#define RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U) +#define RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U) +#define RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U) +#define RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U) +#define RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U) +#define RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U) +#define RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U) +#define RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U) +#define RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U) +#define RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U) +#define RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U) +#define RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U) +#define RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U) +#define RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U) +#define RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U) +#define RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U) +#define RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U) +/** + * @} + */ + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 (0x00000000U) +#define RCC_MCO2 (0x00000001U) +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_HSI (0x00000000U) +#define RCC_MCO1SOURCE_LSE RCC_CFGR1_MCO1SEL_0 +#define RCC_MCO1SOURCE_HSE RCC_CFGR1_MCO1SEL_1 +#define RCC_MCO1SOURCE_PLL1Q ((uint32_t)RCC_CFGR1_MCO1SEL_0 | RCC_CFGR1_MCO1SEL_1) +#define RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCO1SEL_2 + +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_SYSCLK (0x00000000U) +#define RCC_MCO2SOURCE_PLL2P RCC_CFGR1_MCO2SEL_0 +#define RCC_MCO2SOURCE_HSE RCC_CFGR1_MCO2SEL_1 +#define RCC_MCO2SOURCE_PLL1P ((uint32_t)RCC_CFGR1_MCO2SEL_0 | RCC_CFGR1_MCO2SEL_1) +#define RCC_MCO2SOURCE_CSI RCC_CFGR1_MCO2SEL_2 +#define RCC_MCO2SOURCE_LSI ((uint32_t)RCC_CFGR1_MCO2SEL_0 | RCC_CFGR1_MCO2SEL_2) + +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 RCC_CFGR1_MCO1PRE_0 +#define RCC_MCODIV_2 RCC_CFGR1_MCO1PRE_1 +#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1) +#define RCC_MCODIV_4 RCC_CFGR1_MCO1PRE_2 +#define RCC_MCODIV_5 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2) +#define RCC_MCODIV_6 ((uint32_t)RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2) +#define RCC_MCODIV_7 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2) +#define RCC_MCODIV_8 RCC_CFGR1_MCO1PRE_3 +#define RCC_MCODIV_9 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_3) +#define RCC_MCODIV_10 ((uint32_t)RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3) +#define RCC_MCODIV_11 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3) +#define RCC_MCODIV_12 ((uint32_t)RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) +#define RCC_MCODIV_13 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) +#define RCC_MCODIV_14 ((uint32_t)RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) +#define RCC_MCODIV_15 RCC_CFGR1_MCO1PRE +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define RCC_IT_CSIRDY RCC_CIFR_CSIRDYF /*!< CSI Ready Interrupt flag */ +#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ +#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#define RCC_IT_PLL1RDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */ +#define RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ +#if defined(RCC_CR_PLL3ON) +#define RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF /*!< PLL3 Ready Interrupt flag */ +#endif /* RCC_CR_PLL3ON */ +#define RCC_IT_HSECSS RCC_CIFR_HSECSSF /*!< HSE Clock Security System Interrupt flag */ + +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: BDCR register + * - 011: RSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_CSIRDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_CSIRDY_Pos)) /*!< CSI Ready flag */ +#define RCC_FLAG_HSIRDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ +#define RCC_FLAG_HSIDIVF ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSIDIVF_Pos)) /*!< HSI divider flag */ +#define RCC_FLAG_HSERDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ +#define RCC_FLAG_PLL1RDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos)) /*!< PLL1 Ready flag */ +#define RCC_FLAG_PLL2RDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) /*!< PLL2 Ready flag */ +#if defined(RCC_CR_PLL3ON) +#define RCC_FLAG_PLL3RDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /*!< PLL3 Ready flag */ +#endif /* RCC_CR_PLL3ON */ +#define RCC_FLAG_HSI48RDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint32_t)((RCC_BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */ +#define RCC_FLAG_LSECSSD ((uint32_t)((RCC_BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ +#define RCC_FLAG_LSIRDY ((uint32_t)((RCC_BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */ + +/* Flags in the RSR register */ +#define RCC_FLAG_RMVF ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_RMVF_Pos)) /*!< Remove reset flag */ +#define RCC_FLAG_PINRST ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_PINRSTF_Pos)) /*!< PIN reset flag */ +#define RCC_FLAG_BORRST ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_BORRSTF_Pos)) /*!< BOR reset flag */ +#define RCC_FLAG_SFTRST ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_SFTRSTF_Pos)) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ + +/** + * @} + */ + +/** @defgroup RCC_Reset_Flag Reset Flag + * @{ + */ +#define RCC_RESET_FLAG_PIN RCC_RSR_PINRSTF /*!< PIN reset flag */ +#define RCC_RESET_FLAG_PWR RCC_RSR_BORRSTF /*!< BOR or POR/PDR reset flag */ +#define RCC_RESET_FLAG_SW RCC_RSR_SFTRSTF /*!< Software Reset flag */ +#define RCC_RESET_FLAG_IWDG RCC_RSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define RCC_RESET_FLAG_WWDG RCC_RSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define RCC_RESET_FLAG_LPWR RCC_RSR_LPWRRSTF /*!< Low power reset flag */ +#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | RCC_RESET_FLAG_SW | \ + RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | RCC_RESET_FLAG_LPWR) +/** + * @} + */ + +/** @defgroup RCC_LSEDrive_Config LSE Drive Config + * @{ + */ +#if !defined(STM32H5E5xx) && !defined(STM32H5E4xx) && !defined(STM32H5F5xx) && !defined(STM32H5F4xx) +#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< LSE low drive capability */ +#endif /* !STM32H5E5xx && !STM32H5E4xx && !STM32H5F5xx && !STM32H5F4xx */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ +/** + * @} + */ + +/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock + * @{ + */ +#define RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U) /*!< HSI selection after wake-up from STOP */ +#define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR1_STOPWUCK /*!< CSI selection after wake-up from STOP */ +/** + * @} + */ + +/** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock + * @{ + */ +#define RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U) /*!< HSI kernel clock selection after wake-up from STOP */ +#define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR1_STOPKERWUCK /*!< CSI kernel clock selection after wake-up from STOP */ + +/** + * @} + */ + +#if defined(RCC_SECCFGR_HSISEC) +/** @defgroup RCC_items RCC items + * @brief RCC items to configure attributes on + * @{ + */ +#define RCC_HSI RCC_SECCFGR_HSISEC +#define RCC_HSE RCC_SECCFGR_HSESEC +#define RCC_CSI RCC_SECCFGR_CSISEC +#define RCC_LSI RCC_SECCFGR_LSISEC +#define RCC_LSE RCC_SECCFGR_LSESEC +#define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC +#define RCC_PRESC RCC_SECCFGR_PRESCSEC +#define RCC_PLL1 RCC_SECCFGR_PLL1SEC +#define RCC_PLL2 RCC_SECCFGR_PLL2SEC +#if defined(RCC_CR_PLL3ON) +#define RCC_PLL3 RCC_SECCFGR_PLL3SEC +#endif /* RCC_CR_PLL3ON */ +#define RCC_HSI48 RCC_SECCFGR_HSI48SEC +#define RCC_RMVF RCC_SECCFGR_RMVFSEC +#define RCC_CKPERSEL RCC_SECCFGR_CKPERSELSEC +#if defined(RCC_CR_PLL3ON) +#define RCC_ALL (RCC_HSI|RCC_HSE|RCC_CSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ + RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \ + RCC_PLL3|RCC_CKPERSEL|RCC_RMVF) +#else +#define RCC_ALL (RCC_HSI|RCC_HSE|RCC_CSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ + RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \ + RCC_CKPERSEL|RCC_RMVF) +#endif /* RCC_CR_PLL3ON */ +/** + * @} + */ +#endif /* RCC_SECCFGR_HSISEC */ + +/** @defgroup RCC_attributes RCC attributes + * @brief RCC privilege/non-privilege and secure/non-secure attributes + * @{ + */ +#if defined(RCC_PRIVCFGR_NSPRIV) +#define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ +#define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ +#else +#define RCC_PRIV 0x00000001U /*!< Privilege attribute item */ +#define RCC_NPRIV 0x00000002U /*!< Non-privilege attribute item */ +#endif /* RCC_PRIVCFGR_NSPRIV */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ +#define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPDMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* CORDIC */ + +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* FMAC */ + +#if defined(MDF1) +#define __HAL_RCC_MDF1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* MDF1 */ + +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FLASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(ETH) +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETHTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETHRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\ + UNUSED(tmpreg); \ + } while(0) +#if defined(RCC_AHB1ENR_ETHCKEN) +#define __HAL_RCC_ETHINTERN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHCKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHCKEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB1ENR_ETHCKEN */ +#endif /*ETH*/ + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* DMA2D */ + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* JPEG */ + +#define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DCACHE1) +#define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DCACHE1 */ + +#define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) + +#define __HAL_RCC_GPDMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) + +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) +#endif /* CORDIC */ + +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) +#endif /* FMAC */ + +#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) + +#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) + +#if defined(MDF1) +#define __HAL_RCC_MDF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) +#endif /* MDF1 */ + +#define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) + +#if defined(ETH) +#define __HAL_RCC_ETH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) + +#define __HAL_RCC_ETHTX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) + +#define __HAL_RCC_ETHRX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) + +#if defined(RCC_AHB1ENR_ETHCKEN) +#define __HAL_RCC_ETHINTERN_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHCKEN) +#endif /* RCC_AHB1ENR_ETHCKEN */ +#endif /*ETH*/ + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) +#endif /* DMA2D */ + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) +#endif /* JPEG */ + +#define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) + +#define __HAL_RCC_BKPRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) + +#if defined(DCACHE1) +#define __HAL_RCC_DCACHE1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) +#endif /* DCACHE1 */ + +#define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOE */ + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOF */ + +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOG */ + +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOJEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOJEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DCMI) +#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility */ +#endif /* DCMI */ + +#if defined(RCC_AHB2ENR_OTGPHYEN) +#define __HAL_RCC_OTGPHY_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGPHYEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGPHYEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB2ENR_OTGPHYEN */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* HASH */ + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(PKA) +#define __HAL_RCC_PKA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* PKA */ + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SAES */ + +#if defined(CCB) +#define __HAL_RCC_CCB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CCBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CCBEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* CCB */ + +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC3EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* ADC3 */ + +#if defined(ADF1) +#define __HAL_RCC_ADF1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADF1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADF1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* ADF1 */ + +#if defined(GPIOK) +#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOKEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOKEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOK */ + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGHSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGHSEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USB_OTG_FS */ + +#if defined(SRAM4_BASE) +#define __HAL_RCC_SRAM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM4EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SRAM4_BASE */ + +#if defined(SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM5EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SRAM5_BASE */ + +#define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ + UNUSED(tmpreg); \ + } while(0) +#if defined(SRAM3_BASE) +#define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SRAM3_BASE */ + +#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) + +#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) + +#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) + +#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) + +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) +#endif /* GPIOE */ + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) +#endif /* GPIOF */ + +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) +#endif /* GPIOG */ + +#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOJEN) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) + +#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) + +#if defined(DCMI) +#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) +#define __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/ +#endif /* DCMI */ + +#if defined(RCC_AHB2ENR_OTGPHYEN) +#define __HAL_RCC_OTGPHY_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGPHYEN); +#endif /* RCC_AHB2ENR_OTGPHYEN */ + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGHSEN); +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); +#endif /* USB_OTG_FS */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) +#endif /* HASH */ + +#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) + +#if defined(PKA) +#define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) +#endif /* PKA */ + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) +#endif /* SAES */ + +#if defined(CCB) +#define __HAL_RCC_CCB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CCBEN) +#endif /* CCB */ + +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC3EN) +#endif /* ADC3 */ + +#if defined(ADF1) +#define __HAL_RCC_ADF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADF1EN) +#endif /* ADF1 */ + +#if defined(GPIOK) +#define __HAL_RCC_GPIOK_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOKEN) +#endif /* GPIOK */ + +#if defined(SRAM4_BASE) +#define __HAL_RCC_SRAM4_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM4EN) +#endif /* SRAM4_BASE */ + +#if defined(SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM5EN) +#endif /* SRAM5_BASE */ + +#define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) + +#if defined(SRAM3_BASE) +#define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) +#endif /* SRAM3_BASE */ +/** + * @} + */ + +/** @defgroup RCC_AHB4_Clock_Enable_Disable AHB4 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC1 */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC2 */ + +#if defined(SDMMC1) +#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SDMMC1 */ + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SDMMC2 */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* FMC_BASE */ + +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) +#endif /* OTFDEC1 */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN) +#endif /* OTFDEC2 */ + +#if defined(SDMMC1) +#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) +#endif /* SDMMC1 */ + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) +#endif /* SDMMC2 */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) +#endif /* FMC_BASE */ + +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN) +#endif /* OCTOSPIM */ +/** + * @} + */ + + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM4 */ + +#if defined(TIM5) +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(TIM12) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \ + UNUSED(tmpreg); \ + } while(0) + +#endif /* TIM12 */ + +#if defined(TIM13) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM13 */ + +#if defined(TIM14) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM14 */ + +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(OPAMP1) +#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OPAMP1 */ + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(COMP1) +#define __HAL_RCC_COMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* COMP1 */ + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(UART4) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I3C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USART6 */ + +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USART10 */ + +#if defined(USART11) +#define __HAL_RCC_USART11_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USART11 */ + +#if defined(CEC) +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* CEC */ + +#if defined(UART7) +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* UART7 */ + +#if defined(UART8) +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* UART8 */ + +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* UART9 */ + +#if defined(UART12) +#define __HAL_RCC_UART12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* UART12 */ + +#define __HAL_RCC_DTS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* UCPD1 */ + +#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) + +#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) + +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) +#endif /* TIM4 */ + +#if defined(TIM5) +#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) + +#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) + +#if defined(TIM12) +#define __HAL_RCC_TIM12_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) +#endif /* TIM12 */ + +#if defined(TIM13) +#define __HAL_RCC_TIM13_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) +#endif /* TIM13 */ + +#if defined(TIM14) +#define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) +#endif /* TIM14 */ + +#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) + +#if defined(OPAMP1) +#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) +#endif /* OPAMP1 */ + +#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) + +#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) + +#if defined(COMP1) +#define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) +#endif /* COMP1 */ + +#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) + +#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) + +#if defined(UART4) +#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) + +#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) + +#define __HAL_RCC_I3C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) + +#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) + +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) +#endif /* USART6 */ + +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) +#endif /* USART10 */ + +#if defined(USART11) +#define __HAL_RCC_USART11_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) +#endif /* USART11 */ + +#if defined(CEC) +#define __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) +#endif /* CEC */ + +#if defined(UART7) +#define __HAL_RCC_UART7_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) +#endif /* UART7 */ + +#if defined(UART8) +#define __HAL_RCC_UART8_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) +#endif /* UART8 */ + + +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) +#endif /* UART9 */ + +#if defined(UART12) +#define __HAL_RCC_UART12_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) +#endif /* UART12 */ + +#define __HAL_RCC_DTS_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR , RCC_APB1HENR_DTSEN) + +#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) + +#define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) +#endif /* UCPD1 */ + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(TIM8) +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM8 */ + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM15 */ + +#if defined(TIM16) +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM16 */ + +#if defined(TIM17) +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM17 */ + +#if defined(SPI4) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SPI4 */ + +#if defined(SPI6) +#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SPI6 */ + +#if defined(SAI1) +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SAI1 */ + +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /*USB_DRD_FS*/ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /*LTDC*/ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /*GFXTIM*/ + +#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) + +#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) + +#if defined(TIM8) +#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) +#endif /* TIM8 */ + +#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) + +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) +#endif /* TIM15 */ + +#if defined(TIM16) +#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) +#endif /* TIM16 */ + +#if defined(TIM17) +#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) +#endif /* TIM17 */ + +#if defined(SPI4) +#define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) +#endif /* SPI4 */ + +#if defined(SPI6) +#define __HAL_RCC_SPI6_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) +#endif /* SPI6 */ + +#if defined(SAI1) +#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) +#endif /* SAI1 */ + +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) +#endif /* USB_DRD_FS */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) +#endif /* LTDC */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) +#endif /* GFXTIM */ +/** + * @} + */ + +/** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable + * @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SBS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(SPI5) +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SPI5 */ + +#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(I2C3) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C3 */ + +#if defined(I2C4) +#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C4 */ + +#if defined(I3C2) +#define __HAL_RCC_I3C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I3C2 */ + +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(LPTIM3) +#define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* LPTIM3 */ + +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* LPTIM5 */ + +#if defined(LPTIM6) +#define __HAL_RCC_LPTIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* LPTIM6 */ + +#if defined(VREFBUF) +#define __HAL_RCC_VREF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* VREFBUF */ + +#define __HAL_RCC_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined (PLAY1) +#define __HAL_RCC_PLAY1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_PLAY1APB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* PLAY1 */ + +#define __HAL_RCC_SBS_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) + +#if defined(SPI5) +#define __HAL_RCC_SPI5_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) +#endif /* SPI5 */ + +#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) + +#if defined(I2C3) +#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) +#endif /* I2C3 */ + +#if defined(I2C4) +#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) +#endif /* I2C4 */ + +#if defined(I3C2) +#define __HAL_RCC_I3C2_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) +#endif /* I3C2 */ + +#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) + +#if defined(LPTIM3) +#define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) +#endif /* LPTIM3 */ + +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) +#endif /* LPTIM5 */ + +#if defined(LPTIM6) +#define __HAL_RCC_LPTIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) +#endif /* LPTIM6 */ + +#if defined(VREFBUF) +#define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) +#endif /* VREFBUF */ + +#define __HAL_RCC_RTC_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) + +#if defined (PLAY1) +#define __HAL_RCC_PLAY1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN) +#define __HAL_RCC_PLAY1APB_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN) +#endif /* PLAY1 */ +/** + * @} + */ + +/** @defgroup RCC_AHB_APB_Branch_Clock_Disable AHB APB Branch Clock Disable Clear Disable + * @brief Disable or clear Disable the AHBx/APBx branch clock for all AHBx/APBx peripherals. + * @note It is recommended to disable the clock of all peripherals (by writing 0 in + * the AHBxENR/APBxENR register) before Disabling the corresponding Bus Branch clock. + * Some peripheral bus clocks are not affected by branch clock disabling as IWDG (APB1), + * SRAM2/SRAM3 (AHB2) and FLITF/BKRAM/ICACHE/DCACHE/SRAM1 (AHB1). + * @{ + */ + +#define __HAL_RCC_AHB1_CLK_DISABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ + /* Delay after AHB peripherals bus clocks branch disable */ \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_AHB2_CLK_DISABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS); \ + /* Delay after AHB peripherals bus clocks branch disable */ \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(AHB4PERIPH_BASE) +#define __HAL_RCC_AHB4_CLK_DISABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS); \ + /* Delay after AHB peripherals bus clocks branch disable */ \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* AHB4PERIPH_BASE */ + +#define __HAL_RCC_APB1_CLK_DISABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ + /* Delay after APB peripherals bus clocks branch disable */ \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_APB2_CLK_DISABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ + /* Delay after APB peripherals bus clocks branch disable */ \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_APB3_CLK_DISABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS); \ + /* Delay after APB peripherals bus clocks branch disable */ \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS); \ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_AHB1_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS) + +#define __HAL_RCC_AHB2_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS) + +#if defined(AHB4PERIPH_BASE) +#define __HAL_RCC_AHB4_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS) +#endif /* AHB4PERIPH_BASE */ + +#define __HAL_RCC_APB1_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS) + +#define __HAL_RCC_APB2_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS) + +#define __HAL_RCC_APB3_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) + +#define __HAL_RCC_GPDMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) != 0U) + +#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) != 0U) + +#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) + +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) +#endif /* CORDIC */ + +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) +#endif /* FMAC */ + +#if defined(MDF1) +#define __HAL_RCC_MDF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) != 0U) +#endif /* MDF1 */ + +#define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) + +#if defined(ETH) +#define __HAL_RCC_ETH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) != 0U) + +#define __HAL_RCC_ETHTX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) != 0U) + +#define __HAL_RCC_ETHRX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) != 0U) + +#if defined(RCC_AHB1ENR_ETHCKEN) +#define __HAL_RCC_ETHINTERN_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHCKEN) != 0U) +#endif /* RCC_AHB1ENR_ETHCKEN */ +#endif /*ETH*/ + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) +#endif /* DMA2D */ + +#if defined(JPEG) +#define __HAL_RCC_JPEG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) != 0U) +#endif /* JPEG */ + +#define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) != 0U) + +#define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) != 0U) + +#if defined(DCACHE1) +#define __HAL_RCC_DCACHE1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) != 0U) +#endif /* DCACHE1 */ + +#define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) + + +#define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) + +#define __HAL_RCC_GPDMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) == 0U) + +#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) == 0U) + +#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) + +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) +#endif /* CORDIC */ + +#if defined(MDF1) +#define __HAL_RCC_MDF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) == 0U) +#endif /* MDF1 */ + +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) +#endif /* FMAC */ + +#define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) + +#if defined(ETH) +#define __HAL_RCC_ETH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) == 0U) + +#define __HAL_RCC_ETHTX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) == 0U) + +#define __HAL_RCC_ETHRX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) == 0U) + +#if defined(RCC_AHB1ENR_ETHCKEN) +#define __HAL_RCC_ETHINTERN_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHCKEN) == 0U) +#endif /* RCC_AHB1ENR_ETHCKEN */ +#endif /*ETH*/ + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) +#endif /* DMA2D */ + +#if defined(JPEG) +#define __HAL_RCC_JPEG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) == 0U) +#endif /* JPEG */ + +#define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) == 0U) + +#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) == 0U) + +#if defined(DCACHE1) +#define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0U) +#endif /* DCACHE1 */ + +#define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U) +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) + +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) + +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) + +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) + +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) +#endif /* GPIOE */ + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) +#endif /* GPIOF */ + +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) +#endif /* GPIOG */ + +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOJEN) != 0U) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) + +#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U) + +#if defined(DCMI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) != 0U) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility */ +#endif /* DCMI */ + +#if defined(RCC_AHB2ENR_OTGPHYEN) +#define __HAL_RCC_OTGPHY_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGPHYEN) != 0U) +#endif /* RCC_AHB2ENR_OTGPHYEN */ + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGHSEN) != 0U) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != 0U) +#endif /* USB_OTG_FS */ + +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) +#endif /* HASH */ + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) + +#define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) + +#if defined(SAES) +#define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) != 0U) +#endif /*SAES*/ + +#if defined(CCB) +#define __HAL_RCC_CCB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CCBEN) != 0U) +#endif /*CCB*/ + +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC3EN) != 0U) +#endif /*ADC3*/ + +#if defined(ADF1) +#define __HAL_RCC_ADF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADF1EN) != 0U) +#endif /*ADF1*/ + +#if defined(GPIOK) +#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOKEN) != 0U) +#endif /*GPIOK*/ + +#if defined(SRAM4_BASE) +#define __HAL_RCC_SRAM4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM4EN) != 0U) +#endif /*SRAM4_BASE*/ + +#if defined(SRAM5_BASE) +#define __HAL_RCC_SRAM5_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM5EN) != 0U) +#endif /*SRAM5_BASE*/ + +#define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U) + +#if defined(SRAM3_BASE) +#define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) != 0U) +#endif /* SRAM3_BASE */ + +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) + +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) + +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) + +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) +#endif /* GPIOE */ + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) +#endif /* GPIOF */ + +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) +#endif /* GPIOG */ + +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOJEN) == 0U) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U) + +#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U) + +#if defined(DCMI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) == 0U) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility */ +#endif /* DCMI */ + +#if defined(RCC_AHB2ENR_OTGPHYEN) +#define __HAL_RCC_OTGPHY_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGPHYEN) == 0U) +#endif /* RCC_AHB2ENR_OTGPHYEN */ + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGHSEN) == 0U) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == 0U) +#endif /* USB_OTG_FS */ + +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U) +#endif /* HASH */ + +#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) + +#define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) == 0U) + +#if defined(SAES) +#define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) == 0U) +#endif /* SAES */ + +#if defined(CCB) +#define __HAL_RCC_CCB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CCBEN) == 0U) +#endif /* CCB */ + +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC3EN) == 0U) +#endif /* ADC3 */ + +#if defined(ADF1) +#define __HAL_RCC_ADF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADF1EN) == 0U) +#endif /* ADF1 */ + +#if defined(GPIOK) +#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOKEN) == 0U) +#endif /* GPIOK */ + +#if defined(SRAM4_BASE) +#define __HAL_RCC_SRAM4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM4EN) == 0U) +#endif /* SRAM4_BASE */ + +#if defined(SRAM5_BASE) +#define __HAL_RCC_SRAM5_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM5EN) == 0U) +#endif /* SRAM5_BASE */ + +#define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) == 0U) + +#if defined(SRAM3_BASE) +#define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) == 0U) +#endif /* SRAM3_BASE */ +/** + * @} + */ + +/** @defgroup RCC_AHB4_Peripheral_Clock_Enable_Disable_Status AHB4 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB4 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) != 0U) +#endif /* OTFDEC1 */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN) != 0U) +#endif /* OTFDEC2 */ + +#if defined(SDMMC1) +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) != 0U) +#endif /* SDMMC1 */ + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) != 0U) +#endif /* SDMMC2 */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) != 0U) +#endif /* FMC_BASE */ + +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) != 0U) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN) != 0U) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN) != 0U) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) == 0U) +#endif /* OTFDEC1 */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN) == 0U) +#endif /* OTFDEC2 */ + +#if defined(SDMMC1) +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) == 0U) +#endif /* SDMMC1 */ + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) == 0U) +#endif /* SDMMC2 */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) == 0U) +#endif /* FMC_BASE */ + +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) == 0U) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN) == 0U) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN) == 0U) +#endif /* OCTOSPIM */ + +/** + * @} + */ + + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) != 0U) + +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) != 0U) + +#if defined(TIM4) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) != 0U) +#endif /* TIM4 */ + +#if defined(TIM5) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) != 0U) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) != 0U) + +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) != 0U) + +#if defined(TIM12) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) != 0U) +#endif /* TIM12 */ + +#if defined(TIM13) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) != 0U) +#endif /* TIM13 */ + +#if defined(TIM14) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) != 0U) +#endif /* TIM14 */ + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) != 0U) + +#if defined(OPAMP1) +#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) != 0U) +#endif /* OPAMP1 */ + +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) != 0U) + +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) != 0U) + +#if defined(COMP1) +#define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) != 0U) +#endif /* COMP1 */ + +#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) != 0U) + +#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) != 0U) + +#if defined(UART4) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) != 0U) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) != 0U) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) != 0U) + +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) != 0U) + +#define __HAL_RCC_I3C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) != 0U) + +#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) != 0U) + +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) != 0U) +#endif /* USART6 */ + +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) != 0U) +#endif /* USART10 */ + +#if defined(USART11) +#define __HAL_RCC_USART11_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) != 0U) +#endif /* USART11 */ + +#if defined(CEC) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) != 0U) +#endif /* CEC */ + +#if defined(UART7) +#define __HAL_RCC_UART7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) != 0U) +#endif /* UART7 */ + +#if defined(UART8) +#define __HAL_RCC_UART8_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) != 0U) +#endif /* UART8 */ + + +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) != 0U) +#endif /* UART9 */ + +#if defined(UART12) +#define __HAL_RCC_UART12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) != 0U) +#endif /* UART12 */ + +#define __HAL_RCC_DTS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN) != 0U) + +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) != 0U) + +#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN) != 0U) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) != 0U) +#endif /* UCPD1 */ + + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) == 0U) + +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) == 0U) + +#if defined(TIM4) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) == 0U) +#endif /* TIM4 */ + +#if defined(TIM5) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) == 0U) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) == 0U) + +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) == 0U) + +#if defined(TIM12) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) == 0U) +#endif /* TIM12 */ + +#if defined(TIM13) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) == 0U) +#endif /* TIM13 */ + +#if defined(TIM14) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) == 0U) +#endif /* TIM14 */ + +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) == 0U) + +#if defined(OPAMP1) +#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) == 0U) +#endif /* OPAMP1 */ + +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) == 0U) + +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) == 0U) + +#if defined(COMP1) +#define __HAL_RCC_COMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) == 0U) +#endif /* COMP1 */ + +#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) == 0U) + +#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) == 0U) + +#if defined(UART4) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) == 0U) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) == 0U) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) == 0U) + +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) == 0U) + +#define __HAL_RCC_I3C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) == 0U) + +#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) == 0U) + +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) == 0U) +#endif /* USART6 */ + +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) == 0U) +#endif /* USART10 */ + +#if defined(USART11) +#define __HAL_RCC_USART11_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) == 0U) +#endif /* USART11 */ + +#if defined(CEC) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) == 0U) +#endif /* CEC */ + +#if defined(UART7) +#define __HAL_RCC_UART7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) == 0U) +#endif /* UART7 */ + +#if defined(UART8) +#define __HAL_RCC_UART8_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) == 0U) +#endif /* UART8 */ + + +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) == 0U) +#endif /* UART9 */ + +#if defined(UART12) +#define __HAL_RCC_UART12_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) == 0U) +#endif /* UART12 */ + +#define __HAL_RCC_DTS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN) == 0U) + +#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) == 0U) + +#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN) == 0U) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) == 0U) +#endif /* UCPD1 */ +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) + +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) + +#if defined(TIM8) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) +#endif /* TIM8 */ + +#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) + +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) +#endif /* TIM15 */ + +#if defined(TIM16) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) +#endif /* TIM16 */ + +#if defined(TIM17) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) +#endif /* TIM17 */ + +#if defined(SPI4) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U) +#endif /* SPI4 */ + +#if defined(SPI6) +#define __HAL_RCC_SPI6_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) != 0U) +#endif /* SPI6 */ + +#if defined(SAI1) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) +#endif /* SAI1 */ + +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) +#endif /* USB_DRD_FS */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) +#endif /* LTDC */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) != 0U) +#endif /* GFXTIM */ + +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) + +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) + +#if defined(TIM8) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) +#endif /* TIM8 */ + +#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) + +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) +#endif /* TIM15 */ + +#if defined(TIM16) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) +#endif /* TIM16 */ + +#if defined(TIM17) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) +#endif /* TIM17 */ + +#if defined(SPI4) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U) +#endif /* SPI4 */ + +#if defined(SPI6) +#define __HAL_RCC_SPI6_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) == 0U) +#endif /* SPI6 */ + +#if defined(SAI1) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) +#endif /* SAI1 */ + +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U) +#endif /* USB_DRD_FS */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) +#endif /* LTDC */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) == 0U) +#endif /* GFXTIM */ +/** + * @} + */ + +/** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB3 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SBS_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) != 0U) + +#if defined(SPI5) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) != 0U) +#endif /* SPI5 */ + +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) != 0U) + +#if defined(I2C3) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) != 0U) +#endif /* I2C3 */ + +#if defined(I2C4) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) != 0U) +#endif /* I2C4 */ + +#if defined(I3C2) +#define __HAL_RCC_I3C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) != 0U) +#endif /* I3C2 */ + +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) != 0U) + +#if defined(LPTIM3) +#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) != 0U) +#endif /* LPTIM3 */ + +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) != 0U) +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) != 0U) +#endif /* LPTIM5 */ + +#if defined(LPTIM6) +#define __HAL_RCC_LPTIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) != 0U) +#endif /* LPTIM6 */ + +#if defined(VREFBUF) +#define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) != 0U) +#endif /* VREFBUF */ + +#define __HAL_RCC_RTC_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U) + +#if defined(PLAY1) +#define __HAL_RCC_PLAY1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN) != 0U) +#define __HAL_RCC_PLAY1APB_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN) != 0U) +#endif /* PLAY1 */ + +#define __HAL_RCC_SBS_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) == 0U) + +#if defined(SPI5) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) == 0U) +#endif /* SPI5 */ + +#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) == 0U) + +#if defined(I2C3) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) == 0U) +#endif /* I2C3 */ + +#if defined(I2C4) +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) == 0U) +#endif /* I2C4 */ + +#if defined(I3C2) +#define __HAL_RCC_I3C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) == 0U) +#endif /* I3C2 */ + +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) == 0U) + +#if defined(LPTIM3) +#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) == 0U) +#endif /* LPTIM3 */ + +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) == 0U) +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) == 0U) +#endif /* LPTIM5 */ + +#if defined(LPTIM6) +#define __HAL_RCC_LPTIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) == 0U) +#endif /* LPTIM6 */ + +#if defined(VREFBUF) +#define __HAL_RCC_VREF_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) == 0U) +#endif /* VREFBUF */ + +#define __HAL_RCC_RTC_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U) + +#if defined(PLAY1) +#define __HAL_RCC_PLAY1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN) == 0U) +#define __HAL_RCC_PLAY1APB_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN) == 0U) +#endif /* PLAY1 */ + +/** + * @} + */ + +/** @defgroup RCC_AHB_APB_Branch_Clock_Disable_Status AHB APB Branch Clock Disabled Status + * @brief Check whether the AHBx/APBx branch clock for all AHBx/APBx peripherals is disabled or not. + * @note It is recommended to disable the clock of all peripherals (by writing 0 in + * the AHBxENR/APBxENR register) before Disabling the corresponding Bus Branch clock. + * Some peripheral bus clocks are not affected by branch clock disabling as IWDG (APB1), + * SRAM2/SRAM3 (AHB2) and FLITF/BKRAM/ICACHE/DCACHE/SRAM1 (AHB1). + * @{ + */ + +#define __HAL_RCC_AHB1_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS) != 0U) + +#define __HAL_RCC_AHB2_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS) != 0U) + +#if defined(AHB4PERIPH_BASE) +#define __HAL_RCC_AHB4_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS) != 0U) +#endif /* AHB4PERIPH_BASE */ + +#define __HAL_RCC_APB1_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS) != 0U) + +#define __HAL_RCC_APB2_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS) != 0U) + +#define __HAL_RCC_APB3_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ + +#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x010AD003U) + +#define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) + +#define __HAL_RCC_GPDMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA2RST) + +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) +#endif /* CORDIC */ + +#if defined(FMAC) +#define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) +#endif /* FMAC */ + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) +#endif /* DMA2D */ + +#if defined(JPEG) +#define __HAL_RCC_JPEG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) +#endif /* JPEG */ + +#if defined(MDF1) +#define __HAL_RCC_MDF1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) +#endif /* MDF1 */ + +#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) + +#define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) + +#if defined(ETH) +#define __HAL_RCC_ETH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETHRST) +#endif /* ETH */ + +#define __HAL_RCC_GTZC1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TZSC1RST) + + +#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) + +#define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) + +#define __HAL_RCC_GPDMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA2RST) + +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) +#endif /* CORDIC */ + +#if defined(FMAC) +#define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) +#endif /* FMAC */ + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) +#endif /* DMA2D */ + +#if defined(JPEG) +#define __HAL_RCC_JPEG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) +#endif /* JPEG */ + +#if defined(MDF1) +#define __HAL_RCC_MDF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) +#endif /* MDF1 */ + +#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) + +#define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) + +#if defined(ETH) +#define __HAL_RCC_ETH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETHRST) +#endif /* ETH */ + +#define __HAL_RCC_GTZC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TZSC1RST) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ + +#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x001F1DFFU) + +#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) + +#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) + +#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) + +#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) + +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) +#endif /* GPIOE */ + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) +#endif /* GPIOF */ + +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) +#endif /* GPIOG */ + +#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) +#endif /* GPIOI */ + +#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) + +#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) + +#if defined(DCMI) +#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMI_PSSIRST) +#define __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility */ +#endif /* DCMI */ + +#if defined(AES) +#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) +#endif /* HASH */ + +#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) + +#if defined(PKA) +#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) +#endif /* PKA */ + +#if defined(SAES) +#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) +#endif /* SAES*/ + +#if defined(CCB) +#define __HAL_RCC_CCB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_CCBRST) +#endif /* CCB */ + +#if defined(ADC3) +#define __HAL_RCC_ADC3_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC3RST) +#endif /* ADC3 */ + +#if defined(ADF1) +#define __HAL_RCC_ADF1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADF1RST) +#endif /* ADF1 */ + +#if defined(GPIOK) +#define __HAL_RCC_GPIOK_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOKRST) +#endif /* GPIOK */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOJRST) +#endif /* GPIOJ */ + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGHSRST) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) +#endif /* USB_OTG_FS */ + +#if defined(RCC_AHB2RSTR_OTGHSPHYRST) +#define __HAL_RCC_OTGPHY_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGHSPHYRST) +#endif /* RCC_AHB2RSTR_OTGHSPHYRST */ + +#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) + +#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) + +#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) + +#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) + +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) +#endif /* GPIOE */ + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) +#endif /* GPIOF */ + +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) +#endif /* GPIOG */ + +#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) + +#if defined(GPIOG) +#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) +#endif /* GPIOI */ + +#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) + +#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) + +#if defined(DCMI) +#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMI_PSSIRST) +#define __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility */ +#endif /* DCMI */ + +#if defined(AES) +#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) +#endif /* HASH */ + +#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) + +#if defined(PKA) +#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) +#endif /* PKA */ + +#if defined(SAES) +#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) +#endif /* SAES*/ + +#if defined(CCB) +#define __HAL_RCC_CCB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_CCBRST) +#endif /* CCB */ + +#if defined(ADC3) +#define __HAL_RCC_ADC3_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC3RST) +#endif /* ADC3 */ + +#if defined(ADF1) +#define __HAL_RCC_ADF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADF1RST) +#endif /* ADF1 */ + +#if defined(GPIOK) +#define __HAL_RCC_GPIOK_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOKRST) +#endif /* GPIOK */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOJRST) +#endif /* GPIOJ */ + +#if defined(RCC_AHB2RSTR_OTGHSPHYRST) +#define __HAL_RCC_OTGPHY_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGHSPHYRST) +#endif /* RCC_AHB2RSTR_OTGHSPHYRST */ + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGHSRST) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) +#endif /* USB_OTG_FS */ + +/** + * @} + */ + +/** @defgroup RCC_AHB4_Force_Release_Reset AHB4 Peripheral Force Release Reset + * @brief Force or release AHB4 peripheral reset. + * @{ + */ + +#if defined(FMC_BASE) +#define __HAL_RCC_AHB4_FORCE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00111880U) +#endif /* FMC_BASE */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC1RST) +#endif /* OTFDEC1 */ + +#if defined(SDMMC1) +#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC1RST) +#endif /* SDMMC1 */ + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC2RST) +#endif /* SDMMC2 */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_FMCRST) +#endif /* FMC_BASE */ + +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI2RST) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPIMRST) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC2RST) +#endif /* OTFDEC2 */ + +#if defined(FMC_BASE) +#define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00000000U) +#endif /* FMC_BASE */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC1RST) +#endif /* OTFDEC1 */ + +#if defined(SDMMC1) +#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC1RST) +#endif /* SDMMC1 */ + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC2RST) +#endif /* SDMMC2 */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_FMCRST) +#endif /* FMC_BASE */ + +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI2RST) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPIMRST) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC2RST) +#endif /* OTFDEC2 */ + +/** + * @} + */ + + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ + +#define __HAL_RCC_APB1_FORCE_RESET() do { \ + WRITE_REG(RCC->APB1LRSTR, 0xDFFEC1FFU); \ + WRITE_REG(RCC->APB1HRSTR, 0x4080062BU); \ + } while(0) + +#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM2RST) + +#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM3RST) + +#if defined(TIM4) +#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM4RST) +#endif /* TIM4 */ + +#if defined(TIM5) +#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM5RST) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM6RST) + +#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM7RST) + +#if defined(TIM12) +#define __HAL_RCC_TIM12_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM12RST) +#endif /* TIM12 */ + +#if defined(TIM13) +#define __HAL_RCC_TIM13_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM13RST) +#endif /* TIM13 */ + +#if defined(TIM14) +#define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM14RST) +#endif /* TIM14 */ + +#if defined(OPAMP1) +#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST) +#endif /* OPAMP1 */ + +#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST) + +#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI3RST) + +#if defined(COMP1) +#define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_COMPRST) +#endif /* COMP1 */ + +#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART2RST) + +#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART3RST) + +#if defined(UART4) +#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART4RST) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART5RST) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C1RST) + +#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C2RST) + +#define __HAL_RCC_I3C1_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I3C1RST) + +#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CRSRST) + +#if defined(USART6) +#define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART6RST) +#endif /* USART6 */ + +#if defined(USART10) +#define __HAL_RCC_USART10_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART10RST) +#endif /* USART10 */ + +#if defined(USART11) +#define __HAL_RCC_USART11_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART11RST) +#endif /* USART11 */ + +#if defined(CEC) +#define __HAL_RCC_CEC_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CECRST) +#endif /* CEC */ + +#if defined(UART7) +#define __HAL_RCC_UART7_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART7RST) +#endif /* UART7 */ + +#if defined(UART8) +#define __HAL_RCC_UART8_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART8RST) +#endif /* UART8 */ + + +#if defined(UART9) +#define __HAL_RCC_UART9_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART9RST) +#endif /* UART9 */ + +#if defined(UART12) +#define __HAL_RCC_UART12_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART12RST) +#endif /* UART12 */ + +#define __HAL_RCC_DTS_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_DTSRST) + +#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_LPTIM2RST) + +#define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_FDCANRST) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UCPD1RST) +#endif /* UCPD1 */ + + +#define __HAL_RCC_APB1_RELEASE_RESET() do { \ + WRITE_REG(RCC->APB1LRSTR, 0x00000000U); \ + WRITE_REG(RCC->APB1HRSTR, 0x00000000U); \ + } while(0) + +#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM2RST) + +#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM3RST) + +#if defined(TIM4) +#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM4RST) +#endif /* TIM4 */ + +#if defined(TIM5) +#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM5RST) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM6RST) + +#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM7RST) + +#if defined(TIM12) +#define __HAL_RCC_TIM12_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM12RST) +#endif /* TIM12 */ + +#if defined(TIM13) +#define __HAL_RCC_TIM13_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM13RST) +#endif /* TIM13 */ + +#if defined(TIM14) +#define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM14RST) +#endif /* TIM14 */ + +#if defined(OPAMP1) +#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST) +#endif /* OPAMP1 */ + +#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST) + +#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI3RST) + +#if defined(COMP1) +#define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_COMPRST) +#endif /* COMP1 */ + +#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART2RST) + +#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART3RST) + +#if defined(UART4) +#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART4RST) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART5RST) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C1RST) + +#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C2RST) + +#define __HAL_RCC_I3C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I3C1RST) + +#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CRSRST) + +#if defined(USART6) +#define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART6RST) +#endif /* USART6 */ + +#if defined(USART10) +#define __HAL_RCC_USART10_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART10RST) +#endif /* USART10 */ + +#if defined(USART11) +#define __HAL_RCC_USART11_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART11RST) +#endif /* USART11 */ + +#if defined(CEC) +#define __HAL_RCC_CEC_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CECRST) +#endif /* CEC */ + +#if defined(UART7) +#define __HAL_RCC_UART7_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART7RST) +#endif /* UART7 */ + +#if defined(UART8) +#define __HAL_RCC_UART8_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART8RST) +#endif /* UART8 */ + + +#if defined(UART9) +#define __HAL_RCC_UART9_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART9RST) +#endif /* UART9 */ + +#if defined(UART12) +#define __HAL_RCC_UART12_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART12RST) +#endif /* UART12 */ + +#define __HAL_RCC_DTS_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_DTSRST) + +#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_LPTIM2RST) + +#define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_FDCANRST) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UCPD1RST) +#endif /* UCPD1 */ + +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ + +#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0x017F7800U) + +#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) + +#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) + +#if defined(TIM8) +#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) +#endif /* TIM8 */ + +#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) + +#if defined(TIM15) +#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) +#endif /* TIM15 */ + +#if defined(TIM16) +#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) +#endif /* TIM16 */ + +#if defined(TIM17) +#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) +#endif /* TIM17 */ + +#if defined(SPI4) +#define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) +#endif /* SPI4 */ + +#if defined(SPI6) +#define __HAL_RCC_SPI6_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI6RST) +#endif /* SPI6 */ + +#if defined(SAI1) +#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) +#endif /* SAI1 */ + +#if defined(SAI2) +#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) +#endif /* GFXTIM */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#endif /* USB_DRD_FS */ + +#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) + +#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) + +#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) + +#if defined(TIM8) +#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) +#endif /* TIM8 */ + +#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) + +#if defined(TIM15) +#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) +#endif /* TIM15 */ + +#if defined(TIM16) +#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) +#endif /* TIM16 */ + +#if defined(TIM17) +#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) +#endif /* TIM17 */ + +#if defined(SPI4) +#define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) +#endif /* SPI4 */ + +#if defined(SPI6) +#define __HAL_RCC_SPI6_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI6RST) +#endif /* SPI6 */ + +#if defined(SAI1) +#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) +#endif /* SAI1 */ + +#if defined(SAI2) +#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) +#endif /* GFXTIM */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#endif /* USB_DRD_FS */ + +/** + * @} + */ + +/** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset + * @brief Force or release APB3 peripheral reset. + * @{ + */ + +#define __HAL_RCC_APB3_FORCE_RESET() WRITE_REG(RCC->APB3RSTR, 0x001008E0U) + +#if defined(SPI5) +#define __HAL_RCC_SPI5_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI5RST) +#endif /* SPI5 */ + +#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) + +#if defined(I2C3) +#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) +#endif /* I2C3 */ + +#if defined(I2C4) +#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C4RST) +#endif /* I2C4 */ + +#if defined(I3C2) +#define __HAL_RCC_I3C2_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I3C2RST) +#endif /* I3C2 */ + +#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) + +#if defined(LPTIM3) +#define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) +#endif /* LPTIM3 */ + +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM5RST) +#endif /* LPTIM5 */ + +#if defined(LPTIM6) +#define __HAL_RCC_LPTIM6_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM6RST) +#endif /* LPTIM6 */ + +#if defined(VREFBUF) +#define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) +#endif /* VREFBUF */ + +#if defined(PLAY1) +#define __HAL_RCC_PLAY1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1RST) +#define __HAL_RCC_PLAY1POR_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1POR) +#endif /* PLAY1 */ + +#define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U) + +#if defined(SPI5) +#define __HAL_RCC_SPI5_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI5RST) +#endif /* SPI5 */ + +#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) + +#if defined(I2C3) +#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) +#endif /* I2C3 */ + +#if defined(I2C4) +#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C4RST) +#endif /* I2C4 */ + +#if defined(I3C2) +#define __HAL_RCC_I3C2_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I3C2RST) +#endif /* I3C2 */ + +#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) + +#if defined(LPTIM3) +#define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) +#endif /* LPTIM3 */ + +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM5RST) +#endif /* LPTIM5 */ + +#if defined(LPTIM6) +#define __HAL_RCC_LPTIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM6RST) +#endif /* LPTIM6 */ + +#if defined(VREFBUF) +#define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) +#endif /* VREFBUF */ + +#if defined(PLAY1) +#define __HAL_RCC_PLAY1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1RST) +#define __HAL_RCC_PLAY1POR_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1POR) +#endif /* PLAY1 */ +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) + +#define __HAL_RCC_GPDMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA2LPEN) + +#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FLITFLPEN) + +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CRCLPEN) + +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CORDICLPEN) +#endif /* CORDIC */ + +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FMACLPEN) +#endif /* FMAC */ + +#if defined(MDF1) +#define __HAL_RCC_MDF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_MDF1LPEN) +#endif /* MDF1 */ + +#define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_RAMCFGLPEN) + +#if defined(ETH) +#define __HAL_RCC_ETH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHLPEN) + +#define __HAL_RCC_ETHTX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) + +#define __HAL_RCC_ETHRX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) + +#if defined(RCC_AHB1LPENR_ETHCKLPEN) +#define __HAL_RCC_ETHINTERN_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHCKLPEN) +#endif /* RCC_AHB1LPENR_ETHCKLPEN */ +#endif /* ETH */ + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_DMA2DLPEN) +#endif /* DMA2D */ + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_JPEGLPEN) +#endif /* JPEG */ + +#define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) + +#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_BKPRAMLPEN) + +#define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ICACHELPEN) + +#if defined(DCACHE1) +#define __HAL_RCC_DCACHE1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_DCACHE1LPEN) +#endif /* DCACHE1 */ + +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_SRAM1LPEN) + + +#define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) + +#define __HAL_RCC_GPDMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA2LPEN) + +#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FLITFLPEN) + +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CRCLPEN) + +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CORDICLPEN) +#endif /* CORDIC */ + +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FMACLPEN) +#endif /* FMAC */ + +#if defined(MDF1) +#define __HAL_RCC_MDF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_MDF1LPEN) +#endif /* MDF1 */ + +#define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_RAMCFGLPEN) + +#if defined(ETH) +#define __HAL_RCC_ETH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHLPEN) + +#define __HAL_RCC_ETHTX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) + +#define __HAL_RCC_ETHRX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) + +#if defined(RCC_AHB1LPENR_ETHCKLPEN) +#define __HAL_RCC_ETHINTERN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHCKLPEN) +#endif /* RCC_AHB1LPENR_ETHCKLPEN */ +#endif /* ETH */ + +#if defined(DMA2D) +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_DMA2DLPEN) +#endif /* DMA2D */ + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_JPEGLPEN) +#endif /* JPEG */ + +#define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) + +#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_BKPRAMLPEN) + +#define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ICACHELPEN) + +#if defined(DCACHE1) +#define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_DCACHE1LPEN) +#endif /* DCACHE1 */ + +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_SRAM1LPEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOALPEN) + +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOBLPEN) + +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOCLPEN) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIODLPEN) + +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOELPEN) +#endif /* GPIOE */ + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOFLPEN) +#endif /* GPIOF */ + +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOGLPEN) +#endif /* GPIOG */ + +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOHLPEN) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOILPEN) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOJLPEN) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADCLPEN) + +#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DAC1LPEN) + +#if defined(DCMI) +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DCMI_PSSILPEN) +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility */ +#endif /* DCMI */ + +#if defined(RCC_AHB2LPENR_OTGPHYLPEN) +#define __HAL_RCC_OTGPHY_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_OTGPHYLPEN); +#endif /* RCC_AHB2LPENR_OTGPHYLPEN */ + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_OTGHSLPEN); +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_OTGFSLPEN); +#endif /* USB_OTG_FS */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_HASHLPEN) +#endif /* HASH */ + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN) + +#if defined(PKA) +#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PKALPEN) +#endif /*PKA*/ + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SAESLPEN) +#endif /* AES */ + +#if defined(CCB) +#define __HAL_RCC_CCB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_CCBLPEN); +#endif /* CCB */ + +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADC3LPEN); +#endif /* ADC3 */ + +#if defined(ADF1) +#define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADF1LPEN); +#endif /* ADF1 */ + +#if defined(GPIOK) +#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOKLPEN); +#endif /* GPIOK */ + +#if defined(SRAM4_BASE) +#define __HAL_RCC_SRAM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM4LPEN); +#endif /* SRAM4_BASE */ + +#if defined(SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM5LPEN); +#endif /* SRAM5_BASE */ + +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) + +#if defined(SRAM3_BASE) +#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM3LPEN) +#endif /* SRAM3_BASE */ + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOALPEN) + +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOBLPEN) + +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOCLPEN) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIODLPEN) + +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOELPEN) +#endif /* GPIOE */ + +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOFLPEN) +#endif /* GPIOF */ + +#if defined(GPIOG) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOGLPEN) +#endif /* GPIOG */ + +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOHLPEN) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOILPEN) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOJLPEN) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADCLPEN) + +#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DAC1LPEN) + +#if defined(DCMI) +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DCMI_PSSILPEN) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility */ +#endif /* DCMI */ + +#if defined(RCC_AHB2LPENR_OTGPHYLPEN) +#define __HAL_RCC_OTGPHY_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_OTGPHYLPEN) +#endif /* RCC_AHB2LPENR_OTGPHYLPEN */ + +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_OTGHSLPEN) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_OTGFSLPEN) +#endif /* USB_OTG_FS */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); +#endif /* AES */ + +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_HASHLPEN) +#endif /* HASH */ + +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN) + +#if defined(PKA) +#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PKALPEN) +#endif /*PKA*/ + +#define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SAESLPEN) + +#if defined(CCB) +#define __HAL_RCC_CCB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_CCBLPEN) +#endif /* CCB */ + +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADC3LPEN) +#endif /* ADC3 */ + +#if defined(ADF1) +#define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADF1LPEN) +#endif /* ADF1 */ + +#if defined(GPIOK) +#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOKLPEN) +#endif /* GPIOK */ + +#if defined(SRAM4_BASE) +#define __HAL_RCC_SRAM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM4LPEN) +#endif /* SRAM4_BASE */ + +#if defined(SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM5LPEN) +#endif /* SRAM5_BASE */ + +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) + +#if defined(SRAM3_BASE) +#define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM3LPEN) +#endif /* SRAM3_BASE */ +/** + * @} + */ + +/** @defgroup RCC_AHB4_Clock_Sleep_Enable_Disable AHB4 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB4 peripheral clock during Low Power (Sleep) mode. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) +#endif /* OTFDEC1 */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC2LPEN) +#endif /* OTFDEC2 */ + +#if defined(SDMMC1) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) +#endif /* SDMMC1*/ + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC2LPEN) +#endif /* SDMMC2*/ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_FMCLPEN) +#endif /* FMC_BASE */ + +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI2LPEN) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPIMLPEN) +#endif /* OCTOSPIM */ + +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) +#endif /* OTFDEC1 */ + +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC2LPEN) +#endif /* OTFDEC2 */ + +#if defined(SDMMC1) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) +#endif /* SDMMC1*/ + +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC2LPEN) +#endif /* SDMMC2*/ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_FMCLPEN) +#endif /* FMC_BASE */ + +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI2LPEN) +#endif /* OCTOSPI2 */ + +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPIMLPEN) +#endif /* OCTOSPIM */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM2LPEN) + +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM3LPEN) + +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM4LPEN) +#endif /* TIM4 */ + +#if defined(TIM5) +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM5LPEN) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM6LPEN) + +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM7LPEN) + +#if defined(TIM12) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM12LPEN) +#endif /* TIM12 */ + +#if defined(TIM13) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM13LPEN) +#endif /* TIM13 */ + +#if defined(TIM14) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM14LPEN) +#endif /* TIM14 */ + +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_WWDGLPEN) + +#if defined(OPAMP1) +#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_OPAMPLPEN) +#endif /* OPAMP1 */ + +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI2LPEN) + +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI3LPEN) + +#if defined(COMP1) +#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_COMPLPEN) +#endif /* COMP1 */ + +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART2LPEN) + +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART3LPEN) + +#if defined(UART4) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART4LPEN) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART5LPEN) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C1LPEN) + +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C2LPEN) + +#define __HAL_RCC_I3C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I3C1LPEN) + +#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CRSLPEN) + +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART6LPEN) +#endif /* USART6 */ + +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART10LPEN) +#endif /* USART10 */ + +#if defined(USART11) +#define __HAL_RCC_USART11_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART11LPEN) +#endif /* USART11 */ + +#if defined(CEC) +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CECLPEN) +#endif /* CEC */ + +#if defined(UART7) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART7LPEN) +#endif /* UART7 */ + +#if defined(UART8) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART8LPEN) +#endif /* UART8 */ + + +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART9LPEN) +#endif /* UART9 */ + +#if defined(UART12) +#define __HAL_RCC_UART12_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART12LPEN) +#endif /* UART12 */ + +#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_DTSLPEN) + +#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_LPTIM2LPEN) + +#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_FDCANLPEN) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UCPD1LPEN) +#endif /* UCPD1 */ + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM2LPEN) + +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM3LPEN) + +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM4LPEN) +#endif /* TIM4 */ + +#if defined(TIM5) +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM5LPEN) +#endif /* TIM5 */ + +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM6LPEN) + +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM7LPEN) + +#if defined(TIM12) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM12LPEN) +#endif /* TIM12 */ + +#if defined(TIM13) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM13LPEN) +#endif /* TIM12 */ + +#if defined(TIM14) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM14LPEN) +#endif /* TIM14 */ + +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_WWDGLPEN) + +#if defined(OPAMP1) +#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_OPAMPLPEN) +#endif /* OPAMP1 */ + +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI2LPEN) + +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI3LPEN) + +#if defined(COMP1) +#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_COMPLPEN) +#endif /* COMP1 */ + +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART2LPEN) + +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART3LPEN) + +#if defined(UART4) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART4LPEN) +#endif /* UART4 */ + +#if defined(UART5) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART5LPEN) +#endif /* UART5 */ + +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C1LPEN) + +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C2LPEN) + +#define __HAL_RCC_I3C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I3C1LPEN) + +#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CRSLPEN) + +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART6LPEN) +#endif /* USART6 */ + +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART10LPEN) +#endif /* USART10 */ + +#if defined(USART11) +#define __HAL_RCC_USART11_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART11LPEN) +#endif /* USART11 */ + +#if defined(CEC) +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CECLPEN) +#endif /* CEC */ + +#if defined(UART7) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART7LPEN) +#endif /* UART7 */ + +#if defined(UART8) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART8LPEN) +#endif /* UART8 */ + + +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART9LPEN) +#endif /* UART9 */ + +#if defined(UART12) +#define __HAL_RCC_UART12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART12LPEN) +#endif /* UART12 */ + +#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_DTSLPEN) + +#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_LPTIM2LPEN) + +#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_FDCANLPEN) + +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UCPD1LPEN) +#endif /* UCPD1 */ + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) + +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) + +#if defined(TIM8) +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM8LPEN) +#endif /* TIM8 */ + +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) + +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) +#endif /* TIM15 */ + +#if defined(TIM16) +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) +#endif /* TIM16 */ + +#if defined(TIM17) +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) +#endif /* TIM17 */ + +#if defined(SPI4) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) +#endif /* SPI4 */ + +#if defined(SPI6) +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI6LPEN) +#endif /* SPI6 */ + +#if defined(SAI1) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) +#endif /* SAI1 */ + +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) +#endif /* SAI2 */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_LTDCLPEN) +#endif /* LTDC */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_GFXTIMLPEN) +#endif /* GFXTIM */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) +#endif /* USB_DRD_FS */ + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) + +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) + +#if defined(TIM8) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM8LPEN) +#endif /* TIM8 */ + +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) + +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) +#endif /* TIM15 */ + +#if defined(TIM16) +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) +#endif /* TIM16 */ + +#if defined(TIM17) +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) +#endif /* TIM17 */ + +#if defined(SPI4) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) +#endif /* SPI4 */ + +#if defined(SPI6) +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI6LPEN) +#endif /* SPI6 */ + +#if defined(SAI1) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) +#endif /* SAI1 */ + +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) +#endif /* SAI2 */ + + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_LTDCLPEN) +#endif /* LTDC */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_GFXTMLPEN) +#endif /* GFXTIM */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) +#endif /* USB_DRD_FS */ + +/** + * @} + */ + +/** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_SBS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SBSLPEN) + +#if defined(SPI5) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SPI5LPEN) +#endif /* SPI5 */ + +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPUART1LPEN) + +#if defined(I2C3) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C3LPEN) +#endif /* I2C3 */ + +#if defined(I2C4) +#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C4LPEN) +#endif /* I2C4 */ + +#if defined(I3C2) +#define __HAL_RCC_I3C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I3C2LPEN) +#endif /* I3C2 */ + +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM1LPEN) + +#if defined(LPTIM3) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM3LPEN) +#endif /* LPTIM3 */ + +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM4LPEN) +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM5LPEN) +#endif /* LPTIM5 */ + +#if defined(LPTIM6) +#define __HAL_RCC_LPTIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM6LPEN) +#endif /* LPTIM6 */ + +#if defined(VREFBUF) +#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_VREFLPEN) +#endif /* VREFBUF */ + +#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) + +#if defined(PLAY1) +#define __HAL_RCC_PLAY1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_PLAY1LPEN) +#endif /* PLAY1 */ + +#define __HAL_RCC_SBS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SBSLPEN) + +#if defined(SPI5) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SPI5LPEN) +#endif /* SPI5 */ + +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPUART1LPEN) + +#if defined(I2C3) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C3LPEN) +#endif /* I2C3 */ + +#if defined(I2C4) +#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C4LPEN) +#endif /* I2C4 */ + +#if defined(I3C2) +#define __HAL_RCC_I3C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I3C2LPEN) +#endif /* I3C2 */ + +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM1LPEN) + +#if defined(LPTIM3) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM3LPEN) +#endif /* LPTIM3 */ + +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM4LPEN) +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM5LPEN) +#endif /* LPTIM5 */ + +#if defined(LPTIM6) +#define __HAL_RCC_LPTIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM6LPEN) +#endif /* LPTIM6 */ + +#if defined(VREFBUF) +#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_VREFLPEN) +#endif /* VREFBUF */ + +#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) + +#if defined(PLAY1) +#define __HAL_RCC_PLAY1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_PLAY1LPEN) +#endif /* PLAY1 */ +/** + * @} + */ + + +/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset + * @{ + */ + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + * @note The BKPSRAM is not affected by this reset. + * @retval None + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST) + +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST) + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ + +/** @brief Macros to enable or disable the RTC clock. + * @note As the RTC is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the RTC + * (to be done once after reset). + * @note These macros must be used after the RTC clock source was selected. + * @retval None + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** + * @} + */ + +/** @brief Macro to configure the Internal High Speed oscillator (HSI). + * @param __HSIDIV__ specifies the HSI division factor. + * This parameter can be one of the following values: + * @arg RCC_HSI_DIV1 Divide the HSI oscillator clock by 1 (default after reset) + * @arg RCC_HSI_DIV2 Divide the HSI oscillator clock by 2 + * @arg RCC_HSI_DIV4 Divide the HSI oscillator clock by 4 + * @arg RCC_HSI_DIV8 Divide the HSI oscillator clock by 8 + */ +#define __HAL_RCC_HSI_DIVIDER_CONFIG(__HSIDIV__) \ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV , (uint32_t)(__HSIDIV__)) + + +/** @brief Macro to get the HSI divider. + * @retval The HSI divider. The returned value can be one + * of the following: + * - RCC_HSI_DIV1 HSI oscillator divided by 1 + * - RCC_HSI_DIV2 HSI oscillator divided by 2 + * - RCC_HSI_DIV4 HSI oscillator divided by 4 + * - RCC_HSI_DIV8 HSI oscillator divided by 8 + */ +#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) + +/** @brief Macros to enable or disable the Internal High Speed 64MHz oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the HSE Clock + * Security System HSECSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) + +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macro to adjust the Internal High Speed 64MHz oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x7F. + * @retval None + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_HSICFGR_HSITRIM_Pos) + +/** + * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) + * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. + * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the HSI startup time. + * @note The enable of this function has not effect on the HSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) + +#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) + +/** + * @brief Macros to enable or disable the Internal Low-power oscillator (CSI). + * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after + * startup from Reset, wakeup from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the HSE Clock Security System HSECSS is enabled and CSI is selected + * as system clock after wake up from system stop). + * @note CSI can not be stopped if it is used as system clock source. + * In this case, you have to select another source of the system + * clock then stop the CSI. + * @note After enabling the CSI, the application software should wait on + * CSIRDY flag to be set indicating that CSI clock is stable and can + * be used as system clock source. + * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION) + +#define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION) + +/** @brief Macro Adjusts the Internal oscillator (CSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal CSI RC. + * @param __CSICalibrationValue__: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x3F. + */ +#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ + do { \ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ + } while(0) + +/** + * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI) + * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. + * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the CSI start-up time. + * @note The enable of this function has not effect on the CSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON) +#define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON) + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSION) + +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION) + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLLs and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL1 as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @param __STATE__: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. + * @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed with digital external clock. + * @retval None + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + } \ + } while(0) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + * @arg @ref RCC_LSE_BYPASS_DIGITAL LSE oscillator bypassed with external digital clock. + * @retval None + */ + +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + } \ + } while(0) + +/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + * @note After enabling the HSI48, the application software should wait on HSI48RDY + * flag to be set indicating that HSI48 clock is stable. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON) + +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON) + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by + * a Power On Reset (POR). + * @param __RTCCLKSource__: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVx HSE clock divided by x selected + * as RTC clock, where x can be between 2 and 63 + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_RTCPRE, \ + (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE) + +#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ + RCC->BDCR &= ~RCC_BDCR_RTCSEL; \ + RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ + } while (0) + +/** @brief Macro to get the RTC clock source. + * @retval The returned value can be one of the following: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVx HSE clock divided by x selected as + * RTC clock, where x can be between 2 and 63 + (x can be retrieved with @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()) + */ +#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) + +/** @brief Macro to get the HSE division factor for RTC clock. + * + * @retval The HSE division factor for RTC clock. The returned value can be one + * of the following: + * @arg @ref RCC_RTC_HSE_NOCLOCK : No HSE Clock selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV2 : HSE Divided by 2 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV3 : HSE Divided by 3 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV4 : HSE Divided by 4 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV5 : HSE Divided by 5 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV6 : HSE Divided by 6 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV7 : HSE Divided by 7 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV8 : HSE Divided by 8 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV9 : HSE Divided by 9 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV10 : HSE Divided by 10 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV11 : HSE Divided by 11 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV12 : HSE Divided by 12 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV13 : HSE Divided by 13 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV14 : HSE Divided by 14 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV15 : HSE Divided by 15 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV16 : HSE Divided by 16 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV17 : HSE Divided by 17 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV18 : HSE Divided by 18 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV19 : HSE Divided by 19 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV20 : HSE Divided by 20 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV21 : HSE Divided by 21 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV22 : HSE Divided by 22 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV23 : HSE Divided by 23 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV24 : HSE Divided by 24 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV25 : HSE Divided by 25 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV26 : HSE Divided by 26 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV27 : HSE Divided by 27 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV28 : HSE Divided by 28 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV29 : HSE Divided by 29 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV30 : HSE Divided by 30 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV31 : HSE Divided by 31 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV32 : HSE Divided by 32 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV33 : HSE Divided by 33 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV34 : HSE Divided by 34 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV35 : HSE Divided by 35 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV36 : HSE Divided by 36 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV37 : HSE Divided by 37 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV38 : HSE Divided by 38 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV39 : HSE Divided by 39 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV40 : HSE Divided by 40 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV41 : HSE Divided by 41 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV42 : HSE Divided by 42 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV43 : HSE Divided by 43 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV44 : HSE Divided by 44 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV45 : HSE Divided by 45 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV46 : HSE Divided by 46 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV47 : HSE Divided by 47 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV48 : HSE Divided by 48 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV49 : HSE Divided by 49 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV50 : HSE Divided by 50 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV51 : HSE Divided by 51 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV52 : HSE Divided by 52 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV53 : HSE Divided by 53 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV54 : HSE Divided by 54 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV55 : HSE Divided by 55 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV56 : HSE Divided by 56 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV57 : HSE Divided by 57 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV58 : HSE Divided by 58 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV59 : HSE Divided by 59 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV60 : HSE Divided by 60 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV61 : HSE Divided by 61 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV62 : HSE Divided by 62 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV63 : HSE Divided by 63 selected as RTC clock + */ +#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE))) + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) +#define __HAL_RCC_PLL1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) + +/** + * @brief Enables or disables each clock output (PLL1P_CLK, PLL1Q_CLK, PLL1R_CLK) + * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL1, + * (except the ck_pll_p of the System PLL that cannot be stopped if used as System + * Clock. This is mainly used to save Power. + * @param __PLL1_CLOCKOUT__: specifies the PLL clock to be outputted + * This parameter can be one of the following values: + * @arg RCC_PLL1_DIVP: This Clock is used to generate the high speed system clock (up to 250MHz) + * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for USB (48 MHz), RNG (<=48 MHz), + * OCTOSPI, SPI, SAI and Ethernet + * @arg RCC_PLL1_DIVR: This Clock is used to generate an accurate clock + * @retval None + * + */ +#define __HAL_RCC_PLL1_CLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) + +#define __HAL_RCC_PLL1_CLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) + +/** + * @brief Macro to get the PLL clock output enable status. + * @param __PLL1_CLOCKOUT__ specifies the PLL1 clock to be output. + * This parameter can be one of the following values: + * @arg RCC_PLL1_DIVP: This Clock is used to generate the high speed system clock (up to 250MHz) + * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for USB (48 MHz), RNG (<=48 MHz), + * OCTOSPI, SPI, SAI and Ethernet + * @arg RCC_PLL1_DIVR: This Clock is used to generate an accurate clock + * @retval SET / RESET + */ +#define __HAL_RCC_GET_PLL1_CLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 + * @retval None + */ +#define __HAL_RCC_PLL1_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) + +#define __HAL_RCC_PLL1_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) + +/** + * @brief Macro to configures the main PLL (PLL1) clock source, multiplication and division factors. + * @note This function must be used only when the main PLL1 is disabled. + * + * @param __PLL1SOURCE__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLL1_SOURCE_CSI: CSI oscillator clock selected as PLL1 clock entry + * @arg RCC_PLL1_SOURCE_HSI: HSI oscillator clock selected as PLL1 clock entry + * @arg RCC_PLL1_SOURCE_HSE: HSE oscillator clock selected as PLL1 clock entry + * @note This clock source (__PLL1SOURCE__) is the clock source for PLL1 (main PLL) and is different + from PLL2 & PLL3 clock sources. + * + * @param __PLL1M__: specifies the division factor for PLL VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLL1M parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLL1N__: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 4 and 512. + * @note You have to set the PLL1N parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) or + * between 192 and 836 MHZ (when in wide VCO range) + * + * @param __PLL1P__: specifies the division factor for system clock. + * This parameter must be a number between 2 and 128 (where odd numbers not allowed) + * + * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLL1R__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @retval None + */ +#define __HAL_RCC_PLL1_CONFIG(__PLL1SOURCE__, __PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ + do{ MODIFY_REG(RCC->PLL1CFGR, (RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M), \ + ((__PLL1SOURCE__) << RCC_PLL1CFGR_PLL1SRC_Pos) | ((__PLL1M__) << RCC_PLL1CFGR_PLL1M_Pos));\ + WRITE_REG(RCC->PLL1DIVR , ( (((__PLL1N__) - 1U ) & RCC_PLL1DIVR_PLL1N) | \ + ((((__PLL1P__) - 1U ) << RCC_PLL1DIVR_PLL1P_Pos) & RCC_PLL1DIVR_PLL1P) | \ + ((((__PLL1Q__) - 1U) << RCC_PLL1DIVR_PLL1Q_Pos) & RCC_PLL1DIVR_PLL1Q) | \ + ((((__PLL1R__) - 1U) << RCC_PLL1DIVR_PLL1R_Pos) & RCC_PLL1DIVR_PLL1R))); \ + } while(0) + +/** @brief Macro to configure the PLL1 clock source. + * @note This function must be used only when PLL1 is disabled. + * @param __PLL1SOURCE__: specifies the PLL1 entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLL1_SOURCE_CSI: CSI oscillator clock selected as PLL1 clock entry + * @arg RCC_PLL1_SOURCE_HSI: HSI oscillator clock selected as PLL1 clock entry + * @arg RCC_PLL1_SOURCE_HSE: HSE oscillator clock selected as PLL1 clock entry + * + */ +#define __HAL_RCC_PLL1_PLLSOURCE_CONFIG(__PLL1SOURCE__) \ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLL1SOURCE__)) + +/** @brief Macro to configure the PLL1 input clock division factor M. + * + * @note This function must be used only when the PLL1 is disabled. + * @note PLL1 clock source is common with the main PLL (configured through + * __HAL_RCC_PLL1_CONFIG() macro) + * + * @param __PLL1M__ specifies the division factor for PLL1 clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 63. + * In order to save power when PLL1 is not used, the value of PLL1M must be set to 0. + * + * @retval None + */ +#define __HAL_RCC_PLL1_DIVM_CONFIG(__PLL1M__) \ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (__PLL1M__) << RCC_PLL1CFGR_PLL1M_Pos) + +/** + * @brief Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO + * + * @param __PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO + * It should be a value between 0 and 8191 + * @note Warning: The software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz if PLL1VCOSEL = 0 + * 150 to 420 MHz if PLL1VCOSEL = 1. + * + * + * @retval None + */ +#define __HAL_RCC_PLL1_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, \ + (uint32_t)(__PLL1FRACN__) << RCC_PLL1FRACR_PLL1FRACN_Pos) + +/** @brief Macro to select the PLL1 reference frequency range. + * @param __PLL1VCIRange__: specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL1_VCIRANGE_0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL1_VCIRANGE_1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL1_VCIRANGE_2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL1_VCIRANGE_3: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL1_VCIRANGE(__PLL1VCIRange__) \ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__)) + +/** @brief Macro to select the PLL1 reference frequency range. + * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL1_VCORANGE_WIDE: Range frequency is between 192 and 836 MHz + * @arg RCC_PLL1_VCORANGE_MEDIUM: Range frequency is between 150 and 420 MHz + * + * + * @retval None + */ +#define __HAL_RCC_PLL1_VCORANGE(__RCC_PLL1VCORange__) \ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__)) + +/** @brief Macro to get the oscillator used as PLL1 clock source. + * @retval The oscillator used as PLL1 clock source. The returned value can be one + * of the following: + * - RCC_PLL1_SOURCE_NONE: No oscillator is used as PLL clock source. + * - RCC_PLL1_SOURCE_CSI: CSI oscillator is used as PLL clock source. + * - RCC_PLL1_SOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLL1_SOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL1_OSCSOURCE() ((uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC)) + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__: specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLL1CLK: PLL1P output is used as system clock source. + * @retval None + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - RCC_SYSCLKSOURCE_STATUS_CSI: CSI used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_PLL1CLK: PLL1P used as system clock. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR1 & RCC_CFGR1_SWS)) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable the write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. (*) + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + * + * (*): Not available For stm32h5exxx and stm32h5fxxx family lines. + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) + +/** + * @brief Macro to configure the wake up from stop clock. + * @note The configured clock is also used as emergency clock for the Clock Security System on HSE (HSECSS). + * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. + * This parameter can be one of the following values: + * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source + * @arg @ref RCC_STOP_WAKEUPCLOCK_CSI CSI selected as system clock source + * @retval None + */ +#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, (__STOPWUCLK__)) + +#define __HAL_RCC_HSECSS_RECOVCLK_CONFIG __HAL_RCC_WAKEUPSTOP_CLK_CONFIG + +/** + * @brief Macro to configure the Kernel wake up from stop clock. + * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop + * This parameter can be one of the following values: + * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source + * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source + * @retval None + */ +#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO1 clock. + * @param __MCOCLKSOURCE__ specifies the MCO1 clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO1SEL | RCC_CFGR1_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO2 clock. + * @param __MCOCLKSOURCE__ specifies the MCO2 clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLL1PCLK: PLL1P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_CSI: CSI clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_LSI: LSI clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock + */ +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO2SEL | RCC_CFGR1_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7))); + +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt (Perform access to RCC_CIER[8:0] bits to enable + * the selected interrupts). + * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_CSIRDY CSI ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) + * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + * @retval None + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Disable RCC interrupt (Perform access to RCC_CIER[8:0] bits to disable + * the selected interrupts). + * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_CSIRDY CSI ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) + * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + * @retval None + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CICR[10:0] + * bits to clear the selected interrupt pending bits. + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_CSIRDY CSI ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) + * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + * @retval None + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) + +/** @brief Check whether the RCC interrupt has occurred or not. + * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_CSIRDY CSI ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) + * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are: RCC_FLAG_SFTRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + * @retval None + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF) + +/** @brief Check whether the selected RCC flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_CSIRDY CSI oscillator clock ready + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready + * @arg @ref RCC_FLAG_PLL1RDY Main PLL1 clock ready + * @arg @ref RCC_FLAG_PLL2RDY PLL2 clock ready + * @arg @ref RCC_FLAG_PLL3RDY PLL3 clock ready (*) + * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready + * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready + * @arg @ref RCC_FLAG_HSIDIVF HSI Divider + * @arg @ref RCC_FLAG_BORRST BOR reset + * @arg @ref RCC_FLAG_PINRST Pin reset + * @arg @ref RCC_FLAG_RMVF Remove reset Flag + * @arg @ref RCC_FLAG_SFTRST Software reset + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset + * @arg @ref RCC_FLAG_LPWRRST Low Power reset + * @retval The new state of __FLAG__ (TRUE or FALSE). + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ + ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == 3U) ? RCC->RSR : RCC->CIFR))) & \ + (1UL << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ + +/** @defgroup RCC_Timeout_Value Timeout Values + * @{ + */ +#define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define RCC_HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#define RCC_CSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +/** + * @} + */ + +/* Defines used for Flags */ +#define RCC_CR_REG_INDEX (1U) +#define RCC_BDCR_REG_INDEX (2U) +#define RCC_RSR_REG_INDEX (3U) + +#define RCC_FLAG_MASK (0x1FU) + +/* Defines Oscillator Masks */ +#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | \ + RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) +/*!< All Oscillator to configure */ + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros + * @{ + */ + +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) + + +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL)) + +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_DIGITAL)) + +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) + +#define IS_RCC_HSIDIV(__DIV__) (((__DIV__) == RCC_HSI_DIV1) || ((__DIV__) == RCC_HSI_DIV2) || \ + ((__DIV__) == RCC_HSI_DIV4) || ((__DIV__) == RCC_HSI_DIV8)) + +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ + <= (uint32_t)( RCC_HSICFGR_HSITRIM >> RCC_HSICFGR_HSITRIM_Pos)) + +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) + +#define IS_RCC_CSI(__CSI__) (((__CSI__) == RCC_CSI_OFF) || ((__CSI__) == RCC_CSI_ON)) + +#define IS_RCC_CSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ + <= (uint32_t)( RCC_CSICFGR_CSITRIM >> RCC_CSICFGR_CSITRIM_Pos)) + +#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) + +#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ + ((PLL) == RCC_PLL_ON)) + +#define IS_RCC_PLL1_SOURCE(SOURCE) (((SOURCE) == RCC_PLL1_SOURCE_CSI) || \ + ((SOURCE) == RCC_PLL1_SOURCE_HSI) || \ + ((SOURCE) == RCC_PLL1_SOURCE_HSE)) + +#define IS_RCC_PLL1_DIVM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) +#define IS_RCC_PLL1_MULN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#define IS_RCC_PLL1_DIVP_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL1_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL1_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) + +#define IS_RCC_PLL1_CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ + ((VALUE) == RCC_PLL1_DIVQ) || \ + ((VALUE) == RCC_PLL1_DIVR)) + +#define IS_RCC_PLL1_VCIRGE_VALUE(VALUE) (((VALUE) == RCC_PLL1_VCIRANGE_0) || \ + ((VALUE) == RCC_PLL1_VCIRANGE_1) || \ + ((VALUE) == RCC_PLL1_VCIRANGE_2) || \ + ((VALUE) == RCC_PLL1_VCIRANGE_3)) + +#define IS_RCC_PLL1_VCORGE_VALUE(VALUE) (((VALUE) == RCC_PLL1_VCORANGE_WIDE) || ((VALUE) == RCC_PLL1_VCORANGE_MEDIUM)) + +#define IS_RCC_PLL1_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) + +#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x1FU)) + +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) + +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) + +#define IS_RCC_RTCCLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_NO_CLK)) + +#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1Q) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI48)) + +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2P) || \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLL1P) || \ + ((SOURCE) == RCC_MCO2SOURCE_CSI) || ((SOURCE) == RCC_MCO2SOURCE_LSI)) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ + ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \ + ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \ + ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \ + ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \ + ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ + ((DIV) == RCC_MCODIV_15)) + +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) +#else +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) +#endif /* STM32H5E5xx || STM32H5E4xx || !STM32H5F5xx || STM32H5F4xx */ + +#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_CSI) || \ + ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) + +#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \ + ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) + +#if defined(RCC_SECCFGR_HSISEC) + +#define IS_RCC_ITEM_ATTRIBUTES(ITEM) ((((ITEM) & RCC_ALL) != 0U) && (((ITEM) & ~RCC_ALL) == 0U)) + +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_SINGLE_ITEM_ATTRIBUTES(ITEM) (((ITEM) == RCC_HSI) || \ + ((ITEM) == RCC_HSE) || \ + ((ITEM) == RCC_CSI) || \ + ((ITEM) == RCC_LSI) || \ + ((ITEM) == RCC_LSE) || \ + ((ITEM) == RCC_SYSCLK) || \ + ((ITEM) == RCC_PRESC) || \ + ((ITEM) == RCC_PLL1) || \ + ((ITEM) == RCC_PLL2) || \ + ((ITEM) == RCC_PLL3) || \ + ((ITEM) == RCC_HSI48) || \ + ((ITEM) == RCC_RMVF) || \ + ((ITEM) == RCC_CKPERSEL)) +#else +#define IS_RCC_SINGLE_ITEM_ATTRIBUTES(ITEM) (((ITEM) == RCC_HSI) || \ + ((ITEM) == RCC_HSE) || \ + ((ITEM) == RCC_CSI) || \ + ((ITEM) == RCC_LSI) || \ + ((ITEM) == RCC_LSE) || \ + ((ITEM) == RCC_SYSCLK) || \ + ((ITEM) == RCC_PRESC) || \ + ((ITEM) == RCC_PLL1) || \ + ((ITEM) == RCC_PLL2) || \ + ((ITEM) == RCC_HSI48) || \ + ((ITEM) == RCC_RMVF) || \ + ((ITEM) == RCC_CKPERSEL)) +#endif /* RCC_CR_PLL3ON */ +#endif /* RCC_SECCFGR_HSISEC */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_SEC_PRIV) || \ + ((ATTRIBUTES) == RCC_SEC_NPRIV) || \ + ((ATTRIBUTES) == RCC_NSEC_PRIV) || \ + ((ATTRIBUTES) == RCC_NSEC_NPRIV)) +#elif defined(RCC_PRIVCFGR_NSPRIV) +#define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_NSEC_NPRIV) || ((ATTRIBUTES) == RCC_NSEC_PRIV)) +#else +#define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_NPRIV) || ((ATTRIBUTES) == RCC_PRIV)) +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/* Include RCC HAL Extended module */ +#include "stm32h5xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pOscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *pClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +uint32_t HAL_RCC_GetPCLK3Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pOscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pClkInitStruct, uint32_t *pFLatency); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); +uint32_t HAL_RCC_GetResetSource(void); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group3 + * @{ + */ + +/* Attributes management functions ********************************************/ +void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); +HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H5xx_HAL_RCC_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h new file mode 100644 index 00000000..9f9d3fb9 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h @@ -0,0 +1,4827 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H5xx_HAL_RCC_EX_H +#define __STM32H5xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief PLL2 Clock structure definition + */ +typedef struct +{ + uint32_t PLL2Source; /*!< RCC_PLL2Source: PLL2 entry clock source. + This parameter must be a value of @ref RCC_PLL2_Clock_Source */ + + uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ + + uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ + + uint32_t PLL2P; /*!< PLL2P: Division factor for peripheral clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ + + uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 + odd division factors are not allowed */ + + uint32_t PLL2RGE; /*!CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< HSI/1024, CSI/128 and HSI/8 generation for Timers 12,15 and LPTimer2 Input capture */ +#define __HAL_RCC_TIMIC_DISABLE() CLEAR_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< No clock available for Timers Input capture */ + +#if defined (RCC_CCIPR4_OTGPDCTRL) +/** @brief Set the power state of the OTG PHY in SUSPEND mode. + * @param _STATE_ the power state of the OTG PHY in SUSPEND mode. + * This parameter can be one of the following values: + * @arg @ref RCC_OTGPD_SUSPEND_POWERDOWN OTG PHY is powered down when the system is in SUSPEND mode + * @arg @ref RCC_OTGPD_SUSPEND_POWERON OTG PHY is powered down when the system is in SUSPEND mode + * @retval None + */ +#define __HAL_RCC_OTGPD_CONFIG(_STATE_) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OTGPDCTRL, (uint32_t)(_STATE_)) +#endif /* RCC_CCIPR4_OTGPDCTRL */ + +/** @brief Macro to configure the PLL2 clock source. + * @note This function must be used only when all PLL2 is disabled. + * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLL2_SOURCE_NONE: No oscillator clock selected as PLL2 clock entry + * @arg RCC_PLL2_SOURCE_CSI: CSI oscillator clock selected as PLL2 clock entry + * @arg RCC_PLL2_SOURCE_HSI: HSI oscillator clock selected as PLL2 clock entry + * @arg RCC_PLL2_SOURCE_HSE: HSE oscillator clock selected as PLL2 clock entry + * + */ +#define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLL2SOURCE__) MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, \ + (__PLL2SOURCE__)) + +/** @brief Macro to get the oscillator used as PLL2 clock source. + * @retval The oscillator used as PLL2 clock source. The returned value can be one + * of the following: + * - RCC_PLL2_SOURCE_NONE: No oscillator is used as PLL clock source. + * - RCC_PLL2_SOURCE_CSI: CSI oscillator is used as PLL clock source. + * - RCC_PLL2_SOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLL2_SOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL2_OSCSOURCE() ((uint32_t)(RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC)) + +/** + * @brief Macro to configures the PLL2 source, multiplication and division factors. + * @note This function must be used only when PLL2 is disabled. + * + * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLL2_SOURCE_NONE No clock selected as PLL2 clock entry + * @arg @ref RCC_PLL2_SOURCE_CSI CSI oscillator clock selected as PLL2 clock entry + * @arg @ref RCC_PLL2_SOURCE_HSI HSI oscillator clock selected as PLL2 clock entry + * @arg @ref RCC_PLL2_SOURCE_HSE HSE oscillator clock selected as PLL2 clock entry + * + * @param __PLL2M__ specifies the division factor of PLL2 input clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 63. + * + * @param __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock + * This parameter must be a number between 4 and 512. + * @note You have to set the PLL2N parameter correctly to ensure that the VCO + * output frequency is between 192 and 836 MHz (Wide range) or 150 and 420 Mhz (Medium range). + * PLL2 clock frequency = f(PLL2) multiplied by PLL2N + * + * @param __PLL2P__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLL2Q__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLL2R__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @retval None + */ +#define __HAL_RCC_PLL2_CONFIG(__PLL2SOURCE__, __PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__) \ + do{ \ + MODIFY_REG(RCC->PLL2CFGR, (RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M), \ + ((__PLL2SOURCE__) << RCC_PLL2CFGR_PLL2SRC_Pos) | ((__PLL2M__) << RCC_PLL2CFGR_PLL2M_Pos)); \ + WRITE_REG(RCC->PLL2DIVR , ((((__PLL2N__) - 1U) & RCC_PLL2DIVR_PLL2N) | \ + ((((__PLL2P__) - 1U) << RCC_PLL2DIVR_PLL2P_Pos) & RCC_PLL2DIVR_PLL2P) | \ + ((((__PLL2Q__) - 1U) << RCC_PLL2DIVR_PLL2Q_Pos) & RCC_PLL2DIVR_PLL2Q) | \ + ((((__PLL2R__) - 1U) << RCC_PLL2DIVR_PLL2R_Pos) & RCC_PLL2DIVR_PLL2R))); \ + } while(0) +/** + * @brief Macro to configure the PLL2 clock multiplication factor N. + * + * @note This function must be used only when the PLL2 is disabled. + * @note PLL2 clock source is independent from the main PLL and is configured through + * __HAL_RCC_PLL2_CONFIG() macro. + * + * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock. + * This parameter must be a number between 4 and 512. + * @note You have to set the PLL2N parameter correctly to ensure that the VCO + * output frequency is between 192 and 836 MHz (Wide range) or 150 and 420 Mhz (Medium range). + * PLL2 clock frequency = f(PLL2) multiplied by PLL2N + * + * @retval None + */ +#define __HAL_RCC_PLL2_MULN_CONFIG(__PLL2N__) \ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, ((__PLL2N__) - 1U) << RCC_PLL2DIVR_N2_Pos) + +/** @brief Macro to configure the PLL2 input clock division factor M. + * + * @note This function must be used only when the PLL2 is disabled. + * @note PLL2 clock source is independent from the main PLL and is configured through + * __HAL_RCC_PLL2_CONFIG() macro. + * + * @param __PLL2M__ specifies the division factor for PLL2 clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 63. + * In order to save power when PLL2 is not used, the value of PLL2M must be set to 0. + * + * @retval None + */ +#define __HAL_RCC_PLL2_DIVM_CONFIG(__PLL2M__) \ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_DIVM2, (__PLL2M__) << RCC_PLL2CFGR_DIVM2_Pos) + +/** @brief Macro to configure the PLL2 clock division factor P. + * + * @note This function must be used only when the PLL2 is disabled. + * @note PLL2 clock source is independent from the main PLL and is configured through + * __HAL_RCC_PLL2_CONFIG() macro. + * + * @param __PLL2P__ specifies the division factor for PLL2 output P clock. + * This parameter must be a number in the range (1 to 128). + * Use to set PLL2 output P clock frequency = f(PLL2) / PLL2P + * + * @retval None + */ +#define __HAL_RCC_PLL2_DIVP_CONFIG(__PLL2P__) \ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, ((__PLL2P__) - 1U) << RCC_PLL2DIVR_P2_Pos) + +/** @brief Macro to configure the PLL2 clock division factor Q. + * + * @note This function must be used only when the PLL2 is disabled. + * @note PLL2 clock source is independent from the main PLL and is configured through + * __HAL_RCC_PLL2_CONFIG() macro. + * + * @param __PLL2Q__ specifies the division factor for PLL2 output Q clock. + * This parameter must be a number in the range (1 to 128). + * Use to set PLL2 output Q clock frequency = f(PLL2) / PLL2Q + * + * @retval None + */ +#define __HAL_RCC_PLL2_DIVQ_CONFIG(__PLL2Q__) \ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, ((__PLL2Q__) - 1U) << RCC_PLL2DIVR_Q2_Pos) + +/** @brief Macro to configure the PLL2 clock division factor R. + * + * @note This function must be used only when the PLL2 is disabled. + * @note PLL2 clock source is independent from the main PLL and is configured through + * __HAL_RCC_PLL2_CONFIG() macro. + * + * @param __PLL2R__ specifies the division factor for PLL2 output R clock. + * This parameter must be a number in the range (1 to 128). + * Use to set PLL2 output R clock frequency = f(PLL2) / PLL2R + * + * @retval None + */ +#define __HAL_RCC_PLL2_DIVR_CONFIG(__PLL2R__) \ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, ((__PLL2R__) - 1U) << RCC_PLL2DIVR_R2_Pos) + +/** @brief Macros to enable or disable the PLL2. + * @note After enabling PLL2, the application software should wait on + * PLL2RDY flag to be set indicating that PLL2 clock is stable and can + * be used as kernel clock source. + * @note The PLL2 is disabled by hardware when entering STOP and STANDBY modes. + * @retval None + */ +#define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) +#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) + +/** + * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) + * @note Enabling/disabling those clocks can be done at any time without the need to stop the PLL2, + * This is mainly used to save Power. + * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock to be output. + * This parameter can be one or a combination of the following values: + * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate kernel clock to achieve + * high-quality audio performance on SAI interface, SPI/I2S and LPTIM peripherals. + * @arg RCC_PLL2_DIVQ: This clock is used to generate kernel clock for the random number generator RNG + * (<=48 MHz), SPI, FDCAN and UART/USART peripherals. + * @arg RCC_PLL2_DIVR: This clock is used to generate kernel clock for ADC and DAC peripherals. + * @retval None + */ +#define __HAL_RCC_PLL2_CLKOUT_ENABLE(__PLL2_CLOCKOUT__) SET_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) +#define __HAL_RCC_PLL2_CLKOUT_DISABLE(__PLL2_CLOCKOUT__) CLEAR_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) + +/** + * @brief Macro to get the PLL2 clock output enable status. + * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock to be output. + * This parameter can be one or a combination of the following values: + * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate kernel clock to achieve + * high-quality audio performance on SAI interface, SPI/I2S and LPTIM peripherals. + * @arg RCC_PLL2_DIVQ: This clock is used to generate kernel clock for the random number generator RNG + * (<=48 MHz), SPI, FDCAN and UART/USART peripherals. + * @arg RCC_PLL2_DIVR: This clock is used to generate kernel clock for ADC and DAC peripherals. + * @retval SET / RESET + */ +#define __HAL_RCC_GET_PLL2_CLKOUT_CONFIG(__PLL2_CLOCKOUT__) READ_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO + * @note Enabling/disabling Fractional Part can be done at any time without the need to stop the PLL2 + * @retval None + */ +#define __HAL_RCC_PLL2_FRACN_ENABLE() SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) +#define __HAL_RCC_PLL2_FRACN_DISABLE() CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) + +/** + * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO + * + * @param __PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO + * It should be a value between 0 and 8191 + * @note Warning: the software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz if PLL2VCOSEL = 0 + * 150 to 420 MHz if PLL2VCOSEL = 1. + * + * @retval None + */ +#define __HAL_RCC_PLL2_FRACN_CONFIG(__PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN, \ + (uint32_t)(__PLL2FRACN__) << RCC_PLL2FRACR_PLL2FRACN_Pos) + +/** @brief Macro to select the PLL2 reference frequency range. + * @param __PLL2VCIRange__: specifies the PLL2 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL2_VCIRANGE_0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL2_VCIRANGE_1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL2_VCIRANGE_2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL2_VCIRANGE_3: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL2_VCIRANGE(__PLL2VCIRange__) \ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, (__PLL2VCIRange__)) + +/** @brief Macro to select the PLL2 reference frequency range. + * @param __RCC_PLL2VCORange__: specifies the PLL2 output frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL2_VCORANGE_WIDE: Range frequency is between 192 and 836 MHz + * @arg RCC_PLL2_VCORANGE_MEDIUM: Range frequency is between 150 and 420 MHz + * + * @retval None + */ +#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) + +#if defined(RCC_CR_PLL3ON) +/** @brief Macro to configure the PLL3 clock source. + * @note This function must be used only when all PLL3 is disabled. + * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLL3_SOURCE_NONE: No oscillator clock selected as PLL3 clock entry + * @arg RCC_PLL3_SOURCE_CSI: CSI oscillator clock selected as PLL3 clock entry + * @arg RCC_PLL3_SOURCE_HSI: HSI oscillator clock selected as PLL3 clock entry + * @arg RCC_PLL3_SOURCE_HSE: HSE oscillator clock selected as PLL3 clock entry + * + */ +#define __HAL_RCC_PLL3_PLLSOURCE_CONFIG(__PLL3SOURCE__) MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, \ + (__PLL3SOURCE__)) + +/** @brief Macro to get the oscillator used as PLL3 clock source. + * @retval The oscillator used as PLL3 clock source. The returned value can be one + * of the following: + * - RCC_PLL3_SOURCE_NONE: No oscillator is used as PLL3 clock source. + * - RCC_PLL3_SOURCE_CSI: CSI oscillator is used as PLL3 clock source. + * - RCC_PLL3_SOURCE_HSI: HSI oscillator is used as PLL3 clock source. + * - RCC_PLL3_SOURCE_HSE: HSE oscillator is used as PLL3 clock source. + */ +#define __HAL_RCC_GET_PLL3_OSCSOURCE() ((uint32_t)(RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC)) + +/** + * @brief Macro to configures the PLL3 source, multiplication and division factors. + * @note This function must be used only when PLL3 is disabled. + * + * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLL3_SOURCE_NONE No clock selected as PLL3 clock entry + * @arg @ref RCC_PLL3_SOURCE_CSI CSI oscillator clock selected as PLL3 clock entry + * @arg @ref RCC_PLL3_SOURCE_HSI HSI oscillator clock selected as PLL3 clock entry + * @arg @ref RCC_PLL3_SOURCE_HSE HSE oscillator clock selected as PLL3 clock entry + * + * @param __PLL3M__ specifies the division factor of PLL3 input clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 63. + * + * @param __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock + * This parameter must be a number between 4 and 512. + * @note You have to set the PLL3N parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) + * or between 192 and 836 MHZ (when in wide VCO range) + * + * @param __PLL3P__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLL3Q__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLL3R__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @retval None + */ +#define __HAL_RCC_PLL3_CONFIG(__PLL3SOURCE__, __PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__) \ + do{\ + MODIFY_REG(RCC->PLL3CFGR, (RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M), \ + ((__PLL3SOURCE__) << RCC_PLL3CFGR_PLL3SRC_Pos) | ((__PLL3M__) << RCC_PLL3CFGR_PLL3M_Pos)); \ + WRITE_REG(RCC->PLL3DIVR , ( (((__PLL3N__) - 1U) & RCC_PLL3DIVR_PLL3N) | \ + ((((__PLL3P__) - 1U) << RCC_PLL3DIVR_PLL3P_Pos) & RCC_PLL3DIVR_PLL3P) | \ + ((((__PLL3Q__) - 1U) << RCC_PLL3DIVR_PLL3Q_Pos) & RCC_PLL3DIVR_PLL3Q) | \ + ((((__PLL3R__) - 1U) << RCC_PLL3DIVR_PLL3R_Pos) & RCC_PLL3DIVR_PLL3R))); \ + } while(0) + +/** + * @brief Macro to configure the PLL3 clock multiplication factor N. + * + * @note This function must be used only when the PLL3 is disabled. + * @note PLL3 clock source is independent from the main PLL and is configured through + * __HAL_RCC_PLL3_CONFIG() macro. + * + * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock. + * This parameter must be a number between 8 and 86. + * @note You have to set the PLL3N parameter correctly to ensure that the VCO + * output frequency is between 192 and 836 MHz (Wide range) or 150 and 420 Mhz (Medium range). + * PLL3 clock frequency = f(PLL3) multiplied by PLL3N + * + * @retval None + */ +#define __HAL_RCC_PLL3_MULN_CONFIG(__PLL3N__) \ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, ((__PLL3N__) - 1U) << RCC_PLL3DIVR_N3_Pos) + +/** @brief Macro to configure the PLL3 input clock division factor M. + * + * @note This function must be used only when the PLL3 is disabled. + * @note PLL3 clock source is independent from the main PLL and is configured through + * __HAL_RCC_PLL3_CONFIG() macro. + * + * @param __PLL3M__ specifies the division factor for PLL3 clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 63. + * In order to save power when PLL3 is not used, the value of PLL3M must be set to 0. + * + * @retval None + */ +#define __HAL_RCC_PLL3_DIVM_CONFIG(__PLL3M__) \ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_DIVM3, (__PLL3M__) << RCC_PLL3CFGR_DIVM3_Pos) + +/** @brief Macro to configure the PLL3 clock division factor P. + * + * @note This function must be used only when the PLL3 is disabled. + * @note PLL3 clock source is independent from the main PLL and is configured through + * __HAL_RCC_PLL3_CONFIG() macro. + * + * @param __PLL3P__ specifies the division factor for PLL3 output P clock. + * This parameter must be a number in the range (1 to 128). + * Use to set PLL3 output P clock frequency = f(PLL3) / PLL3P + * + * @retval None + */ +#define __HAL_RCC_PLL3_DIVP_CONFIG(__PLL3P__) \ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, ((__PLL3P__) - 1U) << RCC_PLL3DIVR_P3_Pos) + +/** @brief Macro to configure the PLL3 clock division factor Q. + * + * @note This function must be used only when the PLL3 is disabled. + * @note PLL3 clock source is independent from the main PLL and is configured through + * __HAL_RCC_PLL3_CONFIG() macro. + * + * @param __PLL3Q__ specifies the division factor for PLL3 output Q clock. + * This parameter must be a number in the range (1 to 128). + * Use to set PLL3 output Q clock frequency = f(PLL3) / PLL3Q + * + * @retval None + */ +#define __HAL_RCC_PLL3_DIVQ_CONFIG(__PLL3Q__) \ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, ((__PLL3Q__) - 1U) << RCC_PLL3DIVR_Q3_Pos) + +/** @brief Macro to configure the PLL3 clock division factor R. + * + * @note This function must be used only when the PLL3 is disabled. + * @note PLL3 clock source is independent from the main PLL and is configured through + * __HAL_RCC_PLL3_CONFIG() macro. + * + * @param __PLL3R__ specifies the division factor for PLL3 output R clock. + * This parameter must be a number in the range (1 to 128). + * Use to set PLL3 output R clock frequency = f(PLL3) / PLL3R + * + * @retval None + */ +#define __HAL_RCC_PLL3_DIVR_CONFIG(__PLL3R__) \ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, ((__PLL3R__) - 1U) << RCC_PLL3DIVR_R3_Pos) + +/** + * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO + * + * @param __PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO + * It should be a value between 0 and 8191 + * @note Warning: the software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz if PLL3VCOSEL = 0 + * 150 to 420 MHz if PLL3VCOSEL = 1. + * + * @retval None + */ +#define __HAL_RCC_PLL3_FRACN_CONFIG(__PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, \ + (uint32_t)(__PLL3FRACN__) << RCC_PLL3FRACR_PLL3FRACN_Pos) + +/** @brief Macro to select the PLL3 reference frequency range. + * @param __PLL3VCIRange__: specifies the PLL3 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL3_VCIRANGE_0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL3_VCIRANGE_1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL3_VCIRANGE_2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL3_VCIRANGE_3: Range frequency is between 8 and 16 MHz + * + * @retval None + */ +#define __HAL_RCC_PLL3_VCIRANGE(__PLL3VCIRange__) \ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, (__PLL3VCIRange__)) + +/** @brief Macro to select the PLL3 reference frequency range. + * @param __RCC_PLL3VCORange__: specifies the PLL3 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz + * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz + * + * @retval None + */ +#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) + +/** + * @brief Macros to enable or disable the PLL3. + * @note The PLL3 is disabled by hardware when entering STOP and STANDBY modes. + * @retval None + */ + +/** @brief Macros to enable or disable the main PLL3. + * @note After enabling PLL3, the application software should wait on + * PLL3RDY flag to be set indicating that PLL3 clock is stable and can + * be used as kernel clock source. + * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) +#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO + * @note Enabling/disabling Fractional Part can be done at any time without the need to stop the PLL3 + * @retval None + */ +#define __HAL_RCC_PLL3_FRACN_ENABLE() SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) +#define __HAL_RCC_PLL3_FRACN_DISABLE() CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) + +/** + * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) + * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL3, + * This is mainly used to save Power. + * @param __PLL3_CLOCKOUT__: specifies the PLL3 clock to be outputted + * This parameter can be one of the following values: + * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI and SPI/I2S interfaces. + * @arg RCC_PLL3_DIVQ: This clock is used to generate kernel clock for SPI, LPUART, UART/USART + * and USB peripherals. + * @arg RCC_PLL3_DIVR: This clock is used to generate kernel clock for I2C, I3C and LPTIM peripherals. + * + * @retval None + */ +#define __HAL_RCC_PLL3_CLKOUT_ENABLE(__PLL3_CLOCKOUT__) SET_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) +#define __HAL_RCC_PLL3_CLKOUT_DISABLE(__PLL3_CLOCKOUT__) CLEAR_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) + +/** + * @brief Macro to get clock output enable status (PLL3_SAI2). + * @param __PLL3_CLOCKOUT__ specifies the PLL3 clock to be output. + * This parameter can be one or a combination of the following values: + * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI and SPI/I2S interfaces. + * @arg RCC_PLL3_DIVQ: This clock is used to generate kernel clock for SPI, LPUART, UART/USART + * and USB peripherals. + * @arg RCC_PLL3_DIVR: This clock is used to generate kernel clock for I2C, I3C and LPTIM peripherals. + * + * @retval SET / RESET + */ +#define __HAL_RCC_GET_PLL3_CLKOUT_CONFIG(__PLL3_CLOCKOUT__) READ_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) +#endif /* RCC_CR_PLL3ON */ + +/** @brief Macro to configure the ADC and DAC kernel clock source. + * @param __ADCDAC_CLKSOURCE__ specifies the ADC and DAC kernel clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADCDACCLKSOURCE_HCLK AHB bus clock selected as ADC and DAC kernel clock + * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK System clock selected as ADC and DAC kernel clock + * @arg @ref RCC_ADCDACCLKSOURCE_PLL2R PLL2R clock selected as ADC and DAC kernel clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSE HSE clock selected as ADC and DAC kernel clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSI HSI clock selected as ADC and DAC kernel clock + * @arg @ref RCC_ADCDACCLKSOURCE_CSI CSI clock selected as ADC and DAC kernel clock + * @retval None + */ +#define __HAL_RCC_ADCDAC_CONFIG(__ADCDAC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ADCDACSEL, (uint32_t)(__ADCDAC_CLKSOURCE__)) + +/** @brief Macro to get the ADC and DAC kernel clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADCDACCLKSOURCE_HCLK AHB Bus clock used as ADC and DAC kernel clock + * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK System clock used as ADC and DAC kernel clock + * @arg @ref RCC_ADCDACCLKSOURCE_PLL2R PLL2R clock used as ADC and DAC kernel clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSE HSE oscillator used as ADC and DAC kernel clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSI HSI oscillator used as ADC and DAC kernel clock + * @arg @ref RCC_ADCDACCLKSOURCE_CSI CSI oscillator used as ADC and DAC kernel clock + */ +#define __HAL_RCC_GET_ADCDAC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_ADCDACSEL))) + +/** @brief Macro to configure the DAC kernel clock source in low-power mode. + * @param __DACLPCLKSOURCE__ specifies the DAC kernel clock source in low-power mode. + * This parameter can be one of the following values: + * @arg @ref RCC_DACLPCLKSOURCE_LSE LSE oscillator selected as DAC kernel clock in low-power mode + * @arg @ref RCC_DACLPCLKSOURCE_LSI LSI oscillator selected as DAC kernel clock in low-power mode + * @retval None + */ +#define __HAL_RCC_DAC_LP_CONFIG(__DACLPCLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_DACSEL, (uint32_t)(__DACLPCLKSOURCE__)) + +/** @brief Macro to get the DAC kernel clock source in low-power mode. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_DACLPCLKSOURCE_LSE LSE oscillator used as DAC kernel clock in low-power mode + * @arg @ref RCC_DACLPCLKSOURCE_LSI LSI oscillator used as DAC kernel clock in low-power mode + */ +#define __HAL_RCC_GET_DAC_LP_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_DACSEL))) + +/** @brief Macro to configure the FDCAN kernel clock (FDCANCLK). + * + * @param __FDCAN_CLKSOURCE__ specifies the FDCAN kernel clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_FDCANCLKSOURCE_HSE HSE oscillator selected as FDCAN kernel clock + * @arg @ref RCC_FDCANCLKSOURCE_PLL1Q PLL1Q Clock selected as FDCAN kernel clock + * @arg @ref RCC_FDCANCLKSOURCE_PLL2Q PLL2Q Clock selected as FDCAN kernel clock + * @retval None + */ +#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) + +/** @brief Macro to get the FDCAN clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_FDCANCLKSOURCE_HSE HSE oscillator selected as FDCAN kernel clock + * @arg @ref RCC_FDCANCLKSOURCE_PLL1Q PLL1Q Clock selected as FDCAN kernel clock + * @arg @ref RCC_FDCANCLKSOURCE_PLL2Q PLL2Q Clock selected as FDCAN kernel clock + */ +#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_FDCANSEL))) + +/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). + * + * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK3 PCLK3 selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_PLL2P PLL2P selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_PLL3R PLL3R selected as LPTIM1 clock (*) + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_CLKP CLKP selected as LPTIM1 clock + * @retval None + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK3 PCLK3 selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_PLL2P PLL2P selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_PLL3R PLL3R selected as LPTIM1 clock (*) + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_CLKP CLKP selected as LPTIM1 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL))) + +/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). + * + * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_PLL2P PLL2P selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_PLL3R PLL3R selected as LPTIM2 clock (*) + * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_CLKP CLKP selected as LPTIM2 clock + * @retval None + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_PLL2P PLL2P selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_PLL3R PLL3R selected as LPTIM2 clock (*) + * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_CLKP CLKP selected as LPTIM2 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM2SEL))) + +#if defined(LPTIM3) +/** @brief Macro to configure the LPTIM3 clock (LPTIM3CLK). + * + * @param __LPTIM3_CLKSOURCE__ specifies the LPTIM3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK3 PCLK3 selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_PLL2P PLL2P selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_PLL3R PLL3R selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_CLKP CLKP selected as LPTIM3 clock + * @retval None + */ +#define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM3SEL, (uint32_t)(__LPTIM3_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK3 PCLK3 selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_PLL2P PLL2P selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_PLL3R PLL3R selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock + * @arg @ref RCC_LPTIM3CLKSOURCE_CLKP CLKP selected as LPTIM3 clock + */ +#define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM3SEL))) +#endif /* LPTIM3 */ + +#if defined(LPTIM4) +/** @brief Macro to configure the LPTIM4 clock (LPTIM4CLK). + * + * @param __LPTIM4_CLKSOURCE__ specifies the LPTIM4 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM4CLKSOURCE_PCLK3 PCLK3 selected as LPTIM4 clock + * @arg @ref RCC_LPTIM4CLKSOURCE_PLL2P PLL2P selected as LPTIM4 clock + * @arg @ref RCC_LPTIM4CLKSOURCE_PLL3R PLL3R selected as LPTIM4 clock + * @arg @ref RCC_LPTIM4CLKSOURCE_LSE LSE selected as LPTIM4 clock + * @arg @ref RCC_LPTIM4CLKSOURCE_LSI LSI selected as LPTIM4 clock + * @arg @ref RCC_LPTIM4CLKSOURCE_CLKP CLKP selected as LPTIM4 clock + * @retval None + */ +#define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM4SEL, (uint32_t)(__LPTIM4_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM4 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM4CLKSOURCE_PCLK3 PCLK3 selected as LPTIM4 clock + * @arg @ref RCC_LPTIM4CLKSOURCE_PLL2P PLL2P selected as LPTIM4 clock + * @arg @ref RCC_LPTIM4CLKSOURCE_PLL3R PLL3R selected as LPTIM4 clock + * @arg @ref RCC_LPTIM4CLKSOURCE_LSE LSE selected as LPTIM4 clock + * @arg @ref RCC_LPTIM4CLKSOURCE_LSI LSI selected as LPTIM4 clock + * @arg @ref RCC_LPTIM4CLKSOURCE_CLKP CLKP selected as LPTIM4 clock + */ +#define __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM4SEL))) +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +/** @brief Macro to configure the LPTIM5 clock (LPTIM5CLK). + * + * @param __LPTIM5_CLKSOURCE__ specifies the LPTIM5 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM5CLKSOURCE_PCLK3 PCLK3 selected as LPTIM5 clock + * @arg @ref RCC_LPTIM5CLKSOURCE_PLL2P PLL2P selected as LPTIM5 clock + * @arg @ref RCC_LPTIM5CLKSOURCE_PLL3R PLL3R selected as LPTIM5 clock + * @arg @ref RCC_LPTIM5CLKSOURCE_LSE LSE selected as LPTIM5 clock + * @arg @ref RCC_LPTIM5CLKSOURCE_LSI LSI selected as LPTIM5 clock + * @arg @ref RCC_LPTIM5CLKSOURCE_CLKP CLKP selected as LPTIM5 clock + * @retval None + */ +#define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM5SEL, (uint32_t)(__LPTIM5_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM5 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM5CLKSOURCE_PCLK3 PCLK3 selected as LPTIM5 clock + * @arg @ref RCC_LPTIM5CLKSOURCE_PLL2P PLL2P selected as LPTIM5 clock + * @arg @ref RCC_LPTIM5CLKSOURCE_PLL3R PLL3R selected as LPTIM5 clock + * @arg @ref RCC_LPTIM5CLKSOURCE_LSE LSE selected as LPTIM5 clock + * @arg @ref RCC_LPTIM5CLKSOURCE_LSI LSI selected as LPTIM5 clock + * @arg @ref RCC_LPTIM5CLKSOURCE_CLKP CLKP selected as LPTIM5 clock + */ +#define __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM5SEL))) +#endif /* LPTIM5 */ + +#if defined(LPTIM6) +/** @brief Macro to configure the LPTIM6 clock (LPTIM6CLK). + * + * @param __LPTIM6_CLKSOURCE__ specifies the LPTIM6 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM6CLKSOURCE_PCLK3 PCLK3 selected as LPTIM6 clock + * @arg @ref RCC_LPTIM6CLKSOURCE_PLL2P PLL2P selected as LPTIM6 clock + * @arg @ref RCC_LPTIM6CLKSOURCE_PLL3R PLL3R selected as LPTIM6 clock + * @arg @ref RCC_LPTIM6CLKSOURCE_LSE LSE selected as LPTIM6 clock + * @arg @ref RCC_LPTIM6CLKSOURCE_LSI LSI selected as LPTIM6 clock + * @arg @ref RCC_LPTIM6CLKSOURCE_CLKP CLKP selected as LPTIM6 clock + * @retval None + */ +#define __HAL_RCC_LPTIM6_CONFIG(__LPTIM6_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM6SEL, (uint32_t)(__LPTIM6_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM6 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM6CLKSOURCE_PCLK3 PCLK3 selected as LPTIM6 clock + * @arg @ref RCC_LPTIM6CLKSOURCE_PLL2P PLL2P selected as LPTIM6 clock + * @arg @ref RCC_LPTIM6CLKSOURCE_PLL3R PLL3R selected as LPTIM6 clock + * @arg @ref RCC_LPTIM6CLKSOURCE_LSE LSE selected as LPTIM6 clock + * @arg @ref RCC_LPTIM6CLKSOURCE_LSI LSI selected as LPTIM6 clock + * @arg @ref RCC_LPTIM6CLKSOURCE_CLKP CLKP selected as LPTIM6 clock + */ +#define __HAL_RCC_GET_LPTIM6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM6SEL))) +#endif /* LPTIM6 */ + +/** @brief macro to configure the SPI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PLL1Q PLL1Q selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_PLL2P PLL2P selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_PLL3P PLL3P selected as SPI1 clock (*) + * @arg RCC_SPI1CLKSOURCE_PIN External Clock selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_CLKP CLKP selected as SPI1 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_SPI1_CONFIG(__SPI1CLKSource__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI1SEL, (uint32_t)(__SPI1CLKSource__)) + +/** @brief macro to get the SPI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PLL1Q PLL1Q selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_PLL2P PLL2P selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_PLL3P PLL3P selected as SPI1 clock (*) + * @arg RCC_SPI1CLKSOURCE_PIN External Clock selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_CLKP CLKP selected as SPI1 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI1SEL))) + +/** @brief macro to configure the SPI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PLL1Q PLL1Q selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_PLL2P PLL2P selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_PLL3P PLL3P selected as SPI2 clock (*) + * @arg RCC_SPI2CLKSOURCE_PIN External Clock selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_CLKP CLKP selected as SPI2 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_SPI2_CONFIG(__SPI2CLKSource__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI2SEL, (uint32_t)(__SPI2CLKSource__)) + +/** @brief macro to get the SPI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PLL1Q PLL1Q selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_PLL2P PLL2P selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_PLL3P PLL3P selected as SPI2 clock (*) + * @arg RCC_SPI2CLKSOURCE_PIN External Clock selected as SPI2 clock + * @arg RCC_SPI2CLKSOURCE_CLKP CLKP selected as SPI2 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI2SEL))) + +/** @brief macro to configure the SPI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI3CLKSOURCE_PLL1Q PLL1Q used as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_PLL2P PLL2P used as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_PLL3P PLL3P used as SPI3 clock (*) + * @arg RCC_SPI3CLKSOURCE_PIN External Clock used as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_CLKP CLKP used as SPI3 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_SPI3_CONFIG(__SPI3CLKSource__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL, (uint32_t)(__SPI3CLKSource__)) + +/** @brief macro to get the SPI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI3CLKSOURCE_PLL1Q PLL1Q used as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_PLL2P PLL2P used as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_PLL3P PLL3P used as SPI3 clock (*) + * @arg RCC_SPI3CLKSOURCE_PIN External Clock used as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_CLKP CLKP used as SPI3 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL))) + +#if defined(SPI4) +/** @brief macro to configure the SPI4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI4CLKSOURCE_PCLK2 PCLK2 used as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_PLL2Q PLL2Q used as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_PLL3Q PLL3Q used as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_HSI HSI used as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_CSI CSI Clock used as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_HSE HSE Clock used as SPI4 clock + */ +#define __HAL_RCC_SPI4_CONFIG(__SPI4CLKSource__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI4SEL, (uint32_t)(__SPI4CLKSource__)) + +/** @brief macro to get the SPI4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI4CLKSOURCE_PCLK2 PCLK2 used as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_PLL2Q PLL2Q used as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_PLL3Q PLL3Q used as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_HSI HSI used as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_CSI CSI used as SPI4 clock + * @arg RCC_SPI4CLKSOURCE_HSE HSE used as SPI4 clock + */ +#define __HAL_RCC_GET_SPI4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI4SEL))) +#endif /* SPI4 */ + +#if defined(SPI5) +/** @brief macro to configure the SPI5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI5CLKSOURCE_PCLK3 PCLK3 used as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_PLL2Q PLL2Q used as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_PLL3Q PLL3Q used as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_HSI HSI used as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_CSI CSI Clock used as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_HSE HSE Clock used as SPI5 clock + */ +#define __HAL_RCC_SPI5_CONFIG(__SPI5CLKSource__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI5SEL, (uint32_t)(__SPI5CLKSource__)) + +/** @brief macro to get the SPI5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI5CLKSOURCE_PCLK3 PCLK3 used as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_PLL2Q PLL2Q used as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_PLL3Q PLL3Q used as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_HSI HSI used as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_CSI CSI used as SPI5 clock + * @arg RCC_SPI5CLKSOURCE_HSE HSE used as SPI5 clock + */ +#define __HAL_RCC_GET_SPI5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI5SEL))) +#endif /* SPI5 */ + +#if defined(SPI6) +/** @brief macro to configure the SPI6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI6CLKSOURCE_PCLK2 PCLK2 used as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_PLL2Q PLL2Q used as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_PLL3Q PLL3Q used as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_HSI HSI used as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_CSI CSI used as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_HSE HSE used as SPI6 clock + */ +#define __HAL_RCC_SPI6_CONFIG(__SPI6CLKSource__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI6SEL, (uint32_t)(__SPI6CLKSource__)) + +/** @brief macro to get the SPI6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI6CLKSOURCE_PCLK2 PCLK2 used as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_PLL2Q PLL2Q used as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_PLL3Q PLL3Q used as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_HSI HSI used as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_CSI CSI used as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_HSE HSE used as SPI6 clock + */ +#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI6SEL))) +#endif /* SPI6 */ + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * + * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_PLL3R PLL3R selected as I2C1 clock (*) + * @arg @ref RCC_I2C1CLKSOURCE_PLL2R PLL2R selected as I2C1 clock (**) + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_CSI CSI selected as I2C1 clock + * @retval None + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (**) : For stm32h503xx family line. + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_PLL3R PLL3R selected as I2C1 clock (*) + * @arg @ref RCC_I2C1CLKSOURCE_PLL2R PLL2R selected as I2C1 clock (**) + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_CSI CSI selected as I2C1 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (**) : For stm32h503xx family line. + */ +#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C1SEL))) + +/** @brief Macro to configure the I2C2 clock (I2C2CLK). + * + * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_PLL3R PLL3R selected as I2C2 clock (*) + * @arg @ref RCC_I2C2CLKSOURCE_PLL2R PLL2R selected as I2C2 clock (**) + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_CSI CSI selected as I2C2 clock + * @retval None + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (**) : For stm32h503xx family line. + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) + +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_PLL3R PLL3R selected as I2C2 clock (*) + * @arg @ref RCC_I2C2CLKSOURCE_PLL2R PLL2R selected as I2C2 clock (**) + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_CSI CSI selected as I2C2 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (**) : For stm32h503xx family line. + */ +#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C2SEL))) + +#if defined(I2C3) +/** @brief Macro to configure the I2C3 clock (I2C3CLK). + * + * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 PCLK3 selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_PLL3R PLL3R selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_CSI CSI selected as I2C3 clock + * @retval None + */ +#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) + +/** @brief Macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 PCLK3 selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_PLL3R PLL3R selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_CSI CSI selected as I2C3 clock + */ +#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C3SEL))) +#endif /* I2C3 */ + +#if defined(I2C4) +/** @brief Macro to configure the I2C4 clock (I2C4CLK). + * + * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C4CLKSOURCE_PCLK3 PCLK3 selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_PLL3R PLL3R selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_CSI CSI selected as I2C4 clock + * @retval None + */ +#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) + +/** @brief Macro to get the I2C4 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C4CLKSOURCE_PCLK3 PCLK3 selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_PLL3R PLL3R selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock + * @arg @ref RCC_I2C4CLKSOURCE_CSI CSI selected as I2C4 clock + */ +#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C4SEL))) +#endif /* I2C4 */ + +/** @brief Macro to configure the I3C1 clock (I3C1CLK). + * + * @param __I3C1_CLKSOURCE__ specifies the I3C1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I3C1CLKSOURCE_PCLK1 PCLK1 selected as I3C1 clock + * @arg @ref RCC_I3C1CLKSOURCE_PLL3R PLL3R selected as I3C1 clock (*) + * @arg @ref RCC_I3C1CLKSOURCE_PLL2R PLL2R selected as I3C1 clock (**) + * @arg @ref RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock + * @retval None + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (**) : For stm32h503xx family line. + */ +#define __HAL_RCC_I3C1_CONFIG(__I3C1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I3C1SEL, (uint32_t)(__I3C1_CLKSOURCE__)) + +/** @brief Macro to get the I3C1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I3C1CLKSOURCE_PCLK1 PCLK1 selected as I3C1 clock + * @arg @ref RCC_I3C1CLKSOURCE_PLL3R PLL3R selected as I3C1 clock (*) + * @arg @ref RCC_I3C1CLKSOURCE_PLL2R PLL2R selected as I3C1 clock (**) + * @arg @ref RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (**) : For stm32h503xx family line. + */ +#define __HAL_RCC_GET_I3C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I3C1SEL))) + +#if defined(I3C2) +/** @brief Macro to configure the I3C2 clock (I3C2CLK). + * + * @param __I3C2_CLKSOURCE__ specifies the I3C2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I3C2CLKSOURCE_PCLK3 PCLK3 selected as I3C2 clock + * @arg @ref RCC_I3C2CLKSOURCE_PLL3R PLL3R selected as I3C2 clock (*) + * @arg @ref RCC_I3C2CLKSOURCE_PLL2R PLL2R selected as I3C2 clock (**) + * @arg @ref RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock + * @arg @ref RCC_I3C2CLKSOURCE_CSI CSI selected as I3C2 clock (*) + * + * @retval None + * + * (*) : Not available for all stm32h5xxxx family lines. + * (**) : Not available for stm32h5exxx and stm32h5fxxx family lines. + */ +#define __HAL_RCC_I3C2_CONFIG(__I3C2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I3C2SEL, (uint32_t)(__I3C2_CLKSOURCE__)) + +/** @brief Macro to get the I3C2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I3C2CLKSOURCE_PCLK3 PCLK3 selected as I3C2 clock + * @arg @ref RCC_I3C2CLKSOURCE_PLL3R PLL3R selected as I3C2 clock (*) + * @arg @ref RCC_I3C2CLKSOURCE_PLL2R PLL2R selected as I3C2 clock (**) + * @arg @ref RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock + * @arg @ref RCC_I3C2CLKSOURCE_CSI CSI selected as I3C2 clock (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * (**) : Not available for stm32h5exxx and stm32h5fxxx family lines. + */ +#define __HAL_RCC_GET_I3C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I3C2SEL))) +#endif /* I3C2 */ + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_PLL2Q PLL2Q selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_PLL3Q PLL3Q selected as USART1 clock (*) + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_CSI CSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + * @retval None + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_PLL2Q PLL2Q selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_PLL3Q PLL3Q selected as USART1 clock (*) + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_CSI CSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL))) + +/** @brief Macro to configure the USART2 clock (USART2CLK). + * + * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK2 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_PLL2Q PLL2Q selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_PLL3Q PLL3Q selected as USART2 clock (*) + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_CSI CSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + * @retval None + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) + +/** @brief Macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK2 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_PLL2Q PLL2Q selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_PLL3Q PLL3Q selected as USART2 clock (*) + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_CSI CSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL))) + +/** @brief Macro to configure the USART3 clock (USART3CLK). + * + * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK2 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_PLL2Q PLL2Q selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_PLL3Q PLL3Q selected as USART3 clock (*) + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_CSI CSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + * @retval None + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) + +/** @brief Macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK2 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_PLL2Q PLL2Q selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_PLL3Q PLL3Q selected as USART3 clock (*) + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_CSI CSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART3SEL))) + +#if defined(UART4) +/** @brief Macro to configure the UART4 clock (UART4CLK). + * + * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_PLL2Q PLL2Q Clock selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_PLL3Q PLL3Q Clock selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_CSI CSI selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock + * @retval None + */ +#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) + +/** @brief Macro to get the UART4 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_PLL2Q PLL2Q Clock selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_PLL3Q PLL3Q Clock selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_CSI CSI selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock + */ +#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART4SEL))) +#endif /* UART4 */ + +#if defined(UART5) +/** @brief Macro to configure the UART5 clock (UART5CLK). + * + * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_PLL2Q PLL2Q Clock selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_PLL3Q PLL3Q Clock selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_CSI CSI selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock + * @retval None + */ +#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) + +/** @brief Macro to get the UART5 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_PLL2Q PLL2Q Clock selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_PLL3Q PLL3Q Clock selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_CSI CSI selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock + */ +#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL))) +#endif /* UART5 */ + +#if defined(USART6) +/** @brief Macro to configure the USART6 clock (USART6CLK). + * + * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK2 selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_PLL2Q PLL2Q selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_PLL3Q PLL3Q selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_CSI CSI selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock + * @retval None + */ +#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) + +/** @brief Macro to get the USART6 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_PLL2Q PLL2Q selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_PLL3Q PLL3Q selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_CSI CSI selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock + */ +#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART6SEL))) +#endif /* USART6 */ + +#if defined(UART7) +/** @brief Macro to configure the UART7 clock (UART7CLK). + * + * @param __UART7_CLKSOURCE__ specifies the UART7 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock + * @arg @ref RCC_UART7CLKSOURCE_PLL2Q PLL2Q selected as UART7 clock + * @arg @ref RCC_UART7CLKSOURCE_PLL3Q PLL3Q selected as UART7 clock + * @arg @ref RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock + * @arg @ref RCC_UART7CLKSOURCE_CSI CSI selected as UART7 clock + * @arg @ref RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock + * @retval None + */ +#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) + +/** @brief Macro to get the UART7 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock + * @arg @ref RCC_UART7CLKSOURCE_PLL2Q PLL2Q selected as UART7 clock + * @arg @ref RCC_UART7CLKSOURCE_PLL3Q PLL3Q selected as UART7 clock + * @arg @ref RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock + * @arg @ref RCC_UART7CLKSOURCE_CSI CSI selected as UART7 clock + * @arg @ref RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock + */ +#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART7SEL))) +#endif /* UART5 */ + +#if defined(UART8) +/** @brief Macro to configure the UART8 clock (UART8CLK). + * + * @param __UART8_CLKSOURCE__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock + * @arg @ref RCC_UART8CLKSOURCE_PLL2Q PLL2Q selected as UART8 clock + * @arg @ref RCC_UART8CLKSOURCE_PLL3Q PLL3Q selected as UART8 clock + * @arg @ref RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock + * @arg @ref RCC_UART8CLKSOURCE_CSI CSI selected as UART8 clock + * @arg @ref RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock + * @retval None + */ +#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) + +/** @brief Macro to get the UART8 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock + * @arg @ref RCC_UART8CLKSOURCE_PLL2Q PLL2Q selected as UART8 clock + * @arg @ref RCC_UART8CLKSOURCE_PLL3Q PLL3Q selected as UART8 clock + * @arg @ref RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock + * @arg @ref RCC_UART8CLKSOURCE_CSI CSI selected as UART8 clock + * @arg @ref RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock + */ +#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART8SEL))) +#endif /* UART8 */ + +#if defined(UART9) +/** @brief Macro to configure the UART9 clock (UART9CLK). + * + * @param __UART9_CLKSOURCE__ specifies the UART9 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_UART9CLKSOURCE_PCLK1 PCLK1 selected as UART9 clock + * @arg @ref RCC_UART9CLKSOURCE_PLL2Q PLL2Q selected as UART9 clock + * @arg @ref RCC_UART9CLKSOURCE_PLL3Q PLL3Q selected as UART9 clock + * @arg @ref RCC_UART9CLKSOURCE_HSI HSI selected as UART9 clock + * @arg @ref RCC_UART9CLKSOURCE_CSI CSI selected as UART9 clock + * @arg @ref RCC_UART9CLKSOURCE_LSE LSE selected as UART9 clock + * @retval None + */ +#define __HAL_RCC_UART9_CONFIG(__UART9_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART9SEL, (uint32_t)(__UART9_CLKSOURCE__)) + +/** @brief Macro to get the UART9 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_UART9CLKSOURCE_PCLK1 PCLK1 selected as UART9 clock + * @arg @ref RCC_UART9CLKSOURCE_PLL2Q PLL2Q selected as UART9 clock + * @arg @ref RCC_UART9CLKSOURCE_PLL3Q PLL3Q selected as UART9 clock + * @arg @ref RCC_UART9CLKSOURCE_HSI HSI selected as UART9 clock + * @arg @ref RCC_UART9CLKSOURCE_CSI CSI selected as UART9 clock + * @arg @ref RCC_UART9CLKSOURCE_LSE LSE selected as UART9 clock + */ +#define __HAL_RCC_GET_UART9_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART9SEL))) +#endif /* UART9 */ + +#if defined(USART10) +/** @brief Macro to configure the USART10 clock (USART10CLK). + * + * @param __USART10_CLKSOURCE__ specifies the USART10 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART10CLKSOURCE_PCLK1 PCLK1 selected as USART10 clock + * @arg @ref RCC_USART10CLKSOURCE_PLL2Q PLL2Q selected as USART10 clock + * @arg @ref RCC_USART10CLKSOURCE_PLL3Q PLL3Q selected as USART10 clock + * @arg @ref RCC_USART10CLKSOURCE_HSI HSI selected as USART10 clock + * @arg @ref RCC_USART10CLKSOURCE_CSI CSI selected as USART10 clock + * @arg @ref RCC_USART10CLKSOURCE_LSE LSE selected as USART10 clock + * @retval None + */ +#define __HAL_RCC_USART10_CONFIG(__USART10_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART10SEL, (uint32_t)(__USART10_CLKSOURCE__)) + +/** @brief Macro to get the USART10 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART10CLKSOURCE_PCLK1 PCLK1 selected as USART10 clock + * @arg @ref RCC_USART10CLKSOURCE_PLL2Q PLL2Q selected as USART10 clock + * @arg @ref RCC_USART10CLKSOURCE_PLL3Q PLL3Q selected as USART10 clock + * @arg @ref RCC_USART10CLKSOURCE_HSI HSI selected as USART10 clock + * @arg @ref RCC_USART10CLKSOURCE_CSI CSI selected as USART10 clock + * @arg @ref RCC_USART10CLKSOURCE_LSE LSE selected as USART10 clock + */ +#define __HAL_RCC_GET_USART10_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART10SEL))) +#endif /* USART10 */ + +#if defined(USART11) +/** @brief Macro to configure the USART11 clock (USART11CLK). + * + * @param __USART11_CLKSOURCE__ specifies the USART11 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART11CLKSOURCE_PCLK1 PCLK1 selected as USART11 clock + * @arg @ref RCC_USART11CLKSOURCE_PLL2Q PLL2Q selected as USART11 clock + * @arg @ref RCC_USART11CLKSOURCE_PLL3Q PLL3Q selected as USART11 clock + * @arg @ref RCC_USART11CLKSOURCE_HSI HSI selected as USART11 clock + * @arg @ref RCC_USART11CLKSOURCE_CSI CSI selected as USART11 clock + * @arg @ref RCC_USART11CLKSOURCE_LSE LSE selected as USART11 clock + * @retval None + */ +#define __HAL_RCC_USART11_CONFIG(__USART11_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USART11SEL, (uint32_t)(__USART11_CLKSOURCE__)) + +/** @brief Macro to get the USART11 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART11CLKSOURCE_PCLK1 PCLK1 selected as USART11 clock + * @arg @ref RCC_USART11CLKSOURCE_PLL2Q PLL2Q selected as USART11 clock + * @arg @ref RCC_USART11CLKSOURCE_PLL3Q PLL3Q selected as USART11 clock + * @arg @ref RCC_USART11CLKSOURCE_HSI HSI selected as USART11 clock + * @arg @ref RCC_USART11CLKSOURCE_CSI CSI selected as USART11 clock + * @arg @ref RCC_USART11CLKSOURCE_LSE LSE selected as USART11 clock + */ +#define __HAL_RCC_GET_USART11_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USART11SEL))) +#endif /* USART11 */ + +#if defined(UART12) +/** @brief Macro to configure the UART12 clock (UART12CLK). + * + * @param __UART12_CLKSOURCE__ specifies the UART12 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_UART12CLKSOURCE_PCLK1 PCLK1 selected as UART12 clock + * @arg @ref RCC_UART12CLKSOURCE_PLL2Q PLL2Q selected as UART12 clock + * @arg @ref RCC_UART12CLKSOURCE_PLL3Q PLL3Q selected as UART12 clock + * @arg @ref RCC_UART12CLKSOURCE_HSI HSI selected as UART12 clock + * @arg @ref RCC_UART12CLKSOURCE_CSI CSI selected as UART12 clock + * @arg @ref RCC_UART12CLKSOURCE_LSE LSE selected as UART12 clock + * @retval None + */ +#define __HAL_RCC_UART12_CONFIG(__UART12_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_UART12SEL, (uint32_t)(__UART12_CLKSOURCE__)) + +/** @brief Macro to get the UART12 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_UART12CLKSOURCE_PCLK1 PCLK1 selected as UART12 clock + * @arg @ref RCC_UART12CLKSOURCE_PLL2Q PLL2Q selected as UART12 clock + * @arg @ref RCC_UART12CLKSOURCE_PLL3Q PLL3Q selected as UART12 clock + * @arg @ref RCC_UART12CLKSOURCE_HSI HSI selected as UART12 clock + * @arg @ref RCC_UART12CLKSOURCE_CSI CSI selected as UART12 clock + * @arg @ref RCC_UART12CLKSOURCE_LSE LSE selected as UART12 clock + */ +#define __HAL_RCC_GET_UART12_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_UART12SEL))) +#endif /* UART12 */ + +/** @brief Macro to configure the LPUART1 clock (LPUART1CLK). + * + * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_PLL2Q PLL2Q selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_PLL3Q PLL3Q selected as LPUART1 clock (*) + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_CSI CSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + * @retval None + */ +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) + +/** @brief Macro to get the LPUART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_PLL2Q PLL2Q selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_PLL3Q PLL3Q selected as LPUART1 clock (*) + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_CSI CSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL))) + +#if defined(OCTOSPI1) +/** @brief Macro to configure the OctoSPI clock. + * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_OSPICLKSOURCE_HCLK HCLK selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_PLL1Q PLL1Q divider clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_PLL2R PLL2R divider clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_CLKP CLKP selected as OctoSPI clock + * @retval None + */ +#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OCTOSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) + +/** @brief Macro to get the OctoSPI clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_OSPICLKSOURCE_HCLK HCLK selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_PLL1Q PLL1Q divider clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_PLL2R PLL2R divider clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_CLKP CLKP selected as OctoSPI clock + */ +#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_OCTOSPISEL))) +#endif /* OCTOSPI1 */ + +#if defined(SDMMC1) +/** @brief Macro to configure the SDMMC1 clock (SDMMCCLK). + * + * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SDMMC1CLKSOURCE_PLL1Q PLL1Q selected as SDMMC1 clock + * @arg RCC_SDMMC1CLKSOURCE_PLL2R PLL2R selected as SDMMC1 clock + */ +#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) + +/** @brief macro to get the SDMMC1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC1CLKSOURCE_PLL1Q PLL1Q selected as SDMMC1 clock + * @arg RCC_SDMMC1CLKSOURCE_PLL2R PLL2R selected as SDMMC1 clock + */ +#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SDMMC1SEL))) +#endif /* SDMMC1 */ + +#if defined(SDMMC2) +/** @brief Macro to configure the SDMMC2 clock (SDMMCCLK). + * + * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_PLL1Q PLL1Q selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_PLL2R PLL2R selected as SDMMC2 clock + */ +#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) + +/** @brief macro to get the SDMMC2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_PLL1Q PLL1Q selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_PLL2R PLL2R selected as SDMMC2 clock + */ +#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SDMMC2SEL))) +#endif /*SDMMC2*/ + +/** @brief macro to configure the RNG clock (RNGCLK). + * + * @param __RNGCLKSource__: specifies the RNG clock source. + * This parameter can be one of the following values: + * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock + * @arg RCC_RNGCLKSOURCE_PLL1Q: PLL1Q selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock + */ +#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_RNGSEL, (uint32_t)(__RNGCLKSource__)) + +/** @brief macro to get the RNG clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock + * @arg RCC_RNGCLKSOURCE_PLL1Q: PLL1Q selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock + */ +#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_RNGSEL))) + +#if defined(SAI1) +/** + * @brief Macro to configure the SAI1 clock source. + * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SAI1CLKSOURCE_PLL1Q PLL1Q selected as SAI1 clock + * @arg @ref RCC_SAI1CLKSOURCE_PLL2P PLL2Pselected as SAI1 clock + * @arg @ref RCC_SAI1CLKSOURCE_PLL3P PLL3P selected as SAI1 clock + * @arg @ref RCC_SAI1CLKSOURCE_PIN External clock selected as SAI1 clock + * @arg @ref RCC_SAI1CLKSOURCE_CLKP CLKP selected as SAI1 clock + * @retval None + */ +#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) + +/** @brief Macro to get the SAI1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_SAI1CLKSOURCE_PLL1Q PLL1Q selected as SAI1 clock + * @arg @ref RCC_SAI1CLKSOURCE_PLL2P PLL2P selected as SAI1 clock + * @arg @ref RCC_SAI1CLKSOURCE_PLL3P PLL3P selected as SAI1 clock + * @arg @ref RCC_SAI1CLKSOURCE_PIN External clock selected as SAI1 clock + * @arg @ref RCC_SAI1CLKSOURCE_CLKP CLKP selected as SAI1 clock + */ +#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_SAI1SEL))) +#endif /* SAI1 */ + +#if defined(SAI2) +/** + * @brief Macro to configure the SAI2 clock source. + * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SAI2CLKSOURCE_PLL1Q PLL1Q selected as SAI2 clock + * @arg @ref RCC_SAI2CLKSOURCE_PLL2P PLL2P selected as SAI2 clock + * @arg @ref RCC_SAI2CLKSOURCE_PLL3P PLL3P selected as SAI2 clock + * @arg @ref RCC_SAI2CLKSOURCE_PIN External clock selected as SAI2 clock + * @arg @ref RCC_SAI2CLKSOURCE_CLKP CLKP selected as SAI2 clock + * @retval None + */ +#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) + +/** @brief Macro to get the SAI2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_SAI2CLKSOURCE_PLL1Q PLL1Q selected as SAI2 clock + * @arg @ref RCC_SAI2CLKSOURCE_PLL2P PLL2P selected as SAI2 clock + * @arg @ref RCC_SAI2CLKSOURCE_PLL3P PLL3P selected as SAI2 clock + * @arg @ref RCC_SAI2CLKSOURCE_PIN External clock selected as SAI2 clock + * @arg @ref RCC_SAI2CLKSOURCE_CLKP CLKP selected as SAI2 clock + */ +#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_SAI2SEL))) +#endif /* SAI2 */ + +/** @brief Macro to configure the CLKP : Oscillator clock for peripheral + * @param __CLKPSource__ specifies Oscillator clock for peripheral + * This parameter can be one of the following values: + * @arg RCC_CLKPSOURCE_HSI HSI oscillator selected as clock for peripheral + * @arg RCC_CLKPSOURCE_CSI CSI oscillator selected as clock for peripheral + * @arg RCC_CLKPSOURCE_HSE HSE oscillator selected as clock for peripheral + */ +#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CKERPSEL, (uint32_t)(__CLKPSource__)) + +/** @brief Macro to get the oscillator clock for peripheral clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_CLKPSOURCE_HSI HSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_CSI CSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_HSE HSE selected Oscillator clock for peripheral + */ +#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_CKERPSEL))) + +#if defined(CEC) +/** @brief Macro to configure the CEC clock (CECCLK) + * @param __CECCLKSource__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSI LSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_CSI_DIV122 CSI Divided by 122 selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CECSEL, (uint32_t)(__CECCLKSource__)) + +/** @brief Macro to get the CEC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_CSI_DIV122: CSI Divided by 122 selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_CECSEL))) +#endif /* CEC */ + +#if defined(USB_DRD_FS) +/** @brief Macro to configure the USB clock (USBCLK). + * @param __USBCLKSource__ specifies the USB clock source. + * This parameter can be one of the following values: + * @arg RCC_USBCLKSOURCE_PLL1Q PLL1Q selected as USB clock + * @arg RCC_USBCLKSOURCE_PLL3Q PLL3Q selected as USB clock (*) + * @arg RCC_USBCLKSOURCE_PLL2Q PLL2Q selected as USB clock (**) + * @arg RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (**) : For stm32h503xx family line. + */ +#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_USBSEL, (uint32_t)(__USBCLKSource__)) + +/** @brief Macro to get the USB clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USBCLKSOURCE_PLL1Q PLL1Q selected as USB clock + * @arg RCC_USBCLKSOURCE_PLL3Q PLL3Q selected as USB clock (*) + * @arg RCC_USBCLKSOURCE_PLL2Q PLL2Q selected as USB clock (**) + * @arg RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (**) : For stm32h503xx family line. + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_USBSEL))) +#endif /* USB_DRD_FS */ + +#if defined(PLAY1) +/** @brief Macro to configure the PLAY1 clock (PLAY1CLK). + * @param __PLAY1CLKSource__ specifies the PLAY1 clock source. + * This parameter can be one of the following values: + * @arg RCC_PLAY1CLKSOURCE_PCLK3 PCLK3 selected as PLAY1 clock + * @arg RCC_PLAY1CLKSOURCE_PLL2P PLL2P selected as PLAY1 clock + * @arg RCC_PLAY1CLKSOURCE_PLL3R PLL3R selected as PLAY1 clock + * @arg RCC_PLAY1CLKSOURCE_LSE LSE selected as PLAY1 clock + * @arg RCC_PLAY1CLKSOURCE_LSI LSI selected as PLAY1 clock + * @arg RCC_PLAY1CLKSOURCE_CLKP CLKP selected as PLAY1 clock + * + */ +#define __HAL_RCC_PLAY1_CONFIG(__PLAY1CLKSource__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_PLAY1SEL, (uint32_t)(__PLAY1CLKSource__)) + +/** @brief Macro to get the PLAY1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_PLAY1CLKSOURCE_PCLK3 PCLK3 selected as PLAY1 clock + * @arg RCC_PLAY1CLKSOURCE_PLL2P PLL2P selected as PLAY1 clock + * @arg RCC_PLAY1CLKSOURCE_PLL3R PLL3R selected as PLAY1 clock + * @arg RCC_PLAY1CLKSOURCE_LSE LSE selected as PLAY1 clock + * @arg RCC_PLAY1CLKSOURCE_LSI LSI selected as PLAY1 clock + * @arg RCC_PLAY1CLKSOURCE_CLKP CLKP selected as PLAY1 clock + * + */ +#define __HAL_RCC_GET_PLAY1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_PLAY1SEL))) + +/** @brief Macro to configure the PLAY1 kernel clock divider. + * @param __PLAY1_CLKDIV__ specifies the PLAY1 digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLAY1_CLK_DIV_1 PLAY1 kernel clock divided by 1 + * @arg @ref RCC_PLAY1_CLK_DIV_2 PLAY1 kernel clock divided by 2 + * @arg @ref RCC_PLAY1_CLK_DIV_4 PLAY1 kernel clock divided by 4 + * @arg @ref RCC_PLAY1_CLK_DIV_8 PLAY1 kernel clock divided by 8 + * @arg @ref RCC_PLAY1_CLK_DIV_16 PLAY1 kernel clock divided by 16 + * @arg @ref RCC_PLAY1_CLK_DIV_32 PLAY1 kernel clock divided by 32 + * @arg @ref RCC_PLAY1_CLK_DIV_64 PLAY1 kernel clock divided by 64 + * @arg @ref RCC_PLAY1_CLK_DIV_128 PLAY1 kernel clock divided by 128 + * @arg @ref RCC_PLAY1_CLK_DIV_256 PLAY1 kernel clock divided by 256 + * @arg @ref RCC_PLAY1_CLK_DIV_512 PLAY1 kernel clock divided by 512 + * @arg @ref RCC_PLAY1_CLK_DIV_1024 PLAY1 kernel clock divided by 1024 + * @arg @ref RCC_PLAY1_CLK_DIV_2048 PLAY1 kernel clock divided by 2048 + * @arg @ref RCC_PLAY1_CLK_DIV_4096 PLAY1 kernel clock divided by 4096 + * @arg @ref RCC_PLAY1_CLK_DIV_8192 PLAY1 kernel clock divided by 8192 + * @arg @ref RCC_PLAY1_CLK_DIV_16384 PLAY1 kernel clock divided by 16384 + * @arg @ref RCC_PLAY1_CLK_DIV_32768 PLAY1 kernel clock divided by 32768 + * @retval None + */ +#define __HAL_RCC_PLAY1_DIV_CONFIG(__PLAY1_CLKDIV__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_PLAY1DIV, (__PLAY1_CLKDIV__)) + +/** @brief Macro to get the PLAY1 kernel clock divider. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_PLAY1_CLK_DIV_1 PLAY1 kernel clock divided by 1 + * @arg @ref RCC_PLAY1_CLK_DIV_2 PLAY1 kernel clock divided by 2 + * @arg @ref RCC_PLAY1_CLK_DIV_4 PLAY1 kernel clock divided by 4 + * @arg @ref RCC_PLAY1_CLK_DIV_8 PLAY1 kernel clock divided by 8 + * @arg @ref RCC_PLAY1_CLK_DIV_16 PLAY1 kernel clock divided by 16 + * @arg @ref RCC_PLAY1_CLK_DIV_32 PLAY1 kernel clock divided by 32 + * @arg @ref RCC_PLAY1_CLK_DIV_64 PLAY1 kernel clock divided by 64 + * @arg @ref RCC_PLAY1_CLK_DIV_128 PLAY1 kernel clock divided by 128 + * @arg @ref RCC_PLAY1_CLK_DIV_256 PLAY1 kernel clock divided by 256 + * @arg @ref RCC_PLAY1_CLK_DIV_512 PLAY1 kernel clock divided by 512 + * @arg @ref RCC_PLAY1_CLK_DIV_1024 PLAY1 kernel clock divided by 1024 + * @arg @ref RCC_PLAY1_CLK_DIV_2048 PLAY1 kernel clock divided by 2048 + * @arg @ref RCC_PLAY1_CLK_DIV_4096 PLAY1 kernel clock divided by 4096 + * @arg @ref RCC_PLAY1_CLK_DIV_8192 PLAY1 kernel clock divided by 8192 + * @arg @ref RCC_PLAY1_CLK_DIV_16384 PLAY1 kernel clock divided by 16384 + * @arg @ref RCC_PLAY1_CLK_DIV_32768 PLAY1 kernel clock divided by 32768 + */ +#define __HAL_RCC_GET_PLAY1_DIV() READ_BIT(RCC->CCIPR3, RCC_CCIPR3_PLAY1DIV) +#endif /* PLAY1 */ + +#if defined(USB_OTG_FS) +/** @brief Macro to configure the USB_OTG_FS clock (OTGFSCLK). + * @param __OTGFSCLKSource__ specifies the USB_OTG_FS clock source. + * This parameter can be one of the following values: + * @arg RCC_OTGFSCLKSOURCE_PCLK3 PCLK3 selected as USB_OTG_FS clock + * @arg RCC_OTGFSCLKSOURCE_PLL2Q PLL2Q selected as USB_OTG_FS clock + * @arg RCC_OTGFSCLKSOURCE_PLL3Q PLL3Q selected as USB_OTG_FS clock + * @arg RCC_OTGFSCLKSOURCE_CLK48 OTG_HS PHY CLK48 output selected as USB_OTG_FS clock (*) + * + * (*) : Available only on STM32H5E5x/STM32H5F5x when OTG_HS PHY is enabled. + */ +#define __HAL_RCC_OTGFS_CONFIG(__OTGFSCLKSource__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OTGFSSEL, (uint32_t)(__OTGFSCLKSource__)) + +/** @brief Macro to get the USB_OTG_FS clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_OTGFSCLKSOURCE_PCLK3 PCLK3 selected as USB_OTG_FS clock + * @arg RCC_OTGFSCLKSOURCE_PLL2Q PLL2Q selected as USB_OTG_FS clock + * @arg RCC_OTGFSCLKSOURCE_PLL3Q PLL3Q selected as USB_OTG_FS clock + * @arg RCC_OTGFSCLKSOURCE_CLK48 OTG_HS PHY CLK48 output selected as USB_OTG_FS clock (*) + * + * (*) : Available only on STM32H5E5x/STM32H5F5x when OTG_HS PHY is enabled. + */ +#define __HAL_RCC_GET_OTGFS_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_OTGFSSEL))) +#endif /* USB_OTG_FS */ + +#if defined(USB_OTG_HS) +/** @brief Macro to configure the USB_OTG_HS clock (OTGHSCLK). + * @param __OTGHSCLKSource__ specifies the USB_OTG_HS clock source. + * This parameter can be one of the following values: + * @arg RCC_OTGHSCLKSOURCE_HSE HSE selected as USB_OTG_HS clock + * @arg RCC_OTGHSCLKSOURCE_PLL3Q PLL3Q selected as USB_OTG_HS clock + * @arg RCC_OTGHSCLKSOURCE_HSE_DIV2 HSE_DIV2 selected as USB_OTG_HS clock + * @arg RCC_OTGHSCLKSOURCE_PLL1Q_DIV2 PLL1Q_DIV2 selected as USB_OTG_HS clock + * + */ +#define __HAL_RCC_OTGHS_CONFIG(__OTGHSCLKSource__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OTGHSSEL, (uint32_t)(__OTGHSCLKSource__)) + +/** @brief Macro to get the USB_OTG_HS clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_OTGHSCLKSOURCE_HSE HSE selected as USB_OTG_HS clock + * @arg RCC_OTGHSCLKSOURCE_PLL3Q PLL3Q selected as USB_OTG_HS clock + * @arg RCC_OTGHSCLKSOURCE_HSE_DIV2 HSE_DIV2 selected as USB_OTG_HS clock + * @arg RCC_OTGHSCLKSOURCE_PLL1Q_DIV2 PLL1Q_DIV2 selected as USB_OTG_HS clock + * + */ +#define __HAL_RCC_GET_OTGHS_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_OTGHSSEL))) +#endif /* USB_OTG_HS */ + +#if defined(RCC_CCIPR4_OTGPHYREFCKSEL) +/** @brief Macro to configure the OTGPHY clock (OTGPHYCLK). + * @param __OTGPHYCLKSource__ specifies the OTGPHY clock source. + * This parameter can be one of the following values: + * @arg RCC_OTGPHYREFCKCLKSOURCE_16M 16Mhz selected as OTGPHY clock + * @arg RCC_OTGPHYREFCKCLKSOURCE_19_2M 19.2Mhz selected as OTGPHY clock + * @arg RCC_OTGPHYREFCKCLKSOURCE_20M 20Mhz selected as OTGPHY clock + * @arg RCC_OTGPHYREFCKCLKSOURCE_24M 24Mhz selected as OTGPHY clockk + * @arg RCC_OTGPHYREFCKCLKSOURCE_26M 26Mhz selected as OTGPHY clockk + * @arg RCC_OTGPHYREFCKCLKSOURCE_32M 32Mhz selected as OTGPHY clockk + * + */ +#define __HAL_RCC_OTGPHY_CONFIG(__OTGPHYCLKSource__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OTGPHYREFCKSEL, (uint32_t)(__OTGPHYCLKSource__)) + +/** @brief Macro to get the OTGPHY clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_OTGPHYREFCKCLKSOURCE_16M 16Mhz selected as OTGPHY clock + * @arg RCC_OTGPHYREFCKCLKSOURCE_19_2M 19.2Mhz selected as OTGPHY clock + * @arg RCC_OTGPHYREFCKCLKSOURCE_20M 20Mhz selected as OTGPHY clock + * @arg RCC_OTGPHYREFCKCLKSOURCE_24M 24Mhz selected as OTGPHY clockk + * @arg RCC_OTGPHYREFCKCLKSOURCE_26M 26Mhz selected as OTGPHY clockk + * @arg RCC_OTGPHYREFCKCLKSOURCE_32M 32Mhz selected as OTGPHY clockk + * + */ +#define __HAL_RCC_GET_OTGPHY_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_OTGPHYREFCKSEL))) +#endif /* RCC_CCIPR4_OTGPHYREFCKSEL */ + +#if defined(OCTOSPI2) +/** @brief Macro to configure the OctoSPI2 clock. + * @param __OSPI2_CLKSOURCE__ specifies the OctoSPI2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_OSPI2CLKSOURCE_HCLK HCLK selected as OctoSPI2 clock + * @arg @ref RCC_OSPI2CLKSOURCE_PLL1Q PLL1Q divider clock selected as OctoSPI2 clock + * @arg @ref RCC_OSPI2CLKSOURCE_PLL2R PLL2R divider clock selected as OctoSPI2 clock + * @arg @ref RCC_OSPI2CLKSOURCE_CLKP CLKP selected as OctoSPI2 clock + * @retval None + */ +#define __HAL_RCC_OSPI2_CONFIG(__OSPI2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_OCTOSPI2SEL, (uint32_t)(__OSPI2_CLKSOURCE__)) + +/** @brief Macro to get the OctoSPI2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_OSPI2CLKSOURCE_HCLK HCLK selected as OctoSPI2 clock + * @arg @ref RCC_OSPI2CLKSOURCE_PLL1Q PLL1Q divider clock selected as OctoSPI2 clock + * @arg @ref RCC_OSPI2CLKSOURCE_PLL2R PLL2R divider clock selected as OctoSPI2 clock + * @arg @ref RCC_OSPI2CLKSOURCE_CLKP CLKP selected as OctoSPI2 clock + */ +#define __HAL_RCC_GET_OSPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_OCTOSPI2SEL))) +#endif /* OCTOSPI2 */ + +#if defined(LTDC) +/** @brief Macro to configure the LTDC clock (LTDCCLK). + * @param __LTDCCLKSource__ specifies the LTDC clock source. + * This parameter can be one of the following values: + * @arg RCC_LTDCCLKSOURCE_PLL3R PLL3R Clock used as LTDC clock + * @arg RCC_LTDCCLKSOURCE_PLL2R PLL2R Clock used as LTDC clock + */ +#define __HAL_RCC_LTDC_CONFIG(__LTDCCLKSource__) \ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_LTDCSEL, (uint32_t)(__LTDCCLKSource__)) + +/** @brief Macro to get the LTDC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LTDCCLKSOURCE_PLL3R PLL3R Clock used as LTDC clock + * @arg RCC_LTDCCLKSOURCE_PLL2R PLL2R Clock used as LTDC clock + * + */ +#define __HAL_RCC_GET_LTDC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_LTDCSEL))) +#endif /* LTDC */ + +#if defined(ADF1) +/** @brief Macro to configure the ADF1 clock (ADF1CLK). + * @param __ADF1CLKSource__ specifies the ADF1 clock source. + * This parameter can be one of the following values: + * @arg RCC_ADF1CLKSOURCE_PLL1Q PLL1Q Clock used as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PLL2P PLL2P Clock used as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PLL3P PLL3P Clock used as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PIN External Clock used as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_CLKP CLKP Clock used as ADF1 clock + */ +#define __HAL_RCC_ADF1_CONFIG(__ADF1CLKSource__) \ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ADF1SEL, (uint32_t)(__ADF1CLKSource__)) + +/** @brief Macro to get the ADF1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ADF1CLKSOURCE_PLL1Q PLL1Q Clock used as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PLL2P PLL2P Clock used as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PLL3P PLL3P Clock used as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PIN External Clock used as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_CLKP CLKP Clock used as ADF1 clock + * + */ +#define __HAL_RCC_GET_ADF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_ADF1SEL))) +#endif /* ADF1 */ + +#if defined(MDF1) +/** @brief Macro to configure the MDF1 clock (MDF1CLK). + * @param __MDF1CLKSource__ specifies the MDF1 clock source. + * This parameter can be one of the following values: + * @arg RCC_MDF1CLKSOURCE_PLL1Q PLL1Q Clock used as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_PLL2P PLL2P Clock used as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_PLL3P PLL3P Clock used as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_PIN External Clock used as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_CLKP CLKP Clock used as MDF1 clock + */ +#define __HAL_RCC_MDF1_CONFIG(__MDF1CLKSource__) \ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_MDF1SEL, (uint32_t)(__MDF1CLKSource__)) + +/** @brief Macro to get the MDF1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_MDF1CLKSOURCE_PLL1Q PLL1Q Clock used as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_PLL2P PLL2P Clock used as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_PLL3P PLL3P Clock used as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_PIN External Clock used as MDF1 clock + * @arg RCC_MDF1CLKSOURCE_CLKP CLKP Clock used as MDF1 clock + * + */ +#define __HAL_RCC_GET_MDF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_MDF1SEL))) +#endif /* MDF1 */ + +#if defined(RCC_CCIPR4_ETHCLKSEL) +/** @brief Macro to configure the ETH clock (ETHCLK). + * @param __ETHCLKSource__ specifies the ETH clock source. + * This parameter can be one of the following values: + * @arg RCC_ETHCLKSOURCE_HSE HSE Clock used as ETH clock + * @arg RCC_ETHCLKSOURCE_PLL1Q PLL1Q Clock used as ETH clock + */ +#define __HAL_RCC_ETH_CONFIG(__ETHCLKSource__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_ETHCLKSEL, (uint32_t)(__ETHCLKSource__)) + +/** @brief Macro to get the ETH clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ETHCLKSOURCE_HSE HSE Clock used as ETH clock + * @arg RCC_ETHCLKSOURCE_PLL1Q PLL1Q Clock used as ETH clock + * + */ +#define __HAL_RCC_GET_ETH_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_ETHCLKSEL))) +#endif /* RCC_CCIPR4_ETHCLKSEL */ + +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) +/** @brief Macro to configure the ETHPTP clock (ETHPTPCLK). + * @param __ETHPTPCLKSource__ specifies the ETHPTP clock source. + * This parameter can be one of the following values: + * @arg RCC_ETHPTPCLKSOURCE_HCLK HCLK Clock used as ETHPTP clock + * @arg RCC_ETHPTPCLKSOURCE_PLL1R PLL1R Clock used as ETHPTP clock + * @arg RCC_ETHPTPCLKSOURCE_PLL1Q PLL1Q Clock used as ETHPTP clock + * @arg RCC_ETHPTPCLKSOURCE_PLL3P PLL3P Clock used as ETHPTP clock + */ +#define __HAL_RCC_ETHPTP_CONFIG(__ETHPTPCLKSource__) \ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ETHPTPCLKSEL, (uint32_t)(__ETHPTPCLKSource__)) + +/** @brief Macro to get the ETHPTP clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ETHPTPCLKSOURCE_HCLK HCLK Clock used as ETHPTP clock + * @arg RCC_ETHPTPCLKSOURCE_PLL1R PLL1R Clock used as ETHPTP clock + * @arg RCC_ETHPTPCLKSOURCE_PLL1Q PLL1Q Clock used as ETHPTP clock + * @arg RCC_ETHPTPCLKSOURCE_PLL3P PLL3P Clock used as ETHPTP clock + * + */ +#define __HAL_RCC_GET_ETHPTP_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_ETHPTPCLKSEL))) +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + +#if defined(RCC_CCIPR4_ETHPTPDIV) +/** @brief Macro to configure the ETHPTP kernel clock divider. + * @param __ETHPTP_CLKDIV__ specifies the ETHPTP digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ETHPTP_CLK_DIV_1 ETHPTP kernel clock divided by 1 + * @arg @ref RCC_ETHPTP_CLK_DIV_2 ETHPTP kernel clock divided by 2 + * @arg @ref RCC_ETHPTP_CLK_DIV_3 ETHPTP kernel clock divided by 3 + * @arg @ref RCC_ETHPTP_CLK_DIV_4 ETHPTP kernel clock divided by 4 + * @arg @ref RCC_ETHPTP_CLK_DIV_5 ETHPTP kernel clock divided by 5 + * @arg @ref RCC_ETHPTP_CLK_DIV_6 ETHPTP kernel clock divided by 6 + * @arg @ref RCC_ETHPTP_CLK_DIV_7 ETHPTP kernel clock divided by 7 + * @arg @ref RCC_ETHPTP_CLK_DIV_8 ETHPTP kernel clock divided by 8 + * @arg @ref RCC_ETHPTP_CLK_DIV_9 ETHPTP kernel clock divided by 9 + * @arg @ref RCC_ETHPTP_CLK_DIV_10 ETHPTP kernel clock divided by 10 + * @arg @ref RCC_ETHPTP_CLK_DIV_11 ETHPTP kernel clock divided by 11 + * @arg @ref RCC_ETHPTP_CLK_DIV_12 ETHPTP kernel clock divided by 12 + * @arg @ref RCC_ETHPTP_CLK_DIV_13 ETHPTP kernel clock divided by 13 + * @arg @ref RCC_ETHPTP_CLK_DIV_14 ETHPTP kernel clock divided by 14 + * @arg @ref RCC_ETHPTP_CLK_DIV_15 ETHPTP kernel clock divided by 15 + * @arg @ref RCC_ETHPTP_CLK_DIV_16 ETHPTP kernel clock divided by 16 + * @retval None + */ +#define __HAL_RCC_ETHPTP_DIV_CONFIG(__ETHPTP_CLKDIV__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_ETHPTPDIV, (__ETHPTP_CLKDIV__)) + +/** @brief Macro to get the ETHPTP kernel clock divider. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ETHPTP_CLK_DIV_1 ETHPTP kernel clock divided by 1 + * @arg @ref RCC_ETHPTP_CLK_DIV_2 ETHPTP kernel clock divided by 2 + * @arg @ref RCC_ETHPTP_CLK_DIV_3 ETHPTP kernel clock divided by 3 + * @arg @ref RCC_ETHPTP_CLK_DIV_4 ETHPTP kernel clock divided by 4 + * @arg @ref RCC_ETHPTP_CLK_DIV_5 ETHPTP kernel clock divided by 5 + * @arg @ref RCC_ETHPTP_CLK_DIV_6 ETHPTP kernel clock divided by 6 + * @arg @ref RCC_ETHPTP_CLK_DIV_7 ETHPTP kernel clock divided by 7 + * @arg @ref RCC_ETHPTP_CLK_DIV_8 ETHPTP kernel clock divided by 8 + * @arg @ref RCC_ETHPTP_CLK_DIV_9 ETHPTP kernel clock divided by 9 + * @arg @ref RCC_ETHPTP_CLK_DIV_10 ETHPTP kernel clock divided by 10 + * @arg @ref RCC_ETHPTP_CLK_DIV_11 ETHPTP kernel clock divided by 11 + * @arg @ref RCC_ETHPTP_CLK_DIV_12 ETHPTP kernel clock divided by 12 + * @arg @ref RCC_ETHPTP_CLK_DIV_13 ETHPTP kernel clock divided by 13 + * @arg @ref RCC_ETHPTP_CLK_DIV_14 ETHPTP kernel clock divided by 14 + * @arg @ref RCC_ETHPTP_CLK_DIV_15 ETHPTP kernel clock divided by 15 + * @arg @ref RCC_ETHPTP_CLK_DIV_16 ETHPTP kernel clock divided by 16 + */ +#define __HAL_RCC_GET_ETHPTP_DIV() \ + ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_ETHPTPDIV) >> RCC_CCIPR4_ETHPTPDIV_Pos) + 1) +#endif /* RCC_CCIPR4_ETHPTPDIV */ + +#if defined(RCC_CCIPR5_ETHREFCLKSEL) +/** @brief Macro to configure the ETHREF clock (ETHREFCLK). + * @param __ETHREFCLKSource__ specifies the ETHREF clock source. + * This parameter can be one of the following values: + * @arg RCC_ETHREFCLKSOURCE_PLL1Q PLL1Q Clock used as ETHREF clock + * @arg RCC_ETHREFCLKSOURCE_PLL1R PLL1R Clock used as ETHREF clock + */ +#define __HAL_RCC_ETHREF_CONFIG(__ETHREFCLKSource__) \ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ETHREFCLKSEL, (uint32_t)(__ETHREFCLKSource__)) + +/** @brief Macro to get the ETHREF clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ETHREFCLKSOURCE_PLL1Q PLL1Q Clock used as ETHREF clock + * @arg RCC_ETHREFCLKSOURCE_PLL1R PLL1R Clock used as ETHREF clock + * + */ +#define __HAL_RCC_GET_ETHREF_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_ETHREFCLKSEL))) +#endif /* RCC_CCIPR5_ETHREFCLKSEL */ + +/** @brief Macro to configure the Timers clocks prescalers + * @param __PRESC__ specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPRES_DEACTIVATED: The Timers kernels clocks prescaler is + * equal to rcc_hclk1 if PPREx is corresponding to division by 1 or 2, + * else it is equal to 2 x Frcc_pclkx (default after reset) + * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is + * equal to rcc_hclk1 if PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to 4 x Frcc_pclkx + */ +#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR1 &= ~(RCC_CFGR1_TIMPRE);\ + RCC->CFGR1 |= (__PRESC__); \ + }while(0) + +#if defined(CRS) + +/** + * @brief Enable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) + +/** + * @brief Disable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) + +/** @brief Check whether the CRS interrupt has occurred or not. + * @param __INTERRUPT__ specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval The new state of __INTERRUPT__ (0 or 1). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? 1U : 0U) + +/** @brief Clear the CRS interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt + */ +/* CRS IT Error Mask */ +#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF |\ + RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ + ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0) + +/** + * @brief Check whether the specified CRS flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the CRS specified FLAG. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS + and consequently RCC_CRS_FLAG_ERR + * @retval None + */ + +/* CRS Flag Error Mask */ +#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF |\ + RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ + ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0) + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ +/** + * @brief Enable the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Disable the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Enable the automatic hardware adjustment of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Enable or disable the automatic hardware adjustment of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + + +/** + * @} + */ + +#endif /* CRS */ + +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Constants + * @{ + */ +/* Define used for IS_RCC_* macros below */ +#if defined(USB_OTG_HS) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_UART9 | \ + RCC_PERIPHCLK_USART10 | RCC_PERIPHCLK_USART11 | RCC_PERIPHCLK_UART12 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_I3C1 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | \ + RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ + RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SDMMC2 | \ + RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ + RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | \ + RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_CKPER | RCC_PERIPHCLK_PLAY1 | RCC_PERIPHCLK_I3C2 | \ + RCC_PERIPHCLK_OTGFS | RCC_PERIPHCLK_OTGHS | RCC_PERIPHCLK_OSPI2 | \ + RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_MDF1 | \ + RCC_PERIPHCLK_ETH |RCC_PERIPHCLK_ETHPTP | RCC_PERIPHCLK_ETHREF) +#elif defined(PLAY1) +#if defined(RCC_PERIPHCLK_UART9) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_UART9 | \ + RCC_PERIPHCLK_USART10 | RCC_PERIPHCLK_USART11 | RCC_PERIPHCLK_UART12 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_I3C1 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | \ + RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ + RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SDMMC2 | \ + RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ + RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | \ + RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_CKPER | RCC_PERIPHCLK_PLAY1 | RCC_PERIPHCLK_I3C2 | \ + RCC_PERIPHCLK_OSPI2 | RCC_PERIPHCLK_OTGFS | RCC_PERIPHCLK_LTDC | \ + RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ETH | \ + RCC_PERIPHCLK_ETHPTP | RCC_PERIPHCLK_ETHREF) +#else +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_LPUART1|\ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | \ + RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | \ + RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | \ + RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ + RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER | \ + RCC_PERIPHCLK_PLAY1 | RCC_PERIPHCLK_I3C2 | RCC_PERIPHCLK_ETH | \ + RCC_PERIPHCLK_ETHPTP | RCC_PERIPHCLK_ETHREF) +#endif /* RCC_PERIPHCLK_UART9 */ +#elif defined(SDMMC2) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_UART9 | \ + RCC_PERIPHCLK_USART10 | RCC_PERIPHCLK_USART11 | RCC_PERIPHCLK_UART12 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_I3C1 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | \ + RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ + RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SDMMC2 | \ + RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ + RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | \ + RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER) +#elif defined(UART7) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_UART9 | \ + RCC_PERIPHCLK_USART10 | RCC_PERIPHCLK_USART11 | RCC_PERIPHCLK_UART12 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_I3C1 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | \ + RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ + RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SPI1 | \ + RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | \ + RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_OSPI | \ + RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USB | \ + RCC_PERIPHCLK_CKPER) +#elif defined(USART6) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_I3C2 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SPI1 | \ + RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | \ + RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER) +#else +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_I3C2 | RCC_PERIPHCLK_TIM | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_ADCDAC | \ + RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ + RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER) +#endif /*FDCAN2 && SDMMC2 */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Macros + * @{ + */ + +#define IS_RCC_PLL2_SOURCE(SOURCE) (((SOURCE) == RCC_PLL2_SOURCE_CSI) || \ + ((SOURCE) == RCC_PLL2_SOURCE_HSI) || \ + ((SOURCE) == RCC_PLL2_SOURCE_HSE)) + +#define IS_RCC_PLL2_DIVM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) +#define IS_RCC_PLL2_MULN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#define IS_RCC_PLL2_DIVP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL2_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL2_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) + +#define IS_RCC_PLL2_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) + +#define IS_RCC_PLL2_VCIRGE_VALUE(VALUE) (((VALUE) == RCC_PLL2_VCIRANGE_0) || \ + ((VALUE) == RCC_PLL2_VCIRANGE_1) || \ + ((VALUE) == RCC_PLL2_VCIRANGE_2) || \ + ((VALUE) == RCC_PLL2_VCIRANGE_3)) + +#define IS_RCC_PLL2_VCORGE_VALUE(VALUE) (((VALUE) == RCC_PLL2_VCORANGE_WIDE) || ((VALUE) == RCC_PLL2_VCORANGE_MEDIUM)) + +#define IS_RCC_PLL2_CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U)) + +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_PLL3_SOURCE(SOURCE) (((SOURCE) == RCC_PLL3_SOURCE_CSI) || \ + ((SOURCE) == RCC_PLL3_SOURCE_HSI) || \ + ((SOURCE) == RCC_PLL3_SOURCE_HSE)) + +#define IS_RCC_PLL3_VCIRGE_VALUE(VALUE) (((VALUE) == RCC_PLL3_VCIRANGE_0) || \ + ((VALUE) == RCC_PLL3_VCIRANGE_1) || \ + ((VALUE) == RCC_PLL3_VCIRANGE_2) || \ + ((VALUE) == RCC_PLL3_VCIRANGE_3)) + +#define IS_RCC_PLL3_DIVM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) +#define IS_RCC_PLL3_MULN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#define IS_RCC_PLL3_DIVP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL3_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL3_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) + +#define IS_RCC_PLL3_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) + +#define IS_RCC_PLL3_VCORGE_VALUE(VALUE) (((VALUE) == RCC_PLL3_VCORANGE_WIDE) || ((VALUE) == RCC_PLL3_VCORANGE_MEDIUM)) + +#define IS_RCC_PLL3_CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U)) + +#endif /* RCC_CR_PLL3ON */ + +#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) + +#define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \ + ((SOURCE) == RCC_CLKPSOURCE_CSI) || \ + ((SOURCE) == RCC_CLKPSOURCE_HSE)) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != ((uint64_t)0x00)) && \ + (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == ((uint64_t)0x00))) +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) + +#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) + +#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)) + +#else +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) + +#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) + +#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)) + +#endif /* RCC_CR_PLL3ON */ + +#if defined(UART4) +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)) +#else +#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)) +#endif /* RCC_CR_PLL3ON */ +#endif /* UART4 */ + +#if defined(UART5) +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)) +#else +#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)) +#endif /* RCC_CR_PLL3ON */ +#endif /* UART5 */ + +#if defined(USART6) +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_USART6CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE)) +#else +#define IS_RCC_USART6CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE)) +#endif /* RCC_CR_PLL3ON */ +#endif /* USART6 */ + +#if defined(UART7) +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_UART7CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART7CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_LSE)) +#else +#define IS_RCC_UART7CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART7CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_UART7CLKSOURCE_LSE)) +#endif /* RCC_CR_PLL3ON */ +#endif /* UART7 */ + +#if defined(UART8) +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_UART8CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART8CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_LSE)) +#else +#define IS_RCC_UART8CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART8CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_UART8CLKSOURCE_LSE)) +#endif /* RCC_CR_PLL3ON */ +#endif /* UART8 */ + +#if defined(UART9) +#define IS_RCC_UART9CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART9CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART9CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_UART9CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_UART9CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_UART9CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_UART9CLKSOURCE_LSE)) +#endif /* UART9 */ + +#if defined(USART10) +#define IS_RCC_USART10CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART10CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART10CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_USART10CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_USART10CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART10CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_USART10CLKSOURCE_LSE)) +#endif /* USART10 */ + +#if defined(USART11) +#define IS_RCC_USART11CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART11CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART11CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_USART11CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_USART11CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART11CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_USART11CLKSOURCE_LSE)) +#endif /* USART11 */ + +#if defined(UART12) +#define IS_RCC_UART12CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_UART12CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART12CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_UART12CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_UART12CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_UART12CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_UART12CLKSOURCE_LSE)) +#endif /* UART12 */ + +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_CSI)) + +#else +#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_CSI)) + +#endif /* RCC_CR_PLL3ON */ + +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_CSI)) + +#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_CSI)) + +#else +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_PLL2R) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_CSI)) + +#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_PLL2R) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_CSI)) + +#endif /* RCC_CR_PLL3ON */ + + +#if defined(I2C3) +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI ) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_CSI)) +#else +#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_PLL2R) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI ) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_CSI)) +#endif /* RCC_CR_PLL3ON */ +#endif /* I2C3 */ + +#if defined(I2C4) +#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI ) || \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_CSI)) +#endif /* I2C4 */ + +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_I3C1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I3C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I3C1CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_I3C1CLKSOURCE_HSI)) + +#else +#define IS_RCC_I3C1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I3C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I3C1CLKSOURCE_PLL2R) || \ + ((__SOURCE__) == RCC_I3C1CLKSOURCE_HSI)) + +#endif /* RCC_CR_PLL3ON */ + +#if defined(I3C2) +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) +#define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI)) +#else +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI)) +#else +#define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL2R) || \ + ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI)) +#endif /* PLL3 */ +#endif /* STM32H5E5xx || STM32H5E4xx || STM32H5F5xx || STM32H5F4xx */ +#endif /* I3C2 */ + +#if defined(SAI1) +#define IS_RCC_SAI1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1Q)|| \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2P)|| \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3P)|| \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP)) +#endif /* SAI1 */ + +#if defined(SAI2) +#define IS_RCC_SAI2CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1Q)|| \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2P)|| \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3P)|| \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP)) +#endif /* SAI2 */ + +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_LPTIM1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_CLKP)) + +#define IS_RCC_LPTIM2CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_CLKP)) + +#else +#define IS_RCC_LPTIM1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_CLKP)) + +#define IS_RCC_LPTIM2CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_CLKP)) + +#endif /* RCC_CR_PLL3ON */ + +#if defined(LPTIM3) +#define IS_RCC_LPTIM3CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_CLKP)) +#endif /* LPTIM3 */ + +#if defined(LPTIM4) +#define IS_RCC_LPTIM4CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_CLKP)) +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +#define IS_RCC_LPTIM5CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_CLKP)) +#endif /* LPTIM5 */ + +#if defined(LPTIM6) +#define IS_RCC_LPTIM6CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM6CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_CLKP)) +#endif /* LPTIM6 */ + +#define IS_RCC_FDCANCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2Q)) + +#if defined(SDMMC1) +#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL2R)) +#endif /* SDMMC1 */ + +#if defined(SDMMC2) +#define IS_RCC_SDMMC2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SDMMC2CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SDMMC2CLKSOURCE_PLL2R)) +#endif /*SDMMC2*/ + +#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI)) + +#define IS_RCC_ADCDACCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADCDACCLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_ADCDACCLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_ADCDACCLKSOURCE_PLL2R) || \ + ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_ADCDACCLKSOURCE_CSI)) + +#define IS_RCC_DACLPCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_DACLPCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_DACLPCLKSOURCE_LSE)) + +#if defined(OCTOSPI1) +#define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_OSPICLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2R) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP)) +#endif /* OCTOSPI1 */ + +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3P) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP)) + +#define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3P) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP)) + +#define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3P) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP)) +#else +#define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP)) + +#define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP)) + +#define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP)) + +#endif /* RCC_CR_PLL3ON */ + +#if defined(SPI4) +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_SPI4CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI4CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) +#else +#define IS_RCC_SPI4CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI4CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) +#endif /* RCC_CR_PLL3ON */ +#endif /* SPI4 */ + +#if defined(SPI5) +#define IS_RCC_SPI5CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI5CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) +#endif /* SPI5 */ + +#if defined(SPI6) +#define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) +#endif /* SPI6 */ + +#if defined(USB_DRD_FS) +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBCLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)) +#else +#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBCLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)) +#endif /* RCC_CR_PLL3ON */ +#endif /* USB_DRD_FS */ + +#if defined(CEC) +#define IS_RCC_CECCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_CECCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_CECCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_CECCLKSOURCE_CSI_DIV122)) +#endif /*CEC*/ + +#if defined(PLAY1) +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_PLAY1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_PLAY1CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_PLAY1CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_PLAY1CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_PLAY1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_PLAY1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_PLAY1CLKSOURCE_CLKP)) +#else +#define IS_RCC_PLAY1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_PLAY1CLKSOURCE_PCLK3) || \ + ((__SOURCE__) == RCC_PLAY1CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_PLAY1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_PLAY1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_PLAY1CLKSOURCE_CLKP)) +#endif /* RCC_CR_PLL3ON */ + +#define IS_RCC_PLAY1_DIV(__DIVIDER__) \ + (((__DIVIDER__) == RCC_PLAY1_CLK_DIV_1 ) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_2 ) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_4 ) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_8 ) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_16) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_32) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_64) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_128) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_256) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_512) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_1024) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_2048) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_4096) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_8192) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_16384) || \ + ((__DIVIDER__) == RCC_PLAY1_CLK_DIV_32768)) +#endif /* PLAY1 */ + +#if defined(USB_OTG_FS) +#if defined(PWR_USBSCR_OTGHSEN) +#define IS_RCC_OTGFSCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_OTGFSCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_OTGFSCLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_OTGFSCLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_OTGFSCLKSOURCE_CLK48)) +#else +#define IS_RCC_OTGFSCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_OTGFSCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_OTGFSCLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_OTGFSCLKSOURCE_PLL3Q)) +#endif /* PWR_USBSCR_OTGHSEN */ +#endif /* USB_OTG_FS */ + +#if defined(USB_OTG_HS) +#define IS_RCC_OTGHSCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_OTGHSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_OTGHSCLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_OTGHSCLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_OTGHSCLKSOURCE_PLL1Q_DIV2)) +#endif /* USB_OTG_HS */ + +#if defined(RCC_CCIPR4_OTGPHYREFCKSEL) +#define IS_RCC_OTGPHYCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_OTGPHYREFCKCLKSOURCE_16M) || \ + ((__SOURCE__) == RCC_OTGPHYREFCKCLKSOURCE_19_2M) || \ + ((__SOURCE__) == RCC_OTGPHYREFCKCLKSOURCE_24M) || \ + ((__SOURCE__) == RCC_OTGPHYREFCKCLKSOURCE_26M) || \ + ((__SOURCE__) == RCC_OTGPHYREFCKCLKSOURCE_32M)) +#endif /* RCC_CCIPR4_OTGPHYREFCKSEL */ + +#if defined(LTDC) +#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL2R)) +#endif /* LTDC */ + +#if defined(OCTOSPI2) +#define IS_RCC_OSPI2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_OSPI2CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_OSPI2CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_OSPI2CLKSOURCE_PLL2R) || \ + ((__SOURCE__) == RCC_OSPI2CLKSOURCE_CLKP)) +#endif /* OCTOSPI2 */ + +#if defined(ADF1) +#define IS_RCC_ADF1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL3P) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_CLKP)) +#endif /* ADF1 */ + +#if defined(MDF1) +#define IS_RCC_MDF1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL3P) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_MDF1CLKSOURCE_CLKP)) +#endif /* MDF1 */ + +#if defined(RCC_CCIPR4_ETHCLKSEL) +#define IS_RCC_ETHCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ETHCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_ETHCLKSOURCE_PLL1Q)) +#endif /* RCC_CCIPR4_ETHCLKSEL */ + +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) +#if defined(RCC_CR_PLL3ON) +#define IS_RCC_ETHPTPCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ETHPTPCLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_ETHPTPCLKSOURCE_PLL1R) || \ + ((__SOURCE__) == RCC_ETHPTPCLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_ETHPTPCLKSOURCE_PLL3P)) +#else +#define IS_RCC_ETHPTPCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ETHPTPCLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_ETHPTPCLKSOURCE_PLL1R) || \ + ((__SOURCE__) == RCC_ETHPTPCLKSOURCE_PLL1Q)) +#endif /* RCC_CR_PLL3ON */ +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + +#if defined(RCC_CCIPR4_ETHPTPDIV) +#define IS_RCC_ETHPTP_DIV(__DIVIDER__) \ + (((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_1) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_2) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_3) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_4) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_5) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_6) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_7) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_8) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_9) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_10) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_11) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_12) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_13) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_14) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_15) || \ + ((__DIVIDER__) == RCC_ETHPTP_CLK_DIV_16)) +#endif /* RCC_CCIPR4_ETHPTPDIV */ + +#if defined(RCC_CCIPR5_ETHREFCLKSEL) +#define IS_RCC_ETHREFCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ETHREFCLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_ETHREFCLKSOURCE_PLL1R)) +#endif /* RCC_CCIPR5_ETHREFCLKSEL */ + +#define IS_RCC_TIMPRES(VALUE) \ + (((VALUE) == RCC_TIMPRES_DEACTIVATED) || \ + ((VALUE) == RCC_TIMPRES_ACTIVATED)) + +#if defined(CRS) +#if defined(USB_OTG_HS) +#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_OTG_FS) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_OTG_HS)) +#elif defined(USB_OTG_FS) +#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_OTG_FS)) +#elif defined(USB_DRD_FS) +#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) +#endif /* USB_OTG_HS */ + +#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) + +#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) + +#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) + +#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) + +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) + +#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ + ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *pPLL1_Clocks); +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *pPLL2_Clocks); +#if defined(RCC_CR_PLL3ON) +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *pPLL3_Clocks); +#endif /* RCC_CR_PLL3ON */ +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *pPLL2Init); +HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); +#if defined(RCC_CR_PLL3ON) +HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *pPLL3Init); +HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void); +#endif /* RCC_CR_PLL3ON */ + +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); +void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); +void HAL_RCCEx_EnableLSECSS(void); +void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_LSECSS_IRQHandler(void); +void HAL_RCCEx_LSECSS_Callback(void); +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); +void HAL_RCCEx_DisableLSCO(void); +/** + * @} + */ + +#if defined(CRS) + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H5xx_HAL_RCC_EX_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h new file mode 100644 index 00000000..c3cf780d --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h @@ -0,0 +1,1775 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_UART_H +#define STM32H5xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + @note For LPUART : + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ + +} UART_InitTypeDef; + +/** + * @brief UART Advanced Features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several + Advanced Features may be initialized at the same time . + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref UART_Tx_Inv. */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref UART_Rx_Inv. */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref UART_Data_Inv. */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref UART_Rx_Tx_Swap. */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref UART_Overrun_Disable. */ + +#if defined(HAL_DMA_MODULE_ENABLED) + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. + This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref UART_MSB_First. */ +} UART_AdvFeatureInitTypeDef; + +/** + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_UART_StateTypeDef; + +/** + * @brief UART clock sources definition + */ +typedef enum +{ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PLL2Q = 0x01U, /*!< PLL2Q clock source */ + UART_CLOCKSOURCE_PLL3Q = 0x02U, /*!< PLL3Q clock source */ + UART_CLOCKSOURCE_HSI = 0x04U, /*!< HSI clock source */ + UART_CLOCKSOURCE_CSI = 0x08U, /*!< CSI clock source */ + UART_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */ +} UART_ClockSourceTypeDef; + +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * This parameter can be a value of @ref UART_Reception_Type_Values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + uint16_t Mask; /*!< UART Rx RDR register mask */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref UARTEx_FIFO_mode. */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ + HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method + * @{ + */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ +/** + * @} + */ + +/** @defgroup UART_ClockPrescaler UART Clock Prescaler + * @{ + */ +#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ + +/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout + * @{ + */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ +/** + * @} + */ + +/** @defgroup UART_LIN UART Local Interconnection Network mode + * @{ + */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ +/** + * @} + */ + +#if defined(HAL_DMA_MODULE_ENABLED) +/** @defgroup UART_DMA_Tx UART DMA Tx + * @{ + */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ +/** + * @} + */ + +/** @defgroup UART_DMA_Rx UART DMA Rx + * @{ + */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection + * @{ + */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_Methods UART WakeUp Methods + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ +/** + * @} + */ + +/** @defgroup UART_Request_Parameters UART Request Parameters + * @{ + */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type + * @{ + */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +/** + * @} + */ + +/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion + * @{ + */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap + * @{ + */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable + * @{ + */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +/** + * @} + */ + +#if defined(HAL_DMA_MODULE_ENABLED) +/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error + * @{ + */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** @defgroup UART_MSB_First UART Advanced Feature MSB First + * @{ + */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ +/** + * @} + */ + +/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable + * @{ + */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ +/** + * @} + */ + +/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable + * @{ + */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ +/** + * @} + */ + +/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register + * @{ + */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection + * @{ + */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ +/** + * @} + */ + +/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity + * @{ + */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask + * @{ + */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ +/** + * @} + */ + +/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value + * @{ + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ +/** + * @} + */ + +/** @defgroup UART_Flags UART Status Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ +#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ +#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ +#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ +#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ +#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ +#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ +#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ +#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ + +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +/** + * @} + */ + +/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags + * @{ + */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup UART_Reception_Type_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ + +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle states. + * @param __HANDLE__ UART handle. + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flush the UART Data registers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) + +/** @brief Clear the UART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) + +/** @brief Check whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref UART_FLAG_RXFF RXFIFO Full flag + * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag + * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref UART_FLAG_WUF Wake up from stop mode flag + * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) + * @arg @ref UART_FLAG_SBKF Send Break flag + * @arg @ref UART_FLAG_CMF Character match flag + * @arg @ref UART_FLAG_BUSY Busy flag + * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref UART_FLAG_CTS CTS Change flag + * @arg @ref UART_FLAG_LBDF LIN Break detection flag + * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag + * @arg @ref UART_FLAG_TC Transmission Complete flag + * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag + * @arg @ref UART_FLAG_IDLE Idle Line detection flag + * @arg @ref UART_FLAG_ORE Overrun Error flag + * @arg @ref UART_FLAG_NE Noise Error flag + * @arg @ref UART_FLAG_FE Framing Error flag + * @arg @ref UART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Check whether the specified UART interrupt has occurred or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) + +/** @brief Check whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) + +/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific UART request flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref UART_SENDBREAK_REQUEST Send Break Request + * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request + * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Enable CTS flow control. + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control. + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control. + * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control. + * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +/** @brief Get UART clock division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval UART clock division factor + */ +#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) + +/** @brief BRR division operation to set BRR register with LPUART. + * @param __PCLK__ LPUART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \ + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \ + ) + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief Check whether or not UART instance is Low Power UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) + */ +#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance)) + +/** @brief Check UART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on H5 (i.e. 250 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 20000000U) + +/** @brief Check UART assertion time. + * @param __TIME__ 5-bit value assertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** @brief Check UART deassertion time. + * @param __TIME__ 5-bit value deassertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param __STOPBITS__ UART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ + ((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that LPUART frame number of stop bits is valid. + * @param __STOPBITS__ LPUART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that UART frame parity is valid. + * @param __PARITY__ UART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ + ((__PARITY__) == UART_PARITY_EVEN) || \ + ((__PARITY__) == UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param __CONTROL__ UART hardware flow control. + * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART communication mode is valid. + * @param __MODE__ UART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that UART state is valid. + * @param __STATE__ UART state. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ + ((__STATE__) == UART_STATE_ENABLE)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param __SAMPLING__ UART oversampling. + * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) + */ +#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param __ONEBIT__ UART frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that UART auto Baud rate detection mode is valid. + * @param __MODE__ UART auto Baud rate detection mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) + +/** + * @brief Ensure that UART receiver timeout setting is valid. + * @param __TIMEOUT__ UART receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) + +/** + * @brief Ensure that UART LIN state is valid. + * @param __LIN__ UART LIN state. + * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) + */ +#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ + ((__LIN__) == UART_LIN_ENABLE)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param __LENGTH__ UART LIN break detection length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Ensure that UART DMA TX state is valid. + * @param __DMATX__ UART DMA TX state. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ + ((__DMATX__) == UART_DMA_TX_ENABLE)) + +/** + * @brief Ensure that UART DMA RX state is valid. + * @param __DMARX__ UART DMA RX state. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ + ((__DMARX__) == UART_DMA_RX_ENABLE)) + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @brief Ensure that UART half-duplex state is valid. + * @param __HDSEL__ UART half-duplex state. + * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) + */ +#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ + ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) + +/** + * @brief Ensure that UART wake-up method is valid. + * @param __WAKEUP__ UART wake-up method . + * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) + */ +#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) + +/** + * @brief Ensure that UART request parameter is valid. + * @param __PARAM__ UART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that UART advanced features initialization is valid. + * @param __INIT__ UART advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#else +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Ensure that UART frame TX inversion setting is valid. + * @param __TXINV__ UART frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX inversion setting is valid. + * @param __RXINV__ UART frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that UART frame data inversion setting is valid. + * @param __DATAINV__ UART frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX/TX pins swap setting is valid. + * @param __SWAP__ UART frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that UART frame overrun setting is valid. + * @param __OVERRUN__ UART frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that UART auto Baud rate state is valid. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Ensure that UART DMA enabling or disabling on error setting is valid. + * @param __DMA__ UART DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Ensure that UART frame MSB first setting is valid. + * @param __MSBFIRST__ UART frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) + +/** + * @brief Ensure that UART stop mode state is valid. + * @param __STOPMODE__ UART stop mode state. + * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) + +/** + * @brief Ensure that UART mute mode state is valid. + * @param __MUTE__ UART mute mode state. + * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) + */ +#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param __WAKE__ UART wake-up selection. + * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) + */ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param __POLARITY__ UART driver enable polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ + ((__POLARITY__) == UART_DE_POLARITY_LOW)) + +/** + * @brief Ensure that UART Prescaler is valid. + * @param __CLOCKPRESCALER__ UART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) + +/** + * @} + */ + +/* Include UART HAL Extended module */ +#include "stm32h5xx_hal_uart_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -----------------------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + +/* Private variables -----------------------------------------------------------*/ +/** @defgroup UART_Private_variables UART Private variables + * @{ + */ +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_UART_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h new file mode 100644 index 00000000..23157699 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h @@ -0,0 +1,440 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_uart_ex.h + * @author MCD Application Team + * @brief Header file of UART HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_UART_EX_H +#define STM32H5xx_HAL_UART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup UARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Types UARTEx Exported Types + * @{ + */ + +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct +{ + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). + This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. + If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must + be filled up. */ + + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. + This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ + + uint8_t Address; /*!< UART/USART node address (7-bit long max). */ +} UART_WakeUpTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants + * @{ + */ + +/** @defgroup UARTEx_Word_Length UARTEx Word Length + * @{ + */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +/** + * @} + */ + +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length + * @{ + */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +/** + * @} + */ + +/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode + * @brief UART FIFO mode + * @{ + */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level + * @brief UART TXFIFO threshold level + * @{ + */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ +/** + * @} + */ + +/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level + * @brief UART RXFIFO threshold level + * @{ + */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); + +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Macros UARTEx Private Macros + * @{ + */ + +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) \ + || defined(STM32H5E4xx) || defined(STM32H5E5xx) || defined(STM32H5F4xx) || defined(STM32H5F5xx) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \ + } \ + else if((__HANDLE__)->Instance == UART7) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART7; \ + } \ + else if((__HANDLE__)->Instance == UART8) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART8; \ + } \ + else if((__HANDLE__)->Instance == UART9) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART9; \ + } \ + else if((__HANDLE__)->Instance == USART10) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART10; \ + } \ + else if((__HANDLE__)->Instance == USART11) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART11; \ + } \ + else if((__HANDLE__)->Instance == UART12) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART12; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#elif (defined(STM32H523xx) || defined(STM32H533xx)) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#else +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || + * defined(STM32H5E4xx) || defined(STM32H5E5xx) || defined(STM32H5F4xx) || defined(STM32H5F5xx) + */ + + +/** @brief Report the UART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that UART frame length is valid. + * @param __LENGTH__ UART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ + ((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) + +/** + * @brief Ensure that UART wake-up address length is valid. + * @param __ADDRESS__ UART wake-up address length. + * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) + */ +#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ + ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) + +/** + * @brief Ensure that UART TXFIFO threshold level is valid. + * @param __THRESHOLD__ UART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that UART RXFIFO threshold level is valid. + * @param __THRESHOLD__ UART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_UART_EX_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h new file mode 100644 index 00000000..d0c1a6ad --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h @@ -0,0 +1,1293 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_usart.h + * @author MCD Application Team + * @brief Header file of USART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_USART_H +#define STM32H5xx_HAL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USART_Exported_Types USART Exported Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. + The baud rate is computed using the following formula: + Baud Rate Register[15:4] = ((2 * fclk_pres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * fclk_pres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where fclk_pres is the USART input clock frequency (fclk) + divided by a prescaler. + @note Oversampling by 8 is systematically applied to + achieve high baud rates. */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode. */ + + uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity. */ + + uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase. */ + + uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. + This parameter can be a value of @ref USART_ClockPrescaler. */ +} USART_InitTypeDef; + +/** + * @brief HAL USART State structures definition + */ +typedef enum +{ + HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ + HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ + HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04U /*!< Error */ +} HAL_USART_StateTypeDef; + +/** + * @brief USART clock sources definitions + */ +typedef enum +{ + USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + USART_CLOCKSOURCE_CSI = 0x04U, /*!< CSI clock source */ + USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + USART_CLOCKSOURCE_PLL2Q = 0x10U, /*!< PLL2 clock source */ + USART_CLOCKSOURCE_PLL3Q = 0x20U, /*!< PLL3 clock source */ + USART_CLOCKSOURCE_UNDEFINED = 0x40U /*!< Undefined clock source */ +} USART_ClockSourceTypeDef; + +/** + * @brief USART handle Structure definition + */ +typedef struct __USART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< USART registers base address */ + + USART_InitTypeDef Init; /*!< USART communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< USART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< USART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ + + uint16_t Mask; /*!< USART Rx RDR register mask */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value + of @ref USARTEx_Slave_Mode */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value + of @ref USARTEx_FIFO_mode. */ + + void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ + + __IO uint32_t ErrorCode; /*!< USART Error code */ + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */ + void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */ + void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */ + void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */ + void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Fifo Empty Callback */ + + void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */ + void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +} USART_HandleTypeDef; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL USART Callback ID enumeration definition + */ +typedef enum +{ + HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */ + HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */ + HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */ + HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */ + HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */ + HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */ + HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */ + HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U, /*!< USART Rx Fifo Full Callback ID */ + HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, /*!< USART Tx Fifo Empty Callback ID */ + + HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */ + HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */ + +} HAL_USART_CallbackIDTypeDef; + +/** + * @brief HAL USART Callback pointer definition + */ +typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */ + +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_Error_Definition USART Error Definition + * @{ + */ +#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */ +/** + * @} + */ + +/** @defgroup USART_Stop_Bits USART Number of Stop Bits + * @{ + */ +#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */ +#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ +#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_Parity USART Parity + * @{ + */ +#define USART_PARITY_NONE 0x00000000U /*!< No parity */ +#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup USART_Mode USART Mode + * @{ + */ +#define USART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define USART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup USART_Clock USART Clock + * @{ + */ +#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */ +#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */ +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity USART Clock Polarity + * @{ + */ +#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */ +#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup USART_Clock_Phase USART Clock Phase + * @{ + */ +#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */ +#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */ +/** + * @} + */ + +/** @defgroup USART_Last_Bit USART Last Bit + * @{ + */ +#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */ +#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_ClockPrescaler USART Clock Prescaler + * @{ + */ +#define USART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define USART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define USART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define USART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define USART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define USART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define USART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define USART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define USART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ + +/** + * @} + */ + +/** @defgroup USART_Request_Parameters USART Request Parameters + * @{ + */ +#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup USART_Flags USART Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define USART_FLAG_TXFT USART_ISR_TXFT /*!< USART TXFIFO threshold flag */ +#define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */ +#define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */ +#define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */ +#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ +#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ +#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ +#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ +#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ +#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ +#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */ +#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ +#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ +#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ +#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ +#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */ +#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */ +#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */ +#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */ +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition USART Interrupts Definition + * Elements values convention: 0000ZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ + +#define USART_IT_PE 0x0028U /*!< USART parity error interruption */ +#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */ +#define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */ +#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */ +#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */ +#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */ +#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */ +#define USART_IT_ERR 0x0060U /*!< USART error interruption */ +#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */ +#define USART_IT_NE 0x0200U /*!< USART noise error interruption */ +#define USART_IT_FE 0x0100U /*!< USART frame error interruption */ +#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */ +#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */ +#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */ +#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */ + +/** + * @} + */ + +/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags + * @{ + */ +#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ +#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ +#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask + * @{ + */ +#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */ +#define USART_CR_MASK 0x00E0U /*!< USART control register mask */ +#define USART_CR_POS 5U /*!< USART control register position */ +#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */ +#define USART_ISR_POS 8U /*!< USART ISR register position */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup USART_Exported_Macros USART Exported Macros + * @{ + */ + +/** @brief Reset USART handle state. + * @param __HANDLE__ USART handle. + * @retval None + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_USART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** @brief Check whether the specified USART flag is set or not. + * @param __HANDLE__ specifies the USART Handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref USART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref USART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref USART_FLAG_RXFF RXFIFO Full flag + * @arg @ref USART_FLAG_TXFE TXFIFO Empty flag + * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref USART_FLAG_BUSY Busy flag + * @arg @ref USART_FLAG_UDR SPI slave underrun error flag + * @arg @ref USART_FLAG_TXE Transmit data register empty flag + * @arg @ref USART_FLAG_TXFNF TXFIFO not full flag + * @arg @ref USART_FLAG_TC Transmission Complete flag + * @arg @ref USART_FLAG_RXNE Receive data register not empty flag + * @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag + * @arg @ref USART_FLAG_RTOF Receiver Timeout flag + * @arg @ref USART_FLAG_IDLE Idle Line detection flag + * @arg @ref USART_FLAG_ORE OverRun Error flag + * @arg @ref USART_FLAG_NE Noise Error flag + * @arg @ref USART_FLAG_FE Framing Error flag + * @arg @ref USART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified USART pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag + * @retval None + */ +#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the USART PE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF) + +/** @brief Clear the USART FE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF) + +/** @brief Clear the USART NE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF) + +/** @brief Clear the USART ORE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF) + +/** @brief Clear the USART IDLE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF) + +/** @brief Clear the USART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF) + +/** @brief Clear SPI slave underrun error flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF) + +/** @brief Enable the specified USART interrupt. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) + +/** @brief Disable the specified USART interrupt. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) + +/** @brief Check whether the specified USART interrupt has occurred or not. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ + USART_ISR_POS))) != 0U) ? SET : RESET) + +/** @brief Check whether the specified USART interrupt source is enabled or not. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + USART_IT_MASK))) != 0U) ? SET : RESET) + +/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt. + * This parameter can be one of the following values: + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @retval None + */ +#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific USART request flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __REQ__ specifies the request flag to set. + * This parameter can be one of the following values: + * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * + * @retval None + */ +#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the USART one bit sample method. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the USART one bit sample method. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable USART. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable USART. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup USART_Private_Macros USART Private Macros + * @{ + */ + +/** @brief Get USART clock division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ USART prescaler value. + * @retval USART clock division factor + */ +#define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ USART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ USART prescaler value. + * @retval Division result + */ +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\ + (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief Report the USART clock source. + * @param __HANDLE__ specifies the USART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval the USART clocking source, written in __CLOCKSOURCE__. + */ +#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) \ + || defined(STM32H5E4xx) || defined(STM32H5E5xx) || defined(STM32H5F4xx) || defined(STM32H5F5xx) +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART2CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART2CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART3CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART3CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART6CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART6CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART6CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART10) \ + { \ + switch(__HAL_RCC_GET_USART10_SOURCE()) \ + { \ + case RCC_USART10CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART10CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART10CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART10CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART10CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART10CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART11) \ + { \ + switch(__HAL_RCC_GET_USART11_SOURCE()) \ + { \ + case RCC_USART11CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART11CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART11CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART11CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART11CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART11CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif (defined(STM32H523xx) || defined(STM32H533xx)) +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART2CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART2CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART3CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART3CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART6CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART6CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART6CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART2CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + case RCC_USART3CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) + +#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || + * defined(STM32H5E4xx) || defined(STM32H5E5xx) || defined(STM32H5F4xx) || defined(STM32H5F5xx) + */ + +/** @brief Check USART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on H5 (i.e. 250 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 20000000U) + +/** + * @brief Ensure that USART frame number of stop bits is valid. + * @param __STOPBITS__ USART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \ + ((__STOPBITS__) == USART_STOPBITS_1) || \ + ((__STOPBITS__) == USART_STOPBITS_1_5) || \ + ((__STOPBITS__) == USART_STOPBITS_2)) + +/** + * @brief Ensure that USART frame parity is valid. + * @param __PARITY__ USART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ + ((__PARITY__) == USART_PARITY_EVEN) || \ + ((__PARITY__) == USART_PARITY_ODD)) + +/** + * @brief Ensure that USART communication mode is valid. + * @param __MODE__ USART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that USART clock state is valid. + * @param __CLOCK__ USART clock state. + * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid) + */ +#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \ + ((__CLOCK__) == USART_CLOCK_ENABLE)) + +/** + * @brief Ensure that USART frame polarity is valid. + * @param __CPOL__ USART frame polarity. + * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) + */ +#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) + +/** + * @brief Ensure that USART frame phase is valid. + * @param __CPHA__ USART frame phase. + * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) + */ +#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) + +/** + * @brief Ensure that USART frame last bit clock pulse setting is valid. + * @param __LASTBIT__ USART frame last bit clock pulse setting. + * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) + */ +#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \ + ((__LASTBIT__) == USART_LASTBIT_ENABLE)) + +/** + * @brief Ensure that USART request parameter is valid. + * @param __PARAM__ USART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that USART Prescaler is valid. + * @param __CLOCKPRESCALER__ USART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256)) + +/** + * @} + */ + +/* Include USART HAL Extended module */ +#include "stm32h5xx_hal_usart_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); +void HAL_USART_MspInit(USART_HandleTypeDef *husart); +void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart); + +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); +void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); +void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_USART_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h new file mode 100644 index 00000000..6055a3bd --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h @@ -0,0 +1,282 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_usart_ex.h + * @author MCD Application Team + * @brief Header file of USART HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_USART_EX_H +#define STM32H5xx_HAL_USART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup USARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants + * @{ + */ + +/** @defgroup USARTEx_Word_Length USARTEx Word Length + * @{ + */ +#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ +/** + * @} + */ + +/** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management + * @{ + */ +#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ +#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ +/** + * @} + */ + + +/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable + * @brief USART SLAVE mode + * @{ + */ +#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ +#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ +/** + * @} + */ + +/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode + * @brief USART FIFO mode + * @{ + */ +#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level + * @brief USART TXFIFO level + * @{ + */ +#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level + * @brief USART RXFIFO level + * @{ + */ +#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Macros USARTEx Private Macros + * @{ + */ + +/** @brief Compute the USART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the USART Handle. + * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define USART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that USART frame length is valid. + * @param __LENGTH__ USART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \ + ((__LENGTH__) == USART_WORDLENGTH_8B) || \ + ((__LENGTH__) == USART_WORDLENGTH_9B)) + +/** + * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid. + * @param __NSS__ USART Negative Slave Select pin management. + * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) + */ +#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \ + ((__NSS__) == USART_NSS_SOFT)) + +/** + * @brief Ensure that USART Slave Mode is valid. + * @param __STATE__ USART Slave Mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \ + ((__STATE__) == USART_SLAVEMODE_ENABLE)) + +/** + * @brief Ensure that USART FIFO mode is valid. + * @param __STATE__ USART FIFO mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \ + ((__STATE__) == USART_FIFOMODE_ENABLE)) + +/** + * @brief Ensure that USART TXFIFO threshold level is valid. + * @param __THRESHOLD__ USART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that USART RXFIFO threshold level is valid. + * @param __THRESHOLD__ USART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup USARTEx_Exported_Functions_Group1 + * @{ + */ + +/* IO operation functions *****************************************************/ +void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart); +void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** @addtogroup USARTEx_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig); +HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); +HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_USART_EX_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h new file mode 100644 index 00000000..515bbf18 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h @@ -0,0 +1,3016 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB , APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB , APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H5xx_LL_BUS_H +#define __STM32H5xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_AHB_BRANCH_CLK_AHBx BRANCH CLK AHBx + * @{ + */ +#define LL_AHB_BRANCH_CLK_AHB1 RCC_CFGR2_AHB1DIS +#define LL_AHB_BRANCH_CLK_AHB2 RCC_CFGR2_AHB2DIS +#if defined(AHB4PERIPH_BASE) +#define LL_AHB_BRANCH_CLK_AHB4 RCC_CFGR2_AHB4DIS +#endif /* AHB4PERIPH_BASE */ +/** + * @} + */ + +/** @defgroup BUS_LL_APB_BRANCH_CLK_APBx BRANCH CLK APBx + * @{ + */ +#define LL_APB_BRANCH_CLK_APB1 RCC_CFGR2_APB1DIS +#define LL_APB_BRANCH_CLK_APB2 RCC_CFGR2_APB2DIS +#define LL_APB_BRANCH_CLK_APB3 RCC_CFGR2_APB3DIS +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#if defined(CORDIC) +#define LL_AHB1_GRP1_PERIPH_ALL 0xF13AD103U +#elif defined(DCACHE) +#define LL_AHB1_GRP1_PERIPH_ALL 0xF1021103U +#elif defined(JPEG) +#define LL_AHB1_GRP1_PERIPH_ALL 0xD1FFD103U +#else +#define LL_AHB1_GRP1_PERIPH_ALL 0x91021103U +#endif /* CORDIC */ +#define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN +#define LL_AHB1_GRP1_PERIPH_GPDMA2 RCC_AHB1ENR_GPDMA2EN +#if defined(CORDIC) +#define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN +#endif /* CORDIC */ +#if defined(FMAC) +#define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN +#endif /* FMAC */ +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLITFEN +#if defined(ETH) +#define LL_AHB1_GRP1_PERIPH_ETH RCC_AHB1ENR_ETHEN +#define LL_AHB1_GRP1_PERIPH_ETHTX RCC_AHB1ENR_ETHTXEN +#define LL_AHB1_GRP1_PERIPH_ETHRX RCC_AHB1ENR_ETHRXEN +#endif /* ETH */ +#if defined(RCC_AHB1ENR_ETHCKEN) +#define LL_AHB1_GRP1_PERIPH_ETHINTERN RCC_AHB1ENR_ETHCKEN +#endif /* RCC_AHB1ENR_ETHCKEN */ +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN +#define LL_AHB1_GRP1_PERIPH_GTZC1 RCC_AHB1ENR_TZSC1EN +#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPRAMEN +#define LL_AHB1_GRP1_PERIPH_ICACHE RCC_AHB1LPENR_ICACHELPEN +#if defined(DCACHE1) +#define LL_AHB1_GRP1_PERIPH_DCACHE1 RCC_AHB1ENR_DCACHE1EN +#endif /* DCACHE1 */ +#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1ENR_SRAM1EN +#if defined(MDF1) +#define LL_AHB1_GRP1_PERIPH_MDF1 RCC_AHB1ENR_MDF1EN +#endif /* MDF1 */ +#if defined(DMA2D) +#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN +#endif /* DMA2D */ +#if defined(JPEG) +#define LL_AHB1_GRP1_PERIPH_JPEG RCC_AHB1ENR_JPEGEN +#endif /* JPEG */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#if defined(GPIOI) +#define LL_AHB2_GRP1_PERIPH_ALL 0xC01F1DFFU +#elif defined(GPIOE) +#define LL_AHB2_GRP1_PERIPH_ALL 0xC01F1CFFU +#elif defined(GPIOK) +#define LL_AHB2_GRP1_PERIPH_ALL 0xF73FFFFFU +#else +#define LL_AHB2_GRP1_PERIPH_ALL 0x40060C8FU +#endif /* GPIOE */ +#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN +#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN +#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN +#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN +#if defined(GPIOE) +#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN +#endif /* GPIOE */ +#if defined(GPIOF) +#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN +#endif /* GPIOF */ +#if defined(GPIOG) +#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN +#endif /* GPIOG */ +#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN +#if defined(GPIOI) +#define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN +#endif /* GPIOI */ +#if defined(GPIOJ) +#define LL_AHB2_GRP1_PERIPH_GPIOJ RCC_AHB2ENR_GPIOJEN +#endif /* GPIOJ */ +#if defined(GPIOK) +#define LL_AHB2_GRP1_PERIPH_GPIOK RCC_AHB2ENR_GPIOKEN +#endif /* GPIOK */ +#define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN +#define LL_AHB2_GRP1_PERIPH_DAC1 RCC_AHB2ENR_DAC1EN +#if defined(DCMI) +#define LL_AHB2_GRP1_PERIPH_DCMI_PSSI RCC_AHB2ENR_DCMI_PSSIEN +#endif /* DCMI */ +#if defined(AES) +#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN +#endif /* AES */ +#if defined(HASH) +#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN +#endif /* HASH */ +#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#if defined(PKA) +#define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR_PKAEN +#endif /* PKA */ +#if defined(SAES) +#define LL_AHB2_GRP1_PERIPH_SAES RCC_AHB2ENR_SAESEN +#endif /* SAES */ +#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2ENR_SRAM2EN +#if defined(SRAM3_BASE) +#define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2ENR_SRAM3EN +#endif /* SRAM3_BASE */ +#if defined(USB_OTG_FS) +#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN +#endif /* USB_OTG_FS */ +#if defined(USB_OTG_HS) +#define LL_AHB2_GRP1_PERIPH_OTGHS RCC_AHB2ENR_OTGHSEN +#endif /* USB_OTG_HS */ +#if defined(ADF1) +#define LL_AHB2_GRP1_PERIPH_ADF1 RCC_AHB2ENR_ADF1EN +#endif /* ADF1 */ +#if defined(CCB) +#define LL_AHB2_GRP1_PERIPH_CCB RCC_AHB2ENR_CCBEN +#endif /* CCB */ +#if defined(ADC3) +#define LL_AHB2_GRP1_PERIPH_ADC3 RCC_AHB2ENR_ADC3EN +#endif /* ADC3 */ +#if defined(SRAM4_BASE) +#define LL_AHB2_GRP1_PERIPH_SRAM4 RCC_AHB2ENR_SRAM4EN +#endif /* SRAM4_BASE */ +#if defined(SRAM5_BASE) +#define LL_AHB2_GRP1_PERIPH_SRAM5 RCC_AHB2ENR_SRAM5EN +#endif /* SRAM5_BASE */ +/** + * @} + */ +#if defined(AHB4PERIPH_BASE) +/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH + * @{ + */ +#if defined(OTFDEC2) +#define LL_AHB4_GRP1_PERIPH_ALL 0x00711980U +#elif defined(OCTOSPI2) +#define LL_AHB4_GRP1_PERIPH_ALL 0x00711880U +#else +#define LL_AHB4_GRP1_PERIPH_ALL 0x00111880U +#endif /* OTFDEC2 */ +#if defined(OTFDEC1) +#define LL_AHB4_GRP1_PERIPH_OTFDEC RCC_AHB4ENR_OTFDEC1EN +#endif /* OTFDEC1*/ +#define LL_AHB4_GRP1_PERIPH_SDMMC1 RCC_AHB4ENR_SDMMC1EN +#if defined(SDMMC2) +#define LL_AHB4_GRP1_PERIPH_SDMMC2 RCC_AHB4ENR_SDMMC2EN +#endif /* SDMMC2*/ +#define LL_AHB4_GRP1_PERIPH_FMC RCC_AHB4ENR_FMCEN +#define LL_AHB4_GRP1_PERIPH_OSPI1 RCC_AHB4ENR_OCTOSPI1EN +#if defined(OCTOSPI2) +#define LL_AHB4_GRP1_PERIPH_OSPI2 RCC_AHB4ENR_OCTOSPI2EN +#endif /* OCTOSPI2*/ +#if defined(OCTOSPIM) +#define LL_AHB4_GRP1_PERIPH_OSPIM RCC_AHB4ENR_OCTOSPIMEN +#endif /* OCTOSPIM*/ +#if defined(OTFDEC2) +#define LL_AHB4_GRP1_PERIPH_OTFDEC2 RCC_AHB4ENR_OTFDEC2EN +#endif /* OTFDEC2*/ +/** + * @} + */ +#endif /* AHB4PERIPH_BASE */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#if defined(USART11) +#define LL_APB1_GRP1_PERIPH_ALL 0xDFFEC9FFU +#elif defined(USART6) +#define LL_APB1_GRP1_PERIPH_ALL 0x13FEC87FU +#elif defined(OPAMP) +#define LL_APB1_GRP1_PERIPH_ALL 0xDFFFE9FFU +#else +#define LL_APB1_GRP1_PERIPH_ALL 0x01E7E833U +#endif /* TIM4 */ +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN +#if defined(TIM4) +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN +#endif /* TIM4*/ +#if defined(TIM5) +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN +#endif /* TIM5*/ +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN +#if defined(TIM12) +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN +#endif /* TIM12*/ +#if defined(TIM13) +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN +#endif /* TIM13*/ +#if defined(TIM14) +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN +#endif /* TIM14*/ +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1LENR_WWDGEN +#if defined(OPAMP1) +#define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1LENR_OPAMPEN +#endif /* OPAMP1 */ +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN +#if defined(COMP1) +#define LL_APB1_GRP1_PERIPH_COMP RCC_APB1LENR_COMPEN +#endif /* COMP1 */ +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN +#if defined(UART4) +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN +#endif /* UART4*/ +#if defined(UART5) +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN +#endif /* UART5*/ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN +#define LL_APB1_GRP1_PERIPH_I3C1 RCC_APB1LENR_I3C1EN +#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1LENR_CRSEN +#if defined(USART6) +#define LL_APB1_GRP1_PERIPH_USART6 RCC_APB1LENR_USART6EN +#endif /* USART6*/ +#if defined(USART10) +#define LL_APB1_GRP1_PERIPH_USART10 RCC_APB1LENR_USART10EN +#endif /* USART10*/ +#if defined(USART11) +#define LL_APB1_GRP1_PERIPH_USART11 RCC_APB1LENR_USART11EN +#endif /* USART11*/ +#if defined(CEC) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN +#endif /* CEC*/ +#if defined(UART7) +#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN +#endif /* UART7 */ +#if defined(UART8) +#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN +#endif /* UART8 */ +#if defined(OPAMP) +#define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1LENR_OPAMPEN +#endif /* OPAMP */ +#if defined(COMP) +#define LL_APB1_GRP1_PERIPH_COMP RCC_APB1LENR_COMPEN +#endif /* COMP */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#if defined(UART9) +#define LL_APB1_GRP2_PERIPH_ALL 0x0080022BU +#else +#define LL_APB1_GRP2_PERIPH_ALL 0x00000228U +#endif /* UART9 */ +#if defined(UART9) +#define LL_APB1_GRP2_PERIPH_UART9 RCC_APB1HENR_UART9EN +#endif /* UART9 */ +#if defined(UART12) +#define LL_APB1_GRP2_PERIPH_UART12 RCC_APB1HENR_UART12EN +#endif /* UART12*/ +#define LL_APB1_GRP2_PERIPH_DTS RCC_APB1HENR_DTSEN +#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1HENR_LPTIM2EN +#define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN +#if defined(UCPD1) +#define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1HENR_UCPD1EN +#endif /* UCPD1 */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#if defined(TIM16) +#define LL_APB2_GRP1_PERIPH_ALL 0x017F7800U +#elif defined(TIM8) +#define LL_APB2_GRP1_PERIPH_ALL 0x01097800U +#elif defined(LTDC) +#define LL_APB2_GRP1_PERIPH_ALL 0x287F7800U +#else +#define LL_APB2_GRP1_PERIPH_ALL 0x01005800U +#endif /* TIM8 */ +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#if defined(TIM8) +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#endif /* TIM8 */ +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#if defined(TIM15) +#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#endif /* TIM15 */ +#if defined(TIM16) +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#endif /* TIM16 */ +#if defined(TIM17) +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#endif /* TIM17 */ +#if defined(SPI4) +#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN +#endif /* SPI4 */ +#if defined(SPI6) +#define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN +#endif /* SPI6 */ +#if defined(SAI1) +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#endif /* SAI1 */ +#if defined(SAI2) +#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +#endif /* SAI2 */ +#if defined(USB_DRD_FS) +#define LL_APB2_GRP1_PERIPH_USB RCC_APB2ENR_USBEN +#endif /* USB_DRD_FS */ +#if defined(LTDC) +#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN +#endif /* LTDC */ +#if defined(GFXTIM) +#define LL_APB2_GRP1_PERIPH_GFXTIM RCC_APB2ENR_GFXTIMEN +#endif /* GFXTIM */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH + * @{ + */ +#if defined(SPI5) +#define LL_APB3_GRP1_PERIPH_ALL 0x0030F9E2U +#elif defined(I2C4) +#define LL_APB3_GRP1_PERIPH_ALL 0x00300AC2U +#elif defined(PLAY1) +#define LL_APB3_GRP1_PERIPH_ALL 0x00B0FBE2U +#else +#define LL_APB3_GRP1_PERIPH_ALL 0x00200A42U +#endif /* SPI5 */ +#define LL_APB3_GRP1_PERIPH_SBS RCC_APB3ENR_SBSEN +#if defined(SPI5) +#define LL_APB3_GRP1_PERIPH_SPI5 RCC_APB3ENR_SPI5EN +#endif /* SPI5 */ +#define LL_APB3_GRP1_PERIPH_LPUART1 RCC_APB3ENR_LPUART1EN +#if defined(I2C3) +#define LL_APB3_GRP1_PERIPH_I2C3 RCC_APB3ENR_I2C3EN +#endif /* I2C3 */ +#if defined(I2C4) +#define LL_APB3_GRP1_PERIPH_I2C4 RCC_APB3ENR_I2C4EN +#endif /* I2C4 */ +#if defined(I3C2) +#define LL_APB3_GRP1_PERIPH_I3C2 RCC_APB3ENR_I3C2EN +#endif /* I3C2 */ +#define LL_APB3_GRP1_PERIPH_LPTIM1 RCC_APB3ENR_LPTIM1EN +#if defined(LPTIM3) +#define LL_APB3_GRP1_PERIPH_LPTIM3 RCC_APB3ENR_LPTIM3EN +#endif /* LPTIM3 */ +#if defined(LPTIM4) +#define LL_APB3_GRP1_PERIPH_LPTIM4 RCC_APB3ENR_LPTIM4EN +#endif /* LPTIM4 */ +#if defined(LPTIM5) +#define LL_APB3_GRP1_PERIPH_LPTIM5 RCC_APB3ENR_LPTIM5EN +#endif /* LPTIM5 */ +#if defined(LPTIM6) +#define LL_APB3_GRP1_PERIPH_LPTIM6 RCC_APB3ENR_LPTIM6EN +#endif /* LPTIM6 */ +#define LL_APB3_GRP1_PERIPH_VREF RCC_APB3ENR_VREFEN +#define LL_APB3_GRP1_PERIPH_RTCAPB RCC_APB3ENR_RTCAPBEN +#if defined(PLAY1) +#define LL_APB3_GRP1_PERIPH_PLAY1 RCC_APB3ENR_PLAY1EN +#define LL_APB3_GRP1_PERIPH_PLAY1APB RCC_APB3ENR_PLAY1APBEN +#endif /* PLAY1 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHBx AHBx Branch + * @{ + */ +/** + * @brief Disable of AHBx Clock Branch + * @rmtoll CFGR2 AHB1DIS LL_AHB_DisableClock\n + * CFGR2 AHB2DIS LL_AHB_DisableClock\n + * CFGR2 AHB4DIS LL_AHB_DisableClock + * @param AHBx This parameter can be a combination of the following values: + * @arg @ref LL_AHB_BRANCH_CLK_AHB1 + * @arg @ref LL_AHB_BRANCH_CLK_AHB2 + * @arg @ref LL_AHB_BRANCH_CLK_AHB4 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB_DisableClock(uint32_t AHBx) +{ + SET_BIT(RCC->CFGR2, AHBx); +} + +/** + * @brief Enable of AHBx Clock Branch + * @rmtoll CFGR2 AHB1DIS LL_AHB_EnableClock\n + * CFGR2 AHB2DIS LL_AHB_EnableClock\n + * CFGR2 AHB4DIS LL_AHB_EnableClock + * @param AHBx This parameter can be a combination of the following values: + * @arg @ref LL_AHB_BRANCH_CLK_AHB1 + * @arg @ref LL_AHB_BRANCH_CLK_AHB2 + * @arg @ref LL_AHB_BRANCH_CLK_AHB4 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB_EnableClock(uint32_t AHBx) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR2, AHBx); + /* Delay after AHBx clock branch enabling */ + tmpreg = READ_BIT(RCC->CFGR2, AHBx); + (void)tmpreg; +} + +/** + * @brief Check if AHBx clock branch is disabled or not + * @rmtoll CFGR2 AHB1DIS LL_AHB_IsDisabledClock\n + * CFGR2 AHB2DIS LL_AHB_IsDisabledClock\n + * CFGR2 AHB4DIS LL_AHB_IsDisabledClock + * @param AHBx This parameter can be a combination of the following values: + * @arg @ref LL_AHB_BRANCH_CLK_AHB1 + * @arg @ref LL_AHB_BRANCH_CLK_AHB2 + * @arg @ref LL_AHB_BRANCH_CLK_AHB4 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval State of AHBx bus (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB_IsDisabledClock(uint32_t AHBx) +{ + return ((READ_BIT(RCC->CFGR2, AHBx) == AHBx) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APBx APBx Branch + * @{ + */ +/** + * @brief Disable APBx Clock Branch + * @rmtoll CFGR2 APB1DIS LL_APB_DisableClock\n + * CFGR2 APB2DIS LL_APB_DisableClock\n + * CFGR2 APB3DIS LL_APB_DisableClock + * @param APBx This parameter can be a combination of the following values: + * @arg @ref LL_APB_BRANCH_CLK_APB1 + * @arg @ref LL_APB_BRANCH_CLK_APB2 + * @arg @ref LL_APB_BRANCH_CLK_APB3 + * @retval None + */ +__STATIC_INLINE void LL_APB_DisableClock(uint32_t APBx) +{ + SET_BIT(RCC->CFGR2, APBx); +} + +/** + * @brief Enable of APBx Clock Branch + * @rmtoll CFGR2 APB1DIS LL_APB_EnableClock\n + * CFGR2 APB2DIS LL_APB_EnableClock\n + * CFGR2 APB3DIS LL_APB_EnableClock + * @param APBx This parameter can be a combination of the following values: + * @arg @ref LL_APB_BRANCH_CLK_APB1 + * @arg @ref LL_APB_BRANCH_CLK_APB2 + * @arg @ref LL_APB_BRANCH_CLK_APB3 + * @retval None + */ +__STATIC_INLINE void LL_APB_EnableClock(uint32_t APBx) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR2, APBx); + /* Delay after APBx clock branch enabling */ + tmpreg = READ_BIT(RCC->CFGR2, APBx); + (void)tmpreg; +} + +/** + * @brief Check if APBx clock branch is disabled or not + * @rmtoll CFGR2 APB1DIS LL_APB_IsDisabledClock\n + * CFGR2 APB2DIS LL_APB_IsDisabledClock\n + * CFGR2 APB3DIS LL_APB_IsDisabledClock + * @param APBx This parameter can be a combination of the following values: + * @arg @ref LL_APB_BRANCH_CLK_APB1 + * @arg @ref LL_APB_BRANCH_CLK_APB2 + * @arg @ref LL_APB_BRANCH_CLK_APB3 + * @retval State of APBx bus (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB_IsDisabledClock(uint32_t APBx) +{ + return ((READ_BIT(RCC->CFGR2, APBx) == APBx) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 Peripherals + * @{ + */ +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPDMA2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR FLITFEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR RAMCFGEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHTXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHRXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR TZSC1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR BKPRAMEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DCACHE1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock + * AHB1ENR MDF1EN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPDMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR RAMCFGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHTXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHRXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHCKEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR TZSC1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR BKPRAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DCACHE1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock + * AHB1ENR MDF11EN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPDMA2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR FLITFEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR RAMCFGEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHTXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHRXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHCKEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR TZSC1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR BKPRAMEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DCACHE1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock + * AHB1ENR MDF1EN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPDMA1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPDMA2RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR CORDICRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR FMACRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR RAMCFGRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ETHRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR TZSC1RST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPDMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPDMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR CORDICRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR FMACRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR RAMCFGRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ETHRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR TZSC1RST LL_AHB1_GRP1_ReleaseReset + * AHB1RSTR MDF1RST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripheral clocks in Sleep mode + * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR GPDMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR CORDICLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR FMACLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR RAMCFGLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETHLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETHTXLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETHRXLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETHCKLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR TZSC1LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR BKPRAMLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR DCACHE1LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockSleep + * AHB1LPENR MDF1LPEN LL_AHB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clocks in Sleep mode is enabled or not + * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR GPDMA2LPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR CORDICLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR FMACLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR RAMCFGLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR ETHLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR ETHTXLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR ETHRXLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR ETHCKLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR TZSC1LPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR BKPRAMLPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR DCACHE1LPEN LL_AHB1_GRP1_IsEnabledClockSleep\n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_IsEnabledClockSleep + * AHB1LPENR MDF11LPEN LL_AHB1_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1LPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripheral clocks in Sleep mode + * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR GPDMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR CORDICLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR FMACLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR RAMCFGLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETHLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETHTXLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETHRXLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETHCKLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR TZSC1LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR BKPRAMLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR DCACHE1LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockSleep + * AHB1LPENR MDF1LPEN LL_AHB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB2 AHB2 Peripherals + * @{ + */ +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR DAC1EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR DCMI_PSSIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR PKAEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR SAESEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR SRAM2EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR SRAM3EN LL_AHB2_GRP1_EnableClock + * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock + * AHB2ENR OTGHSEN LL_AHB2_GRP1_EnableClock + * AHB2ENR ADF1EN LL_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR DAC1EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR DCMI_PSSIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR PKAEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SAESEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SRAM3EN LL_AHB2_GRP1_IsEnabledClock + * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock + * AHB2ENR OTGHSEN LL_AHB2_GRP1_IsEnabledClock + * AHB2ENR ADF1EN LL_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR DAC1EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR DCMI_PSSIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR PKAEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR SAESEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR SRAM2EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR SRAM3EN LL_AHB2_GRP1_DisableClock + * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock + * AHB2ENR OTGHSEN LL_AHB2_GRP1_DisableClock + * AHB2ENR ADF1EN LL_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RST GPIOARST LL_AHB2_GRP1_ForceReset\n + * AHB2RST GPIOBRST LL_AHB2_GRP1_ForceReset\n + * AHB2RST GPIOCRST LL_AHB2_GRP1_ForceReset\n + * AHB2RST GPIODRST LL_AHB2_GRP1_ForceReset\n + * AHB2RST GPIOERST LL_AHB2_GRP1_ForceReset\n + * AHB2RST GPIOFRST LL_AHB2_GRP1_ForceReset\n + * AHB2RST GPIOGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RST GPIOHRST LL_AHB2_GRP1_ForceReset\n + * AHB2RST GPIOIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RST ADCRST LL_AHB2_GRP1_ForceReset\n + * AHB2RST DAC1RST LL_AHB2_GRP1_ForceReset\n + * AHB2RST DCMI_PSSIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RST AESRST LL_AHB2_GRP1_ForceReset\n + * AHB2RST HASHRST LL_AHB2_GRP1_ForceReset\n + * AHB2RST RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RST PKARST LL_AHB2_GRP1_ForceReset\n + * AHB2RST SAESRST LL_AHB2_GRP1_ForceReset + * AHB2RST OTGFSRST LL_AHB2_GRP1_ForceReset + * AHB2RST OTGHSRST LL_AHB2_GRP1_ForceReset + * AHB2RST ADF1RST LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RST GPIOARST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST GPIOBRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST GPIOCRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST GPIODRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST GPIOERST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST GPIOFRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST GPIOGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST GPIOHRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST GPIOIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST ADCRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST DAC1RST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST DCMI_PSSIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST AESRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST HASHRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST PKARST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RST SAESRST LL_AHB2_GRP1_ReleaseReset + * AHB2RST OTGFSRST LL_AHB2_GRP1_ReleaseReset + * AHB2RST OTGHSRST LL_AHB2_GRP1_ReleaseReset + * AHB2RST ADF1RST LL_AHB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Enable AHB2 peripheral clocks in Sleep mode + * @rmtoll AHB2LPENR GPIOALPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR GPIOBLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR GPIOCLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR GPIODLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR GPIOELPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR GPIOFLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR GPIOGLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR GPIOHLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR GPIOILPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR ADCLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR DAC1LPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR DCMI_PSSILPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR PKALPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR SAESLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep + * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockSleep + * AHB2LPENR OTGHSLPEN LL_AHB2_GRP1_EnableClockSleep + * AHB2LPENR ADF1LPEN LL_AHB2_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clocks in Sleep mode is enabled or not + * @rmtoll AHB2LPENR GPIOALPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR GPIOBLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR GPIOCLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR GPIODLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR GPIOELPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR GPIOFLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR GPIOGLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR GPIOHLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR GPIOILPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR ADCLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR DAC1LPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR DCMI_PSSILPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR PKALPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR SAESLPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR SRAM2LPEN LL_AHB2_GRP1_IsEnabledClockSleep\n + * AHB2LPENR SRAM3LPEN LL_AHB2_GRP1_IsEnabledClockSleep + * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_IsEnabledClockSleep + * AHB2LPENR OTGHSLPEN LL_AHB2_GRP1_IsEnabledClockSleep + * AHB2LPENR ADF1LPEN LL_AHB2_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2LPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2 peripheral clocks in Sleep mode + * @rmtoll AHB2LPENR GPIOALPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR GPIOBLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR GPIOCLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR GPIODLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR GPIOELPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR GPIOFLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR GPIOGLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR GPIOHLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR GPIOILPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR ADCLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR DAC1LPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR DCMI_PSSILPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR PKALPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR SAESLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep + * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockSleep + * AHB2LPENR OTGHSLPEN LL_AHB2_GRP1_DisableClockSleep + * AHB2LPENR ADF1LPEN LL_AHB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC + * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADF1 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2LPENR, Periphs); +} + +/** + * @} + */ + +#if defined(AHB4PERIPH_BASE) +/** @defgroup BUS_LL_EF_AHB4 AHB4 Peripherals + * @{ + */ +/** + * @brief Enable AHB4 peripherals clock. + * @rmtoll AHB4ENR OTFDEC1EN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR SDMMC1EN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR SDMMC2EN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR FMCEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR OCTOSPI1EN LL_AHB4_GRP1_EnableClock + * AHB4ENR OCTOSPI2EN LL_AHB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_FMC + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB4 peripheral clock is enabled or not + * @rmtoll AHB4ENR OTFDEC1EN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR SDMMC1EN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR SDMMC2EN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR FMCEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR OCTOSPI1EN LL_AHB4_GRP1_IsEnabledClock + * AHB4ENR OCTOSPI2EN LL_AHB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_FMC + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB4 peripherals clock. + * @rmtoll AHB4ENR OTFDEC1EN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR SDMMC1EN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR SDMMC2EN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR FMCEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR OCTOSPI1EN LL_AHB4_GRP1_DisableClock + * AHB4ENR OCTOSPI2EN LL_AHB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_FMC + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4ENR, Periphs); +} + +/** + * @brief Force AHB4 peripherals reset. + * @rmtoll AHB4RSTR OTFDEC1RST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR SDMMC1RST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR SDMMC2RST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR FMCRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR OCTOSPI1RST LL_AHB4_GRP1_ForceReset + * AHB4RSTR OCTOSPI2RST LL_AHB4_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_FMC + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB4RSTR, Periphs); +} + +/** + * @brief Release AHB4 peripherals reset. + * @rmtoll AHB4RSTR OTFDEC1RST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR SDMMC1RST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR SDMMC2RST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR FMCRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR OCTOSPI1RST LL_AHB4_GRP1_ReleaseReset + * AHB4RSTR OCTOSPI2RST LL_AHB4_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_FMC + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4RSTR, Periphs); +} + +/** + * @brief Enable AHB4 peripheral clocks in Sleep mode + * @rmtoll AHB4LPENR OTFDEC1LPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR SDMMC1LPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR SDMMC2LPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR FMCLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR OCTOSPI1LPEN LL_AHB4_GRP1_EnableClockSleep + * AHB4LPENR OCTOSPI2LPEN LL_AHB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_FMC + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB4 peripheral clocks in Sleep mode is enabled or not + * @rmtoll AHB4LPENR OTFDEC1LPEN LL_AHB4_GRP1_IsEnabledClockSleep\n + * AHB4LPENR SDMMC1LPEN LL_AHB4_GRP1_IsEnabledClockSleep\n + * AHB4LPENR SDMMC2LPEN LL_AHB4_GRP1_IsEnabledClockSleep\n + * AHB4LPENR FMCLPEN LL_AHB4_GRP1_IsEnabledClockSleep\n + * AHB4LPENR OCTOSPI1LPEN LL_AHB4_GRP1_IsEnabledClockSleep + * AHB4LPENR OCTOSPI2LPEN LL_AHB4_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_FMC + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB4LPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB4 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB4LPENR OTFDEC1LPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR SDMMC1LPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR SDMMC2LPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR FMCLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR OCTOSPI1LPEN LL_AHB4_GRP1_DisableClockSleep + * AHB4LPENR OCTOSPI2LPEN LL_AHB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_OTFDEC + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB4_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB4_GRP1_PERIPH_FMC + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI1 + * @arg @ref LL_AHB4_GRP1_PERIPH_OSPI2 + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4LPENR, Periphs); +} + +/** + * @} + */ +#endif /* AHB4PERIPH_BASE */ + +/** @defgroup BUS_LL_EF_APB1 APB1 Peripherals + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM12EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM13EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1LENR WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1LENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART4EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART5EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I3C1EN LL_APB1_GRP1_EnableClock\n + * APB1LENR CRSEN LL_APB1_GRP1_EnableClock\n + * APB1LENR USART6EN LL_APB1_GRP1_EnableClock\n + * APB1LENR USART10EN LL_APB1_GRP1_EnableClock\n + * APB1LENR USART11EN LL_APB1_GRP1_EnableClock\n + * APB1LENR CECEN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART7EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART8EN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1HENR UART9EN LL_APB1_GRP2_EnableClock\n + * APB1HENR UART12EN LL_APB1_GRP2_EnableClock\n + * APB1HENR DTSEN LL_APB1_GRP2_EnableClock\n + * APB1HENR LPTIM2EN LL_APB1_GRP2_EnableClock\n + * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock\n + * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock\n + * APB1HENR UCPD1EN LL_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_DTS + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1HENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1HENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I3C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART10EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART11EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1HENR UART9EN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR UART12EN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR DTSEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR LPTIM2EN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR UCPD1EN LL_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_DTS + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1LENR WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1LENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART4EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART5EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I3C1EN LL_APB1_GRP1_DisableClock\n + * APB1LENR CRSEN LL_APB1_GRP1_DisableClock\n + * APB1LENR USART6EN LL_APB1_GRP1_DisableClock\n + * APB1LENR USART10EN LL_APB1_GRP1_DisableClock\n + * APB1LENR USART11EN LL_APB1_GRP1_DisableClock\n + * APB1LENR CECEN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART7EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART8EN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LENR, Periphs); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1HENR UART9EN LL_APB1_GRP2_DisableClock\n + * APB1HENR UART12EN LL_APB1_GRP2_DisableClock\n + * APB1HENR DTSEN LL_APB1_GRP2_DisableClock\n + * APB1HENR LPTIM2EN LL_APB1_GRP2_DisableClock\n + * APB1HENR FDCANEN LL_APB1_GRP2_DisableClock\n + * APB1HENR UCPD1EN LL_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_DTS + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1HENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I3C1RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR CRSRST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR USART6RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR USART10RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR USART11RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR CECRST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1LRSTR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1HRSTR UART9RST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR UART12RST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR DTSRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR LPTIM2RST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR UCPD1RST LL_APB1_GRP2_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_DTS + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1HRSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I3C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR USART6RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR USART10RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR USART11RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LRSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1HRSTR UART9RST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR UART12RST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR DTSRST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR LPTIM2RST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR FDCAN LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR UCPD1RST LL_APB1_GRP2_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_DTS + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1HRSTR, Periphs); +} + +/** + * @brief Enable APB1 peripheral clocks in Sleep mode + * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR WWDGLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I3C1LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR CRSLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART6LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART10LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART11LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clocks in Sleep mode is enabled or not + * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR TIM3LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR TIM4LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR TIM5LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR TIM6LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR TIM7LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR WWDGLPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR SPI2LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR SPI3LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR USART2LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR USART3LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR UART4LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR UART5LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR I2C1LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR I2C2LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR I3C1LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR CRSLPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR USART6LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR USART10LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR USART11LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR CECLPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR UART7LPEN LL_APB1_GRP1_IsEnabledClockSleep\n + * APB1LLPENR UART8LPEN LL_APB1_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART11 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1LLPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripheral clocks in Sleep mode + * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR WWDGLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I3C1LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR CRSLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART6LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART10LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART11LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART11 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LLPENR, Periphs); +} + +/** + * @brief Enable APB1 peripheral clocks in Sleep mode + * @rmtoll APB1HLPENR UART9LPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR UART12LPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR DTSLPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR LPTIM2LPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR FDCAN12LPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR FDCAN1LPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR UCPD1LPEN LL_APB1_GRP2_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_DTS + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1HLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clocks in Sleep mode is enabled or not + * @rmtoll APB1HLPENR UART9LPEN LL_APB1_GRP2_IsEnabledClockSleep\n + * APB1HLPENR UART12LPEN LL_APB1_GRP2_IsEnabledClockSleep\n + * APB1HLPENR DTSLPEN LL_APB1_GRP2_IsEnabledClockSleep\n + * APB1HLPENR LPTIM2LPEN LL_APB1_GRP2_IsEnabledClockSleep\n + * APB1HLPENR FDCAN12LPEN LL_APB1_GRP2_IsEnabledClockSleep\n + * APB1HLPENR FDCAN1LPEN LL_APB1_GRP2_IsEnabledClockSleep\n + * APB1HLPENR UCPD1LPEN LL_APB1_GRP2_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_DTS + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1HLPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripheral clocks in Sleep mode + * @rmtoll APB1HLPENR UART9LPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR UART12LPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR DTSLPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR LPTIM2LPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR FDCAN12LPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR FDCAN1LPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR UCPD1LPEN LL_APB1_GRP2_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_UART9 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_UART12 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_DTS + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1HLPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 Peripherals + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USBEN LL_APB2_GRP1_EnableClock + * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USBEN LL_APB2_GRP1_IsEnabledClock + * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USBEN LL_APB2_GRP1_DisableClock + * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USBRST LL_APB2_GRP1_ForceReset + * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USBRST LL_APB2_GRP1_ReleaseReset + * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripheral clocks in Sleep mode + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USBLPEN LL_APB2_GRP1_EnableClockSleep + * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); + (void)tmpreg; +} + + +/** + * @brief Check if APB2 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2LPENR SPI6LPEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_IsEnabledClockSleep\n + * APB2LPENR USBLPEN LL_APB2_GRP1_IsEnabledClockSleep + * APB2LPENR LTDCLPEN LL_APB2_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2LPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripheral clocks in Sleep mode + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USBLPEN LL_APB2_GRP1_DisableClockSleep + * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2LPENR, Periphs); +} + +/** + * @} + */ + + +/** @defgroup BUS_LL_EF_APB3 APB3 Peripherals + */ + +/** + * @brief Enable APB3 peripherals clock. + * @rmtoll APB3ENR SBSEN LL_APB3_GRP1_EnableClock\n + * APB3ENR SPI5EN LL_APB3_GRP1_EnableClock\n + * APB3ENR LPUART1EN LL_APB3_GRP1_EnableClock\n + * APB3ENR I2C3EN LL_APB3_GRP1_EnableClock\n + * APB3ENR I2C4EN LL_APB3_GRP1_EnableClock\n + * APB3ENR LPTIM1EN LL_APB3_GRP1_EnableClock\n + * APB3ENR LPTIM3EN LL_APB3_GRP1_EnableClock\n + * APB3ENR LPTIM4EN LL_APB3_GRP1_EnableClock\n + * APB3ENR LPTIM5EN LL_APB3_GRP1_EnableClock\n + * APB3ENR LPTIM6EN LL_APB3_GRP1_EnableClock\n + * APB3ENR VREFEN LL_APB3_GRP1_EnableClock\n + * APB3ENR RTCAPBEN LL_APB3_GRP1_EnableClock + * APB3ENR PLAY1EN LL_APB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB3_GRP1_PERIPH_PLAY1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB3 peripheral clock is enabled or not + * @rmtoll APB3ENR SBSEN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR SPI5EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR LPUART1EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR I2C3EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR I2C4EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR LPTIM1EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR LPTIM3EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR LPTIM4EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR LPTIM5EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR LPTIM6EN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR VREFEN LL_APB3_GRP1_IsEnabledClock\n + * APB3ENR RTCAPBEN LL_APB3_GRP1_IsEnabledClock + * APB3ENR PLAY1EN LL_APB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB3_GRP1_PERIPH_PLAY1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB3ENR SBSEN LL_APB3_GRP1_DisableClock\n + * APB3ENR SPI5EN LL_APB3_GRP1_DisableClock\n + * APB3ENR LPUART1EN LL_APB3_GRP1_DisableClock\n + * APB3ENR I2C3EN LL_APB3_GRP1_DisableClock\n + * APB3ENR I2C4EN LL_APB3_GRP1_DisableClock\n + * APB3ENR LPTIM1EN LL_APB3_GRP1_DisableClock\n + * APB3ENR LPTIM3EN LL_APB3_GRP1_DisableClock\n + * APB3ENR LPTIM4EN LL_APB3_GRP1_DisableClock\n + * APB3ENR LPTIM5EN LL_APB3_GRP1_DisableClock\n + * APB3ENR LPTIM6EN LL_APB3_GRP1_DisableClock\n + * APB3ENR VREFEN LL_APB3_GRP1_DisableClock\n + * APB3ENR RTCAPBEN LL_APB3_GRP1_DisableClock + * APB3ENR PLAY1EN LL_APB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB3_GRP1_PERIPH_PLAY1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3ENR, Periphs); +} + +/** + * @brief Force APB3 peripherals reset. + * @rmtoll APB3RSTR SPI5RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR LPUART1RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR I2C3RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR I2C4RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR LPTIM1RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR LPTIM3RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR LPTIM4RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR LPTIM5RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR LPTIM6RST LL_APB3_GRP1_ForceReset\n + * APB3RSTR VREFRST LL_APB3_GRP1_ForceReset + * APB3RSTR PLAY1 LL_APB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_PLAY1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB3RSTR, Periphs); +} + +/** + * @brief Release APB3 peripherals reset. + * @rmtoll APB3RSTR SPI5RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR LPUART1RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR I2C3RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR I2C4RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR LPTIM1RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR LPTIM3RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR LPTIM4RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR LPTIM5RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR LPTIM6RST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR VREFRST LL_APB3_GRP1_ReleaseReset + * APB3RSTR PLAY1 LL_APB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_PLAY1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3RSTR, Periphs); +} + +/** + * @brief Enable APB3 peripheral clocks in Sleep mode + * @rmtoll APB3LPENR SBSLPEN LL_APB3_GRP1_EnableClockSleep\n + * APB3LPENR SPI5LPEN LL_APB3_GRP1_EnableClockSleep\n + * APB3LPENR LPUART1LPEN LL_APB3_GRP1_EnableClockSleep\n + * APB3LPENR I2C3LPEN LL_APB3_GRP1_EnableClockSleep\n + * APB3LPENR I2C4LPEN LL_APB3_GRP1_EnableClockSleep\n + * APB3LPENR LPTIM1LPEN LL_APB3_GRP1_EnableClockSleep\n + * APB3LPENR LPTIM3LPEN LL_APB3_GRP1_EnableClockSleep\n + * APB3LPENR LPTIM4LPEN LL_APB3_GRP1_EnableClockSleep\n + * APB3LPENR LPTIM5LPEN LL_APB3_GRP1_EnableClockSleep\n + * APB3LPENR LPTIM6LPEN LL_APB3_GRP1_EnableClockSleep\n + * APB3LPENR VREFLPEN LL_APB3_GRP1_EnableClockSleep\n + * APB3LPENR RTCAPBLPEN LL_APB3_GRP1_EnableClockSleep + * APB3LPENR PAYLPEN LL_APB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB3_GRP1_PERIPH_PLAY1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3LPENR, Periphs); + (void)tmpreg; +} + + +/** + * @brief Check if APB3 peripheral clocks in Sleep mode is enabled or not + * @rmtoll APB3LPENR SBSLPEN LL_APB3_GRP1_IsEnabledClockSleep\n + * APB3LPENR SPI5LPEN LL_APB3_GRP1_IsEnabledClockSleep\n + * APB3LPENR LPUART1LPEN LL_APB3_GRP1_IsEnabledClockSleep\n + * APB3LPENR I2C3LPEN LL_APB3_GRP1_IsEnabledClockSleep\n + * APB3LPENR I2C4LPEN LL_APB3_GRP1_IsEnabledClockSleep\n + * APB3LPENR LPTIM1LPEN LL_APB3_GRP1_IsEnabledClockSleep\n + * APB3LPENR LPTIM3LPEN LL_APB3_GRP1_IsEnabledClockSleep\n + * APB3LPENR LPTIM4LPEN LL_APB3_GRP1_IsEnabledClockSleep\n + * APB3LPENR LPTIM5LPEN LL_APB3_GRP1_IsEnabledClockSleep\n + * APB3LPENR LPTIM6LPEN LL_APB3_GRP1_IsEnabledClockSleep\n + * APB3LPENR VREFLPEN LL_APB3_GRP1_IsEnabledClockSleep\n + * APB3LPENR RTCAPBLPEN LL_APB3_GRP1_IsEnabledClockSleep + * APB3LPENR PLAY1LPEN LL_APB3_GRP1_IsEnabledClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB3_GRP1_PERIPH_PLAY1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClockSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB3LPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB3 peripheral clocks in Sleep mode + * @rmtoll APB3LPENR SBSLPEN LL_APB3_GRP1_DisableClockSleep\n + * APB3LPENR SPI5LPEN LL_APB3_GRP1_DisableClockSleep\n + * APB3LPENR LPUART1LPEN LL_APB3_GRP1_DisableClockSleep\n + * APB3LPENR I2C3LPEN LL_APB3_GRP1_DisableClockSleep\n + * APB3LPENR I2C4LPEN LL_APB3_GRP1_DisableClockSleep\n + * APB3LPENR LPTIM1LPEN LL_APB3_GRP1_DisableClockSleep\n + * APB3LPENR LPTIM3LPEN LL_APB3_GRP1_DisableClockSleep\n + * APB3LPENR LPTIM4LPEN LL_APB3_GRP1_DisableClockSleep\n + * APB3LPENR LPTIM5LPEN LL_APB3_GRP1_DisableClockSleep\n + * APB3LPENR LPTIM6LPEN LL_APB3_GRP1_DisableClockSleep\n + * APB3LPENR VREFLPEN LL_APB3_GRP1_DisableClockSleep\n + * APB3LPENR RTCAPBLPEN LL_APB3_GRP1_DisableClockSleep + * APB3LPENR PLAY1LPEN LL_APB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_ALL + * @arg @ref LL_APB3_GRP1_PERIPH_SBS + * @arg @ref LL_APB3_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_I3C2 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM3 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM6 (*) + * @arg @ref LL_APB3_GRP1_PERIPH_VREF + * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB3_GRP1_PERIPH_PLAY1 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3LPENR, Periphs); +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H5xx_LL_BUS_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h new file mode 100644 index 00000000..7421801f --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h @@ -0,0 +1,1388 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick with + HCLK source or @ref LL_Init1msTick_HCLK_Div8, @ref LL_Init1msTick_LSI or + @ref LL_Init1msTick_LSE with external source + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + (+) API to enable and disable the MPU secure and non-secure + (+) API to configure the region of MPU secure and non-secure + (+) API to configure the attributes region of MPU secure and non-secure + + @endverbatim + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_LL_CORTEX_H +#define STM32H5xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes + * @{ + */ +/* Register MPU_RBAR (Cortex-M33) : bits [4:0] */ +#define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_EXTERNAL 0x00000000U /*!< External clock source selected as SysTick + clock source */ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick + clock source */ +/** Legacy definitions for backward compatibility purpose + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 LL_SYSTICK_CLKSOURCE_EXTERNAL +/** + */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +#define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes + * @{ + */ +/* Device memory attributes */ +#define LL_MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define LL_MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* Non-cacheable memory attribute */ +#define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */ +#define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */ +/* - transient mode attribute */ +#define LL_MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */ +#define LL_MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */ +/* - allocation attribute */ +#define LL_MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */ +#define LL_MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */ +#define LL_MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */ +#define LL_MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable + * @{ + */ +#define LL_MPU_REGION_ENABLE 1U /*!< MPU region enabled */ +#define LL_MPU_REGION_DISABLE 0U /*!< MPU region disabled */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< Execute attribute */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< Execute never attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable + * @{ + */ +#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< Not shareable attribute */ +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< Outer shareable attribute */ +#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< Inner shareable attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes + * @{ + */ +#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< Read/write privileged-only attribute */ +#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< Read/write privileged/unprivileged attribute */ +#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< Read-only privileged-only attribute */ +#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< Read-only privileged/unprivileged attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0U /*!< MPU region number 0 */ +#define LL_MPU_REGION_NUMBER1 1U /*!< MPU region number 1 */ +#define LL_MPU_REGION_NUMBER2 2U /*!< MPU region number 2 */ +#define LL_MPU_REGION_NUMBER3 3U /*!< MPU region number 3 */ +#define LL_MPU_REGION_NUMBER4 4U /*!< MPU region number 4 */ +#define LL_MPU_REGION_NUMBER5 5U /*!< MPU region number 5 */ +#define LL_MPU_REGION_NUMBER6 6U /*!< MPU region number 6 */ +#define LL_MPU_REGION_NUMBER7 7U /*!< MPU region number 7 */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define LL_MPU_REGION_NUMBER8 8U /*!< MPU region number 8 */ +#define LL_MPU_REGION_NUMBER9 9U /*!< MPU region number 9 */ +#define LL_MPU_REGION_NUMBER10 10U /*!< MPU region number 10 */ +#define LL_MPU_REGION_NUMBER11 11U /*!< MPU region number 11 */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index + * @{ + */ +#define LL_MPU_ATTRIBUTES_NUMBER0 0U /*!< MPU attribute number 0 */ +#define LL_MPU_ATTRIBUTES_NUMBER1 1U /*!< MPU attribute number 1 */ +#define LL_MPU_ATTRIBUTES_NUMBER2 2U /*!< MPU attribute number 2 */ +#define LL_MPU_ATTRIBUTES_NUMBER3 3U /*!< MPU attribute number 3 */ +#define LL_MPU_ATTRIBUTES_NUMBER4 4U /*!< MPU attribute number 4 */ +#define LL_MPU_ATTRIBUTES_NUMBER5 5U /*!< MPU attribute number 5 */ +#define LL_MPU_ATTRIBUTES_NUMBER6 6U /*!< MPU attribute number 6 */ +#define LL_MPU_ATTRIBUTES_NUMBER7 7U /*!< MPU attribute number 7 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @brief CORTEX SYSTICK LL module driver + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @arg @ref LL_HANDLER_FAULT_SECURE (*) + * + * (*) value applicable in secure when the system implements the security. + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @arg @ref LL_HANDLER_FAULT_SECURE (*) + * + * (*) value applicable in secure when the system implements the security. + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Architecture version + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xF for Cortex-M33 ("ARMv8-M with Main Extension") + */ +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xD21 for Cortex-M33 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param MPU_Control This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + + /* Enable the MPU*/ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable non-secure MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param MPU_Control This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + + /* Enable the MPU*/ + MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */ + + /* Disable MPU */ + WRITE_REG(MPU->CTRL, 0U); + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable the non-secure MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable_NS(void) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */ + + /* Disable MPU*/ + WRITE_REG(MPU_NS->CTRL, 0U); + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} +#endif /* __ARM_FEATURE_CMSE */ + + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Check if non-secure MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void) +{ + return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 (*) + * @arg @ref LL_MPU_REGION_NUMBER9 (*) + * @arg @ref LL_MPU_REGION_NUMBER10 (*) + * @arg @ref LL_MPU_REGION_NUMBER11 (*) + * @note cortex-M33 supports 12 secure and 8 non secure regions. + * (*) : For MPU_S only + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Enable the MPU region */ + SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Check if MPU region is enabled or not + * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 (*) + * @arg @ref LL_MPU_REGION_NUMBER9 (*) + * @arg @ref LL_MPU_REGION_NUMBER10 (*) + * @arg @ref LL_MPU_REGION_NUMBER11 (*) + * @note cortex-M33 supports 12 secure and 8 non secure regions. + * (*) : For MPU_S only + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region) +{ + /* Set region index */ + WRITE_REG(MPU->RNR, Region); + + /* Return MPU region status */ + return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable a non-secure MPU region + * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Enable the MPU region */ + SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Check if non-secure MPU region is enabled or not + * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 non secure regions. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region_NS(uint32_t Region) +{ + /* Set region index */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Return non-secure MPU region status */ + return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Disable a MPU region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RLAR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 (*) + * @arg @ref LL_MPU_REGION_NUMBER9 (*) + * @arg @ref LL_MPU_REGION_NUMBER10 (*) + * @arg @ref LL_MPU_REGION_NUMBER11 (*) + * @note cortex-M33 supports 12 secure and 8 non secure regions. + * (*) : For MPU_S only + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Disable the MPU region */ + CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable a non-secure MPU region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n + * MPU_RLAR ENABLE LL_MPU_DisableRegion_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Disable the MPU region */ + CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure and enable a MPU region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RLAR ADDR LL_MPU_ConfigRegion\n + * MPU_RBAR XN LL_MPU_ConfigRegion\n + * MPU_RBAR AP LL_MPU_ConfigRegion\n + * MPU_RBAR SH LL_MPU_ConfigRegion\n + * MPU_RLAR EN LL_MPU_ConfigRegion\n + * MPU_RLAR AttrIndx LL_MPU_ConfigRegion\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 (*) + * @arg @ref LL_MPU_REGION_NUMBER9 (*) + * @arg @ref LL_MPU_REGION_NUMBER10 (*) + * @arg @ref LL_MPU_REGION_NUMBER11 (*) + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @param AttrIndx This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 12 secure and 8 non secure regions. + * (*) : For MPU_S only + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress, + uint32_t LimitAddress) +{ + /* Set region index */ + WRITE_REG(MPU->RNR, Region); + + /* Set region base address and region access attributes */ + WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); + + /* Set region limit address, memory attributes index and enable region */ + WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | (AttrIndx << 1) | MPU_RLAR_EN_Msk)); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure and enable a non-secure MPU region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n + * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n + * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n + * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n + * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n + * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n + * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @param AttrIndx This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 12 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, + uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set region base address and region access attributes */ + WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); + + /* Set region limit address, memory attributes index and enable region */ + WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk)); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure a MPU region address range + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n + * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n + * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 (*) + * @arg @ref LL_MPU_REGION_NUMBER9 (*) + * @arg @ref LL_MPU_REGION_NUMBER10 (*) + * @arg @ref LL_MPU_REGION_NUMBER11 (*) + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 12 secure and 8 non secure regions. + * (*) : For MPU_S only + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Modify region base address */ + MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); + + /* Modify region limit address */ + MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure a non-secure MPU region address range + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n + * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n + * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 12 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); + + /* Set limit address */ + MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure a MPU attributes index + * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes\n + * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes\n + * @param AttIndex This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes) +{ + /* When selected index is in range [0;3] */ + if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) + { + /* Modify Attr field of MPU_MAIR0 accordingly */ + MODIFY_REG(MPU->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + } + /* When selected index is in range [4;7] */ + else + { + /* Modify Attr field of MPU_MAIR1 accordingly */ + MODIFY_REG(MPU->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure a non-secure MPU attributes index + * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes_NS\n + * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes_NS\n + * @param AttIndex This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes) +{ + /* When selected index is in range [0;3] */ + if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) + { + /* Modify Attr field of MPU_MAIR0_NS accordingly */ + MODIFY_REG(MPU_NS->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + } + /* When selected index is in range [4;7] */ + else + { + /* Modify Attr field of MPU_MAIR1_NS accordingly */ + MODIFY_REG(MPU_NS->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + } +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure a MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n + * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 (*) + * @arg @ref LL_MPU_REGION_NUMBER9 (*) + * @arg @ref LL_MPU_REGION_NUMBER10 (*) + * @arg @ref LL_MPU_REGION_NUMBER11 (*) + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 12 secure and 8 non secure regions. + * (*) : For MPU_S only + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set limit address */ + MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Get a MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 (*) + * @arg @ref LL_MPU_REGION_NUMBER9 (*) + * @arg @ref LL_MPU_REGION_NUMBER10 (*) + * @arg @ref LL_MPU_REGION_NUMBER11 (*) + * (*) : For MPU_S only + * @retval Value of the region limit address + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Configure a MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n + * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 (*) + * @arg @ref LL_MPU_REGION_NUMBER9 (*) + * @arg @ref LL_MPU_REGION_NUMBER10 (*) + * @arg @ref LL_MPU_REGION_NUMBER11 (*) + * @param BaseAddress Value of region base address + * @note cortex-M33 supports 12 secure and 8 non secure regions. + * (*) : For MPU_S only + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Get a MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 (*) + * @arg @ref LL_MPU_REGION_NUMBER9 (*) + * @arg @ref LL_MPU_REGION_NUMBER10 (*) + * @arg @ref LL_MPU_REGION_NUMBER11 (*) + * @note cortex-M33 supports 12 secure and 8 non secure regions. + * (*) : For MPU_S only + * @retval Value of the region base address + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Configure a MPU region access attributes and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n + * MPU_RBAR XN LL_MPU_SetRegionAccess\n + * MPU_RBAR AP LL_MPU_SetRegionAccess\n + * MPU_RBAR SH LL_MPU_SetRegionAccess\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 (*) + * @arg @ref LL_MPU_REGION_NUMBER9 (*) + * @arg @ref LL_MPU_REGION_NUMBER10 (*) + * @arg @ref LL_MPU_REGION_NUMBER11 (*) + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @note cortex-M33 supports 12 secure and 8 non secure regions. + * (*) : For MPU_S only + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK)); +} + +/** + * @brief Get a MPU region access attributes + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n + * MPU_RBAR XN LL_MPU_GetRegionAccess\n + * MPU_RBAR AP LL_MPU_GetRegionAccess\n + * MPU_RBAR SH LL_MPU_GetRegionAccess\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 (*) + * @arg @ref LL_MPU_REGION_NUMBER9 (*) + * @arg @ref LL_MPU_REGION_NUMBER10 (*) + * @arg @ref LL_MPU_REGION_NUMBER11 (*) + * (*) : For MPU_S only + * @retval return a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure a non-secure MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n + * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set limit address */ + MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Get a non-secure MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval Value of the region limit address. + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Configure a non-secure MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n + * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @note cortex-M33 supports 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Get a non-secure MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval Value of the region base address. + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Configure a non-secure MPU region access attributes and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR SH LL_MPU_SetRegionAccess_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @note cortex-M33 supports 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address Attributes */ + MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK)); +} + +/** + * @brief Get a non-secure MPU region access attributes + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR SH LL_MPU_GetRegionAccess_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval return a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_LL_CORTEX_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h new file mode 100644 index 00000000..309447ca --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h @@ -0,0 +1,812 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_crs.h + * @author MCD Application Team + * @brief Header file of CRS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_LL_CRS_H +#define STM32H5xx_LL_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +#if defined(CRS) + +/** @defgroup CRS_LL CRS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CRS_LL_Private_Constants CRS Private Constants + * @{ + */ + +/* Defines used for the bit position in the register and perform offsets*/ +#define CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */ +#define CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */ +#define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */ + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants + * @{ + */ + +/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_CRS_ReadReg function + * @{ + */ +#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF +#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF +#define LL_CRS_ISR_ERRF CRS_ISR_ERRF +#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF +#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR +#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS +#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF +/** + * @} + */ + +/** @defgroup CRS_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions + * @{ + */ +#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE +#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE +#define LL_CRS_CR_ERRIE CRS_CR_ERRIE +#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider + * @{ + */ +#define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */ +#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source + * @{ + */ +#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#if defined(USB_DRD_FS) +#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +#elif defined(USB_OTG_FS) +#define LL_CRS_SYNC_SOURCE_OTG_FS CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source OTG_FS SOF (default)*/ +#endif /* USB_DRD_FS */ +#if defined(USB_OTG_HS) +#define LL_CRS_SYNC_SOURCE_OTG_HS (CRS_CFGR_SYNCSRC_0 | CRS_CFGR_SYNCSRC_1) /*!< Synchro Signal source OTG_HS SOF */ +#endif /* USB_OTG_HS */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity + * @{ + */ +#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ +#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction + * @{ + */ +#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ +#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values + * @{ + */ +/** + * @brief Reset value of the RELOAD field + * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz + * and a synchronization signal frequency of 1 kHz (SOF signal from USB) + */ +#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU + +/** + * @brief Reset value of Frequency error limit. + */ +#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U + +/** + * @brief Reset value of the HSI48 Calibration field + * @note The default value is 32, which corresponds to the middle of the trimming interval. + * The trimming step is specified in the product datasheet. + * A higher TRIM value corresponds to a higher output frequency. + */ +#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros + * @{ + */ + +/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload + * @{ + */ + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between + * the target frequency and the frequency of the synchronization source after + * prescaling. It is then decreased by one in order to reach the expected + * synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval Reload value (in Hz) + */ +#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions + * @{ + */ + +/** @defgroup CRS_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Frequency error counter + * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified + * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) +{ + SET_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Disable Frequency error counter + * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Check if Frequency error counter is enabled or not + * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) +{ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Disable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Check if Automatic trimming is enabled or not + * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL); +} + +/** + * @brief Set HSI48 oscillator smooth trimming + * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only + * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming + * @param Value a number between Min_Data = 0 and Max_Data = 63 + * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM); +} + +/** + * @brief Get HSI48 oscillator smooth trimming + * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming + * @retval a number between Min_Data = 0 and Max_Data = 63 + */ +__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) +{ + return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM); +} + +/** + * @brief Set counter reload value + * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter + * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT + * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); +} + +/** + * @brief Get counter reload value + * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter + * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); +} + +/** + * @brief Set frequency error limit + * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit + * @param Value a number between Min_Data = 0 and Max_Data = 255 + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM); +} + +/** + * @brief Get frequency error limit + * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit + * @retval A number between Min_Data = 0 and Max_Data = 255 + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM); +} + +/** + * @brief Set division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); +} + +/** + * @brief Get division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); +} + +/** + * @brief Set SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB (*) + * @arg @ref LL_CRS_SYNC_SOURCE_OTG_FS (*) + * @arg @ref LL_CRS_SYNC_SOURCE_OTG_HS (*) + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); +} + +/** + * @brief Get SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB (*) + * @arg @ref LL_CRS_SYNC_SOURCE_OTG_FS (*) + * @arg @ref LL_CRS_SYNC_SOURCE_OTG_HS (*) + * (*) : Not available for all stm32h5xxxx family lines. + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); +} + +/** + * @brief Set input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); +} + +/** + * @brief Get input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); +} + +/** + * @brief Configure CRS for the synchronization + * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n + * CFGR RELOAD LL_CRS_ConfigSynchronization\n + * CFGR FELIM LL_CRS_ConfigSynchronization\n + * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n + * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n + * CFGR SYNCPOL LL_CRS_ConfigSynchronization + * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 + * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF + * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 + * @param Settings This parameter can be a combination of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 + * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 + * or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB (*) + * or @arg @ref LL_CRS_SYNC_SOURCE_OTG_FS (*) or @arg @ref LL_CRS_SYNC_SOURCE_OTG_HS (*) + * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING + * (*) : Not available for all stm32h5xxxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, + uint32_t ReloadValue, uint32_t Settings) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); + MODIFY_REG(CRS->CFGR, + CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, + ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_CRS_Management CRS_Management + * @{ + */ + +/** + * @brief Generate software SYNC event + * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Get the frequency error direction latched in the time of the last + * SYNC event + * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP + * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Get the frequency error counter value latched in the time of the last SYNC event + * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture + * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if SYNC event OK signal occurred or not + * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC warning signal occurred or not + * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Synchronization or trimming error signal occurred or not + * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Expected SYNC signal occurred or not + * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC error signal occurred or not + * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC missed error signal occurred or not + * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL); +} + +/** + * @brief Check if Trimming overflow or underflow occurred or not + * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the SYNC event OK flag + * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); +} + +/** + * @brief Clear the SYNC warning flag + * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); +} + +/** + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * the ERR flag + * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); +} + +/** + * @brief Clear Expected SYNC flag + * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Disable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Check if SYNC event OK interrupt is enabled or not + * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Disable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Check if SYNC warning interrupt is enabled or not + * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) +{ + SET_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Disable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Check if Synchronization or trimming error interrupt is enabled or not + * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Disable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Check if Expected SYNC interrupt is enabled or not + * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRS_DeInit(void); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRS) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_LL_CRS_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h new file mode 100644 index 00000000..6f841938 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h @@ -0,0 +1,7481 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### LL DMA driver acronyms ##### + ============================================================================== + [..] Acronyms table : + ========================================= + || Acronym || || + ========================================= + || SRC || Source || + || DEST || Destination || + || ADDR || Address || + || ADDRS || Addresses || + || INC || Increment / Incremented || + || DEC || Decrement / Decremented || + || BLK || Block || + || RPT || Repeat / Repeated || + || TRIG || Trigger || + ========================================= + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_LL_DMA_H +#define STM32H5xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +#if defined (GPDMA1) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +#define DMA_CHANNEL0_OFFSET (0x00000050UL) +#define DMA_CHANNEL1_OFFSET (0x000000D0UL) +#define DMA_CHANNEL2_OFFSET (0x00000150UL) +#define DMA_CHANNEL3_OFFSET (0x000001D0UL) +#define DMA_CHANNEL4_OFFSET (0x00000250UL) +#define DMA_CHANNEL5_OFFSET (0x000002D0UL) +#define DMA_CHANNEL6_OFFSET (0x00000350UL) +#define DMA_CHANNEL7_OFFSET (0x000003D0UL) +#if defined(GPDMA1_Channel11) +#define DMA_CHANNEL8_OFFSET (0x00000450UL) +#define DMA_CHANNEL9_OFFSET (0x000004D0UL) +#define DMA_CHANNEL10_OFFSET (0x00000550UL) +#define DMA_CHANNEL11_OFFSET (0x000005D0UL) +#endif /* GPDMA1_Channel11 */ + + +/* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */ +static const uint32_t LL_DMA_CH_OFFSET_TAB[] = +{ + DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET, + DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET, +#if defined(GPDMA1_Channel11) + DMA_CHANNEL8_OFFSET, DMA_CHANNEL9_OFFSET, DMA_CHANNEL10_OFFSET, DMA_CHANNEL11_OFFSET, +#endif /* GPDMA1_Channel11 */ +}; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ + +/** + * @brief LL DMA init structure definition. + */ +typedef struct +{ + uint32_t SrcAddress; /*!< This field specify the data transfer source address. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAddress(). */ + + uint32_t DestAddress; /*!< This field specify the data transfer destination address. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAddress(). */ + + uint32_t Direction; /*!< This field specify the data transfer direction. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t BlkHWRequest; /*!< This field specify the hardware request unity. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkHWRequest(). */ + + uint32_t DataAlignment; /*!< This field specify the transfer data alignment. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDataAlignment(). */ + + uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcBurstLength(). */ + + uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestBurstLength(). */ + + uint32_t SrcDataWidth; /*!< This field specify the source data width. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcDataWidth(). */ + + uint32_t DestDataWidth; /*!< This field specify the destination data width. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestDataWidth(). */ + + uint32_t SrcIncMode; /*!< This field specify the source burst increment mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcIncMode(). */ + + uint32_t DestIncMode; /*!< This field specify the destination burst increment mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestIncMode(). */ + + uint32_t Priority; /*!< This field specify the channel priority level. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetChannelPriorityLevel(). */ + + uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkDataLength(). */ + + uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value between 1 and 2048 Min_Data = 0 + and Max_Data = 0x000007FF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptCount(). */ + + uint32_t TriggerMode; /*!< This field specify the trigger mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTriggerMode(). */ + + uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTriggerPolarity(). */ + + uint32_t TriggerSelection; /*!< This field specify the trigger event selection. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetHWTrigger(). */ + + uint32_t Request; /*!< This field specify the peripheral request selection. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetPeriphRequest(). */ + + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTransferEventMode(). */ + + uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestHWordExchange(). */ + + uint32_t DestByteExchange; /*!< This field specify the destination byte exchange. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestByteExchange(). */ + + uint32_t SrcByteExchange; /*!< This field specify the source byte exchange. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcByteExchange(). */ + + uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAllocatedPort(). */ + + uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAllocatedPort(). */ + + uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkAllocatedPort(). */ + + uint32_t LinkStepMode; /*!< This field specify the link step mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkStepMode(). */ + + uint32_t SrcAddrUpdateMode; /*!< This field specify the source address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAddrUpdate(). */ + + uint32_t DestAddrUpdateMode; /*!< This field specify the destination address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAddrUpdate(). */ + + uint32_t SrcAddrOffset; /*!< This field specifies the source address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x00001FFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAddrUpdateValue(). */ + + uint32_t DestAddrOffset; /*!< This field specifies the destination address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x00001FFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAddrUpdateValue(). */ + + uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptSrcAddrUpdate(). */ + + uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptDestAddrUpdate(). */ + + uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x0000FFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptSrcAddrUpdateValue(). */ + + uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x0000FFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptDestAddrUpdateValue(). */ + + uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first + bytes are always forced to 0). + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkedListBaseAddr(). */ + + uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value Between 0 to 0x0000FFFC. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkedListAddrOffset(). */ + + uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. + This parameter can be a value of @ref DMA_LL_TRANSFER_MODE */ +} LL_DMA_InitTypeDef; + + +/** + * @brief LL DMA init linked list structure definition. + */ +typedef struct +{ + uint32_t Priority; /*!< This field specify the channel priority level. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetChannelPriorityLevel(). */ + + uint32_t LinkStepMode; /*!< This field specify the link step mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkStepMode(). */ + + uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkAllocatedPort(). */ + + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTransferEventMode(). */ +} LL_DMA_InitLinkedListTypeDef; + + +/** + * @brief LL DMA node init structure definition. + */ +typedef struct +{ + /* CTR1 register fields ****************************************************** + If any CTR1 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR1 register fields and enable update + CTR1 register in UpdateRegisters fields if it is not enabled in the + previous node. + + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t DestSecure; /*!< This field specify the destination secure. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */ + + uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange. + This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */ + + uint32_t DestByteExchange; /*!< This field specify the destination byte exchange. + This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */ + + uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. */ + + uint32_t DestIncMode; /*!< This field specify the destination increment mode. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */ + + uint32_t DestDataWidth; /*!< This field specify the destination data width. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t SrcSecure; /*!< This field specify the source secure. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */ + + uint32_t SrcByteExchange; /*!< This field specify the source byte exchange. + This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */ + + uint32_t DataAlignment; /*!< This field specify the transfer data alignment. + This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */ + + uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. */ + + uint32_t SrcIncMode; /*!< This field specify the source increment mode. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */ + + uint32_t SrcDataWidth; /*!< This field specify the source data width. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */ + + + /* CTR2 register fields ****************************************************** + If any CTR2 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR2 register fields and enable update + CTR2 register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */ + + uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */ + + uint32_t TriggerSelection; /*!< This field specify the trigger event selection. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */ + + uint32_t TriggerMode; /*!< This field specify the trigger mode. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */ + + uint32_t BlkHWRequest; /*!< This field specify the hardware request unity. + This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */ + + uint32_t Direction; /*!< This field specify the transfer direction. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */ + + uint32_t Request; /*!< This field specify the peripheral request selection. + This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */ + + uint32_t Mode; /*!< This field DMA Transfer Mode. + This parameter can be a value of @ref DMA_LL_TRANSFER_MODE. */ + + /* CBR1 register fields ****************************************************** + If any CBR1 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CBR1 register fields and enable update + CBR1 register in UpdateRegisters fields if it is not enabled in the + previous node. + + If the node to be created is not for 2D addressing channels, there is no + need to fill the following fields for CBR1 register : + - BlkReptDestAddrUpdate. + - BlkRptSrcAddrUpdate. + - DestAddrUpdate. + - SrcAddrUpdate. + - BlkRptCount. + */ + uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode. + This parameter can be a value of + @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. */ + + uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode. + This parameter can be a value of + @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. */ + + uint32_t DestAddrUpdateMode; /*!< This field specify the Destination address update mode. + This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. */ + + uint32_t SrcAddrUpdateMode; /*!< This field specify the Source address update mode. + This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. */ + + uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block. + This parameter can be a value between 1 and 2048 Min_Data = 0 + and Max_Data = 0x000007FF. */ + + uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0x0000FFFF. */ + + /* CSAR register fields ****************************************************** + If any CSAR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CSAR register fields and enable update + CSAR register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t SrcAddress; /*!< This field specify the transfer source address. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0xFFFFFFFF. */ + + + /* CDAR register fields ****************************************************** + If any CDAR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CDAR register fields and enable update + CDAR register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t DestAddress; /*!< This field specify the transfer destination address. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0xFFFFFFFF. */ + + /* CTR3 register fields ****************************************************** + If any CTR3 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR3 register fields and enable update + CTR3 register in UpdateRegisters fields if it is not enabled in the + previous node. + + This register is used only for 2D addressing channels. + If used channel is linear addressing, this register will be overwritten by + CLLR register in memory. + When this register is enabled on UpdateRegisters and the selected channel + is linear addressing, LL APIs will discard this register update in memory. + */ + uint32_t DestAddrOffset; /*!< This field specifies the destination address offset. + This parameter can be a value Between 0 to 0x00001FFF. */ + + uint32_t SrcAddrOffset; /*!< This field specifies the source address offset. + This parameter can be a value Between 0 to 0x00001FFF. */ + + + /* CBR2 register fields ****************************************************** + If any CBR2 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CBR2 register fields and enable update + CBR2 register in UpdateRegisters fields if it is not enabled in the + previous node. + + This register is used only for 2D addressing channels. + If used channel is linear addressing, this register will be discarded in + memory. When this register is enabled on UpdateRegisters and the selected + channel is linear addressing, LL APIs will discard this register update in + memory. + */ + uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset. + This parameter can be a value Between 0 to 0x0000FFFF. */ + + uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset. + This parameter can be a value Between 0 to 0x0000FFFF. */ + + /* CLLR register fields ****************************************************** + If any CLLR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CLLR register fields and enable update + CLLR register in UpdateRegisters fields if it is not enabled in the + previous node. + + If used channel is linear addressing, there is no need to enable/disable + CTR3 and CBR2 register in UpdateRegisters fields as they will be discarded + by LL APIs. + */ + uint32_t UpdateRegisters; /*!< Specifies the linked list register update. + This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */ + + /* DMA Node type field ******************************************************* + This parameter defines node types as node size and node content varies + between channels. + Thanks to this fields, linked list queue could be created independently + from channel selection. So, one queue could be executed by all DMA channels. + */ + uint32_t NodeType; /*!< Specifies the node type to be created. + This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */ +} LL_DMA_InitNodeTypeDef; + +/** + * @brief LL DMA linked list node structure definition. + * @note For 2D addressing channels, the maximum node size is : + * (4 Bytes * 8 registers = 32 Bytes). + * For GPDMA linear addressing channels, the maximum node size is : + * (4 Bytes * 6 registers = 24 Bytes). + */ +typedef struct +{ + __IO uint32_t LinkRegisters[8U]; + +} LL_DMA_LinkNodeTypeDef; +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_DMA_CHANNEL_0 (0x00U) +#define LL_DMA_CHANNEL_1 (0x01U) +#define LL_DMA_CHANNEL_2 (0x02U) +#define LL_DMA_CHANNEL_3 (0x03U) +#define LL_DMA_CHANNEL_4 (0x04U) +#define LL_DMA_CHANNEL_5 (0x05U) +#define LL_DMA_CHANNEL_6 (0x06U) +#define LL_DMA_CHANNEL_7 (0x07U) +#define LL_DMA_CHANNEL_8 (0x08U) +#define LL_DMA_CHANNEL_9 (0x09U) +#define LL_DMA_CHANNEL_10 (0x0AU) +#define LL_DMA_CHANNEL_11 (0x0BU) +#define LL_DMA_CHANNEL_12 (0x0CU) +#define LL_DMA_CHANNEL_13 (0x0DU) +#define LL_DMA_CHANNEL_14 (0x0EU) +#define LL_DMA_CHANNEL_15 (0x0FU) +#if defined (USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL (0x10U) +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset + * @{ + */ +#define LL_DMA_CLLR_OFFSET0 (0x00U) +#define LL_DMA_CLLR_OFFSET1 (0x01U) +#define LL_DMA_CLLR_OFFSET2 (0x02U) +#define LL_DMA_CLLR_OFFSET3 (0x03U) +#define LL_DMA_CLLR_OFFSET4 (0x04U) +#define LL_DMA_CLLR_OFFSET5 (0x05U) +#define LL_DMA_CLLR_OFFSET6 (0x06U) +#define LL_DMA_CLLR_OFFSET7 (0x07U) +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level + * @{ + */ +#define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */ +#define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */ +#define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */ +#define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port + * @{ + */ +#define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */ +#define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode + * @{ + */ +#define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */ +#define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange + * @{ + */ +#define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destination Half-Word exchange when destination data width + is word */ +#define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width + is word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange + * @{ + */ +#define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */ +#define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange + * @{ + */ +#define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */ +#define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port + * @{ + */ +#define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */ +#define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port + * @{ + */ +#define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */ +#define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode + * @{ + */ +#define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */ +#define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width + * @{ + */ +#define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */ +#define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */ +#define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment + * @{ + */ +#define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width : + => Right Aligned padded with 0 up to destination + data width. + If src data width > dest data width : + => Right Aligned Left Truncated down to destination + data width. */ +#define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width : + => Right Aligned padded with sign extended up to destination + data width. + If src data width > dest data width : + => Left Aligned Right Truncated down to the destination + data width */ +#define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width : + => Packed at the destination data width + If src data width > dest data width : + => Unpacked at the destination data width */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode + * @{ + */ +#define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */ +#define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width + * @{ + */ +#define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */ +#define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */ +#define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request + * @{ + */ +#define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol at a burst level */ +#define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol at a block level */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode + * @{ + */ +#define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the + (respectively half) end of each block */ +#define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the + (respectively half) end of the repeated block */ +#define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the + (respectively half) end of each linked-list item */ +#define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the + (respectively half) end of the last linked-list item */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity + * @{ + */ +#define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. + Masked trigger event */ +#define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising + edge of the selected trigger event input */ +#define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling + edge of the selected trigger event input */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode + * @{ + */ +#define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least) + one hit trigger */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_DMA_NORMAL 0x00000000U /*!< Normal DMA transfer */ +#define LL_DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE Block Repeat Source Address Update Mode + * @{ + */ +#define LL_DMA_BLKRPT_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each block + transfer by source update value */ +#define LL_DMA_BLKRPT_SRC_ADDR_DECREMENT DMA_CBR1_BRSDEC /*!< Source address pointer is decremented after each block + transfer by source update value */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination Address Update Mode + * @{ + */ +#define LL_DMA_BLKRPT_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address is incremented after each block + transfer by destination update value */ +#define LL_DMA_BLKRPT_DEST_ADDR_DECREMENT DMA_CBR1_BRDDEC /*!< Destination address is decremented after each block + transfer by destination update value */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SRC_ADDR_UPDATE_MODE Burst Source Address Update Mode + * @{ + */ +#define LL_DMA_BURST_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each burst + transfer by source update value */ +#define LL_DMA_BURST_SRC_ADDR_DECREMENT DMA_CBR1_SDEC /*!< Source address pointer is decremented after each burst + transfer by source update value */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DEST_ADDR_UPDATE_MODE Burst Destination Address Update Mode + * @{ + */ +#define LL_DMA_BURST_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address pointer is incremented after each + burst transfer by destination update value */ +#define LL_DMA_BURST_DEST_ADDR_DECREMENT DMA_CBR1_DDEC /*!< Destination address pointer is decremented after each + burst transfer by destination update value */ +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute + * @{ + */ +#define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */ +#define LL_DMA_CHANNEL_SEC 0x00000001U /*!< Secure channel */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute + * @{ + */ +#define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< NSecure transfer from the source */ +#define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute + * @{ + */ +#define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< NSecure transfer from the destination */ +#define LL_DMA_CHANNEL_DEST_SEC DMA_CTR1_DSEC /*!< Secure transfer from the destination */ +/** + * @} + */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type + * @{ + */ +#define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */ +#define LL_DMA_GPDMA_2D_NODE 0x02U /*!< GPDMA node : 2 dimension addressing node */ + +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update + * @{ + */ +#define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory : + available only for 2D addressing DMA channels */ +#define LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 /*!< Update CBR2 register from memory : + available only for 2D addressing DMA channels */ +#define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory : + available for all DMA channels */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection + * @{ + */ +/* GPDMA1 Hardware Requests */ +#define LL_GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */ +#if defined (ADC2) +#define LL_GPDMA1_REQUEST_ADC2 1U /*!< GPDMA1 HW request is ADC2 */ +#endif /* ADC2 */ +#define LL_GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW request is DAC1_CH1 */ +#define LL_GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW request is DAC1_CH2 */ +#define LL_GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW request is TIM6_UP */ +#define LL_GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW request is TIM7_UP */ +#define LL_GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW request is SPI1_RX */ +#define LL_GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW request is SPI1_TX */ +#define LL_GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW request is SPI2_RX */ +#define LL_GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW request is SPI2_TX */ +#define LL_GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW request is SPI3_RX */ +#define LL_GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW request is SPI3_TX */ +#define LL_GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW request is I2C1_RX */ +#define LL_GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW request is I2C1_TX */ +#define LL_GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW request is I2C2_RX */ +#define LL_GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW request is I2C2_TX */ +#if defined (I2C3) +#define LL_GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW request is I2C3_RX */ +#define LL_GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW request is I2C3_TX */ +#endif /* I2C3 */ +#define LL_GPDMA1_REQUEST_USART1_RX 21U /*!< GPDMA1 HW request is USART1_RX */ +#define LL_GPDMA1_REQUEST_USART1_TX 22U /*!< GPDMA1 HW request is USART1_TX */ +#define LL_GPDMA1_REQUEST_USART2_RX 23U /*!< GPDMA1 HW request is USART2_RX */ +#define LL_GPDMA1_REQUEST_USART2_TX 24U /*!< GPDMA1 HW request is USART2_TX */ +#define LL_GPDMA1_REQUEST_USART3_RX 25U /*!< GPDMA1 HW request is USART3_RX */ +#define LL_GPDMA1_REQUEST_USART3_TX 26U /*!< GPDMA1 HW request is USART3_TX */ +#if defined (UART4) +#define LL_GPDMA1_REQUEST_UART4_RX 27U /*!< GPDMA1 HW request is UART4_RX */ +#define LL_GPDMA1_REQUEST_UART4_TX 28U /*!< GPDMA1 HW request is UART4_TX */ +#endif /* UART4 */ +#if defined (UART5) +#define LL_GPDMA1_REQUEST_UART5_RX 29U /*!< GPDMA1 HW request is UART5_RX */ +#define LL_GPDMA1_REQUEST_UART5_TX 30U /*!< GPDMA1 HW request is UART5_TX */ +#endif /* UART5 */ +#if defined (USART6) +#define LL_GPDMA1_REQUEST_USART6_RX 31U /*!< GPDMA1 HW request is USART6_RX */ +#define LL_GPDMA1_REQUEST_USART6_TX 32U /*!< GPDMA1 HW request is USART6_TX */ +#endif /* USART6 */ +#if defined (UART7) +#define LL_GPDMA1_REQUEST_UART7_RX 33U /*!< GPDMA1 HW request is UART7_RX */ +#define LL_GPDMA1_REQUEST_UART7_TX 34U /*!< GPDMA1 HW request is UART7_TX */ +#endif /* UART7 */ +#if defined (UART8) +#define LL_GPDMA1_REQUEST_UART8_RX 35U /*!< GPDMA1 HW request is UART8_RX */ +#define LL_GPDMA1_REQUEST_UART8_TX 36U /*!< GPDMA1 HW request is UART8_TX */ +#endif /* UART8 */ +#if defined (UART9) +#define LL_GPDMA1_REQUEST_UART9_RX 37U /*!< GPDMA1 HW request is UART9_RX */ +#define LL_GPDMA1_REQUEST_UART9_TX 38U /*!< GPDMA1 HW request is UART9_TX */ +#endif /* UART9 */ +#if defined (USART10) +#define LL_GPDMA1_REQUEST_USART10_RX 39U /*!< GPDMA1 HW request is USART10_RX */ +#define LL_GPDMA1_REQUEST_USART10_TX 40U /*!< GPDMA1 HW request is USART10_TX */ +#endif /* USART10 */ +#if defined (USART11) +#define LL_GPDMA1_REQUEST_USART11_RX 41U /*!< GPDMA1 HW request is USART11_RX */ +#define LL_GPDMA1_REQUEST_USART11_TX 42U /*!< GPDMA1 HW request is USART11_TX */ +#endif /* USART11 */ +#if defined (UART12) +#define LL_GPDMA1_REQUEST_UART12_RX 43U /*!< GPDMA1 HW request is UART12_RX */ +#define LL_GPDMA1_REQUEST_UART12_TX 44U /*!< GPDMA1 HW request is UART12_TX */ +#endif /* UART12 */ +#define LL_GPDMA1_REQUEST_LPUART1_RX 45U /*!< GPDMA1 HW request is LPUART1_RX */ +#define LL_GPDMA1_REQUEST_LPUART1_TX 46U /*!< GPDMA1 HW request is LPUART1_TX */ +#if defined (SPI4) +#define LL_GPDMA1_REQUEST_SPI4_RX 47U /*!< GPDMA1 HW request is SPI4_RX */ +#define LL_GPDMA1_REQUEST_SPI4_TX 48U /*!< GPDMA1 HW request is SPI4_TX */ +#endif /* SPI4 */ +#if defined (SPI5) +#define LL_GPDMA1_REQUEST_SPI5_RX 49U /*!< GPDMA1 HW request is SPI5_RX */ +#define LL_GPDMA1_REQUEST_SPI5_TX 50U /*!< GPDMA1 HW request is SPI5_TX */ +#endif /* SPI5 */ +#if defined (SPI6) +#define LL_GPDMA1_REQUEST_SPI6_RX 51U /*!< GPDMA1 HW request is SPI6_RX */ +#define LL_GPDMA1_REQUEST_SPI6_TX 52U /*!< GPDMA1 HW request is SPI6_TX */ +#endif /* SPI6 */ +#if defined (SAI1) +#define LL_GPDMA1_REQUEST_SAI1_A 53U /*!< GPDMA1 HW request is SAI1_A */ +#define LL_GPDMA1_REQUEST_SAI1_B 54U /*!< GPDMA1 HW request is SAI1_B */ +#endif /* SAI1 */ +#if defined (SAI2) +#define LL_GPDMA1_REQUEST_SAI2_A 55U /*!< GPDMA1 HW request is SAI2_A */ +#define LL_GPDMA1_REQUEST_SAI2_B 56U /*!< GPDMA1 HW request is SAI2_B */ +#endif /* SAI2 */ +#if defined (OCTOSPI1) +#define LL_GPDMA1_REQUEST_OCTOSPI1 57U /*!< GPDMA1 HW request is OCTOSPI1 */ +#endif /* OCTOSPI1 */ +#define LL_GPDMA1_REQUEST_TIM1_CH1 58U /*!< GPDMA1 HW request is TIM1_CH1 */ +#define LL_GPDMA1_REQUEST_TIM1_CH2 59U /*!< GPDMA1 HW request is TIM1_CH2 */ +#define LL_GPDMA1_REQUEST_TIM1_CH3 60U /*!< GPDMA1 HW request is TIM1_CH3 */ +#define LL_GPDMA1_REQUEST_TIM1_CH4 61U /*!< GPDMA1 HW request is TIM1_CH4 */ +#define LL_GPDMA1_REQUEST_TIM1_UP 62U /*!< GPDMA1 HW request is TIM1_UP */ +#define LL_GPDMA1_REQUEST_TIM1_TRIG 63U /*!< GPDMA1 HW request is TIM1_TRIG */ +#define LL_GPDMA1_REQUEST_TIM1_COM 64U /*!< GPDMA1 HW request is TIM1_COM */ +#if defined (TIM8) +#define LL_GPDMA1_REQUEST_TIM8_CH1 65U /*!< GPDMA1 HW request is TIM8_CH1 */ +#define LL_GPDMA1_REQUEST_TIM8_CH2 66U /*!< GPDMA1 HW request is TIM8_CH2 */ +#define LL_GPDMA1_REQUEST_TIM8_CH3 67U /*!< GPDMA1 HW request is TIM8_CH3 */ +#define LL_GPDMA1_REQUEST_TIM8_CH4 68U /*!< GPDMA1 HW request is TIM8_CH4 */ +#define LL_GPDMA1_REQUEST_TIM8_UP 69U /*!< GPDMA1 HW request is TIM8_UP */ +#define LL_GPDMA1_REQUEST_TIM8_TRIG 70U /*!< GPDMA1 HW request is TIM8_TRIG */ +#define LL_GPDMA1_REQUEST_TIM8_COM 71U /*!< GPDMA1 HW request is TIM8_COM */ +#endif /* TIM8 */ +#define LL_GPDMA1_REQUEST_TIM2_CH1 72U /*!< GPDMA1 HW request is TIM2_CH1 */ +#define LL_GPDMA1_REQUEST_TIM2_CH2 73U /*!< GPDMA1 HW request is TIM2_CH2 */ +#define LL_GPDMA1_REQUEST_TIM2_CH3 74U /*!< GPDMA1 HW request is TIM2_CH3 */ +#define LL_GPDMA1_REQUEST_TIM2_CH4 75U /*!< GPDMA1 HW request is TIM2_CH4 */ +#define LL_GPDMA1_REQUEST_TIM2_UP 76U /*!< GPDMA1 HW request is TIM2_UP */ +#define LL_GPDMA1_REQUEST_TIM3_CH1 77U /*!< GPDMA1 HW request is TIM3_CH1 */ +#define LL_GPDMA1_REQUEST_TIM3_CH2 78U /*!< GPDMA1 HW request is TIM3_CH2 */ +#define LL_GPDMA1_REQUEST_TIM3_CH3 79U /*!< GPDMA1 HW request is TIM3_CH3 */ +#define LL_GPDMA1_REQUEST_TIM3_CH4 80U /*!< GPDMA1 HW request is TIM3_CH4 */ +#define LL_GPDMA1_REQUEST_TIM3_UP 81U /*!< GPDMA1 HW request is TIM3_UP */ +#define LL_GPDMA1_REQUEST_TIM3_TRIG 82U /*!< GPDMA1 HW request is TIM3_TRIG */ +#if defined (TIM4) +#define LL_GPDMA1_REQUEST_TIM4_CH1 83U /*!< GPDMA1 HW request is TIM4_CH1 */ +#define LL_GPDMA1_REQUEST_TIM4_CH2 84U /*!< GPDMA1 HW request is TIM4_CH2 */ +#define LL_GPDMA1_REQUEST_TIM4_CH3 85U /*!< GPDMA1 HW request is TIM4_CH3 */ +#define LL_GPDMA1_REQUEST_TIM4_CH4 86U /*!< GPDMA1 HW request is TIM4_CH4 */ +#define LL_GPDMA1_REQUEST_TIM4_UP 87U /*!< GPDMA1 HW request is TIM4_UP */ +#endif /* TIM4 */ +#if defined (TIM5) +#define LL_GPDMA1_REQUEST_TIM5_CH1 88U /*!< GPDMA1 HW request is TIM5_CH1 */ +#define LL_GPDMA1_REQUEST_TIM5_CH2 89U /*!< GPDMA1 HW request is TIM5_CH2 */ +#define LL_GPDMA1_REQUEST_TIM5_CH3 90U /*!< GPDMA1 HW request is TIM5_CH3 */ +#define LL_GPDMA1_REQUEST_TIM5_CH4 91U /*!< GPDMA1 HW request is TIM5_CH4 */ +#define LL_GPDMA1_REQUEST_TIM5_UP 92U /*!< GPDMA1 HW request is TIM5_UP */ +#define LL_GPDMA1_REQUEST_TIM5_TRIG 93U /*!< GPDMA1 HW request is TIM5_TRIG */ +#endif /* TIM5 */ +#if defined (TIM15) +#define LL_GPDMA1_REQUEST_TIM15_CH1 94U /*!< GPDMA1 HW request is TIM15_CH1 */ +#define LL_GPDMA1_REQUEST_TIM15_UP 95U /*!< GPDMA1 HW request is TIM15_UP */ +#define LL_GPDMA1_REQUEST_TIM15_TRIG 96U /*!< GPDMA1 HW request is TIM15_TRIG */ +#define LL_GPDMA1_REQUEST_TIM15_COM 97U /*!< GPDMA1 HW request is TIM15_COM */ +#endif /* TIM15 */ +#if defined (TIM16) +#define LL_GPDMA1_REQUEST_TIM16_CH1 98U /*!< GPDMA1 HW request is TIM16_CH1 */ +#define LL_GPDMA1_REQUEST_TIM16_UP 99U /*!< GPDMA1 HW request is TIM16_UP */ +#endif /* TIM16 */ +#if defined (TIM17) +#define LL_GPDMA1_REQUEST_TIM17_CH1 100U /*!< GPDMA1 HW request is TIM17_CH1 */ +#define LL_GPDMA1_REQUEST_TIM17_UP 101U /*!< GPDMA1 HW request is TIM17_UP */ +#endif /* TIM17 */ +#define LL_GPDMA1_REQUEST_LPTIM1_IC1 102U /*!< GPDMA1 HW request is LPTIM1_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM1_IC2 103U /*!< GPDMA1 HW request is LPTIM1_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM1_UE 104U /*!< GPDMA1 HW request is LPTIM1_UE */ +#define LL_GPDMA1_REQUEST_LPTIM2_IC1 105U /*!< GPDMA1 HW request is LPTIM2_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM2_IC2 106U /*!< GPDMA1 HW request is LPTIM2_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM2_UE 107U /*!< GPDMA1 HW request is LPTIM2_UE */ +#if defined (DCMI) +#define LL_GPDMA1_REQUEST_DCMI 108U /*!< GPDMA1 HW request is DCMI */ +#endif /* DCMI */ +#if defined (AES) +#define LL_GPDMA1_REQUEST_AES_OUT 109U /*!< GPDMA1 HW request is AES_OUT */ +#define LL_GPDMA1_REQUEST_AES_IN 110U /*!< GPDMA1 HW request is AES_IN */ +#endif /* AES */ +#define LL_GPDMA1_REQUEST_HASH_IN 111U /*!< GPDMA1 HW request is HASH_IN */ +#if defined (UCPD1) +#define LL_GPDMA1_REQUEST_UCPD1_RX 112U /*!< GPDMA1 HW request is UCPD1_RX */ +#define LL_GPDMA1_REQUEST_UCPD1_TX 113U /*!< GPDMA1 HW request is UCPD1_TX */ +#endif /* UCPD1 */ +#if defined (CORDIC) +#define LL_GPDMA1_REQUEST_CORDIC_READ 114U /*!< GPDMA1 HW request is CORDIC_READ */ +#define LL_GPDMA1_REQUEST_CORDIC_WRITE 115U /*!< GPDMA1 HW request is CORDIC_WRITE */ +#endif /* CORDIC */ +#if defined (FMAC) +#define LL_GPDMA1_REQUEST_FMAC_READ 116U /*!< GPDMA1 HW request is FMAC_READ */ +#define LL_GPDMA1_REQUEST_FMAC_WRITE 117U /*!< GPDMA1 HW request is FMAC_WRITE */ +#endif /* FMAC */ +#if defined (SAES) +#define LL_GPDMA1_REQUEST_SAES_OUT 118U /*!< GPDMA1 HW request is SAES_OUT */ +#define LL_GPDMA1_REQUEST_SAES_IN 119U /*!< GPDMA1 HW request is SAES_IN */ +#endif /* SAES */ +#define LL_GPDMA1_REQUEST_I3C1_RX 120U /*!< GPDMA1 HW request is I3C1_RX */ +#define LL_GPDMA1_REQUEST_I3C1_TX 121U /*!< GPDMA1 HW request is I3C1_TX */ +#define LL_GPDMA1_REQUEST_I3C1_TC 122U /*!< GPDMA1 HW request is I3C1_TC */ +#define LL_GPDMA1_REQUEST_I3C1_RS 123U /*!< GPDMA1 HW request is I3C1_RS */ +#if defined (I2C4) +#define LL_GPDMA1_REQUEST_I2C4_RX 124U /*!< GPDMA1 HW request is I2C4_RX */ +#define LL_GPDMA1_REQUEST_I2C4_TX 125U /*!< GPDMA1 HW request is I2C4_TX */ +#endif /* I2C4 */ +#if defined (LPTIM3) +#define LL_GPDMA1_REQUEST_LPTIM3_IC1 127U /*!< GPDMA1 HW request is LPTIM3_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM3_IC2 128U /*!< GPDMA1 HW request is LPTIM3_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM3_UE 129U /*!< GPDMA1 HW request is LPTIM3_UE */ +#endif /* LPTIM3 */ +#if defined (LPTIM5) +#define LL_GPDMA1_REQUEST_LPTIM5_IC1 130U /*!< GPDMA1 HW request is LPTIM5_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM5_IC2 131U /*!< GPDMA1 HW request is LPTIM5_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM5_UE 132U /*!< GPDMA1 HW request is LPTIM5_UE */ +#endif /* LPTIM5 */ +#if defined (LPTIM6) +#define LL_GPDMA1_REQUEST_LPTIM6_IC1 133U /*!< GPDMA1 HW request is LPTIM6_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM6_IC2 134U /*!< GPDMA1 HW request is LPTIM6_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM6_UE 135U /*!< GPDMA1 HW request is LPTIM6_UE */ +#endif /* LPTIM6 */ +#if defined (I3C2) +#define LL_GPDMA1_REQUEST_I3C2_RX 136U /*!< GPDMA1 HW request is I3C2_RX */ +#define LL_GPDMA1_REQUEST_I3C2_TX 137U /*!< GPDMA1 HW request is I3C2_TX */ +#define LL_GPDMA1_REQUEST_I3C2_TC 138U /*!< GPDMA1 HW request is I3C2_TC */ +#define LL_GPDMA1_REQUEST_I3C2_RS 139U /*!< GPDMA1 HW request is I3C2_RS */ +#endif /* I3C2 */ +#if defined (JPEG) +#define LL_GPDMA1_REQUEST_JPEG_RX_REQ 140U /*!< GPDMA1 HW request is JPEG_TX_REQ */ +#define LL_GPDMA1_REQUEST_JPEG_TX_REQ 141U /*!< GPDMA1 HW request is JPEG_TX_REQ */ +#endif /* JPEG */ +#if defined (ADC3) +#define LL_GPDMA1_REQUEST_ADC3 142U /*!< GPDMA1 HW request is ADC3 */ +#endif /* ADC3 */ +#if defined (OCTOSPI2) +#define LL_GPDMA1_REQUEST_OCTOSPI2 143U /*!< GPDMA1 HW request is OCTOSPI2 */ +#endif /* OCTOSPI2 */ +#if defined (MDF1) +#define LL_GPDMA1_REQUEST_MDF1_FLT0 144U /*!< GPDMA1 HW request is MDF1_FLT0 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT1 145U /*!< GPDMA1 HW request is MDF1_FLT1 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT2 146U /*!< GPDMA1 HW request is MDF1_FLT2 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT3 147U /*!< GPDMA1 HW request is MDF1_FLT3 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT4 148U /*!< GPDMA1 HW request is MDF1_FLT4 */ +#define LL_GPDMA1_REQUEST_MDF1_FLT5 149U /*!< GPDMA1 HW request is MDF1_FLT5 */ +#endif /* MDF1 */ +#if defined (ADF1) +#define LL_GPDMA1_REQUEST_ADF1_FLT0 150U /*!< GPDMA1 HW request is ADF1_FLT0 */ +#endif /* ADF1 */ + +/* GPDMA2 Hardware Requests */ +#define LL_GPDMA2_REQUEST_ADC1 0U /*!< GPDMA2 HW request is ADC1 */ +#if defined (ADC2) +#define LL_GPDMA2_REQUEST_ADC2 1U /*!< GPDMA2 HW request is ADC2 */ +#endif /* ADC2 */ +#define LL_GPDMA2_REQUEST_DAC1_CH1 2U /*!< GPDMA2 HW request is DAC1_CH1 */ +#define LL_GPDMA2_REQUEST_DAC1_CH2 3U /*!< GPDMA2 HW request is DAC1_CH2 */ +#define LL_GPDMA2_REQUEST_TIM6_UP 4U /*!< GPDMA2 HW request is TIM6_UP */ +#define LL_GPDMA2_REQUEST_TIM7_UP 5U /*!< GPDMA2 HW request is TIM7_UP */ +#define LL_GPDMA2_REQUEST_SPI1_RX 6U /*!< GPDMA2 HW request is SPI1_RX */ +#define LL_GPDMA2_REQUEST_SPI1_TX 7U /*!< GPDMA2 HW request is SPI1_TX */ +#define LL_GPDMA2_REQUEST_SPI2_RX 8U /*!< GPDMA2 HW request is SPI2_RX */ +#define LL_GPDMA2_REQUEST_SPI2_TX 9U /*!< GPDMA2 HW request is SPI2_TX */ +#define LL_GPDMA2_REQUEST_SPI3_RX 10U /*!< GPDMA2 HW request is SPI3_RX */ +#define LL_GPDMA2_REQUEST_SPI3_TX 11U /*!< GPDMA2 HW request is SPI3_TX */ +#define LL_GPDMA2_REQUEST_I2C1_RX 12U /*!< GPDMA2 HW request is I2C1_RX */ +#define LL_GPDMA2_REQUEST_I2C1_TX 13U /*!< GPDMA2 HW request is I2C1_TX */ +#define LL_GPDMA2_REQUEST_I2C2_RX 15U /*!< GPDMA2 HW request is I2C2_RX */ +#define LL_GPDMA2_REQUEST_I2C2_TX 16U /*!< GPDMA2 HW request is I2C2_TX */ +#if defined (I2C3) +#define LL_GPDMA2_REQUEST_I2C3_RX 18U /*!< GPDMA2 HW request is I2C3_RX */ +#define LL_GPDMA2_REQUEST_I2C3_TX 19U /*!< GPDMA2 HW request is I2C3_TX */ +#endif /* I2C3 */ +#define LL_GPDMA2_REQUEST_USART1_RX 21U /*!< GPDMA2 HW request is USART1_RX */ +#define LL_GPDMA2_REQUEST_USART1_TX 22U /*!< GPDMA2 HW request is USART1_TX */ +#define LL_GPDMA2_REQUEST_USART2_RX 23U /*!< GPDMA2 HW request is USART2_RX */ +#define LL_GPDMA2_REQUEST_USART2_TX 24U /*!< GPDMA2 HW request is USART2_TX */ +#define LL_GPDMA2_REQUEST_USART3_RX 25U /*!< GPDMA2 HW request is USART3_RX */ +#define LL_GPDMA2_REQUEST_USART3_TX 26U /*!< GPDMA2 HW request is USART3_TX */ +#if defined (UART4) +#define LL_GPDMA2_REQUEST_UART4_RX 27U /*!< GPDMA2 HW request is UART4_RX */ +#define LL_GPDMA2_REQUEST_UART4_TX 28U /*!< GPDMA2 HW request is UART4_TX */ +#endif /* UART4 */ +#if defined (UART5) +#define LL_GPDMA2_REQUEST_UART5_RX 29U /*!< GPDMA2 HW request is UART5_RX */ +#define LL_GPDMA2_REQUEST_UART5_TX 30U /*!< GPDMA2 HW request is UART5_TX */ +#endif /* UART5 */ +#if defined (USART6) +#define LL_GPDMA2_REQUEST_USART6_RX 31U /*!< GPDMA2 HW request is USART6_RX */ +#define LL_GPDMA2_REQUEST_USART6_TX 32U /*!< GPDMA2 HW request is USART6_TX */ +#endif /* USART6 */ +#if defined (UART7) +#define LL_GPDMA2_REQUEST_UART7_RX 33U /*!< GPDMA2 HW request is UART7_RX */ +#define LL_GPDMA2_REQUEST_UART7_TX 34U /*!< GPDMA2 HW request is UART7_TX */ +#endif /* UART7 */ +#if defined (UART8) +#define LL_GPDMA2_REQUEST_UART8_RX 35U /*!< GPDMA2 HW request is UART8_RX */ +#define LL_GPDMA2_REQUEST_UART8_TX 36U /*!< GPDMA2 HW request is UART8_TX */ +#endif /* UART8 */ +#if defined (UART9) +#define LL_GPDMA2_REQUEST_UART9_RX 37U /*!< GPDMA2 HW request is UART9_RX */ +#define LL_GPDMA2_REQUEST_UART9_TX 38U /*!< GPDMA2 HW request is UART9_TX */ +#endif /* UART9 */ +#if defined (USART10) +#define LL_GPDMA2_REQUEST_USART10_RX 39U /*!< GPDMA2 HW request is USART10_RX */ +#define LL_GPDMA2_REQUEST_USART10_TX 40U /*!< GPDMA2 HW request is USART10_TX */ +#endif /* USART10 */ +#if defined (USART11) +#define LL_GPDMA2_REQUEST_USART11_RX 41U /*!< GPDMA2 HW request is USART11_RX */ +#define LL_GPDMA2_REQUEST_USART11_TX 42U /*!< GPDMA2 HW request is USART11_TX */ +#endif /* USART11 */ +#if defined (UART12) +#define LL_GPDMA2_REQUEST_UART12_RX 43U /*!< GPDMA2 HW request is UART12_RX */ +#define LL_GPDMA2_REQUEST_UART12_TX 44U /*!< GPDMA2 HW request is UART12_TX */ +#endif /* UART12 */ +#define LL_GPDMA2_REQUEST_LPUART1_RX 45U /*!< GPDMA2 HW request is LPUART1_RX */ +#define LL_GPDMA2_REQUEST_LPUART1_TX 46U /*!< GPDMA2 HW request is LPUART1_TX */ +#if defined (SPI4) +#define LL_GPDMA2_REQUEST_SPI4_RX 47U /*!< GPDMA2 HW request is SPI4_RX */ +#define LL_GPDMA2_REQUEST_SPI4_TX 48U /*!< GPDMA2 HW request is SPI4_TX */ +#endif /* SPI4 */ +#if defined (SPI5) +#define LL_GPDMA2_REQUEST_SPI5_RX 49U /*!< GPDMA2 HW request is SPI5_RX */ +#define LL_GPDMA2_REQUEST_SPI5_TX 50U /*!< GPDMA2 HW request is SPI5_TX */ +#endif /* SPI5 */ +#if defined (SPI6) +#define LL_GPDMA2_REQUEST_SPI6_RX 51U /*!< GPDMA2 HW request is SPI6_RX */ +#define LL_GPDMA2_REQUEST_SPI6_TX 52U /*!< GPDMA2 HW request is SPI6_TX */ +#endif /* SPI6 */ +#if defined (SAI1) +#define LL_GPDMA2_REQUEST_SAI1_A 53U /*!< GPDMA2 HW request is SAI1_A */ +#define LL_GPDMA2_REQUEST_SAI1_B 54U /*!< GPDMA2 HW request is SAI1_B */ +#endif /* SAI1 */ +#if defined (SAI2) +#define LL_GPDMA2_REQUEST_SAI2_A 55U /*!< GPDMA2 HW request is SAI2_A */ +#define LL_GPDMA2_REQUEST_SAI2_B 56U /*!< GPDMA2 HW request is SAI2_B */ +#endif /* SAI2 */ +#if defined (OCTOSPI1) +#define LL_GPDMA2_REQUEST_OCTOSPI1 57U /*!< GPDMA2 HW request is OCTOSPI1 */ +#endif /* OCTOSPI1 */ +#define LL_GPDMA2_REQUEST_TIM1_CH1 58U /*!< GPDMA2 HW request is TIM1_CH1 */ +#define LL_GPDMA2_REQUEST_TIM1_CH2 59U /*!< GPDMA2 HW request is TIM1_CH2 */ +#define LL_GPDMA2_REQUEST_TIM1_CH3 60U /*!< GPDMA2 HW request is TIM1_CH3 */ +#define LL_GPDMA2_REQUEST_TIM1_CH4 61U /*!< GPDMA2 HW request is TIM1_CH4 */ +#define LL_GPDMA2_REQUEST_TIM1_UP 62U /*!< GPDMA2 HW request is TIM1_UP */ +#define LL_GPDMA2_REQUEST_TIM1_TRIG 63U /*!< GPDMA2 HW request is TIM1_TRIG */ +#define LL_GPDMA2_REQUEST_TIM1_COM 64U /*!< GPDMA2 HW request is TIM1_COM */ +#if defined (TIM8) +#define LL_GPDMA2_REQUEST_TIM8_CH1 65U /*!< GPDMA2 HW request is TIM8_CH1 */ +#define LL_GPDMA2_REQUEST_TIM8_CH2 66U /*!< GPDMA2 HW request is TIM8_CH2 */ +#define LL_GPDMA2_REQUEST_TIM8_CH3 67U /*!< GPDMA2 HW request is TIM8_CH3 */ +#define LL_GPDMA2_REQUEST_TIM8_CH4 68U /*!< GPDMA2 HW request is TIM8_CH4 */ +#define LL_GPDMA2_REQUEST_TIM8_UP 69U /*!< GPDMA2 HW request is TIM8_UP */ +#define LL_GPDMA2_REQUEST_TIM8_TRIG 70U /*!< GPDMA2 HW request is TIM8_TRIG */ +#define LL_GPDMA2_REQUEST_TIM8_COM 71U /*!< GPDMA2 HW request is TIM8_COM */ +#endif /* TIM8 */ +#define LL_GPDMA2_REQUEST_TIM2_CH1 72U /*!< GPDMA2 HW request is TIM2_CH1 */ +#define LL_GPDMA2_REQUEST_TIM2_CH2 73U /*!< GPDMA2 HW request is TIM2_CH2 */ +#define LL_GPDMA2_REQUEST_TIM2_CH3 74U /*!< GPDMA2 HW request is TIM2_CH3 */ +#define LL_GPDMA2_REQUEST_TIM2_CH4 75U /*!< GPDMA2 HW request is TIM2_CH4 */ +#define LL_GPDMA2_REQUEST_TIM2_UP 76U /*!< GPDMA2 HW request is TIM2_UP */ +#define LL_GPDMA2_REQUEST_TIM3_CH1 77U /*!< GPDMA2 HW request is TIM3_CH1 */ +#define LL_GPDMA2_REQUEST_TIM3_CH2 78U /*!< GPDMA2 HW request is TIM3_CH2 */ +#define LL_GPDMA2_REQUEST_TIM3_CH3 79U /*!< GPDMA2 HW request is TIM3_CH3 */ +#define LL_GPDMA2_REQUEST_TIM3_CH4 80U /*!< GPDMA2 HW request is TIM3_CH4 */ +#define LL_GPDMA2_REQUEST_TIM3_UP 81U /*!< GPDMA2 HW request is TIM3_UP */ +#define LL_GPDMA2_REQUEST_TIM3_TRIG 82U /*!< GPDMA2 HW request is TIM3_TRIG */ +#if defined (TIM4) +#define LL_GPDMA2_REQUEST_TIM4_CH1 83U /*!< GPDMA2 HW request is TIM4_CH1 */ +#define LL_GPDMA2_REQUEST_TIM4_CH2 84U /*!< GPDMA2 HW request is TIM4_CH2 */ +#define LL_GPDMA2_REQUEST_TIM4_CH3 85U /*!< GPDMA2 HW request is TIM4_CH3 */ +#define LL_GPDMA2_REQUEST_TIM4_CH4 86U /*!< GPDMA2 HW request is TIM4_CH4 */ +#define LL_GPDMA2_REQUEST_TIM4_UP 87U /*!< GPDMA2 HW request is TIM4_UP */ +#endif /* TIM4 */ +#if defined (TIM5) +#define LL_GPDMA2_REQUEST_TIM5_CH1 88U /*!< GPDMA2 HW request is TIM5_CH1 */ +#define LL_GPDMA2_REQUEST_TIM5_CH2 89U /*!< GPDMA2 HW request is TIM5_CH2 */ +#define LL_GPDMA2_REQUEST_TIM5_CH3 90U /*!< GPDMA2 HW request is TIM5_CH3 */ +#define LL_GPDMA2_REQUEST_TIM5_CH4 91U /*!< GPDMA2 HW request is TIM5_CH4 */ +#define LL_GPDMA2_REQUEST_TIM5_UP 92U /*!< GPDMA2 HW request is TIM5_UP */ +#define LL_GPDMA2_REQUEST_TIM5_TRIG 93U /*!< GPDMA2 HW request is TIM5_TRIG */ +#endif /* TIM5 */ +#if defined (TIM15) +#define LL_GPDMA2_REQUEST_TIM15_CH1 94U /*!< GPDMA2 HW request is TIM15_CH1 */ +#define LL_GPDMA2_REQUEST_TIM15_UP 95U /*!< GPDMA2 HW request is TIM15_UP */ +#define LL_GPDMA2_REQUEST_TIM15_TRIG 96U /*!< GPDMA2 HW request is TIM15_TRIG */ +#define LL_GPDMA2_REQUEST_TIM15_COM 97U /*!< GPDMA2 HW request is TIM15_COM */ +#endif /* TIM15 */ +#if defined (TIM16) +#define LL_GPDMA2_REQUEST_TIM16_CH1 98U /*!< GPDMA2 HW request is TIM16_CH1 */ +#define LL_GPDMA2_REQUEST_TIM16_UP 99U /*!< GPDMA2 HW request is TIM16_UP */ +#endif /* TIM16 */ +#if defined (TIM17) +#define LL_GPDMA2_REQUEST_TIM17_CH1 100U /*!< GPDMA2 HW request is TIM17_CH1 */ +#define LL_GPDMA2_REQUEST_TIM17_UP 101U /*!< GPDMA2 HW request is TIM17_UP */ +#endif /* TIM17 */ +#define LL_GPDMA2_REQUEST_LPTIM1_IC1 102U /*!< GPDMA2 HW request is LPTIM1_IC1 */ +#define LL_GPDMA2_REQUEST_LPTIM1_IC2 103U /*!< GPDMA2 HW request is LPTIM1_IC2 */ +#define LL_GPDMA2_REQUEST_LPTIM1_UE 104U /*!< GPDMA2 HW request is LPTIM1_UE */ +#define LL_GPDMA2_REQUEST_LPTIM2_IC1 105U /*!< GPDMA2 HW request is LPTIM2_IC1 */ +#define LL_GPDMA2_REQUEST_LPTIM2_IC2 106U /*!< GPDMA2 HW request is LPTIM2_IC2 */ +#define LL_GPDMA2_REQUEST_LPTIM2_UE 107U /*!< GPDMA2 HW request is LPTIM2_UE */ +#if defined (DCMI) +#define LL_GPDMA2_REQUEST_DCMI 108U /*!< GPDMA2 HW request is DCMI */ +#endif /* DCMI */ +#if defined (AES) +#define LL_GPDMA2_REQUEST_AES_OUT 109U /*!< GPDMA2 HW request is AES_OUT */ +#define LL_GPDMA2_REQUEST_AES_IN 110U /*!< GPDMA2 HW request is AES_IN */ +#endif /* AES */ +#define LL_GPDMA2_REQUEST_HASH_IN 111U /*!< GPDMA2 HW request is HASH_IN */ +#if defined (UCPD1) +#define LL_GPDMA2_REQUEST_UCPD1_RX 112U /*!< GPDMA2 HW request is UCPD1_RX */ +#define LL_GPDMA2_REQUEST_UCPD1_TX 113U /*!< GPDMA2 HW request is UCPD1_TX */ +#endif /* UCPD1 */ +#if defined (CORDIC) +#define LL_GPDMA2_REQUEST_CORDIC_READ 114U /*!< GPDMA2 HW request is CORDIC_READ */ +#define LL_GPDMA2_REQUEST_CORDIC_WRITE 115U /*!< GPDMA2 HW request is CORDIC_WRITE */ +#endif /* CORDIC */ +#if defined (FMAC) +#define LL_GPDMA2_REQUEST_FMAC_READ 116U /*!< GPDMA2 HW request is FMAC_READ */ +#define LL_GPDMA2_REQUEST_FMAC_WRITE 117U /*!< GPDMA2 HW request is FMAC_WRITE */ +#endif /* FMAC */ +#if defined (SAES) +#define LL_GPDMA2_REQUEST_SAES_OUT 118U /*!< GPDMA2 HW request is SAES_OUT */ +#define LL_GPDMA2_REQUEST_SAES_IN 119U /*!< GPDMA2 HW request is SAES_IN */ +#endif /* SAES */ +#define LL_GPDMA2_REQUEST_I3C1_RX 120U /*!< GPDMA2 HW request is I3C1_RX */ +#define LL_GPDMA2_REQUEST_I3C1_TX 121U /*!< GPDMA2 HW request is I3C1_TX */ +#define LL_GPDMA2_REQUEST_I3C1_TC 122U /*!< GPDMA2 HW request is I3C1_TC */ +#define LL_GPDMA2_REQUEST_I3C1_RS 123U /*!< GPDMA2 HW request is I3C1_RS */ +#if defined (I2C4) +#define LL_GPDMA2_REQUEST_I2C4_RX 124U /*!< GPDMA2 HW request is I2C4_RX */ +#define LL_GPDMA2_REQUEST_I2C4_TX 125U /*!< GPDMA2 HW request is I2C4_TX */ +#endif /* I2C4 */ +#if defined (LPTIM3) +#define LL_GPDMA2_REQUEST_LPTIM3_IC1 127U /*!< GPDMA2 HW request is LPTIM3_IC1 */ +#define LL_GPDMA2_REQUEST_LPTIM3_IC2 128U /*!< GPDMA2 HW request is LPTIM3_IC2 */ +#define LL_GPDMA2_REQUEST_LPTIM3_UE 129U /*!< GPDMA2 HW request is LPTIM3_UE */ +#endif /* LPTIM3 */ +#if defined (LPTIM5) +#define LL_GPDMA2_REQUEST_LPTIM5_IC1 130U /*!< GPDMA2 HW request is LPTIM5_IC1 */ +#define LL_GPDMA2_REQUEST_LPTIM5_IC2 131U /*!< GPDMA2 HW request is LPTIM5_IC2 */ +#define LL_GPDMA2_REQUEST_LPTIM5_UE 132U /*!< GPDMA2 HW request is LPTIM5_UE */ +#endif /* LPTIM5 */ +#if defined (LPTIM6) +#define LL_GPDMA2_REQUEST_LPTIM6_IC1 133U /*!< GPDMA2 HW request is LPTIM6_IC1 */ +#define LL_GPDMA2_REQUEST_LPTIM6_IC2 134U /*!< GPDMA2 HW request is LPTIM6_IC2 */ +#define LL_GPDMA2_REQUEST_LPTIM6_UE 135U /*!< GPDMA2 HW request is LPTIM6_UE */ +#endif /* LPTIM6 */ +#if defined (I3C2) +#define LL_GPDMA2_REQUEST_I3C2_RX 136U /*!< GPDMA2 HW request is I3C2_RX */ +#define LL_GPDMA2_REQUEST_I3C2_TX 137U /*!< GPDMA2 HW request is I3C2_TX */ +#define LL_GPDMA2_REQUEST_I3C2_TC 138U /*!< GPDMA2 HW request is I3C2_TC */ +#define LL_GPDMA2_REQUEST_I3C2_RS 139U /*!< GPDMA2 HW request is I3C2_RS */ +#endif /* I3C2 */ +#if defined (JPEG) +#define LL_GPDMA2_REQUEST_JPEG_RX_REQ 140U /*!< GPDMA2 HW request is JPEG_TX_REQ */ +#define LL_GPDMA2_REQUEST_JPEG_TX_REQ 141U /*!< GPDMA2 HW request is JPEG_TX_REQ */ +#endif /* JPEG */ +#if defined (ADC3) +#define LL_GPDMA2_REQUEST_ADC3 142U /*!< GPDMA2 HW request is ADC3 */ +#endif /* ADC3 */ +#if defined (OCTOSPI2) +#define LL_GPDMA2_REQUEST_OCTOSPI2 143U /*!< GPDMA2 HW request is OCTOSPI2 */ +#endif /* OCTOSPI2 */ +#if defined (MDF1) +#define LL_GPDMA2_REQUEST_MDF1_FLT0 144U /*!< GPDMA2 HW request is MDF1_FLT0 */ +#define LL_GPDMA2_REQUEST_MDF1_FLT1 145U /*!< GPDMA2 HW request is MDF1_FLT1 */ +#define LL_GPDMA2_REQUEST_MDF1_FLT2 146U /*!< GPDMA2 HW request is MDF1_FLT2 */ +#define LL_GPDMA2_REQUEST_MDF1_FLT3 147U /*!< GPDMA2 HW request is MDF1_FLT3 */ +#define LL_GPDMA2_REQUEST_MDF1_FLT4 148U /*!< GPDMA2 HW request is MDF1_FLT4 */ +#define LL_GPDMA2_REQUEST_MDF1_FLT5 149U /*!< GPDMA2 HW request is MDF1_FLT5 */ +#endif /* MDF1 */ +#if defined (ADF1) +#define LL_GPDMA2_REQUEST_ADF1_FLT0 150U /*!< GPDMA2 HW request is ADF1_FLT0 */ +#endif /* ADF1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection + * @{ + */ +/* GPDMA1 Hardware Triggers */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */ +#define LL_GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */ +#define LL_GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */ +#if defined (TAMP_CR1_TAMP3E) +#define LL_GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */ +#endif /* TAMP_CR1_TAMP3E */ +#define LL_GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 15U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ +#define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 16U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ +#define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 17U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 18U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 19U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 20U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 21U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA2_CH0_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH0_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA2_CH1_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH1_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA2_CH2_TCF 28U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH2_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA2_CH3_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH3_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA2_CH4_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH4_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA2_CH5_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH5_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA2_CH6_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH6_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA2_CH7_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH7_TCF */ +#define LL_GPDMA1_TRIGGER_TIM2_TRGO 34U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ +#if defined (TIM15) +#define LL_GPDMA1_TRIGGER_TIM15_TRGO 35U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ +#endif /* TIM15 */ +#if defined (TIM12) +#define LL_GPDMA1_TRIGGER_TIM12_TRGO 36U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */ +#endif /* TIM12 */ +#if defined (LPTIM3) +#define LL_GPDMA1_TRIGGER_LPTIM3_CH1 37U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM3_CH2 38U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */ +#endif /* LPTIM3 */ +#if defined (LPTIM4) +#define LL_GPDMA1_TRIGGER_LPTIM4_AIT 39U /*!< GPDMA1 HW Trigger signal is LPTIM4_AIT */ +#endif /* LPTIM4 */ +#if defined (LPTIM5) +#define LL_GPDMA1_TRIGGER_LPTIM5_CH1 40U /*!< GPDMA1 HW Trigger signal is LPTIM5_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM5_CH2 41U /*!< GPDMA1 HW Trigger signal is LPTIM5_CH2 */ +#endif /* LPTIM5 */ +#if defined (LPTIM6) +#define LL_GPDMA1_TRIGGER_LPTIM6_CH1 42U /*!< GPDMA1 HW Trigger signal is LPTIM6_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM6_CH2 43U /*!< GPDMA1 HW Trigger signal is LPTIM6_CH2 */ +#endif /* LPTIM6 */ +#if defined (COMP1) +#define LL_GPDMA1_TRIGGER_COMP1_OUT 44U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ +#endif /* COMP1 */ +#if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) \ + || defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx) +#define LL_GPDMA1_TRIGGER_EVENTOUT 45U /*!< GPDMA1 HW Trigger signal is EVENTOUT */ +#endif /* STM32H503xx || STM32H523xx || STM32H533xx || STM32H5F5xx || STM32H5F4xx || + STM32H5E5xx || STM32H5E4xx || STM32H553xx || STM32H543xx */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx)|| defined(STM32H553xx) || defined(STM32H543xx) +#define LL_GPDMA1_TRIGGER_COMP2_OUT 46U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define LL_GPDMA1_TRIGGER_DMA2D_TC_FLAG 47U /*!< GPDMA1 HW Trigger signal is TC_FLAG */ +#define LL_GPDMA1_TRIGGER_DMA2D_CTC_FLAG 48U /*!< GPDMA1 HW Trigger signal is CTC_FLAG */ +#define LL_GPDMA1_TRIGGER_DMA2D_TW_FLAG 49U /*!< GPDMA1 HW Trigger signal is TW_FLAG */ +#define LL_GPDMA1_TRIGGER_DMA2D_GPFLAGS0 50U /*!< GPDMA1 HW Trigger signal is GPFLAGS[0] */ +#define LL_GPDMA1_TRIGGER_DMA2D_GPFLAGS1 51U /*!< GPDMA1 HW Trigger signal is GPFLAGS[1] */ +#define LL_GPDMA1_TRIGGER_DMA2D_GPFLAGS2 52U /*!< GPDMA1 HW Trigger signal is GPFLAGS[2] */ +#define LL_GPDMA1_TRIGGER_DMA2D_GPFLAGS3 53U /*!< GPDMA1 HW Trigger signal is GPFLAGS[3] */ +#define LL_GPDMA1_TRIGGER_JPEG_IFT_FLAG 54U /*!< GPDMA1 HW Trigger signal is JPEG_IFT_FLAG */ +#define LL_GPDMA1_TRIGGER_JPEG_IFNF_FLAG 55U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF_FLAG */ +#define LL_GPDMA1_TRIGGER_JPEG_OFT_FLAG 56U /*!< GPDMA1 HW Trigger signal is JPEG_OFT_FLAG */ +#define LL_GPDMA1_TRIGGER_JPEG_OFNE_FLAG 57U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE_FLAG */ +#define LL_GPDMA1_TRIGGER_JPEG_EOC_FLAG 58U /*!< GPDMA1 HW Trigger signal is JPEG_EOC_FLAG */ +#define LL_GPDMA1_TRIGGER_GFXTIM_EVT1 59U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT[1] */ +#define LL_GPDMA1_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT[2] */ +#define LL_GPDMA1_TRIGGER_GFXTIM_EVT3 61U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT[2+4] */ +#define LL_GPDMA1_TRIGGER_GFXTIM_EVT4 62U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT[4] */ +#define LL_GPDMA1_TRIGGER_LCD_CTRL_SCANLINE 63U /*!< GPDMA1 HW Trigger signal is LCD_CTRL_SCANLINE */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF 64U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TC */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF 65U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TC */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF 66U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TC */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF 67U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TC */ +#define LL_GPDMA1_TRIGGER_GPDMA2_CH8_TCF 68U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH8_TC */ +#define LL_GPDMA1_TRIGGER_GPDMA2_CH9_TCF 69U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH9_TC */ +#define LL_GPDMA1_TRIGGER_GPDMA2_CH10_TCF 70U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH10_TC */ +#define LL_GPDMA1_TRIGGER_GPDMA2_CH11_TCF 71U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH11_TC */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#define LL_GPDMA1_TRIGGER_PLAY1_OUT15 72U /*!< GPDMA1 HW Trigger signal is PLAY1_OUT15 */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx || STM32H553xx || STM32H543xx*/ + +/* GPDMA2 Hardware Triggers */ +#define LL_GPDMA2_TRIGGER_EXTI_LINE0 0U /*!< GPDMA2 HW Trigger signal is EXTI_LINE0 */ +#define LL_GPDMA2_TRIGGER_EXTI_LINE1 1U /*!< GPDMA2 HW Trigger signal is EXTI_LINE1 */ +#define LL_GPDMA2_TRIGGER_EXTI_LINE2 2U /*!< GPDMA2 HW Trigger signal is EXTI_LINE2 */ +#define LL_GPDMA2_TRIGGER_EXTI_LINE3 3U /*!< GPDMA2 HW Trigger signal is EXTI_LINE3 */ +#define LL_GPDMA2_TRIGGER_EXTI_LINE4 4U /*!< GPDMA2 HW Trigger signal is EXTI_LINE4 */ +#define LL_GPDMA2_TRIGGER_EXTI_LINE5 5U /*!< GPDMA2 HW Trigger signal is EXTI_LINE5 */ +#define LL_GPDMA2_TRIGGER_EXTI_LINE6 6U /*!< GPDMA2 HW Trigger signal is EXTI_LINE6 */ +#define LL_GPDMA2_TRIGGER_EXTI_LINE7 7U /*!< GPDMA2 HW Trigger signal is EXTI_LINE7 */ +#define LL_GPDMA2_TRIGGER_TAMP_TRG1 8U /*!< GPDMA2 HW Trigger signal is TAMP_TRG1 */ +#define LL_GPDMA2_TRIGGER_TAMP_TRG2 9U /*!< GPDMA2 HW Trigger signal is TAMP_TRG2 */ +#define LL_GPDMA2_TRIGGER_TAMP_TRG3 10U /*!< GPDMA2 HW Trigger signal is TAMP_TRG3 */ +#define LL_GPDMA2_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA2 HW Trigger signal is LPTIM1_CH1 */ +#define LL_GPDMA2_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA2 HW Trigger signal is LPTIM1_CH2 */ +#define LL_GPDMA2_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA2 HW Trigger signal is LPTIM2_CH1 */ +#define LL_GPDMA2_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA2 HW Trigger signal is LPTIM2_CH2 */ +#define LL_GPDMA2_TRIGGER_RTC_ALRA_TRG 15U /*!< GPDMA2 HW Trigger signal is RTC_ALRA_TRG */ +#define LL_GPDMA2_TRIGGER_RTC_ALRB_TRG 16U /*!< GPDMA2 HW Trigger signal is RTC_ALRB_TRG */ +#define LL_GPDMA2_TRIGGER_RTC_WUT_TRG 17U /*!< GPDMA2 HW Trigger signal is RTC_WUT_TRG */ +#define LL_GPDMA2_TRIGGER_GPDMA1_CH0_TCF 18U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH0_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA1_CH1_TCF 19U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH1_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA1_CH2_TCF 20U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH2_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA1_CH3_TCF 21U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH3_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA1_CH4_TCF 22U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH4_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA1_CH5_TCF 23U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH5_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA1_CH6_TCF 24U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH6_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA1_CH7_TCF 25U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH7_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA2_CH0_TCF 26U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH0_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA2_CH1_TCF 27U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH1_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA2_CH2_TCF 28U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH2_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA2_CH3_TCF 29U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH3_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA2_CH4_TCF 30U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH4_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA2_CH5_TCF 31U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH5_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA2_CH6_TCF 32U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH6_TCF */ +#define LL_GPDMA2_TRIGGER_GPDMA2_CH7_TCF 33U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH7_TCF */ +#define LL_GPDMA2_TRIGGER_TIM2_TRGO 34U /*!< GPDMA2 HW Trigger signal is TIM2_TRGO */ +#if defined (TIM15) +#define LL_GPDMA2_TRIGGER_TIM15_TRGO 35U /*!< GPDMA2 HW Trigger signal is TIM15_TRGO */ +#endif /* TIM15 */ +#if defined (TIM12) +#define LL_GPDMA2_TRIGGER_TIM12_TRGO 36U /*!< GPDMA2 HW Trigger signal is TIM12_TRGO */ +#endif /* TIM12 */ +#if defined (LPTIM3) +#define LL_GPDMA2_TRIGGER_LPTIM3_CH1 37U /*!< GPDMA2 HW Trigger signal is LPTIM3_CH1 */ +#define LL_GPDMA2_TRIGGER_LPTIM3_CH2 38U /*!< GPDMA2 HW Trigger signal is LPTIM3_CH2 */ +#endif /* LPTIM3 */ +#if defined (LPTIM4) +#define LL_GPDMA2_TRIGGER_LPTIM4_AIT 39U /*!< GPDMA2 HW Trigger signal is LPTIM4_AIT */ +#endif /* LPTIM4 */ +#if defined (LPTIM5) +#define LL_GPDMA2_TRIGGER_LPTIM5_CH1 40U /*!< GPDMA2 HW Trigger signal is LPTIM5_CH1 */ +#define LL_GPDMA2_TRIGGER_LPTIM5_CH2 41U /*!< GPDMA2 HW Trigger signal is LPTIM5_CH2 */ +#endif /* LPTIM5 */ +#if defined (LPTIM6) +#define LL_GPDMA2_TRIGGER_LPTIM6_CH1 42U /*!< GPDMA2 HW Trigger signal is LPTIM6_CH1 */ +#define LL_GPDMA2_TRIGGER_LPTIM6_CH2 43U /*!< GPDMA2 HW Trigger signal is LPTIM6_CH2 */ +#endif /* LPTIM6 */ +#if defined (COMP1) +#define LL_GPDMA2_TRIGGER_COMP1_OUT 44U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */ +#endif /* COMP1 */ +#if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) \ + || defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx) +#define LL_GPDMA2_TRIGGER_EVENTOUT 45U /*!< GPDMA2 HW Trigger signal is EVENTOUT */ +#endif /* STM32H503xx || STM32H523xx || STM32H533xx || STM32H5F5xx || STM32H5F4xx || + STM32H5E5xx || STM32H5E4xx || STM32H553xx || STM32H543xx */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H553xx) || defined(STM32H543xx) +#define LL_GPDMA2_TRIGGER_COMP2_OUT 46U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */ +#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx) +#define LL_GPDMA2_TRIGGER_DMA2D_TC_FLAG 47U /*!< GPDMA2 HW Trigger signal is TC_FLAG */ +#define LL_GPDMA2_TRIGGER_DMA2D_CTC_FLAG 48U /*!< GPDMA2 HW Trigger signal is CTC_FLAG */ +#define LL_GPDMA2_TRIGGER_DMA2D_TW_FLAG 49U /*!< GPDMA2 HW Trigger signal is TW_FLAG */ +#define LL_GPDMA2_TRIGGER_DMA2D_GPFLAGS0 50U /*!< GPDMA2 HW Trigger signal is GPFLAGS[0] */ +#define LL_GPDMA2_TRIGGER_DMA2D_GPFLAGS1 51U /*!< GPDMA2 HW Trigger signal is GPFLAGS[1] */ +#define LL_GPDMA2_TRIGGER_DMA2D_GPFLAGS2 52U /*!< GPDMA2 HW Trigger signal is GPFLAGS[2] */ +#define LL_GPDMA2_TRIGGER_DMA2D_GPFLAGS3 53U /*!< GPDMA2 HW Trigger signal is GPFLAGS[3] */ +#define LL_GPDMA2_TRIGGER_JPEG_IFT_FLAG 54U /*!< GPDMA2 HW Trigger signal is JPEG_IFT_FLAG */ +#define LL_GPDMA2_TRIGGER_JPEG_IFNF_FLAG 55U /*!< GPDMA2 HW Trigger signal is JPEG_IFNF_FLAG */ +#define LL_GPDMA2_TRIGGER_JPEG_OFT_FLAG 56U /*!< GPDMA2 HW Trigger signal is JPEG_OFT_FLAG */ +#define LL_GPDMA2_TRIGGER_JPEG_OFNE_FLAG 57U /*!< GPDMA2 HW Trigger signal is JPEG_OFNE_FLAG */ +#define LL_GPDMA2_TRIGGER_JPEG_EOC_FLAG 58U /*!< GPDMA2 HW Trigger signal is JPEG_EOC_FLAG */ +#define LL_GPDMA2_TRIGGER_GFXTIM_EVT1 59U /*!< GPDMA2 HW Trigger signal is GFXTIM_EVT[1] */ +#define LL_GPDMA2_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA2 HW Trigger signal is GFXTIM_EVT[2] */ +#define LL_GPDMA2_TRIGGER_GFXTIM_EVT3 61U /*!< GPDMA2 HW Trigger signal is GFXTIM_EVT[2+4] */ +#define LL_GPDMA2_TRIGGER_GFXTIM_EVT4 62U /*!< GPDMA2 HW Trigger signal is GFXTIM_EVT[4] */ +#define LL_GPDMA2_TRIGGER_LCD_CTRL_SCANLINE 63U /*!< GPDMA2 HW Trigger signal is LCD_CTRL_SCANLINE */ +#define LL_GPDMA2_TRIGGER_GPDMA1_CH8_TCF 64U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH8_TC */ +#define LL_GPDMA2_TRIGGER_GPDMA1_CH9_TCF 65U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH9_TC */ +#define LL_GPDMA2_TRIGGER_GPDMA1_CH10_TCF 66U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH10_TC */ +#define LL_GPDMA2_TRIGGER_GPDMA1_CH11_TCF 67U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH11_TC */ +#define LL_GPDMA2_TRIGGER_GPDMA2_CH8_TCF 68U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH8_TC */ +#define LL_GPDMA2_TRIGGER_GPDMA2_CH9_TCF 69U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH9_TC */ +#define LL_GPDMA2_TRIGGER_GPDMA2_CH10_TCF 70U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH10_TC */ +#define LL_GPDMA2_TRIGGER_GPDMA2_CH11_TCF 71U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH11_TC */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */ +#define LL_GPDMA2_TRIGGER_PLAY1_OUT15 72U /*!< GPDMA2 HW Trigger signal is PLAY1_OUT15 */ +#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx || STM32H553xx || STM32H543xx */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros + * @{ + */ +/** + * @brief Write a value in DMA register. + * @param __INSTANCE__ DMA Instance. + * @param __REG__ Register to be written. + * @param __VALUE__ Value to be written in the register. + * @retval None. + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register. + * @param __INSTANCE__ DMA Instance. + * @param __REG__ Register to be read. + * @retval Register value. + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx. + * @param __CHANNEL_INSTANCE__ DMAx_Channely. + * @retval DMAx. + */ +#if defined(GPDMA1_Channel11) +#define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel11)) ? GPDMA2 : GPDMA1) +#else +#define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel7)) ? GPDMA2 : GPDMA1) +#endif /* GPDMA1_Channel11 */ + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y. + * @param __CHANNEL_INSTANCE__ DMAx_Channely. + * @retval LL_DMA_CHANNEL_y. + */ +#if defined(GPDMA1_Channel11) +#define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel7)) ? LL_DMA_CHANNEL_7 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel8)) ? LL_DMA_CHANNEL_8 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel9)) ? LL_DMA_CHANNEL_9 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel10)) ? LL_DMA_CHANNEL_10 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \ + LL_DMA_CHANNEL_11) +#else +#define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \ + LL_DMA_CHANNEL_7) +#endif /* GPDMA1_Channel11 */ + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely. + * @param __DMA_INSTANCE__ DMAx. + * @param __CHANNEL__ LL_DMA_CHANNEL_y. + * @retval DMAx_Channely. + */ +#if defined(GPDMA1_Channel11) +#define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? GPDMA1_Channel0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? GPDMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? GPDMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? GPDMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \ + ? GPDMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \ + ? GPDMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \ + ? GPDMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \ + ? GPDMA1_Channel7 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \ + ? GPDMA1_Channel8 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \ + ? GPDMA1_Channel9 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\ + ? GPDMA1_Channel10 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\ + ? GPDMA1_Channel11 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? GPDMA2_Channel0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? GPDMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2)))\ + ? GPDMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3)))\ + ? GPDMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4)))\ + ? GPDMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5)))\ + ? GPDMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6)))\ + ? GPDMA2_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7)))\ + ? GPDMA2_Channel7 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8)))\ + ? GPDMA2_Channel8 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9)))\ + ? GPDMA2_Channel9 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\ + ? GPDMA2_Channel10 : GPDMA2_Channel11) +#else +#define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? GPDMA1_Channel0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? GPDMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? GPDMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? GPDMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \ + ? GPDMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \ + ? GPDMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \ + ? GPDMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \ + ? GPDMA1_Channel7 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? GPDMA2_Channel0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? GPDMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2)))\ + ? GPDMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3)))\ + ? GPDMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4)))\ + ? GPDMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5)))\ + ? GPDMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6)))\ + ? GPDMA2_Channel6 : GPDMA2_Channel7) +#endif /* GPDMA1_Channel11 */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance. + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance. + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + (DMA_CCR_SUSP | DMA_CCR_RESET)); +} + +/** + * @brief Check if channel is enabled or disabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN) + == (DMA_CCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Reset channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR RESET LL_DMA_ResetChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ResetChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET); +} + +/** + * @brief Suspend channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_SuspendChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SuspendChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP); +} + +/** + * @brief Resume channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_ResumeChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ResumeChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP); +} + +/** + * @brief Check if channel is suspended. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP) + == (DMA_CCR_SUSP)) ? 1UL : 0UL); +} + +/** + * @brief Set linked-list base address. + * @note This API is used for all available DMA channels. + * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes + * are always 0) + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t LinkedListBaseAddr) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA, + (LinkedListBaseAddr & DMA_CLBAR_LBA)); +} + +/** + * @brief Get linked-list base address. + * @note This API is used for all available DMA channels. + * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0) + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA)); +} + +/** + * @brief Configure all parameters linked to channel control. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_ConfigControl\n + * CCR LAP LL_DMA_ConfigControl\n + * CCR LSM LL_DMA_ConfigControl + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or + * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1 + * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); +} + +/** + * @brief Set priority level. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT + * @arg @ref LL_DMA_HIGH_PRIORITY + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority); +} + +/** + * @brief Get Channel priority level. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT + * @arg @ref LL_DMA_HIGH_PRIORITY + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO)); +} + +/** + * @brief Set linked-list allocated port. + * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param LinkAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_LAP, LinkAllocatedPort); +} + +/** + * @brief Get linked-list allocated port. + * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP)); +} + +/** + * @brief Set link step mode. + * @note This API is used for all available DMA channels. + * @rmtoll CCR LSM LL_DMA_SetLinkStepMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param LinkStepMode This parameter can be one of the following values: + * @arg @ref LL_DMA_LSM_FULL_EXECUTION + * @arg @ref LL_DMA_LSM_1LINK_EXECUTION + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode); +} + +/** + * @brief Get Link step mode. + * @note This API is used for all available DMA channels. + * @rmtoll CCR LSM LL_DMA_GetLinkStepMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LSM_FULL_EXECUTION + * @arg @ref LL_DMA_LSM_1LINK_EXECUTION + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM)); +} + +/** + * @brief Configure data transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n + * CTR1 DHX LL_DMA_ConfigTransfer\n + * CTR1 DBX LL_DMA_ConfigTransfer\n + * CTR1 DINC LL_DMA_ConfigTransfer\n + * CTR1 SAP LL_DMA_ConfigTransfer\n + * CTR1 SBX LL_DMA_ConfigTransfer\n + * CTR1 PAM LL_DMA_ConfigTransfer\n + * CTR1 SINC LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1 + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE + * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or + * @ref LL_DMA_DEST_DATAWIDTH_WORD + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1 + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or + * @ref LL_DMA_DATA_PACK_UNPACK + * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or + * @ref LL_DMA_SRC_DATAWIDTH_WORD + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \ + DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); +} + +/** + * @brief Configure source and destination burst length. + * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n + * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param SrcBurstLength Between 1 to 64 + * @param DestBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength, + uint32_t DestBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \ + (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1)); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure all secure parameters linked to DMA channel. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SEC LL_DMA_ConfigChannelSecure\n + * @rmtoll CTR1 SSEC LL_DMA_ConfigChannelSecure\n + * @rmtoll CTR1 DSEC LL_DMA_ConfigChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_CHANNEL_NSEC or @ref LL_DMA_CHANNEL_SEC + * @arg @ref LL_DMA_CHANNEL_SRC_NSEC or @ref LL_DMA_CHANNEL_SRC_SEC + * @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel)); + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); +} + +/** + * @brief Enable security attribute of the DMA transfer to the destination. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DSEC LL_DMA_EnableChannelDestSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC); +} + +/** + * @brief Disable security attribute of the DMA transfer to the destination. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DSEC LL_DMA_DisableChannelDestSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined (DMA_SECCFGR_SEC0) +/** + * @brief Check security attribute of the DMA transfer to the destination. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DSEC LL_DMA_IsEnabledChannelDestSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC) + == (DMA_CTR1_DSEC)) ? 1UL : 0UL); +} +#endif /* DMA_SECCFGR_SEC0 */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable security attribute of the DMA transfer from the source. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SSEC LL_DMA_EnableChannelSrcSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); +} + +/** + * @brief Disable security attribute of the DMA transfer from the source. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SSEC LL_DMA_DisableChannelSrcSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined (DMA_SECCFGR_SEC0) +/** + * @brief Check security attribute of the DMA transfer from the source. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SSEC LL_DMA_IsEnabledChannelSrcSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC) + == (DMA_CTR1_SSEC)) ? 1UL : 0UL); +} +#endif /* DMA_SECCFGR_SEC0 */ + +/** + * @brief Set destination allocated port. + * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param DestAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP, + DestAllocatedPort); +} + +/** + * @brief Get destination allocated port. + * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP)); +} + +/** + * @brief Set destination half-word exchange. + * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param DestHWordExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE + * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX, + DestHWordExchange); +} + +/** + * @brief Get destination half-word exchange. + * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE + * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX)); +} + +/** + * @brief Set destination byte exchange. + * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param DestByteExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE + * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX, + DestByteExchange); +} + +/** + * @brief Get destination byte exchange. + * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE + * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX)); +} + +/** + * @brief Set source byte exchange. + * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param SrcByteExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE + * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX, + SrcByteExchange); +} + +/** + * @brief Get source byte exchange. + * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE + * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX)); +} + +/** + * @brief Set destination burst length. + * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param DestBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1, + ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1); +} + +/** + * @brief Get destination burst length. + * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Between 1 to 64. + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U); +} + +/** + * @brief Set destination increment mode. + * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param DestInc This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_FIXED + * @arg @ref LL_DMA_DEST_INCREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc); +} + +/** + * @brief Get destination increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_FIXED + * @arg @ref LL_DMA_DEST_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC)); +} + +/** + * @brief Set destination data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param DestDataWidth This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE + * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2, + DestDataWidth); +} + +/** + * @brief Get destination data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE + * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2)); +} + +/** + * @brief Set source allocated port. + * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param SrcAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP, + SrcAllocatedPort); +} + +/** + * @brief Get source allocated port. + * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP)); +} + +/** + * @brief Set data alignment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD + * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD + * @arg @ref LL_DMA_DATA_PACK_UNPACK + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM, + DataAlignment); +} + +/** + * @brief Get data alignment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD + * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD + * @arg @ref LL_DMA_DATA_PACK_UNPACK + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM)); +} + +/** + * @brief Set source burst length. + * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param SrcBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1, + ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1); +} + +/** + * @brief Get source burst length. + * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U); +} + +/** + * @brief Set source increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param SrcInc This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_FIXED + * @arg @ref LL_DMA_SRC_INCREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc); +} + +/** + * @brief Get source increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_FIXED + * @arg @ref LL_DMA_SRC_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC)); +} + +/** + * @brief Set source data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param SrcDataWidth This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE + * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2, + SrcDataWidth); +} + +/** + * @brief Get Source Data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE + * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2)); +} + +/** + * @brief Configure channel transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n + * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n + * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n + * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 SWREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 PFREQ LL_DMA_ConfigChannelTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or + * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or + * @ref LL_DMA_TRIG_POLARITY_FALLING + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or + * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or + * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_NORMAL or @ref LL_DMA_PFCTRL + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ | + DMA_CTR2_PFREQ), Configuration); +} + +/** + * @brief Set transfer event mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param TransferEventMode This parameter can be one of the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER + * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM, + TransferEventMode); +} + +/** + * @brief Get transfer event mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER + * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + */ +__STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM)); +} + +/** + * @brief Set trigger polarity. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param TriggerPolarity This parameter can be one of the following values: + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED + * @arg @ref LL_DMA_TRIG_POLARITY_RISING + * @arg @ref LL_DMA_TRIG_POLARITY_FALLING + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL, + TriggerPolarity); +} + +/** + * @brief Get trigger polarity. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED + * @arg @ref LL_DMA_TRIG_POLARITY_RISING + * @arg @ref LL_DMA_TRIG_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL)); +} + +/** + * @brief Set trigger Mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param TriggerMode This parameter can be one of the following values: + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER + * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER + * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM, + TriggerMode); +} + +/** + * @brief Get trigger Mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER + * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER + * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + */ +__STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM)); +} + +/** + * @brief Set destination hardware and software transfer request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n + * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction); +} + +/** + * @brief Get destination hardware and software transfer request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n + * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_DREQ | DMA_CTR2_SWREQ)); +} + +/** + * @brief Set block hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param BlkHWRequest This parameter can be one of the following values: + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST + * @arg @ref LL_DMA_HWREQUEST_BLK + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ, + BlkHWRequest); +} + +/** + * @brief Get block hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST + * @arg @ref LL_DMA_HWREQUEST_BLK + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ)); +} + +/** + * @brief Set hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param Request This parameter can be one of the following values: + * @arg @ref LL_GPDMA1_REQUEST_ADC1 + * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*) + * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP + * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART1_RX + * @arg @ref LL_GPDMA1_REQUEST_USART1_TX + * @arg @ref LL_GPDMA1_REQUEST_USART2_RX + * @arg @ref LL_GPDMA1_REQUEST_USART2_TX + * @arg @ref LL_GPDMA1_REQUEST_USART3_RX + * @arg @ref LL_GPDMA1_REQUEST_USART3_TX + * @arg @ref LL_GPDMA1_REQUEST_UART4_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART4_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART5_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART5_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART7_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART7_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART8_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART8_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART9_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART9_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART10_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART10_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART11_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART11_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART12_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART12_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI1_A (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI1_B (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*) + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE + * @arg @ref LL_GPDMA1_REQUEST_DCMI (*) + * @arg @ref LL_GPDMA1_REQUEST_AES_OUT (*) + * @arg @ref LL_GPDMA1_REQUEST_AES_IN (*) + * @arg @ref LL_GPDMA1_REQUEST_HASH_IN + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ (*) + * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE (*) + * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ (*) + * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE (*) + * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT (*) + * @arg @ref LL_GPDMA1_REQUEST_SAES_IN (*) + * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC + * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS + * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_IC1 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_IC2 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_UE (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_IC1 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_IC2 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_UE (*) + * @arg @ref LL_GPDMA1_REQUEST_I3C2_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I3C2_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I3C2_TC (*) + * @arg @ref LL_GPDMA1_REQUEST_I3C2_RS (*) + * @arg @ref LL_GPDMA1_REQUEST_JPEG_RX_REQ (*) + * @arg @ref LL_GPDMA1_REQUEST_JPEG_TX_REQ (*) + * @arg @ref LL_GPDMA1_REQUEST_ADC3 (*) + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0 (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1 (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2 (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3 (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4 (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5 (*) + * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0 (*) + * + * @arg @ref LL_GPDMA2_REQUEST_ADC1 + * @arg @ref LL_GPDMA2_REQUEST_ADC2 (*) + * @arg @ref LL_GPDMA2_REQUEST_DAC1_CH1 + * @arg @ref LL_GPDMA2_REQUEST_DAC1_CH2 + * @arg @ref LL_GPDMA2_REQUEST_TIM6_UP + * @arg @ref LL_GPDMA2_REQUEST_TIM7_UP + * @arg @ref LL_GPDMA2_REQUEST_SPI1_RX + * @arg @ref LL_GPDMA2_REQUEST_SPI1_TX + * @arg @ref LL_GPDMA2_REQUEST_SPI2_RX + * @arg @ref LL_GPDMA2_REQUEST_SPI2_TX + * @arg @ref LL_GPDMA2_REQUEST_SPI3_RX + * @arg @ref LL_GPDMA2_REQUEST_SPI3_TX + * @arg @ref LL_GPDMA2_REQUEST_I2C1_RX + * @arg @ref LL_GPDMA2_REQUEST_I2C1_TX + * @arg @ref LL_GPDMA2_REQUEST_I2C2_RX + * @arg @ref LL_GPDMA2_REQUEST_I2C2_TX + * @arg @ref LL_GPDMA2_REQUEST_I2C3_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_I2C3_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART1_RX + * @arg @ref LL_GPDMA2_REQUEST_USART1_TX + * @arg @ref LL_GPDMA2_REQUEST_USART2_RX + * @arg @ref LL_GPDMA2_REQUEST_USART2_TX + * @arg @ref LL_GPDMA2_REQUEST_USART3_RX + * @arg @ref LL_GPDMA2_REQUEST_USART3_TX + * @arg @ref LL_GPDMA2_REQUEST_UART4_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART4_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART5_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART5_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART6_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART6_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART7_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART7_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART8_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART8_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART9_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART9_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART10_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART10_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART11_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART11_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART12_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART12_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_LPUART1_RX + * @arg @ref LL_GPDMA2_REQUEST_LPUART1_TX + * @arg @ref LL_GPDMA2_REQUEST_SPI4_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_SPI4_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_SPI5_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_SPI5_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_SPI6_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_SPI6_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_SAI1_A (*) + * @arg @ref LL_GPDMA2_REQUEST_SAI1_B (*) + * @arg @ref LL_GPDMA2_REQUEST_SAI2_A (*) + * @arg @ref LL_GPDMA2_REQUEST_SAI2_B (*) + * @arg @ref LL_GPDMA2_REQUEST_OCTOSPI1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH1 + * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH2 + * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH3 + * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH4 + * @arg @ref LL_GPDMA2_REQUEST_TIM1_UP + * @arg @ref LL_GPDMA2_REQUEST_TIM1_TRIG + * @arg @ref LL_GPDMA2_REQUEST_TIM1_COM + * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH2 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH3 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH4 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM8_UP (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM8_TRIG (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM8_COM (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH1 + * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH2 + * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH3 + * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH4 + * @arg @ref LL_GPDMA2_REQUEST_TIM2_UP + * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH1 + * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH2 + * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH3 + * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH4 + * @arg @ref LL_GPDMA2_REQUEST_TIM3_UP + * @arg @ref LL_GPDMA2_REQUEST_TIM3_TRIG + * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH2 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH3 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH4 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM4_UP (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH2 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH3 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH4 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM5_UP (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM5_TRIG (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM15_CH1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM15_UP (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM15_TRIG (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM15_COM (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM16_CH1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM16_UP (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM17_CH1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM17_UP (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_IC1 + * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_IC2 + * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_UE + * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_IC1 + * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_IC2 + * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_UE + * @arg @ref LL_GPDMA2_REQUEST_DCMI (*) + * @arg @ref LL_GPDMA2_REQUEST_AES_OUT (*) + * @arg @ref LL_GPDMA2_REQUEST_AES_IN (*) + * @arg @ref LL_GPDMA2_REQUEST_HASH_IN + * @arg @ref LL_GPDMA2_REQUEST_UCPD1_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UCPD1_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_CORDIC_READ (*) + * @arg @ref LL_GPDMA2_REQUEST_CORDIC_WRITE (*) + * @arg @ref LL_GPDMA2_REQUEST_FMAC_READ (*) + * @arg @ref LL_GPDMA2_REQUEST_FMAC_WRITE (*) + * @arg @ref LL_GPDMA2_REQUEST_SAES_OUT (*) + * @arg @ref LL_GPDMA2_REQUEST_SAES_IN (*) + * @arg @ref LL_GPDMA2_REQUEST_I3C1_RX + * @arg @ref LL_GPDMA2_REQUEST_I3C1_TX + * @arg @ref LL_GPDMA2_REQUEST_I3C1_TC + * @arg @ref LL_GPDMA2_REQUEST_I3C1_RS + * @arg @ref LL_GPDMA2_REQUEST_I2C4_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_I2C4_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_IC1 (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_IC2 (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_UE (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_IC1 (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_IC2 (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_UE (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_IC1 (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_IC2 (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_UE (*) + * @arg @ref LL_GPDMA2_REQUEST_I3C2_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_I3C2_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_I3C2_TC (*) + * @arg @ref LL_GPDMA2_REQUEST_I3C2_RS (*) + * @arg @ref LL_GPDMA2_REQUEST_JPEG_RX_REQ (*) + * @arg @ref LL_GPDMA2_REQUEST_JPEG_TX_REQ (*) + * @arg @ref LL_GPDMA2_REQUEST_ADC3 (*) + * @arg @ref LL_GPDMA2_REQUEST_OCTOSPI2 (*) + * @arg @ref LL_GPDMA2_REQUEST_MDF1_FLT0 (*) + * @arg @ref LL_GPDMA2_REQUEST_MDF1_FLT1 (*) + * @arg @ref LL_GPDMA2_REQUEST_MDF1_FLT2 (*) + * @arg @ref LL_GPDMA2_REQUEST_MDF1_FLT3 (*) + * @arg @ref LL_GPDMA2_REQUEST_MDF1_FLT4 (*) + * @arg @ref LL_GPDMA2_REQUEST_MDF1_FLT5 (*) + * @arg @ref LL_GPDMA2_REQUEST_ADF1_FLT0 (*) + * + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request); +} + +/** + * @brief Get hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPDMA1_REQUEST_ADC1 + * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*) + * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP + * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART1_RX + * @arg @ref LL_GPDMA1_REQUEST_USART1_TX + * @arg @ref LL_GPDMA1_REQUEST_USART2_RX + * @arg @ref LL_GPDMA1_REQUEST_USART2_TX + * @arg @ref LL_GPDMA1_REQUEST_USART3_RX + * @arg @ref LL_GPDMA1_REQUEST_USART3_TX + * @arg @ref LL_GPDMA1_REQUEST_UART4_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART4_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART5_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART5_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART7_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART7_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART8_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART8_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART9_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART9_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART10_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART10_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART11_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART11_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART12_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UART12_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI1_A (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI1_B (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*) + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE + * @arg @ref LL_GPDMA1_REQUEST_DCMI (*) + * @arg @ref LL_GPDMA1_REQUEST_AES_OUT (*) + * @arg @ref LL_GPDMA1_REQUEST_AES_IN (*) + * @arg @ref LL_GPDMA1_REQUEST_HASH_IN + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ (*) + * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE (*) + * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ (*) + * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE (*) + * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT (*) + * @arg @ref LL_GPDMA1_REQUEST_SAES_IN (*) + * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC + * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS + * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_IC1 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_IC2 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_UE (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_IC1 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_IC2 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_UE (*) + * @arg @ref LL_GPDMA1_REQUEST_I3C2_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I3C2_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I3C2_TC (*) + * @arg @ref LL_GPDMA1_REQUEST_I3C2_RS (*) + * @arg @ref LL_GPDMA1_REQUEST_JPEG_RX_REQ (*) + * @arg @ref LL_GPDMA1_REQUEST_JPEG_TX_REQ (*) + * @arg @ref LL_GPDMA1_REQUEST_ADC3 (*) + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0 (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1 (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2 (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3 (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4 (*) + * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5 (*) + * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0 (*) + * + * @arg @ref LL_GPDMA2_REQUEST_ADC1 + * @arg @ref LL_GPDMA2_REQUEST_ADC2 (*) + * @arg @ref LL_GPDMA2_REQUEST_DAC1_CH1 + * @arg @ref LL_GPDMA2_REQUEST_DAC1_CH2 + * @arg @ref LL_GPDMA2_REQUEST_TIM6_UP + * @arg @ref LL_GPDMA2_REQUEST_TIM7_UP + * @arg @ref LL_GPDMA2_REQUEST_SPI1_RX + * @arg @ref LL_GPDMA2_REQUEST_SPI1_TX + * @arg @ref LL_GPDMA2_REQUEST_SPI2_RX + * @arg @ref LL_GPDMA2_REQUEST_SPI2_TX + * @arg @ref LL_GPDMA2_REQUEST_SPI3_RX + * @arg @ref LL_GPDMA2_REQUEST_SPI3_TX + * @arg @ref LL_GPDMA2_REQUEST_I2C1_RX + * @arg @ref LL_GPDMA2_REQUEST_I2C1_TX + * @arg @ref LL_GPDMA2_REQUEST_I2C2_RX + * @arg @ref LL_GPDMA2_REQUEST_I2C2_TX + * @arg @ref LL_GPDMA2_REQUEST_I2C3_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_I2C3_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART1_RX + * @arg @ref LL_GPDMA2_REQUEST_USART1_TX + * @arg @ref LL_GPDMA2_REQUEST_USART2_RX + * @arg @ref LL_GPDMA2_REQUEST_USART2_TX + * @arg @ref LL_GPDMA2_REQUEST_USART3_RX + * @arg @ref LL_GPDMA2_REQUEST_USART3_TX + * @arg @ref LL_GPDMA2_REQUEST_UART4_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART4_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART5_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART5_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART6_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART6_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART7_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART7_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART8_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART8_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART9_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART9_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART10_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART10_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART11_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_USART11_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART12_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UART12_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_LPUART1_RX + * @arg @ref LL_GPDMA2_REQUEST_LPUART1_TX + * @arg @ref LL_GPDMA2_REQUEST_SPI4_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_SPI4_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_SPI5_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_SPI5_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_SPI6_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_SPI6_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_SAI1_A (*) + * @arg @ref LL_GPDMA2_REQUEST_SAI1_B (*) + * @arg @ref LL_GPDMA2_REQUEST_SAI2_A (*) + * @arg @ref LL_GPDMA2_REQUEST_SAI2_B (*) + * @arg @ref LL_GPDMA2_REQUEST_OCTOSPI1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH1 + * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH2 + * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH3 + * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH4 + * @arg @ref LL_GPDMA2_REQUEST_TIM1_UP + * @arg @ref LL_GPDMA2_REQUEST_TIM1_TRIG + * @arg @ref LL_GPDMA2_REQUEST_TIM1_COM + * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH2 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH3 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH4 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM8_UP (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM8_TRIG (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM8_COM (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH1 + * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH2 + * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH3 + * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH4 + * @arg @ref LL_GPDMA2_REQUEST_TIM2_UP + * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH1 + * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH2 + * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH3 + * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH4 + * @arg @ref LL_GPDMA2_REQUEST_TIM3_UP + * @arg @ref LL_GPDMA2_REQUEST_TIM3_TRIG + * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH2 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH3 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH4 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM4_UP (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH2 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH3 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH4 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM5_UP (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM5_TRIG (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM15_CH1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM15_UP (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM15_TRIG (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM15_COM (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM16_CH1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM16_UP (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM17_CH1 (*) + * @arg @ref LL_GPDMA2_REQUEST_TIM17_UP (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_IC1 + * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_IC2 + * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_UE + * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_IC1 + * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_IC2 + * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_UE + * @arg @ref LL_GPDMA2_REQUEST_DCMI (*) + * @arg @ref LL_GPDMA2_REQUEST_AES_OUT (*) + * @arg @ref LL_GPDMA2_REQUEST_AES_IN (*) + * @arg @ref LL_GPDMA2_REQUEST_HASH_IN + * @arg @ref LL_GPDMA2_REQUEST_UCPD1_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_UCPD1_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_CORDIC_READ (*) + * @arg @ref LL_GPDMA2_REQUEST_CORDIC_WRITE (*) + * @arg @ref LL_GPDMA2_REQUEST_FMAC_READ (*) + * @arg @ref LL_GPDMA2_REQUEST_FMAC_WRITE (*) + * @arg @ref LL_GPDMA2_REQUEST_SAES_OUT (*) + * @arg @ref LL_GPDMA2_REQUEST_SAES_IN (*) + * @arg @ref LL_GPDMA2_REQUEST_I3C1_RX + * @arg @ref LL_GPDMA2_REQUEST_I3C1_TX + * @arg @ref LL_GPDMA2_REQUEST_I3C1_TC + * @arg @ref LL_GPDMA2_REQUEST_I3C1_RS + * @arg @ref LL_GPDMA2_REQUEST_I2C4_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_I2C4_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_IC1 (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_IC2 (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_UE (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_IC1 (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_IC2 (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_UE (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_IC1 (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_IC2 (*) + * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_UE (*) + * @arg @ref LL_GPDMA2_REQUEST_I3C2_RX (*) + * @arg @ref LL_GPDMA2_REQUEST_I3C2_TX (*) + * @arg @ref LL_GPDMA2_REQUEST_I3C2_TC (*) + * @arg @ref LL_GPDMA2_REQUEST_I3C2_RS (*) + * @arg @ref LL_GPDMA2_REQUEST_JPEG_RX_REQ (*) + * @arg @ref LL_GPDMA2_REQUEST_JPEG_TX_REQ (*) + * @arg @ref LL_GPDMA2_REQUEST_ADC3 (*) + * @arg @ref LL_GPDMA2_REQUEST_OCTOSPI2 (*) + * @arg @ref LL_GPDMA2_REQUEST_MDF1_FLT0 (*) + * @arg @ref LL_GPDMA2_REQUEST_MDF1_FLT1 (*) + * @arg @ref LL_GPDMA2_REQUEST_MDF1_FLT2 (*) + * @arg @ref LL_GPDMA2_REQUEST_MDF1_FLT3 (*) + * @arg @ref LL_GPDMA2_REQUEST_MDF1_FLT4 (*) + * @arg @ref LL_GPDMA2_REQUEST_MDF1_FLT5 (*) + * @arg @ref LL_GPDMA2_REQUEST_ADF1_FLT0 (*) + * + * @note (*) Availability depends on devices. + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL)); +} + +/** + * @brief Set hardware trigger. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param Trigger This parameter can be one of the following values: + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE4 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE5 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE6 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE7 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_AIT + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_AIT (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT (*) + * @arg @ref LL_GPDMA1_TRIGGER_EVENTOUT (*) + * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_GPFLAGS0 (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_GPFLAGS1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_GPFLAGS2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_GPFLAGS3 (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT3 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT4 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LCD_CTRL_SCANLINE (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH8_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH9_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH10_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH11_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_PLAY1_OUT15 (*) + * + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE0 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE1 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE2 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE3 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE4 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE5 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE6 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE7 + * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG1 + * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG2 + * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG3 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM2_CH1 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM2_CH2 + * @arg @ref LL_GPDMA2_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_GPDMA2_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_GPDMA2_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH0_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH1_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH2_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH3_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH4_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH5_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH6_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH7_TCF + * @arg @ref LL_GPDMA2_TRIGGER_TIM2_TRGO + * @arg @ref LL_GPDMA2_TRIGGER_TIM15_TRGO + * @arg @ref LL_GPDMA2_TRIGGER_TIM12_TRGO + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH1 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH2 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM4_AIT + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH1 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH2 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH1 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH2 + * @arg @ref LL_GPDMA2_TRIGGER_TIM15_TRGO (*) + * @arg @ref LL_GPDMA2_TRIGGER_TIM12_TRGO (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH1 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH2 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM4_AIT (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH1 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH2 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH1 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH2 (*) + * @arg @ref LL_GPDMA2_TRIGGER_COMP1_OUT (*) + * @arg @ref LL_GPDMA2_TRIGGER_EVENTOUT (*) + * @arg @ref LL_GPDMA2_TRIGGER_COMP2_OUT (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_TC_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_CTC_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_TW_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_GPFLAGS0 (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_GPFLAGS1 (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_GPFLAGS2 (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_GPFLAGS3 (*) + * @arg @ref LL_GPDMA2_TRIGGER_JPEG_IFT_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_JPEG_IFNF_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_JPEG_OFT_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_JPEG_OFNE_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_JPEG_EOC_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_GFXTIM_EVT1 (*) + * @arg @ref LL_GPDMA2_TRIGGER_GFXTIM_EVT2 (*) + * @arg @ref LL_GPDMA2_TRIGGER_GFXTIM_EVT3 (*) + * @arg @ref LL_GPDMA2_TRIGGER_GFXTIM_EVT4 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LCD_CTRL_SCANLINE (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH8_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH9_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH10_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH11_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH8_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH9_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH10_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH11_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_PLAY1_OUT15 (*) + * + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL, + (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); +} + +/** + * @brief Get hardware triggers. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE4 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE5 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE6 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE7 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_AIT + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_AIT (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT (*) + * @arg @ref LL_GPDMA1_TRIGGER_EVENTOUT (*) + * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_GPFLAGS0 (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_GPFLAGS1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_GPFLAGS2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_GPFLAGS3 (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC_FLAG (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT3 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT4 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LCD_CTRL_SCANLINE (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH8_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH9_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH10_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH11_TCF (*) + * @arg @ref LL_GPDMA1_TRIGGER_PLAY1_OUT15 (*) + * + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE0 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE1 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE2 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE3 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE4 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE5 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE6 + * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE7 + * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG1 + * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG2 + * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG3 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM2_CH1 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM2_CH2 + * @arg @ref LL_GPDMA2_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_GPDMA2_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_GPDMA2_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH0_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH1_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH2_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH3_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH4_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH5_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH6_TCF + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH7_TCF + * @arg @ref LL_GPDMA2_TRIGGER_TIM2_TRGO + * @arg @ref LL_GPDMA2_TRIGGER_TIM15_TRGO + * @arg @ref LL_GPDMA2_TRIGGER_TIM12_TRGO + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH1 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH2 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM4_AIT + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH1 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH2 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH1 + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH2 + * @arg @ref LL_GPDMA2_TRIGGER_TIM15_TRGO (*) + * @arg @ref LL_GPDMA2_TRIGGER_TIM12_TRGO (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH1 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH2 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM4_AIT (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH1 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH2 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH1 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH2 (*) + * @arg @ref LL_GPDMA2_TRIGGER_COMP1_OUT (*) + * @arg @ref LL_GPDMA2_TRIGGER_EVENTOUT (*) + * @arg @ref LL_GPDMA2_TRIGGER_COMP2_OUT (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_TC_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_CTC_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_TW_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_GPFLAGS0 (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_GPFLAGS1 (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_GPFLAGS2 (*) + * @arg @ref LL_GPDMA2_TRIGGER_DMA2D_GPFLAGS3 (*) + * @arg @ref LL_GPDMA2_TRIGGER_JPEG_IFT_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_JPEG_IFNF_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_JPEG_OFT_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_JPEG_OFNE_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_JPEG_EOC_FLAG (*) + * @arg @ref LL_GPDMA2_TRIGGER_GFXTIM_EVT1 (*) + * @arg @ref LL_GPDMA2_TRIGGER_GFXTIM_EVT2 (*) + * @arg @ref LL_GPDMA2_TRIGGER_GFXTIM_EVT3 (*) + * @arg @ref LL_GPDMA2_TRIGGER_GFXTIM_EVT4 (*) + * @arg @ref LL_GPDMA2_TRIGGER_LCD_CTRL_SCANLINE (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH8_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH9_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH10_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH11_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH8_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH9_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH10_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH11_TCF (*) + * @arg @ref LL_GPDMA2_TRIGGER_PLAY1_OUT15 (*) + * + * @note (*) Availability depends on devices. + */ +__STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos); +} + +/** + * @brief Set DMA transfer mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 PFREQ LL_DMA_SetTransferMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_1 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_NORMAL + * @arg @ref LL_DMA_PFCTRL + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_PFREQ, + Mode & DMA_CTR2_PFREQ); +} + +/** + * @brief Get DMA transfer mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGSEL LL_DMA_GetTransferMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_1 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_NORMAL + * @arg @ref LL_DMA_PFCTRL + */ +__STATIC_INLINE uint32_t LL_DMA_GetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_PFREQ)); +} + +/** + * @brief Configure addresses update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRDDEC LL_DMA_ConfigBlkRptAddrUpdate\n + * CBR1 BRSDEC LL_DMA_ConfigBlkRptAddrUpdate\n + * CBR1 DDEC LL_DMA_ConfigBlkRptAddrUpdate\n + * CBR1 SDEC LL_DMA_ConfigBlkRptAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT + * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT or @ref LL_DMA_BURST_DEST_ADDR_DECREMENT + * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT or @ref LL_DMA_BURST_SRC_ADDR_DECREMENT + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, + DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration); +} + +/** + * @brief Configure DMA Block number of data and repeat Count. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BNDT LL_DMA_ConfigBlkCounters\n + * CBR1 BRC LL_DMA_ConfigBlkCounters + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param BlkDataLength Block transfer length + Value between 0 to 0x0000FFFF + * @param BlkRptCount Block repeat counter + * Value between 0 to 0x000007FF + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength, + uint32_t BlkRptCount) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, + (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos))); +} + +/** + * @brief Set block repeat destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRDDEC LL_DMA_SetBlkRptDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param BlkRptDestAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptDestAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC, + BlkRptDestAddrUpdate); +} + +/** + * @brief Get block repeat destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRDDEC LL_DMA_GetBlkRptDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC)); +} + +/** + * @brief Set block repeat source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRSDEC LL_DMA_SetBlkRptSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param BlkRptSrcAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptSrcAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC, + BlkRptSrcAddrUpdate); +} + +/** + * @brief Get block repeat source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRSDEC LL_DMA_GetBlkRptSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC)); +} + +/** + * @brief Set destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 DDEC LL_DMA_SetDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param DestAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC, + DestAddrUpdate); +} + +/** + * @brief Get destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 DDEC LL_DMA_GetDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC)); +} + +/** + * @brief Set source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 SDEC LL_DMA_SetSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param SrcAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC, + SrcAddrUpdate); +} + +/** + * @brief Get source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 SDEC LL_DMA_GetSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC)); +} + +/** + * @brief Set block repeat count. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRC LL_DMA_SetBlkRptCount + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param BlkRptCount Block repeat counter + * Value between 0 to 0x000007FF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC, + (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC); +} + +/** + * @brief Get block repeat count. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRC LL_DMA_GetBlkRptCount + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Between 0 to 0x000007FF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, + DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos); +} + +/** + * @brief Set block data length in bytes to transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param BlkDataLength Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT, + BlkDataLength); +} + +/** + * @brief Get block data length in bytes to transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Between 0 to 0x0000FFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT)); +} + +/** + * @brief Configure the source and destination addresses. + * @note This API is used for all available DMA channels. + * @note This API must not be called when the DMA Channel is enabled. + * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n + * CDAR DA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @param DestAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t + DestAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); +} + +/** + * @brief Set source address. + * @note This API is used for all available DMA channels. + * @rmtoll CSAR SA LL_DMA_SetSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); +} + +/** + * @brief Get source address. + * @note This API is used for all available DMA channels. + * @rmtoll CSAR SA LL_DMA_GetSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR)); +} + +/** + * @brief Set destination address. + * @note This API is used for all available DMA channels. + * @rmtoll CDAR DA LL_DMA_SetDestAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param DestAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); +} + +/** + * @brief Get destination address. + * @note This API is used for all available DMA channels. + * @rmtoll CDAR DA LL_DMA_GetDestAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR)); +} + +/** + * @brief Configure source and destination addresses offset. + * @note This API is used only for 2D addressing channels. + * @note This API must not be called when the DMA Channel is enabled. + * @rmtoll CTR3 DAO LL_DMA_ConfigAddrUpdateValue\n + * CTR3 SAO LL_DMA_ConfigAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param DestAddrOffset Between 0 to 0x00001FFF + * @param SrcAddrOffset Between 0 to 0x00001FFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset, + uint32_t DestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, + (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); +} + +/** + * @brief Set destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CTR3 DAO LL_DMA_SetDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param DestAddrOffset Between 0 to 0x00001FFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO, + ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); +} + +/** + * @brief Get destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CDAR DAO LL_DMA_GetDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Between 0 to 0x00001FFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, + DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos); +} + +/** + * @brief Set source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CTR3 SAO LL_DMA_SetSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param SrcAddrOffset Between 0 to 0x00001FFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO, + SrcAddrOffset & DMA_CTR3_SAO); +} + +/** + * @brief Get source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CTR3 SAO LL_DMA_GetSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Between 0 to 0x00001FFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO)); +} + +/** + * @brief Configure the block repeated source and destination addresses offset. + * @note This API is used only for 2D addressing channels. + * @note This API must not be called when the DMA Channel is enabled. + * @rmtoll CBR2 BRDAO LL_DMA_ConfigBlkRptAddrUpdateValue\n + * CBR2 BRSAO LL_DMA_ConfigBlkRptAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF + * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, + ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO)); +} + +/** + * @brief Set block repeated destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRDAO LL_DMA_SetBlkRptDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptDestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO, + ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO)); +} + +/** + * @brief Get block repeated destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRDAO LL_DMA_GetBlkRptDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Between 0 to 0x0000FFFF. + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, + DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos); +} + +/** + * @brief Set block repeated source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRSAO LL_DMA_SetBlkRptSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptSrcAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO, + BlkRptSrcAddrOffset); +} + +/** + * @brief Get block repeated source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRSAO LL_DMA_GetBlkRptSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Between 0 to 0x0000FFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO)); +} + +/** + * @brief Configure registers update and node address offset during the link transfer. + * @note This API is used for all available DMA channels. + * For linear addressing channels, UT3 and UB2 fields are discarded. + * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UT3 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UB2 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param RegistersUpdate This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_UPDATE_CTR1 + * @arg @ref LL_DMA_UPDATE_CTR2 + * @arg @ref LL_DMA_UPDATE_CBR1 + * @arg @ref LL_DMA_UPDATE_CSAR + * @arg @ref LL_DMA_UPDATE_CDAR + * @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_UPDATE_CLLR + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate, + uint32_t LinkedListAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, + (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ + DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA))); +} + +/** + * @brief Enable CTR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); +} + +/** + * @brief Disable CTR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); +} + +/** + * @brief Check if CTR1 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1) + == (DMA_CLLR_UT1)) ? 1UL : 0UL); +} + +/** + * @brief Enable CTR2 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); +} + +/** + * @brief Disable CTR2 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); +} + +/** + * @brief Check if CTR2 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2) + == (DMA_CLLR_UT2)) ? 1UL : 0UL); +} + +/** + * @brief Enable CBR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); +} + +/** + * @brief Disable CBR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); +} + +/** + * @brief Check if CBR1 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1) + == (DMA_CLLR_UB1)) ? 1UL : 0UL); +} + +/** + * @brief Enable CSAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); +} + +/** + * @brief Disable CSAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); +} + +/** + * @brief Check if CSAR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) + == (DMA_CLLR_USA)) ? 1UL : 0UL); +} + +/** + * @brief Enable CDAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); +} + +/** + * @brief Disable CDAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); +} + +/** + * @brief Check if CDAR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA) + == (DMA_CLLR_UDA)) ? 1UL : 0UL); +} + +/** + * @brief Enable CTR3 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UT3 LL_DMA_EnableCTR3Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); +} + +/** + * @brief Disable CTR3 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UT3 LL_DMA_DisableCTR3Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); +} + +/** + * @brief Check if CTR3 update during the link transfer is enabled. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UT3 LL_DMA_IsEnabledCTR3Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3) + == (DMA_CLLR_UT3)) ? 1UL : 0UL); +} + +/** + * @brief Enable CBR2 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UB2 LL_DMA_EnableCBR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2); +} + +/** + * @brief Disable CBR2 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UB2 LL_DMA_DisableCBR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2); +} + +/** + * @brief Check if CBR2 update during the link transfer is enabled. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UB2 LL_DMA_IsEnabledCBR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2) + == (DMA_CLLR_UB2)) ? 1UL : 0UL); +} + +/** + * @brief Enable CLLR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); +} + +/** + * @brief Disable CLLR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); +} + +/** + * @brief Check if CLLR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) + == (DMA_CLLR_ULL)) ? 1UL : 0UL); +} + +/** + * @brief Set linked list address offset. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t LinkedListAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA, + (LinkedListAddrOffset & DMA_CLLR_LA)); +} + +/** + * @brief Get linked list address offset. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Between 0 to 0x0000FFFC. + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, + DMA_CLLR_LA) >> DMA_CLLR_LA_Pos); +} + +/** + * @brief Get FIFO level. + * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval Between 0 to 0x000000FF. + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, + DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the DMA channel secure attribute. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SECx LL_DMA_EnableChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Disable the DMA channel secure attribute. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SECx LL_DMA_DisableChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined (DMA_SECCFGR_SEC0) +/** + * @brief Check if DMA channel secure is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SECx LL_DMA_IsEnabledChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) + == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} +#endif /* DMA_SECCFGR_SEC0 */ + +/** + * @brief Enable the DMA channel privilege attribute. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Disable the DMA channel privilege attribute. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Check if DMA Channel privilege is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) + == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the DMA channel lock attributes. + * @note This API is used for all available DMA channels. + * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined (DMA_RCFGLOCKR_LOCK0) +/** + * @brief Check if DMA channel attributes are locked. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) + == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} + +#endif /* DMA_RCFGLOCKR_LOCK0 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management Flag Management + * @{ + */ + +/** + * @brief Clear trigger overrun flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF); +} + +/** + * @brief Clear suspension flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF); +} + +/** + * @brief Clear user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF); +} + +/** + * @brief Clear link transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF); +} + +/** + * @brief Clear data transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF); +} + +/** + * @brief Clear half transfer flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF); +} + +/** + * @brief Clear transfer complete flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF); +} + +/** + * @brief Get trigger overrun flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF) + == (DMA_CSR_TOF)) ? 1UL : 0UL); +} + +/** + * @brief Get suspension flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF) + == (DMA_CSR_SUSPF)) ? 1UL : 0UL); +} + +/** + * @brief Get user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF) + == (DMA_CSR_USEF)) ? 1UL : 0UL); +} + +/** + * @brief Get user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF) + == (DMA_CSR_ULEF)) ? 1UL : 0UL); +} + +/** + * @brief Get data transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF) + == (DMA_CSR_DTEF)) ? 1UL : 0UL); +} + +/** + * @brief Get half transfer flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF) + == (DMA_CSR_HTF)) ? 1UL : 0UL); +} + +/** + * @brief Get transfer complete flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF) + == (DMA_CSR_TCF)) ? 1UL : 0UL); +} + +/** + * @brief Get idle flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF) + == (DMA_CSR_IDLEF)) ? 1UL : 0UL); +} + +/** + * @brief Check if nsecure masked interrupt is active. + * @note This API is used for all available DMA channels. + * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU))) + == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Check if secure masked interrupt is active. + * @note This API is used for all available DMA channels. + * @rmtoll SMISR MISx LL_DMA_IsActiveFlag_SMIS + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) + == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable trigger overrun interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_EnableIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); +} + +/** + * @brief Enable suspension interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); +} + +/** + * @brief Enable user setting error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_EnableIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); +} + +/** + * @brief Enable update link transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); +} + +/** + * @brief Enable data transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); +} + +/** + * @brief Enable half transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable trigger overrun interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_DisableIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); +} + +/** + * @brief Disable suspension interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); +} + +/** + * @brief Disable user setting error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_DisableIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); +} + +/** + * @brief Disable update link transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); +} + +/** + * @brief Disable data transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); +} + +/** + * @brief Disable half transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Check if trigger overrun interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE) + == DMA_CCR_TOIE) ? 1UL : 0UL); +} + +/** + * @brief Check if suspension interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE) + == DMA_CCR_SUSPIE) ? 1UL : 0UL); +} + +/** + * @brief Check if user setting error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE) + == DMA_CCR_USEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if update link transfer error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE) + == DMA_CCR_ULEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if data transfer error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE) + == DMA_CCR_DTEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if half transfer complete interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE) + == DMA_CCR_HTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if transfer complete interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @note (*) Availability depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE) + == DMA_CCR_TCIE) ? 1UL : 0UL); +} +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); + +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); +void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); +void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct); + +uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, + LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); +uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); + +uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode); +void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx, + LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx); +void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* GPDMA1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32H5xx_LL_DMA_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h new file mode 100644 index 00000000..b78b8c86 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h @@ -0,0 +1,2892 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_LL_EXTI_H +#define STM32H5xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +#define LL_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */ + +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + +#if defined(EXTI_IMR3_IM) + uint32_t Line_64_95; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ +#endif /* EXTI_IMR3_IM */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ +#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ +#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR1_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#endif /* EXTI_IMR1_IM18 */ +#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR1_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#endif /* EXTI_IMR1_IM20 */ +#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ +#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#if defined(EXTI_IMR1_IM23) +#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#endif /* EXTI_IMR1_IM23 */ +#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ +#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ +#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ +#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ +#if defined(EXTI_IMR1_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ +#endif /* EXTI_IMR1_IM30 */ +#if defined(EXTI_IMR1_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#endif /* EXTI_IMR1_IM31 */ +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< All Extended line not reserved */ + +#if defined(EXTI_IMR2_IM32) +#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ +#endif /* EXTI_IMR2_IM32 */ +#if defined(EXTI_IMR2_IM33) +#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ +#endif /* EXTI_IMR2_IM33 */ +#if defined(EXTI_IMR2_IM34) +#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#endif /* EXTI_IMR2_IM34 */ +#if defined(EXTI_IMR2_IM35) +#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ +#endif /* EXTI_IMR2_IM35 */ +#if defined(EXTI_IMR2_IM36) +#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#endif /* EXTI_IMR2_IM36 */ +#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ +#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ +#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ +#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ +#define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */ +#define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */ +#if defined(EXTI_IMR2_IM43) +#define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */ +#endif /* EXTI_IMR2_IM43 */ +#if defined(EXTI_IMR2_IM44) +#define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */ +#endif /* EXTI_IMR2_IM44 */ +#if defined(EXTI_IMR2_IM45) +#define LL_EXTI_LINE_45 EXTI_IMR2_IM45 /*!< Extended line 45 */ +#endif /* EXTI_IMR2_IM45 */ +#if defined(ETH) +#define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */ +#endif /* ETH */ +#define LL_EXTI_LINE_47 EXTI_IMR2_IM47 /*!< Extended line 47 */ +#if defined(EXTI_IMR2_IM48) +#define LL_EXTI_LINE_48 EXTI_IMR2_IM48 /*!< Extended line 48 */ +#endif /* EXTI_IMR2_IM48 */ +#define LL_EXTI_LINE_49 EXTI_IMR2_IM49 /*!< Extended line 49 */ +#define LL_EXTI_LINE_50 EXTI_IMR2_IM50 /*!< Extended line 50 */ +#if defined(EXTI_IMR2_IM51) +#define LL_EXTI_LINE_51 EXTI_IMR2_IM51 /*!< Extended line 51 */ +#endif /* EXTI_IMR2_IM51 */ +#if defined(EXTI_IMR2_IM52) +#define LL_EXTI_LINE_52 EXTI_IMR2_IM52 /*!< Extended line 52 */ +#endif /* EXTI_IMR2_IM52 */ +#define LL_EXTI_LINE_53 EXTI_IMR2_IM53 /*!< Extended line 53 */ +#if defined(EXTI_IMR2_IM54) +#define LL_EXTI_LINE_54 EXTI_IMR2_IM54 /*!< Extended line 54 */ +#endif /* EXTI_IMR2_IM54 */ +#if defined(EXTI_IMR2_IM55) +#define LL_EXTI_LINE_55 EXTI_IMR2_IM55 /*!< Extended line 55 */ +#endif /* EXTI_IMR2_IM55 */ +#if defined(EXTI_IMR2_IM56) +#define LL_EXTI_LINE_56 EXTI_IMR2_IM56 /*!< Extended line 56 */ +#endif /* EXTI_IMR2_IM56 */ +#if defined(EXTI_IMR2_IM57) +#define LL_EXTI_LINE_57 EXTI_IMR2_IM57 /*!< Extended line 57 */ +#endif /* EXTI_IMR2_IM57 */ +#if defined(EXTI_IMR2_IM58) +#define LL_EXTI_LINE_58 EXTI_IMR2_IM58 /*!< Extended line 58 */ +#endif /* EXTI_IMR2_IM58 */ +#if defined(EXTI_IMR2_IM59) +#define LL_EXTI_LINE_59 EXTI_IMR2_IM59 /*!< Extended line 59 */ +#endif /* EXTI_IMR2_IM59 */ +#if defined(EXTI_IMR2_IM60) +#define LL_EXTI_LINE_60 EXTI_IMR2_IM60 /*!< Extended line 60 */ +#endif /* EXTI_IMR2_IM60 */ +#if defined(EXTI_IMR2_IM61) +#define LL_EXTI_LINE_61 EXTI_IMR2_IM61 /*!< Extended line 61 */ +#endif /* EXTI_IMR2_IM61 */ +#if defined(EXTI_IMR2_IM62) +#define LL_EXTI_LINE_62 EXTI_IMR2_IM62 /*!< Extended line 62 */ +#endif /* EXTI_IMR2_IM62 */ +#if defined(EXTI_IMR2_IM63) +#define LL_EXTI_LINE_63 EXTI_IMR2_IM63 /*!< Extended line 63 */ +#endif /* EXTI_IMR2_IM63 */ +#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< ALL Extended lines */ + +#if defined(EXTI_IMR3_IM64) +#define LL_EXTI_LINE_64 EXTI_IMR3_IM64 /*!< Extended line 64 */ +#endif /* EXTI_IMR3_IM64 */ +#if defined(EXTI_IMR3_IM65) +#define LL_EXTI_LINE_65 EXTI_IMR3_IM65 /*!< Extended line 65 */ +#endif /* EXTI_IMR3_IM65 */ +#if defined(EXTI_IMR3_IM66) +#define LL_EXTI_LINE_66 EXTI_IMR3_IM66 /*!< Extended line 66 */ +#endif /* EXTI_IMR3_IM66 */ +#define LL_EXTI_LINE_ALL_64_95 EXTI_IMR3_IM /*!< ALL Extended lines */ + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT EXTI EXTI PORT + * @{ + */ +#define LL_EXTI_EXTI_PORTA 0U /*!< EXTI PORT A */ +#define LL_EXTI_EXTI_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */ +#define LL_EXTI_EXTI_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */ +#define LL_EXTI_EXTI_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */ +#if defined(GPIOE) +#define LL_EXTI_EXTI_PORTE EXTI_EXTICR1_EXTI0_2 /*!< EXTI PORT E */ +#endif /* GPIO E */ +#if defined(GPIOF) +#define LL_EXTI_EXTI_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */ +#endif /* GPIO F */ +#if defined(GPIOG) +#define LL_EXTI_EXTI_PORTG (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1) /*!< EXTI PORT G */ +#endif /* GPIO G */ +#define LL_EXTI_EXTI_PORTH (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT H */ +#if defined(GPIOI) +#define LL_EXTI_EXTI_PORTI EXTI_EXTICR1_EXTI0_3 /*!< EXTI PORT I */ +#endif /* GPIO I */ +#if defined(GPIOJ) +#define LL_EXTI_EXTI_PORTJ (EXTI_EXTICR1_EXTI0_3|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT J */ +#endif /* GPIO J */ +#if defined(GPIOK) +#define LL_EXTI_EXTI_PORTK (EXTI_EXTICR1_EXTI0_3|EXTI_EXTICR1_EXTI0_1) /*!< EXTI PORT K */ +#endif /* GPIO K */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE EXTI EXTI LINE + * @{ + */ +#define LL_EXTI_EXTI_LINE0 ((0UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_EXTI_EXTI_LINE1 ((8UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_EXTI_EXTI_LINE2 ((16UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_16 | EXTICR[0] */ +#define LL_EXTI_EXTI_LINE3 ((24UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_24 | EXTICR[0] */ +#define LL_EXTI_EXTI_LINE4 ((0UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_EXTI_EXTI_LINE5 ((8UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_EXTI_EXTI_LINE6 ((16UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_16 | EXTICR[1] */ +#define LL_EXTI_EXTI_LINE7 ((24UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_24 | EXTICR[1] */ +#define LL_EXTI_EXTI_LINE8 ((0UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_EXTI_EXTI_LINE9 ((8UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_EXTI_EXTI_LINE10 ((16UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_16 | EXTICR[2] */ +#define LL_EXTI_EXTI_LINE11 ((24UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_24 | EXTICR[2] */ +#define LL_EXTI_EXTI_LINE12 ((0UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_EXTI_EXTI_LINE13 ((8UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_EXTI_EXTI_LINE14 ((16UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_16 | EXTICR[3] */ +#define LL_EXTI_EXTI_LINE15 ((24UL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_24 | EXTICR[3] */ +/** + * @} + */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 (*) + * @arg @ref LL_EXTI_LINE_61 (*) + * @arg @ref LL_EXTI_LINE_62 (*) + * @arg @ref LL_EXTI_LINE_63 (*) + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR2, ExtiLine); +} + +#if defined(EXTI_IMR3_IM) +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 64 to 95 + * @rmtoll IMR3 IMx LL_EXTI_EnableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR3, ExtiLine); +} +#endif /* EXTI_IMR3_IM */ + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR1, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 (*) + * @arg @ref LL_EXTI_LINE_61 (*) + * @arg @ref LL_EXTI_LINE_62 (*) + * @arg @ref LL_EXTI_LINE_63 (*) + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR2, ExtiLine); +} + +#if defined(EXTI_IMR3_IM) +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 64 to 95 + * @rmtoll IMR3 IMx LL_EXTI_DisableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR3, ExtiLine); +} +#endif /* EXTI_IMR3_IM */ + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 (*) + * @arg @ref LL_EXTI_LINE_61 (*) + * @arg @ref LL_EXTI_LINE_62 (*) + * @arg @ref LL_EXTI_LINE_63 (*) + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +#if defined(EXTI_IMR3_IM) +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95 + * @rmtoll IMR3 IMx LL_EXTI_IsEnabledIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} +#endif /* EXTI_IMR3_IM */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_45 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 (*) + * @arg @ref LL_EXTI_LINE_61 (*) + * @arg @ref LL_EXTI_LINE_62 (*) + * @arg @ref LL_EXTI_LINE_63 (*) + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR2, ExtiLine); +} + +#if defined(EXTI_EMR3_EM) +/** + * @brief Enable ExtiLine Event request for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_EnableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR3, ExtiLine); +} +#endif /* EXTI_EMR3_EM */ + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 (*) + * @arg @ref LL_EXTI_LINE_61 (*) + * @arg @ref LL_EXTI_LINE_62 (*) + * @arg @ref LL_EXTI_LINE_63 (*) + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR2, ExtiLine); +} + +#if defined(EXTI_EMR3_EM) +/** + * @brief Disable ExtiLine Event request for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_DisableEvent_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR3, ExtiLine); +} + +#endif /* EXTI_EMR3_EM */ + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 (*) + * @arg @ref LL_EXTI_LINE_61 (*) + * @arg @ref LL_EXTI_LINE_62 (*) + * @arg @ref LL_EXTI_LINE_63 (*) + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +#if defined(EXTI_EMR3_EM) +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_IsEnabledEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} +#endif /* EXTI_EMR3_EM */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR2, ExtiLine); +} + +#if defined(EXTI_RTSR3_RT64) +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR3 RTx LL_EXTI_EnableRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_66 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR3, ExtiLine); +} +#endif /* EXTI_RTSR3_RT64 */ + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_58 (*) + * @arg @ref LL_EXTI_LINE_59 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR2, ExtiLine); +} + +#if defined(EXTI_RTSR3_RT64) +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR3 RTx LL_EXTI_DisableRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_66 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR3, ExtiLine); +} +#endif /* EXTI_RTSR3_RT64 */ + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_58 (*) + * @arg @ref LL_EXTI_LINE_59 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +#if defined(EXTI_RTSR3_RT64) +/** + * @brief Check if rising edge trigger is enabled for Lines in range 64 to 95 + * @rmtoll RTSR3 RTx LL_EXTI_IsEnabledRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_66 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} +#endif /* EXTI_RTSR3_RT64 */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_58 (*) + * @arg @ref LL_EXTI_LINE_59 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR2, ExtiLine); +} + +#if defined(EXTI_FTSR3_FT64) +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR3 FTx LL_EXTI_EnableFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_66 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR3, ExtiLine); +} +#endif /* EXTI_FTSR3_FT64 */ + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_58 (*) + * @arg @ref LL_EXTI_LINE_59 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR2, ExtiLine); +} + +#if defined(EXTI_FTSR3_FT64) +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR3 FTx LL_EXTI_DisableFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_66 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR3, ExtiLine); +} +#endif /* EXTI_FTSR3_FT64 */ + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_58 (*) + * @arg @ref LL_EXTI_LINE_59 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +#if defined(EXTI_FTSR3_FT64) +/** + * @brief Check if falling edge trigger is enabled for Lines in range 64 to 95 + * @rmtoll FTSR3 FTx LL_EXTI_IsEnabledFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_66 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} +#endif /* EXTI_FTSR3_FT64 */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_C1IMR1, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR1 + * register (by writing a 1 into the bit) + * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER1, ExtiLine); +} + +/** + * @brief Generate a software Interrupt Event for Lines in range 32 to 63 + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 + * register (by writing a 1 into the bit) + * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_58 (*) + * @arg @ref LL_EXTI_LINE_59 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER2, ExtiLine); +} + +#if defined(EXTI_SWIER3_SWIER64) +/** + * @brief Generate a software Interrupt Event for Lines in range 64 to 95 + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 + * register (by writing a 1 into the bit) + * @rmtoll SWIER3 SWIx LL_EXTI_GenerateSWI_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_66 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER3, ExtiLine); +} +#endif /* EXTI_SWIER3_SWIER64 */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_IsActiveFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if the ExtLine Falling Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR2 FPIFx LL_EXTI_IsActiveFallingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_58 (*) + * @arg @ref LL_EXTI_LINE_59 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(EXTI_FPR3_FPIF) +/** + * @brief Check if the ExtLine Falling Flag is set or not for Lines in range 64 to 95 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR3 FPIFx LL_EXTI_IsActiveFallingFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_66 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FPR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* EXTI_FPR3_FPIF */ + +/** + * @brief Read ExtLine Combination Falling Flag for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_ReadFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->FPR1, ExtiLine)); +} + +/** + * @brief Read ExtLine Combination Falling Flag for Lines in range 32 to 63 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR2 FPIFx LL_EXTI_ReadFallingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_58 (*) + * @arg @ref LL_EXTI_LINE_59 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->FPR2, ExtiLine)); +} + +#if defined(EXTI_FPR3_FPIF) +/** + * @brief Read ExtLine Combination Falling Flag for Lines in range 64 to 95 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR3 FPIFx LL_EXTI_ReadFallingFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_66 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_64_95(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->FPR3, ExtiLine)); +} +#endif /* EXTI_FPR3_FPIF */ + +/** + * @brief Clear ExtLine Falling Flags for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_ClearFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->FPR1, ExtiLine); +} + +/** + * @brief Clear ExtLine Falling Flags for Lines in range 32 to 63 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR2 FPIFx LL_EXTI_ClearFallingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_58 (*) + * @arg @ref LL_EXTI_LINE_59 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->FPR2, ExtiLine); +} + +#if defined(EXTI_FPR3_FPIF) +/** + * @brief Clear ExtLine Falling Flags for Lines in range 64 to 95 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR3 FPIFx LL_EXTI_ClearFallingFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_66 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_64_95(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->FPR3, ExtiLine); +} +#endif /* EXTI_FPR3_FPIF */ + +/** + * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_IsActiveRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR2 RPIFx LL_EXTI_IsActiveRisingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_58 (*) + * @arg @ref LL_EXTI_LINE_59 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(EXTI_RPR3_RPIF) +/** + * @brief Check if the ExtLine Rising Flag is set or not for Lines 64 to 95 + * @note This bit is set when the rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR3 RPIFx LL_EXTI_IsActiveRisingFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_66 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RPR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* EXTI_RPR3_RPIF */ + +/** + * @brief Read ExtLine Combination Rising Flag for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_ReadRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->RPR1, ExtiLine)); +} + +/** + * @brief Read ExtLine Combination Rising Flag for Lines in range 32 to 63 + * @note This bit is set when the rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR2 RPIFx LL_EXTI_ReadRisingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_58 (*) + * @arg @ref LL_EXTI_LINE_59 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->RPR2, ExtiLine)); +} + +#if defined(EXTI_RPR3_RPIF) +/** + * @brief Read ExtLine Combination Rising Flag for Lines in range 64 to 95 + * @note This bit is set when the rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR3 RPIFx LL_EXTI_ReadRisingFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_66 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_64_95(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->RPR3, ExtiLine)); +} +#endif /* EXTI_RPR3_RPIF */ + +/** + * @brief Clear ExtLine Rising Flags for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_ClearRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->RPR1, ExtiLine); +} + +/** + * @brief Clear ExtLine Rising Flags for Lines in range 32 to 63 + * @note This bit is set when the rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR2 RPIFx LL_EXTI_ClearRisingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_58 (*) + * @arg @ref LL_EXTI_LINE_59 (*) + * + * (*) : Not available for all stm32h5xxxx family lines. + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->RPR2, ExtiLine); +} + +#if defined(EXTI_RPR3_RPIF) +/** + * @brief Clear ExtLine Rising Flags for Lines in range 64 to 95 + * @note This bit is set when the rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR3 RPIFx LL_EXTI_ClearRisingFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_66 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_64_95(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->RPR3, ExtiLine); +} +#endif /* EXTI_RPR3_RPIF */ + +/** + * @} + */ +/** @defgroup EXTI_LL_EF_Config EF configuration functions + * @{ + */ + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_EXTI_EXTI_PORTA + * @arg @ref LL_EXTI_EXTI_PORTB + * @arg @ref LL_EXTI_EXTI_PORTC + * @arg @ref LL_EXTI_EXTI_PORTD + * @arg @ref LL_EXTI_EXTI_PORTE (*) + * @arg @ref LL_EXTI_EXTI_PORTF (*) + * @arg @ref LL_EXTI_EXTI_PORTG (*) + * @arg @ref LL_EXTI_EXTI_PORTH + * @arg @ref LL_EXTI_EXTI_PORTI (*) + * @arg @ref LL_EXTI_EXTI_PORTJ (*) + * @arg @ref LL_EXTI_EXTI_PORTK (*) + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_EXTI_LINE0 + * @arg @ref LL_EXTI_EXTI_LINE1 + * @arg @ref LL_EXTI_EXTI_LINE2 + * @arg @ref LL_EXTI_EXTI_LINE3 + * @arg @ref LL_EXTI_EXTI_LINE4 + * @arg @ref LL_EXTI_EXTI_LINE5 + * @arg @ref LL_EXTI_EXTI_LINE6 + * @arg @ref LL_EXTI_EXTI_LINE7 + * @arg @ref LL_EXTI_EXTI_LINE8 + * @arg @ref LL_EXTI_EXTI_LINE9 + * @arg @ref LL_EXTI_EXTI_LINE10 + * @arg @ref LL_EXTI_EXTI_LINE11 + * @arg @ref LL_EXTI_EXTI_LINE12 + * @arg @ref LL_EXTI_EXTI_LINE13 + * @arg @ref LL_EXTI_EXTI_LINE14 + * @arg @ref LL_EXTI_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(EXTI->EXTICR[Line & 0x03U], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), \ + Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR1 EXTI1 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR1 EXTI2 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR1 EXTI3 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI4 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI5 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI6 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI7 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI8 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI9 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI10 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI11 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI12 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI13 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI14 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI15 LL_EXTI_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_EXTI_LINE0 + * @arg @ref LL_EXTI_EXTI_LINE1 + * @arg @ref LL_EXTI_EXTI_LINE2 + * @arg @ref LL_EXTI_EXTI_LINE3 + * @arg @ref LL_EXTI_EXTI_LINE4 + * @arg @ref LL_EXTI_EXTI_LINE5 + * @arg @ref LL_EXTI_EXTI_LINE6 + * @arg @ref LL_EXTI_EXTI_LINE7 + * @arg @ref LL_EXTI_EXTI_LINE8 + * @arg @ref LL_EXTI_EXTI_LINE9 + * @arg @ref LL_EXTI_EXTI_LINE10 + * @arg @ref LL_EXTI_EXTI_LINE11 + * @arg @ref LL_EXTI_EXTI_LINE12 + * @arg @ref LL_EXTI_EXTI_LINE13 + * @arg @ref LL_EXTI_EXTI_LINE14 + * @arg @ref LL_EXTI_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_EXTI_PORTA + * @arg @ref LL_EXTI_EXTI_PORTB + * @arg @ref LL_EXTI_EXTI_PORTC + * @arg @ref LL_EXTI_EXTI_PORTD + * @arg @ref LL_EXTI_EXTI_PORTE (*) + * @arg @ref LL_EXTI_EXTI_PORTF (*) + * @arg @ref LL_EXTI_EXTI_PORTG (*) + * @arg @ref LL_EXTI_EXTI_PORTH + * @arg @ref LL_EXTI_EXTI_PORTI (*) + * @arg @ref LL_EXTI_EXTI_PORTJ (*) + * @arg @ref LL_EXTI_EXTI_PORTK (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(EXTI->EXTICR[Line & 0x03U], + (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> + (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +} +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Secure_Management Secure_Management + * @{ + */ + +#if defined(__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) + +/** + * @brief Enable ExtiLine Secure attribute for Lines in range 0 to 31 + * @rmtoll SECCFGR1 SECx LL_EXTI_EnableSecure_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableSecure_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SECCFGR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Secure attribute for Lines in range 32 to 63 + * @rmtoll SECCFGR2 SECx LL_EXTI_EnableSecure_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableSecure_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SECCFGR2, ExtiLine); +} + +#if defined(EXTI_SECENR3_SEC64) +/** + * @brief Enable ExtiLine Secure attribute for Lines in range 64 to 95 + * @rmtoll SECCFGR3 SECx LL_EXTI_EnableSecure_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableSecure_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SECCFGR3, ExtiLine); +} +#endif /* EXTI_SECENR3_SEC64 */ + +/** + * @brief Disable ExtiLine Secure attribute for Lines in range 0 to 31 + * @rmtoll SECCFGR1 SECx LL_EXTI_DisableSecure_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableSecure_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->SECCFGR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Secure attribute for Lines in range 32 to 63 + * @rmtoll SECCFGR2 SECx LL_EXTI_DisableSecure_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableSecure_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->SECCFGR2, ExtiLine); +} + +#if defined(EXTI_SECENR3_SEC64) +/** + * @brief Disable ExtiLine Secure attribute for Lines in range 64 to 95 + * @rmtoll SECCFGR3 SECx LL_EXTI_DisableSecure_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableSecure_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->SECCFGR3, ExtiLine); +} +#endif /* EXTI_SECENR3_SEC64 */ + +#endif /* __ARM_FEATURE_CMSE */ + +#if defined(EXTI_SECENR1_SEC0) +/** + * @brief Indicate if ExtiLine Secure attribute is enabled for Lines in range 0 to 31 + * @rmtoll SECCFGR1 SECx LL_EXTI_IsEnabledSecure_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->SECCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Secure attribute is enabled for Lines in range 32 to 63 + * @rmtoll SECCFGR2 SECx LL_EXTI_IsEnabledSecure_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->SECCFGR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* EXTI_SECENR1_SEC0 */ + +#if defined(EXTI_SECENR3_SEC64) +/** + * @brief Indicate if ExtiLine Secure attribute is enabled for Lines in range 64 to 95 + * @rmtoll SECCFGR3 SECx LL_EXTI_IsEnabledSecure_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->SECCFGR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* EXTI_SECENR3_SEC64 */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Privilege_Management Privilege_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Privilege attribute for Lines in range 0 to 31 + * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_EnablePrivilege_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->PRIVCFGR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Privilege attribute for Lines in range 32 to 63 + * @rmtoll PRIVCFGR2 PRIVx LL_EXTI_EnablePrivilege_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnablePrivilege_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->PRIVCFGR2, ExtiLine); +} + +#if defined(EXTI_PRIVENR3_PRIV64) +/** + * @brief Enable ExtiLine Privilege attribute for Lines in range 64 to 95 + * @rmtoll PRIVCFGR3 PRIVx LL_EXTI_EnablePrivilege_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnablePrivilege_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->PRIVCFGR3, ExtiLine); +} +#endif /* EXTI_PRIVENR3_PRIV64 */ + +/** + * @brief Disable ExtiLine Privilege attribute for Lines in range 0 to 31 + * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_DisablePrivilege_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->PRIVCFGR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Privilege attribute for Lines in range 32 to 63 + * @rmtoll PRIVCFGR2 PRIVx LL_EXTI_DisablePrivilege_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisablePrivilege_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->PRIVCFGR2, ExtiLine); +} + +#if defined(EXTI_PRIVENR3_PRIV64) +/** + * @brief Disable ExtiLine Privilege attribute for Lines in range 64 to 95 + * @rmtoll PRIVCFGR3 PRIVx LL_EXTI_DisablePrivilege_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisablePrivilege_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->PRIVCFGR3, ExtiLine); +} +#endif /* EXTI_PRIVENR3_PRIV64 */ + +/** + * @brief Indicate if ExtiLine Privilege attribute is enabled for Lines in range 0 to 31 + * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_IsEnabledPrivilege_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PRIVCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Privilege attribute is enabled for Lines in range 32 to 63 + * @rmtoll PRIVCFGR2 PRIVx LL_EXTI_IsEnabledPrivilege_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PRIVCFGR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(EXTI_PRIVENR3_PRIV64) +/** + * @brief Indicate if ExtiLine Privilege attribute is enabled for Lines in range 64 to 95 + * @rmtoll PRIVCFGR3 PRIVx LL_EXTI_IsEnabledPrivilege_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PRIVCFGR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* EXTI_PRIVENR3_PRIV64 */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the EXTI lock attributes. + * @rmtoll LOCKR LOCK LL_EXTI_EnableLockAttribute + * @retval None. + */ +__STATIC_INLINE void LL_EXTI_EnableLockAttribute(void) +{ + SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} + +/** + * @brief Check if EXTI attributes are locked. + * @rmtoll LOCKR LOCK LL_EXTI_IsEnabledLockAttribute + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledLockAttribute(void) +{ + return ((READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK) == EXTI_LOCKR_LOCK) ? 1UL : 0UL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +ErrorStatus LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_LL_EXTI_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h new file mode 100644 index 00000000..a5c0c602 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h @@ -0,0 +1,1182 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H5xx_LL_GPIO_H +#define __STM32H5xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \ + defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function + @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \ + GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \ + GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \ + GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \ + GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \ + GPIO_BSRR_BS15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)), + (Mode << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))) >> \ + (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)), + (Speed << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << \ + (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))) >> \ + (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)), + (Pull << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))) >> \ + (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)), + (Alternate << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))) >> \ + (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)), + (Alternate << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))) >> \ + (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)); +} + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) +{ + return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @brief Enable speed optimization for several pin of dedicated port. + * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding + * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must + * be kept at reset value. + * @note It must be used only if the I/O supply voltage is below 2.7 V. + * @rmtoll HSLVR HSLVy LL_GPIO_EnableHighSPeedLowVoltage + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + SET_BIT(GPIOx->HSLVR, PinMask); +} + + +/** + * @brief Disable speed optimization for several pin of dedicated port. + * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding + * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must + * be kept at reset value. + * @note It must be used only if the I/O supply voltage is below 2.7 V. + * @rmtoll HSLVR HSLVy LL_GPIO_DisableHighSPeedLowVoltage + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + CLEAR_BIT(GPIOx->HSLVR, PinMask); +} + +/** + * @brief Return if speed optimization for several pin of dedicated port is enabled or not. + * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding + * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must + * be kept at reset value. + * @note It must be used only if the I/O supply voltage is below 2.7 V. + * @rmtoll HSLVR HSLVy LL_GPIO_IsEnabledHighSPeedLowVoltage + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsEnabledHighSPeedLowVoltage(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->HSLVR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + * @brief Enable secure write only access for several pin of dedicated port. + * @rmtoll SECCFGR SECy LL_GPIO_EnablePinSecure + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_EnablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + SET_BIT(GPIOx->SECCFGR, PinMask); +} + + +/** + * @brief Disable secure write only access for several pin of dedicated port. + * @rmtoll SECCFGR SECy LL_GPIO_DisablePinSecure + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_DisablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + CLEAR_BIT(GPIOx->SECCFGR, PinMask); +} + +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Return if secure write only access for several pin of dedicated port is enabled or not. + * @rmtoll SECCFGR SECy LL_GPIO_IsEnabledPinSecure + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->SECCFGR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \ + defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || \ + defined (GPIOK) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_LL_GPIO_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h new file mode 100644 index 00000000..ce663d68 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h @@ -0,0 +1,788 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_icache.h + * @author MCD Application Team + * @brief Header file of ICACHE LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion ------------------------------------*/ +#ifndef STM32H5xx_LL_ICACHE_H +#define STM32H5xx_LL_ICACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -----------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +#if defined(ICACHE) + +/** @defgroup ICACHE_LL ICACHE + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(ICACHE_CRRx_REN) +/** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure + * @{ + */ + +/** + * @brief LL ICACHE region configuration structure definition + */ +typedef struct +{ + uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */ + + uint32_t RemapAddress; /*!< Configures the remap address to be remapped */ + + uint32_t Size; /*!< Configures the region size. + This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */ + + uint32_t TrafficRoute; /*!< Selects the traffic route. + This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */ + + uint32_t OutputBurstType; /*!< Selects the output burst type. + This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */ +} LL_ICACHE_RegionTypeDef; + +/** + * @} + */ +#endif /* ICACHE_CRRx_REN */ + +/* Exported constants -------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants + * @{ + */ + +/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection + * @{ + */ +#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ +#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type + * @{ + */ +#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */ +#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */ +#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_ICACHE_ReadReg function + * @{ + */ +#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */ +#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */ +#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_ICACHE_WriteReg function + * @{ + */ +#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */ +#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions + * @{ + */ +#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ +#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */ +/** + * @} + */ + +#if defined(ICACHE_CRRx_REN) +/** @defgroup ICACHE_LL_EC_Region Remapped Region number + * @{ + */ +#define LL_ICACHE_REGION_0 0U /*!< Region 0 */ +#define LL_ICACHE_REGION_1 1U /*!< Region 1 */ +#define LL_ICACHE_REGION_2 2U /*!< Region 2 */ +#define LL_ICACHE_REGION_3 3U /*!< Region 3 */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size + * @{ + */ +#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ +#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ +#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ +#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ +#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ +#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ +#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route + * @{ + */ +#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */ +#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type + * @{ + */ +#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ +#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ +/** + * @} + */ +#endif /* ICACHE_CRRx_REN */ + +/** + * @} + */ + +/* Exported macros ----------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros + * @{ + */ + +/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ICACHE register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ICACHE register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions + * @{ + */ + +/** @defgroup ICACHE_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable the ICACHE. + * @rmtoll CR EN LL_ICACHE_Enable + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Enable(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_EN); +} + +/** + * @brief Disable the ICACHE. + * @rmtoll CR EN LL_ICACHE_Disable + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Disable(void) +{ + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); +} + +/** + * @brief Return if ICACHE is enabled or not. + * @rmtoll CR EN LL_ICACHE_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void) +{ + return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Select the ICACHE operating mode. + * @rmtoll CR WAYSEL LL_ICACHE_SetMode + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_ICACHE_1WAY + * @arg @ref LL_ICACHE_2WAYS + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode) +{ + MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode); +} + +/** + * @brief Get the selected ICACHE operating mode. + * @rmtoll CR WAYSEL LL_ICACHE_GetMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_1WAY + * @arg @ref LL_ICACHE_2WAYS + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void) +{ + return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL)); +} + +/** + * @brief Invalidate the ICACHE. + * @note Until the BSYEND flag is set, the cache is bypassed. + * @rmtoll CR CACHEINV LL_ICACHE_Invalidate + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Invalidate(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_Monitors Monitors + * @{ + */ + +/** + * @brief Enable the hit/miss monitor(s). + * @rmtoll CR HITMEN LL_ICACHE_EnableMonitors + * @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors) +{ + SET_BIT(ICACHE->CR, Monitors); +} + +/** + * @brief Disable the hit/miss monitor(s). + * @rmtoll CR HITMEN LL_ICACHE_DisableMonitors + * @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors) +{ + CLEAR_BIT(ICACHE->CR, Monitors); +} + +/** + * @brief Check if the monitor(s) is(are) enabled or disabled. + * @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors + * @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval State of parameter value (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors) +{ + return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL); +} + +/** + * @brief Reset the hit/miss monitor(s). + * @rmtoll CR HITMRST LL_ICACHE_ResetMonitors + * @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors) +{ + /* Reset */ + SET_BIT(ICACHE->CR, (Monitors << 2U)); + /* Release reset */ + CLEAR_BIT(ICACHE->CR, (Monitors << 2U)); +} + +/** + * @brief Get the Hit monitor. + * @note Upon reaching the 32-bit maximum value, hit monitor does not wrap. + * @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void) +{ + return (ICACHE->HMONR); +} + +/** + * @brief Get the Miss monitor. + * @note Upon reaching the 16-bit maximum value, miss monitor does not wrap. + * @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor + * @retval Value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void) +{ + return (ICACHE->MMONR); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable BSYEND interrupt. + * @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void) +{ + SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); +} + +/** + * @brief Disable BSYEND interrupt. + * @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void) +{ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); +} + +/** + * @brief Check if the BSYEND Interrupt is enabled or disabled. + * @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void) +{ + return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable ERR interrupt. + * @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void) +{ + SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE); +} + +/** + * @brief Disable ERR interrupt. + * @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void) +{ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); +} + +/** + * @brief Check if the ERR Interrupt is enabled or disabled. + * @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void) +{ + return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Indicate the status of an ongoing operation flag. + * @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of an operation end flag. + * @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of an error flag. + * @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear busy end of operation flag. + * @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void) +{ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); +} + +/** + * @brief Clear error flag. + * @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void) +{ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); +} + +/** + * @} + */ + +#if defined(ICACHE_CRRx_REN) +/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management + * @{ + */ + +/** + * @brief Enable the remapped memory region. + * @note The region must have been already configured. + * @rmtoll CRRx REN LL_ICACHE_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region) +{ + SET_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REN); +} + +/** + * @brief Disable the remapped memory region. + * @rmtoll CRRx REN LL_ICACHE_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region) +{ + CLEAR_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REN); +} + +/** + * @brief Return if remapped memory region is enabled or not. + * @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region) +{ + return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL); +} + +/** + * @brief Select the memory remapped region base address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. + * @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Address Alias address in the Code region + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_BASEADDR, ((Address & 0x1FFFFFFFU) >> 21U)); +} + +/** + * @brief Get the memory remapped region base address. + * @note The base address is the alias in the Code region. + * @note The useful bits depends on RSIZE as described in the Reference Manual. + * @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Address Alias address in the Code region + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region) +{ + return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_BASEADDR) << 21U); +} + +/** + * @brief Select the memory remapped region address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. + * @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Address Memory address to remap + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos)); +} + +/** + * @brief Get the memory remapped region address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. + * @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Address Remapped memory address + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region) +{ + return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U); +} + +/** + * @brief Select the memory remapped region size. + * @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGIONSIZE_2MB + * @arg @ref LL_ICACHE_REGIONSIZE_4MB + * @arg @ref LL_ICACHE_REGIONSIZE_8MB + * @arg @ref LL_ICACHE_REGIONSIZE_16MB + * @arg @ref LL_ICACHE_REGIONSIZE_32MB + * @arg @ref LL_ICACHE_REGIONSIZE_64MB + * @arg @ref LL_ICACHE_REGIONSIZE_128MB + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos)); +} + +/** + * @brief Get the selected the memory remapped region size. + * @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_REGIONSIZE_2MB + * @arg @ref LL_ICACHE_REGIONSIZE_4MB + * @arg @ref LL_ICACHE_REGIONSIZE_8MB + * @arg @ref LL_ICACHE_REGIONSIZE_16MB + * @arg @ref LL_ICACHE_REGIONSIZE_32MB + * @arg @ref LL_ICACHE_REGIONSIZE_64MB + * @arg @ref LL_ICACHE_REGIONSIZE_128MB + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region) +{ + return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos); +} + +/** + * @brief Select the memory remapped region output burst type. + * @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Type This parameter can be one of the following values: + * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP + * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_HBURST, Type); +} + +/** + * @brief Get the selected the memory remapped region output burst type. + * @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP + * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region) +{ + return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_HBURST)); +} + +/** + * @brief Select the memory remapped region cache master port. + * @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Port This parameter can be one of the following values: + * @arg @ref LL_ICACHE_MASTER1_PORT + * @arg @ref LL_ICACHE_MASTER2_PORT + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_MSTSEL, Port); +} + +/** + * @brief Get the selected the memory remapped region cache master port. + * @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_MASTER1_PORT + * @arg @ref LL_ICACHE_MASTER2_PORT + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region) +{ + return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_MSTSEL)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions + * @{ + */ + +void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +#endif /* ICACHE_CRRx_REN */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* ICACHE */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_LL_ICACHE_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h new file mode 100644 index 00000000..a2501a22 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h @@ -0,0 +1,2269 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_LL_PWR_H +#define STM32H5xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +#if defined (PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_LL_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +/* Wake-Up Pins PWR register offsets */ +#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL +#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x7FU +/** + * @} + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_PMCR_CSSF PWR_PMCR_CSSF /*!< Clear STOP and STANDBY flags */ +#define LL_PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1 /*!< Clear Wakeup flag 1 */ +#define LL_PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2 /*!< Clear Wakeup flag 2 */ +#define LL_PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3 /*!< Clear Wakeup flag 3 */ +#define LL_PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4 /*!< Clear Wakeup flag 4 */ +#define LL_PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5 /*!< Clear Wakeup flag 5 */ +#define LL_PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6 /*!< Clear Wakeup flag 6 */ +#define LL_PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7 /*!< Clear Wakeup flag 7 */ +#define LL_PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8 /*!< Clear Wakeup flag 8 */ +#define LL_PWR_WUSCR_CWUF_ALL PWR_WUSCR_CWUF /*!< Clear all Wakeup flags */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */ +#define LL_PWR_FLAG_ACTVOSRDY PWR_VOSR_ACTOVSRDY /*!< Currently applied VOS ready flag */ +#define LL_PWR_FLAG_STOPF PWR_PMSR_STOPF /*!< STOP flag */ +#define LL_PWR_FLAG_SBF PWR_PMSR_SBF /*!< STANDBY flag */ +#define LL_PWR_FLAG_AVDO PWR_VMSR_AVDO /*!< Analog voltage detector output on VDDA flag */ +#define LL_PWR_FLAG_VDDIO2RDY PWR_VMSR_VDDIO2RDY /*!< VDDIO2 ready flag */ +#define LL_PWR_FLAG_PVDO PWR_VMSR_PVDO /*!< Programmable voltage detect output flag */ +#define LL_PWR_FLAG_USB33RDY PWR_VMSR_USB33RDY /*!< VDDUSB ready flag */ +#define LL_PWR_FLAG_TEMPH PWR_BDSR_TEMPH /*!< Temperature level flag (versus high threshold) */ +#define LL_PWR_FLAG_TEMPL PWR_BDSR_TEMPL /*!< Temperature level flag (versus low threshold) */ +#define LL_PWR_FLAG_VBATH PWR_BDSR_VBATH /*!< VBAT level flag (versus high threshold) */ +#define LL_PWR_FLAG_VBATL PWR_BDSR_VBATL /*!< VBAT level flag (versus low threshold) */ + + +#define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */ +#define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */ +#define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */ +#define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */ +#define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */ +#define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */ +#define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */ +#define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELCTION Low Power Mode Selection + * @{ + */ +#define LL_PWR_STOP_MODE (0U) /*!< STOP 0 mode */ +#define LL_PWR_STANDBY_MODE PWR_PMCR_LPMS /*!< STANDBY mode */ + + +/** + * @} + */ + +/** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SCALE0 PWR_VOSCR_VOS /*!< Voltage scaling range 0 */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSCR_VOS_1 /*!< Voltage scaling range 1 */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_VOSCR_VOS_0 /*!< Voltage scaling range 2 */ +#define LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U /*!< Voltage scaling range 3 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_PMCR_SVOS_0 /*!< Select voltage scale 5 when system enters STOP mode */ +#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_PMCR_SVOS_1 /*!< Select voltage scale 4 when system enters STOP mode */ +#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_PMCR_SVOS_0 | PWR_PMCR_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVD_LEVEL_SELECTION PWR Power Voltage Detector Level Selection + * @{ + */ +#define LL_PWR_PVDLEVEL_0 0U /*!< Voltage threshold detected by PVD 1.95 V */ +#define LL_PWR_PVDLEVEL_1 PWR_VMCR_PLS_0 /*!< Voltage threshold detected by PVD 2.10 V */ +#define LL_PWR_PVDLEVEL_2 PWR_VMCR_PLS_1 /*!< Voltage threshold detected by PVD 2.25 V */ +#define LL_PWR_PVDLEVEL_3 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_1) /*!< Voltage threshold detected by PVD 2.40 V */ +#define LL_PWR_PVDLEVEL_4 PWR_VMCR_PLS_2 /*!< Voltage threshold detected by PVD 2.55 V */ +#define LL_PWR_PVDLEVEL_5 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_2) /*!< Voltage threshold detected by PVD 2.70 V */ +#define LL_PWR_PVDLEVEL_6 (PWR_VMCR_PLS_1 | PWR_VMCR_PLS_2) /*!< Voltage threshold detected by PVD 2.85 V */ +#define LL_PWR_PVDLEVEL_7 PWR_VMCR_PLS /*!< External input analog voltage on PVD_IN + pin, compared to internal VREFINT level */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector + * @{ + */ +#define LL_PWR_AVDLEVEL_0 0U /*!< Analog Voltage threshold detected by AVD 1.7 V */ +#define LL_PWR_AVDLEVEL_1 PWR_VMCR_ALS_0 /*!< Analog Voltage threshold detected by AVD 2.1 V */ +#define LL_PWR_AVDLEVEL_2 PWR_VMCR_ALS_1 /*!< Analog Voltage threshold detected by AVD 2.5 V */ +#define LL_PWR_AVDLEVEL_3 PWR_VMCR_ALS /*!< Analog Voltage threshold detected by AVD 2.8 V */ + +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN PWR Wake Up Pin + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 PWR_WUCR_WUPEN1 /*!< Wakeup pin 1 enable */ +#define LL_PWR_WAKEUP_PIN2 PWR_WUCR_WUPEN2 /*!< Wakeup pin 2 enable */ +#define LL_PWR_WAKEUP_PIN3 PWR_WUCR_WUPEN3 /*!< Wakeup pin 3 enable */ +#define LL_PWR_WAKEUP_PIN4 PWR_WUCR_WUPEN4 /*!< Wakeup pin 4 enable */ +#define LL_PWR_WAKEUP_PIN5 PWR_WUCR_WUPEN5 /*!< Wakeup pin 5 enable */ +#define LL_PWR_WAKEUP_PIN6 PWR_WUCR_WUPEN6 /*!< Wakeup pin 6 enable */ +#define LL_PWR_WAKEUP_PIN7 PWR_WUCR_WUPEN7 /*!< Wakeup pin 7 enable */ +#define LL_PWR_WAKEUP_PIN8 PWR_WUCR_WUPEN8 /*!< Wakeup pin 8 enable */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration + * @{ + */ +#define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /*!< Configure Wake-Up pin in no pull */ +#define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /*!< Configure Wake-Up pin in pull Up */ +#define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /*!< Configure Wake-Up pin in pull Down */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration + * @{ + */ +#define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_SCCR_BYPASS /*!< The SMPS and the LDO are Bypassed. + The Core domains are supplied from an external source */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_CHARGING_RESISTOR_SELECTION PWR VBAT Charging Resistor Selection + * @{ + */ +#define LL_PWR_BATT_CHARG_RESISTOR_5K 0U /*!< Charge the battery through a 5 kO resistor */ +#define LL_PWR_BATT_CHARG_RESISTOR_1_5K PWR_BDCR_VBRS /*!< Charge the battery through a 1.5 kO resistor */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute + * @{ + */ +#define LL_PWR_WAKEUP_PIN1_NSEC 0U /* Wake up pin 1 nsecure mode */ +#define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC /* Wake up pin 1 secure mode */ +#define LL_PWR_WAKEUP_PIN2_NSEC 0U /* Wake up pin 2 nsecure mode */ +#define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC /* Wake up pin 2 secure mode */ +#define LL_PWR_WAKEUP_PIN3_NSEC 0U /* Wake up pin 3 nsecure mode */ +#define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC /* Wake up pin 3 secure mode */ +#define LL_PWR_WAKEUP_PIN4_NSEC 0U /* Wake up pin 4 nsecure mode */ +#define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC /* Wake up pin 4 secure mode */ +#define LL_PWR_WAKEUP_PIN5_NSEC 0U /* Wake up pin 5 nsecure mode */ +#define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC /* Wake up pin 5 secure mode */ +#define LL_PWR_WAKEUP_PIN6_NSEC 0U /* Wake up pin 6 nsecure mode */ +#define LL_PWR_WAKEUP_PIN6_SEC PWR_SECCFGR_WUP6SEC /* Wake up pin 6 secure mode */ +#define LL_PWR_WAKEUP_PIN7_NSEC 0U /* Wake up pin 7 nsecure mode */ +#define LL_PWR_WAKEUP_PIN7_SEC PWR_SECCFGR_WUP7SEC /* Wake up pin 7 secure mode */ +#define LL_PWR_WAKEUP_PIN8_NSEC 0U /* Wake up pin 8 nsecure mode */ +#define LL_PWR_WAKEUP_PIN8_SEC PWR_SECCFGR_WUP8SEC /* Wake up pin 8 secure mode */ + +#define LL_PWR_RET_NSEC 0U /* Retention nsecure mode */ +#define LL_PWR_RET_SEC PWR_SECCFGR_RETSEC /* Retention secure mode */ +#define LL_PWR_LPM_NSEC 0U /* Low-power modes nsecure mode */ +#define LL_PWR_LPM_SEC PWR_SECCFGR_LPMSEC /* Low-power modes secure mode */ +#define LL_PWR_VDM_NSEC 0U /* Voltage detection and monitoring nsecure mode */ +#define LL_PWR_VDM_SEC PWR_SECCFGR_SCMSEC /* Voltage detection and monitoring secure mode */ +#define LL_PWR_VB_NSEC 0U /* Backup domain nsecure mode */ +#define LL_PWR_VB_SEC PWR_SECCFGR_VBSEC /* Backup domain secure mode */ +#define LL_PWR_APC_NSEC 0U /* Pull-up/pull-down nsecure mode */ +#define LL_PWR_APC_SEC PWR_SECCFGR_VUSBSEC /* Pull-up/pull-down secure mode */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common Write and Read Registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register. + * @param __REG__ Register to be written. + * @param __VALUE__ Value to be written in the register. + * @retval None. + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register. + * @param __REG__ Register to be read. + * @retval Register value. + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_CONFIGURATION PWR Configuration + * @{ + */ + +/** + * @brief Set system power mode. + * @rmtoll PMCR LPMS LL_PWR_SetPowerMode + * @param Mode : This parameter can be one of the following values: + * @arg @ref LL_PWR_STOP_MODE + * @arg @ref LL_PWR_STANDBY_MODE + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode) +{ + MODIFY_REG(PWR->PMCR, PWR_PMCR_LPMS, Mode); +} + +/** + * @brief Get system power mode. + * @rmtoll PMCR LPMS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_STOP_MODE + * @arg @ref LL_PWR_STANDBY_MODE + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (READ_BIT(PWR->PMCR, PWR_PMCR_LPMS)); +} + +/** + * @brief Set the internal Regulator output voltage in STOP mode + * @rmtoll PMCR SVOS LL_PWR_SetStopModeRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->PMCR, PWR_PMCR_SVOS, VoltageScaling); +} + +/** + * @brief Get the internal Regulator output voltage in STOP mode + * @rmtoll PMCR SVOS LL_PWR_GetStopModeRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 + */ +__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->PMCR, PWR_PMCR_SVOS)); +} + +/** + * @brief Enable the Flash Power Down in Stop Mode + * @rmtoll PMCR FLPS LL_PWR_EnableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_FLPS); +} + +/** + * @brief Disable the Flash Power Down in Stop Mode + * @rmtoll PMCR FLPS LL_PWR_DisableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_FLPS); +} + +/** + * @brief Check if the Flash Power Down in Stop Mode is enabled + * @rmtoll PMCR FLPS LL_PWR_IsEnabledFlashPowerDown + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_FLPS) == (PWR_PMCR_FLPS)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Analog Voltage Booster (VDDA) + * @rmtoll PMCR BOOSTE LL_PWR_EnableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAnalogBooster(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_BOOSTE); +} + +/** + * @brief Disable the Analog Voltage Booster (VDDA) + * @rmtoll PMCR BOOSTE LL_PWR_DisableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAnalogBooster(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_BOOSTE); +} + +/** + * @brief Check if the Analog Voltage Booster (VDDA) is enabled + * @rmtoll PMCR BOOSTE LL_PWR_IsEnabledAnalogBooster + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_BOOSTE) == (PWR_PMCR_BOOSTE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready + * @rmtoll PMCR AVD_READY LL_PWR_EnableAnalogVoltageReady + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_AVD_READY); +} + +/** + * @brief Disable the Analog Voltage Ready (VDDA) + * @rmtoll PMCR AVD_READY LL_PWR_DisableAnalogVoltageReady + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_AVD_READY); +} + +/** + * @brief Check if the Analog Voltage Booster (VDDA) is enabled + * @rmtoll PMCR AVD_READY LL_PWR_IsEnabledAnalogVoltageReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_AVD_READY) == (PWR_PMCR_AVD_READY)) ? 1UL : 0UL); +} + +/** + * @brief Enable the AHB RAM1 shut-off in Stop mode + * @rmtoll PMCR SRAM1SO LL_PWR_EnableAHBRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO); +} + +/** + * @brief Disable the AHB RAM1 shut-off in Stop mode + * @rmtoll PMCR SRAM1SO LL_PWR_DisableAHBRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO); +} + +/** + * @brief Check if the AHB RAM1 shut-off in Stop mode is enabled + * @rmtoll CR1 SRAM1SO LL_PWR_IsEnabledAHBRAM1ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO) == (PWR_PMCR_SRAM1SO)) ? 1UL : 0UL); +} +#if defined (PWR_PMCR_SRAM2_48SO) +/** + * @brief Enable the AHB RAM2 48K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_48SO LL_PWR_EnableAHBRAM2_48K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM2_48K_ShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO); +} + +/** + * @brief Disable the AHB RAM2 48K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_48SO LL_PWR_DisableAHBRAM2_48K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM2_48K_ShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO); +} + +/** + * @brief Check if the AHB RAM2 shut-off in Stop mode is enabled + * @rmtoll PMCR SRAM2_48SO LL_PWR_IsEnabledAHBRAM2_48K_ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_48K_ShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO) == (PWR_PMCR_SRAM2_48SO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_SRAM2_48SO */ + +#if defined (PWR_PMCR_SRAM2_16SO) +/** + * @brief Enable the AHB RAM2 16K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_16SO LL_PWR_EnableAHBRAM2_16K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM2_16K_ShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO); +} + +/** + * @brief Disable the AHB RAM2 16K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_16SO LL_PWR_DisableAHBRAM2_16K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM2_16K_ShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO); +} + +/** + * @brief Check if the AHB RAM2 shut-off in Stop mode is enabled + * @rmtoll PMCR SRAM2_16SO LL_PWR_IsEnabledAHBRAM2_16K_ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_16K_ShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO) == (PWR_PMCR_SRAM2_16SO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_SRAM2_16SO */ + +#if defined(PWR_PMCR_SRAM2_16HSO) +/** + * @brief Enable the AHB RAM2 high 16K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_16HSO LL_PWR_EnableAHBRAM2_High_16K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM2_High_16K_ShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO); +} + +/** + * @brief Disable the AHB RAM2 high 16K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_16HSO LL_PWR_DisableAHBRAM2_High_16K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM2_High_16K_ShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO); +} + +/** + * @brief Check if the high AHB RAM2 shut-off in Stop mode is enabled + * @rmtoll PMCR SRAM2_16HSO LL_PWR_IsEnabledAHBRAM2_16K_ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_High_16K_ShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO) == (PWR_PMCR_SRAM2_16HSO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_SRAM2_16HSO */ + +#if defined(PWR_PMCR_SRAM2_16LSO) +/** + * @brief Enable the AHB RAM2 low 16K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_16LSO LL_PWR_EnableAHBRAM2_Low_16K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM2_Low_16K_ShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO); +} + +/** + * @brief Disable the AHB RAM2 low 16K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_16LSO LL_PWR_DisableAHBRAM2_Low_16K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM2_Low_16K_ShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO); +} + +/** + * @brief Check if the low 16K AHB RAM2 shut-off in Stop mode is enabled + * @rmtoll PMCR SRAM2_16LSO LL_PWR_IsEnabledAHBRAM2_Low_16K_ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_Low_16K_ShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO) == (PWR_PMCR_SRAM2_16LSO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_SRAM2_16LSO */ + +#if defined(PWR_PMCR_SRAM2_48HSO) +/** + * @brief Enable the AHB RAM2 high 48K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_48HSO LL_PWR_EnableAHBRAM2_High_48K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM2_High_48K_ShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48HSO); +} + +/** + * @brief Disable the AHB RAM2 high 48K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_48HSO LL_PWR_DisableAHBRAM2_High_48K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM2_High_48K_ShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48HSO); +} + +/** + * @brief Check if the high AHB RAM2 shut-off in Stop mode is enabled + * @rmtoll PMCR SRAM2_48HSO LL_PWR_IsEnabledAHBRAM2_High_48K_ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_High_48K_ShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48HSO) == (PWR_PMCR_SRAM2_48HSO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_SRAM2_48HSO */ + +#if defined(PWR_PMCR_SRAM2_48LSO) +/** + * @brief Enable the AHB RAM2 low 48K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_48LSO LL_PWR_EnableAHBRAM2_Low_48K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM2_Low_48K_ShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48LSO); +} + +/** + * @brief Disable the AHB RAM2 low 48K Bytes shut-off in Stop mode + * @rmtoll PMCR SRAM2_48LSO LL_PWR_DisableAHBRAM2_Low_48K_ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM2_Low_48K_ShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48LSO); +} + +/** + * @brief Check if the low 48K AHB RAM2 shut-off in Stop mode is enabled + * @rmtoll PMCR SRAM2_48LSO LL_PWR_IsEnabledAHBRAM2_Low_48K_ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_Low_48K_ShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48LSO) == (PWR_PMCR_SRAM2_48LSO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_SRAM2_48LSO */ + +#if defined (PWR_PMCR_SRAM2SO) +/** + * @brief Enable the AHB RAM2 shut-off in Stop mode + * @rmtoll PMCR SRAM2SO LL_PWR_EnableAHBRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO); +} + +/** + * @brief Disable the AHB RAM2 shut-off in Stop mode + * @rmtoll PMCR SRAM2SO LL_PWR_DisableAHBRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO); +} + +/** + * @brief Check if the AHB RAM2 shut-off in Stop mode is enabled + * @rmtoll PMCR SRAM2SO LL_PWR_IsEnabledAHBRAM2ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO) == (PWR_PMCR_SRAM2SO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_SRAM2SO */ + +#if defined (PWR_PMCR_SRAM3SO) +/** + * @brief Enable the AHB RAM3 shut-off in Stop mode + * @rmtoll PMCR SRAM3SO LL_PWR_EnableAHBRAM3ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM3ShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO); +} + +/** + * @brief Disable the AHB RAM3 shut-off in Stop mode + * @rmtoll PMCR SRAM3SO LL_PWR_DisableAHBRAM3ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM3ShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO); +} + +/** + * @brief Check if the AHB RAM3 shut-off in Stop mode is enabled + * @rmtoll PMCR SRAM3SO LL_PWR_IsEnabledAHBRAM3ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM3ShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO) == (PWR_PMCR_SRAM3SO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_SRAM3SO */ + +#if defined (PWR_PMCR_SRAM4SO) +/** + * @brief Enable the AHB RAM4 shut-off in Stop mode + * @rmtoll PMCR SRAM4SO LL_PWR_EnableAHBRAM4ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM4ShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_SRAM4SO); +} + +/** + * @brief Disable the AHB RAM4 shut-off in Stop mode + * @rmtoll PMCR SRAM4SO LL_PWR_DisableAHBRAM4ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM4ShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM4SO); +} + +/** + * @brief Check if the AHB RAM4 shut-off in Stop mode is enabled + * @rmtoll PMCR SRAM4SO LL_PWR_IsEnabledAHBRAM4ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM4ShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM4SO) == (PWR_PMCR_SRAM4SO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_SRAM4SO */ + +#if defined (PWR_PMCR_SRAM5SO) +/** + * @brief Enable the AHB RAM5 shut-off in Stop mode + * @rmtoll PMCR SRAM5SO LL_PWR_EnableAHBRAM5ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM5ShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_SRAM5SO); +} + +/** + * @brief Disable the AHB RAM5 shut-off in Stop mode + * @rmtoll PMCR SRAM5SO LL_PWR_DisableAHBRAM5ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM5ShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM5SO); +} + +/** + * @brief Check if the AHB RAM5 shut-off in Stop mode is enabled + * @rmtoll PMCR SRAM5SO LL_PWR_IsEnabledAHBRAM5ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM5ShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM5SO) == (PWR_PMCR_SRAM5SO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_SRAM5SO */ + +#if defined (PWR_PMCR_ETHERNETSO) +/** + * @brief Enable the ETHERNET RAM shut-off in Stop mode + * @rmtoll PMCR ETHERNETSO LL_PWR_EnableETHERNETRAMShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableETHERNETRAMShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO); +} + +/** + * @brief Disable the ETHERNET RAM shut-off in Stop mode + * @rmtoll PMCR ETHERNETSO LL_PWR_DisableETHERNETRAMShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableETHERNETRAMShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO); +} + +/** + * @brief Check if the ETHERNET RAM shut-off in Stop mode is enabled + * @rmtoll PMCR ETHERNETSO LL_PWR_IsEnabledETHERNETRAMShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledETHERNETRAMShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO) == (PWR_PMCR_ETHERNETSO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_ETHERNETSO */ + +#if defined (PWR_PMCR_LTDCSO) +/** + * @brief Enable the LTDC RAM shut-off in Stop mode + * @rmtoll PMCR LTDCSO LL_PWR_EnableLTDCRAMShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableLTDCRAMShutOff(void) +{ + SET_BIT(PWR->PMCR, PWR_PMCR_LTDCSO); +} + +/** + * @brief Disable the LTDC RAM shut-off in Stop mode + * @rmtoll PMCR LTDCSO LL_PWR_DisableLTDCRAMShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableLTDCRAMShutOff(void) +{ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_LTDCSO); +} + +/** + * @brief Check if the LTDC RAM shut-off in Stop mode is enabled + * @rmtoll PMCR LTDCSO LL_PWR_IsEnabledLTDCRAMShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledLTDCRAMShutOff(void) +{ + return ((READ_BIT(PWR->PMCR, PWR_PMCR_LTDCSO) == (PWR_PMCR_LTDCSO)) ? 1UL : 0UL); +} +#endif /* PWR_PMCR_LTDCSO */ + +/** + * @brief Set the regulator supply output voltage. + * @rmtoll VOSCR VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, VoltageScaling); +} + +/** + * @brief Get the regulator supply output voltage. + * @rmtoll VOSCR VOS LL_PWR_GetRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->VOSCR, PWR_VOSCR_VOS)); +} + +/** + * @brief Get currently voltage scaling applied to VCORE. + * @rmtoll VOSSR ACTVOS[1:0] LL_PWR_GetCurrentVOS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetCurrentVOS(void) +{ + return (READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOS)); +} + +/** + * @brief Enable Backup Regulator + * @rmtoll BDCR BREN LL_PWR_EnableBkUpRegulator + * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and + * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup + * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set, + * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that + * the data written into the RAM will be maintained in the Standby and VBAT modes. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) +{ + SET_BIT(PWR->BDCR, PWR_BDCR_BREN); +} + +/** + * @brief Disable Backup Regulator + * @rmtoll BDCR BREN LL_PWR_DisableBkUpRegulator + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) +{ + CLEAR_BIT(PWR->BDCR, PWR_BDCR_BREN); +} + +/** + * @brief Check if the backup Regulator is enabled + * @rmtoll BDCR BREN LL_PWR_IsEnabledBkUpRegulator + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) +{ + return ((READ_BIT(PWR->BDCR, PWR_BDCR_BREN) == (PWR_BDCR_BREN)) ? 1UL : 0UL); +} + +/** + * @brief Enable VBAT and Temperature monitoring + * @rmtoll BDCR MONEN LL_PWR_EnableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableMonitoring(void) +{ + SET_BIT(PWR->BDCR, PWR_BDCR_MONEN); +} + +/** + * @brief Disable VBAT and Temperature monitoring + * @rmtoll BDCR MONEN LL_PWR_DisableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableMonitoring(void) +{ + CLEAR_BIT(PWR->BDCR, PWR_BDCR_MONEN); +} + +/** + * @brief Check if the VBAT and Temperature monitoring is enabled + * @rmtoll BDCR MONEN LL_PWR_IsEnabledMonitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void) +{ + return ((READ_BIT(PWR->BDCR, PWR_BDCR_MONEN) == (PWR_BDCR_MONEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable battery charging + * @rmtoll BDCR VBE LL_PWR_EnableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) +{ + SET_BIT(PWR->BDCR, PWR_BDCR_VBE); +} + +/** + * @brief Disable battery charging + * @rmtoll BDCR VBE LL_PWR_DisableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->BDCR, PWR_BDCR_VBE); +} + +/** + * @brief Check if battery charging is enabled + * @rmtoll BDCR VBE LL_PWR_IsEnabledBatteryCharging + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) +{ + return ((READ_BIT(PWR->BDCR, PWR_BDCR_VBE) == (PWR_BDCR_VBE)) ? 1UL : 0UL); +} + +/** + * @brief Set the Battery charge resistor impedance + * @rmtoll BDCR VBRS LL_PWR_SetBattChargResistor + * @param Resistor This parameter can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) +{ + MODIFY_REG(PWR->BDCR, PWR_BDCR_VBRS, Resistor); +} + +/** + * @brief Get the Battery charge resistor impedance + * @rmtoll BDCR VBRS LL_PWR_GetBattChargResistor + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K + */ +__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) +{ + return (uint32_t)(READ_BIT(PWR->BDCR, PWR_BDCR_VBRS)); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll DBPCR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll DBPCR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->DBPCR, PWR_DBPCR_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll DBPCR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return ((READ_BIT(PWR->DBPCR, PWR_DBPCR_DBP) == (PWR_DBPCR_DBP)) ? 1UL : 0UL); +} + +#if defined (PWR_UCPDR_UCPD_STBY) +/** + * @brief Enable the USB type-C and power delivery memorization in Standby + * mode. + * @note This function must be called just before entering Standby mode. + * @rmtoll UCPDR UCPD_STDBY LL_PWR_EnableUCPDStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void) +{ + SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY); +} + +/** + * @brief Disable the USB type-C and power delivery memorization in Standby + * mode. + * @note This function must be called after exiting Standby mode and before + * any UCPD configuration update. + * @rmtoll UCPDR UCPD_STDBY LL_PWR_DisableUCPDStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void) +{ + CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY); +} + +/** + * @brief Check if the USB Type-C and Power Delivery Standby mode memorization + * is enabled. + * @rmtoll UCPDR UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void) +{ + return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY) == (PWR_UCPDR_UCPD_STBY)) ? 1UL : 0UL); +} +#endif /* PWR_UCPDR_UCPD_STBY */ + +#if defined (PWR_UCPDR_UCPD_DBDIS) +/** + * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior + * on UCPD CC1 and CC2 pins. + * @note After exiting reset, the USB Type-C dead battery behavior is enabled, + * which may have a pull-down effect on CC1 and CC2 pins. It is recommended + * to disable it in all cases, either to stop this pull-down or to hand over + * control to the UCPD (which should therefore be initialized before doing the disable). + * @rmtoll UCPDR UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void) +{ + CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); +} + +/** + * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior + * on UCPD CC1 and CC2 pins. + * @note After exiting reset, the USB Type-C dead battery behavior is enabled, + * which may have a pull-down effect on CC1 and CC2 pins. It is recommended + * to disable it in all cases, either to stop this pull-down or to hand over + * control to the UCPD (which should therefore be initialized before doing the disable). + * @rmtoll UCPDR UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void) +{ + SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); +} + +/** + * @brief Check the USB Type-C and power delivery dead battery pull-down behavior + * on UCPD CC1 and CC2 pins. + * @note After exiting reset, the USB Type-C dead battery behavior is enabled, + * which may have a pull-down effect on CC1 and CC2 pins. It is recommended + * to disable it in all cases, either to stop this pull-down or to hand over + * control to the UCPD (which should therefore be initialized before doing the disable). + * @rmtoll UCPDR UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery + * @retval State of feature (1 : enabled; 0 : disabled). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void) +{ + return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 0UL : 1UL); +} +#endif /* PWR_UCPDR_UCPD_DBDIS */ + +/** + * @brief Configure the PWR supply + * @rmtoll SCCR BYPASS LL_PWR_ConfigSupply + * @param SupplySource This parameter can be one of the following values: + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + * @retval None + */ +__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource) +{ + /* Set the power supply configuration */ + MODIFY_REG(PWR->SCCR, (PWR_SCCR_BYPASS), SupplySource); +} + +/** + * @brief Get the PWR supply + * @rmtoll SCCR BYPASS LL_PWR_GetSupply + * @retval The supply configuration. + */ +__STATIC_INLINE uint32_t LL_PWR_GetSupply(void) +{ +#if defined (PWR_SCCR_SMPSEN) + /* Get the power supply configuration */ + return (uint32_t)(READ_BIT(PWR->SCCR, (PWR_SCCR_SMPSEN | PWR_SCCR_LDOEN | PWR_SCCR_BYPASS))); +#else + /* Get the power supply configuration */ + return (uint32_t)(READ_BIT(PWR->SCCR, (PWR_SCCR_LDOEN | PWR_SCCR_BYPASS))); +#endif /* PWR_SCCR_SMPSEN */ +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll VMCR PVDEN LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->VMCR, PWR_VMCR_PVDEN); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll VMCR PVDEN LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->VMCR, PWR_VMCR_PVDEN); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll VMCR PVDEN LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return ((READ_BIT(PWR->VMCR, PWR_VMCR_PVDEN) == (PWR_VMCR_PVDEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll VMCR PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->VMCR, PWR_VMCR_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll VMCR PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->VMCR, PWR_VMCR_PLS)); +} + + +/** + * @brief Enable Analog Power Voltage Detector + * @rmtoll VMCR AVDEN LL_PWR_EnableAVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAVD(void) +{ + SET_BIT(PWR->VMCR, PWR_VMCR_AVDEN); +} + +/** + * @brief Disable Analog Power Voltage Detector + * @rmtoll VMCR AVDEN LL_PWR_DisableAVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAVD(void) +{ + CLEAR_BIT(PWR->VMCR, PWR_VMCR_AVDEN); +} + +/** + * @brief Check if Analog Power Voltage Detector is enabled + * @rmtoll VMCR AVDEN LL_PWR_IsEnabledAVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void) +{ + return ((READ_BIT(PWR->VMCR, PWR_VMCR_AVDEN) == (PWR_VMCR_AVDEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector + * @rmtoll VMCR ALS LL_PWR_SetAVDLevel + * @param AVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_AVDLEVEL_0 + * @arg @ref LL_PWR_AVDLEVEL_1 + * @arg @ref LL_PWR_AVDLEVEL_2 + * @arg @ref LL_PWR_AVDLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel) +{ + MODIFY_REG(PWR->VMCR, PWR_VMCR_ALS, AVDLevel); +} + +/** + * @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector + * @rmtoll CR1 ALS LL_PWR_GetAVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_AVDLEVEL_0 + * @arg @ref LL_PWR_AVDLEVEL_1 + * @arg @ref LL_PWR_AVDLEVEL_2 + * @arg @ref LL_PWR_AVDLEVEL_3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->VMCR, PWR_VMCR_ALS)); +} + +#if defined (PWR_USBSCR_USB33DEN) +/** + * @brief Enable the USB voltage detector + * @rmtoll USBSCR USB33DEN LL_PWR_EnableUSBVoltageDetector + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void) +{ + SET_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN); +} + +/** + * @brief Disable the USB voltage detector + * @rmtoll USBSCR USB33DEN LL_PWR_DisableUSBVoltageDetector + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void) +{ + CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN); +} + +/** + * @brief Check if the USB voltage detector is enabled + * @rmtoll USBSCR USB33DEN LL_PWR_IsEnabledUSBVoltageDetector + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void) +{ + return ((READ_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN) == (PWR_USBSCR_USB33DEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the independent USB supply. + * @rmtoll USBSCR USB33SV LL_PWR_EnableVddUSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVddUSB(void) +{ + SET_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV); +} +#define LL_PWR_EnableVDDUSB LL_PWR_EnableVddUSB /* for API backward compatibility */ + +/** + * @brief Disable the independent USB supply. + * @rmtoll USBSCR USB33SV LL_PWR_DisableVddUSB + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVddUSB(void) +{ + CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV); +} +#define LL_PWR_DisableVDDUSB LL_PWR_DisableVddUSB /* for API backward compatibility */ + +/** + * @brief Check if the independent USB supply is enabled. + * @rmtoll USBSCR USB33SV LL_PWR_IsEnabledVddUSB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) +{ + return ((READ_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV) == (PWR_USBSCR_USB33SV)) ? 1UL : 0UL); +} +#define LL_PWR_IsEnabledVDDUSB LL_PWR_IsEnabledVddUSB /* for API backward compatibility */ +#endif /* PWR_USBSCR_USB33DEN */ + +#if defined (PWR_USBSCR_OTGHSEN) +/** + * @brief Enable the USB OTGHS phy + * @rmtoll USBSCR OTGHSEN LL_PWR_EnableUSBOTGHSPhy + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBOTGHSPhy(void) +{ + SET_BIT(PWR->USBSCR, PWR_USBSCR_OTGHSEN); +} + +/** + * @brief Disable the USB OTGHS phy + * @rmtoll USBSCR OTGHSEN LL_PWR_DisableUSBOTGHSPhy + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBOTGHSPhy(void) +{ + CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_OTGHSEN); +} + +/** + * @brief Check if the USB OTGHS phy is enabled + * @rmtoll USBSCR OTGHSEN LL_PWR_IsEnabledUSBOTGHSPhy + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBOTGHSPhy(void) +{ + return ((READ_BIT(PWR->USBSCR, PWR_USBSCR_OTGHSEN) == (PWR_USBSCR_OTGHSEN)) ? 1UL : 0UL); +} +#endif /* PWR_USBSCR_OTGHSEN */ + +/** + * @brief Enable the wake up pin_x. + * @rmtoll WUCR WUPENx LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WUCR, WakeUpPin); +} + +/** + * @brief Disable the wake up pin_x. + * @rmtoll WUCR WUPENx LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WUCR, WakeUpPin); +} + +/** + * @brief Check if the wake up pin_x is enabled. + * @rmtoll WUCR WUPPx LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WUCR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin polarity low for the event detection + * @rmtoll WUCR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WKUPP7 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WKUPP8 LL_PWR_SetWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WUCR, (WakeUpPin << PWR_WUCR_WUPP1_Pos)); +} + +/** + * @brief Set the Wake-Up pin polarity high for the event detection + * @rmtoll WUCR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n + * WUCR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n + * WUCR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n + * WUCR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n + * WUCR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n + * WUCR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh\n + * WUCR WKUPP7 LL_PWR_SetWakeUpPinPolarityHigh\n + * WUCR WKUPP8 LL_PWR_SetWakeUpPinPolarityHigh + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WUCR, (WakeUpPin << PWR_WUCR_WUPP1_Pos)); +} + +/** + * @brief Get the Wake-Up pin polarity for the event detection + * @rmtoll WUCR WUPP1 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WUPP2 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WUPP3 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WUPP4 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WUPP5 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WUPP6 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WUPP7 LL_PWR_SetWakeUpPinPolarityLow\n + * WUCR WUPP8 LL_PWR_SetWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WUCR, (WakeUpPin << PWR_WUCR_WUPP1_Pos)) == (WakeUpPin << PWR_WUCR_WUPP1_Pos)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin Pull None + * @rmtoll WUCR WUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n + * WUCR WUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n + * WUCR WUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n + * WUCR WUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n + * WUCR WUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n + * WUCR WUPPUPD6 LL_PWR_SetWakeUpPinPullNone\n + * WUCR WUPPUPD7 LL_PWR_SetWakeUpPinPullNone\n + * WUCR WUPPUPD8 LL_PWR_SetWakeUpPinPullNone + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WUCR, + (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * (POSITION_VAL(WakeUpPin) & 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), + (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \ + POSITION_VAL(WakeUpPin)) & 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin Pull Up + * @rmtoll WUCR WUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n + * WUCR WUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n + * WUCR WUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n + * WUCR WUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n + * WUCR WUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n + * WUCR WUPPUPD6 LL_PWR_SetWakeUpPinPullUp\n + * WUCR WUPPUPD7 LL_PWR_SetWakeUpPinPullUp\n + * WUCR WUPPUPD8 LL_PWR_SetWakeUpPinPullUp + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WUCR, + (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * (POSITION_VAL(WakeUpPin) & 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), + (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \ + POSITION_VAL(WakeUpPin)) & 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin Pull Down + * @rmtoll WUCR WUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n + * WUCR WUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n + * WUCR WUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n + * WUCR WUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n + * WUCR WUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n + * WUCR WUPPUPD6 LL_PWR_SetWakeUpPinPullDown\n + * WUCR WUPPUPD7 LL_PWR_SetWakeUpPinPullDown\n + * WUCR WUPPUPD8 LL_PWR_SetWakeUpPinPullDown + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WUCR, + (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * (POSITION_VAL(WakeUpPin) & 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), + (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \ + POSITION_VAL(WakeUpPin)) & 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Get the Wake-Up pin pull + * @rmtoll WUCR WUPPUPD1 LL_PWR_GetWakeUpPinPull\n + * WUCR WUPPUPD2 LL_PWR_GetWakeUpPinPull\n + * WUCR WUPPUPD3 LL_PWR_GetWakeUpPinPull\n + * WUCR WUPPUPD4 LL_PWR_GetWakeUpPinPull\n + * WUCR WUPPUPD5 LL_PWR_GetWakeUpPinPull\n + * WUCR WUPPUPD7 LL_PWR_GetWakeUpPinPull\n + * WUCR WUPPUPD7 LL_PWR_GetWakeUpPinPull\n + * WUCR WUPPUPD8 LL_PWR_GetWakeUpPinPull + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL + * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP + * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin) +{ + uint32_t regValue = READ_BIT(PWR->WUCR, (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \ + (POSITION_VAL(WakeUpPin) & 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); + + return (uint32_t)(regValue >> ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \ + POSITION_VAL(WakeUpPin)) & 0xFU)) & \ + LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)); +} + +/** + * @brief Enable IO Retention + * @rmtoll IORETR IORETEN LL_PWR_EnableIORetention + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableIORetention(void) +{ + SET_BIT(PWR->IORETR, PWR_IORETR_IORETEN); +} + +/** + * @brief Disable IO Retention + * @rmtoll IORETR IORETEN LL_PWR_DisableIORetention + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableIORetention(void) +{ + CLEAR_BIT(PWR->IORETR, PWR_IORETR_IORETEN); +} + +/** + * @brief Check if IO Retention is enabled + * @rmtoll IORETR IORETEN LL_PWR_IsEnabledIORetention + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledIORetention(void) +{ + return ((READ_BIT(PWR->IORETR, PWR_IORETR_IORETEN) == (PWR_IORETR_IORETEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable JTAGIO Retention + * @rmtoll JTAGIORETR JTAGIORETEN LL_PWR_EnableJTAGIORetention + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableJTAGIORetention(void) +{ + SET_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN); +} + +/** + * @brief Disable JTAGIO Retention + * @rmtoll JTAGIORETR JTAGIORETEN LL_PWR_DisableJTAGIORetention + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableJTAGIORetention(void) +{ + CLEAR_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN); +} + +/** + * @brief Check if JTAGIO Retention is enabled + * @rmtoll IORETR JTAGIORETEN LL_PWR_IsEnabledJTAGIORetention + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledJTAGIORetention(void) +{ + return ((READ_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN) == (PWR_IORETR_JTAGIORETEN)) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management + * @{ + */ + +/** + * @brief Indicate whether the regulator voltage output is above voltage + * scaling range or not. + * @rmtoll VOSSR VOSRDY LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ + return ((READ_BIT(PWR->VOSSR, PWR_VOSSR_VOSRDY) == (PWR_VOSSR_VOSRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the system was in standby mode or not. + * @rmtoll PMSR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->PMSR, PWR_PMSR_SBF) == (PWR_PMSR_SBF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the system was in stop mode or not. + * @rmtoll PMSR STOPF LL_PWR_IsActiveFlag_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void) +{ + return ((READ_BIT(PWR->PMSR, PWR_PMSR_STOPF) == (PWR_PMSR_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VDD voltage is below the threshold or not. + * @rmtoll VMSR PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return ((READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == (PWR_VMSR_PVDO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VDDA voltage is below the threshold or not. + * @rmtoll VMSR AVDO LL_PWR_IsActiveFlag_AVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void) +{ + return ((READ_BIT(PWR->VMSR, PWR_VMSR_AVDO) == (PWR_VMSR_AVDO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the regulator voltage output is equal to current + * used voltage scaling range or not. + * @rmtoll VOSSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void) +{ + return ((READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOSRDY) == (PWR_VOSSR_ACTVOSRDY)) ? 1UL : 0UL); +} + +#if defined (PWR_VMSR_USB33RDY) +/** + * @brief Indicate whether the VDDUSB is below the threshold of monitor or not. + * @rmtoll VMSR USB33RDY LL_PWR_IsActiveFlag_VDDUSB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDUSB(void) +{ + return ((READ_BIT(PWR->VMSR, PWR_VMSR_USB33RDY) == (PWR_VMSR_USB33RDY)) ? 1UL : 0UL); +} +#endif /* PWR_VMSR_USB33RDY */ + +/** + * @brief Indicate whether VDDMMC voltage is below 1V2 + * @rmtoll VMSR VDDIO2RDY LL_PWR_IsActiveFlag_VDDIO2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO2(void) +{ + return ((READ_BIT(PWR->VMCR, PWR_VMSR_VDDIO2RDY) == (PWR_VMSR_VDDIO2RDY)) ? 1UL : 0UL); +} + +/** + * @brief Get Backup Regulator ready Flag + * @rmtoll BDSR BRRDY LL_PWR_IsActiveFlag_BRR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void) +{ + return ((READ_BIT(PWR->BDSR, PWR_BDSR_BRRDY) == (PWR_BDSR_BRRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VBAT level is below high threshold or not. + * @rmtoll BDSR VBATL LL_PWR_IsActiveFlag_VBATL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void) +{ + return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATL) == (PWR_BDSR_VBATL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VBAT level is below high threshold or not. + * @rmtoll BDSR VBATH LL_PWR_IsActiveFlag_VBATH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void) +{ + return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == (PWR_BDSR_VBATH)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is above low threshold or + * not. + * @rmtoll BDSR TEMPL LL_PWR_IsActiveFlag_TEMPL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void) +{ + return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == (PWR_BDSR_TEMPL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is below high threshold + * or not. + * @rmtoll BDSR TEMPH LL_PWR_IsActiveFlag_TEMPH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void) +{ + return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == (PWR_BDSR_TEMPH)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 1. + * @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 2. + * @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 3. + * @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 4. + * @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 5. + * @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL); +} + +#if defined (PWR_WUSR_WUF6) +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 6. + * @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL); +} +#endif /* PWR_WUSR_WUF6 */ + +#if defined (PWR_WUSR_WUF7) +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 7. + * @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL); +} +#endif /* PWR_WUSR_WUF7 */ + +#if defined (PWR_WUSR_WUF8) +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 8. + * @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL); +} +#endif /* PWR_WUSR_WUF8 */ + +/** + * @brief Clear stop flag. + * @rmtoll PMCR CSSF LL_PWR_ClearFlag_STOP + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_STOP(void) +{ + WRITE_REG(PWR->PMCR, PWR_PMCR_CSSF); +} + +/** + * @brief Clear standby flag. + * @rmtoll PMCR CSSF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + WRITE_REG(PWR->PMCR, PWR_PMCR_CSSF); +} + +/** + * @brief Clear wake up flag 1. + * @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1); +} + +/** + * @brief Clear wake up flag 2. + * @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2); +} + +/** + * @brief Clear wake up flag 3. + * @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3); +} + +/** + * @brief Clear wake up flag 4. + * @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4); +} + +/** + * @brief Clear wake up flag 5. + * @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5); +} + +#if defined (PWR_WUSCR_CWUF6) +/** + * @brief Clear wake up flag 6. + * @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6); +} +#endif /* PWR_WUSCR_CWUF6 */ + +#if defined (PWR_WUSCR_CWUF7) +/** + * @brief Clear wake up flag 7. + * @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU7(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7); +} +#endif /* PWR_WUSCR_CWUF7 */ + +#if defined (PWR_WUSCR_CWUF8) +/** + * @brief Clear wake up flag 8. + * @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU8(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8); +} +#endif /* PWR_WUSCR_CWUF8 */ + +/** + * @brief Clear all wake up flags. + * @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF); +} +/** + * @} + */ + +/** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management + * @{ + */ + +#if defined(PWR_PRIVCFGR_NSPRIV) +/** + * @brief Enable privileged mode for nsecure items. + * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void) +{ + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); +} + +/** + * @brief Disable privileged mode for nsecure items. + * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void) +{ + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); +} + +/** + * @brief Check if privileged mode for nsecure items is enabled. + * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void) +{ + return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL); +} +#else +/** + * @brief Enable privileged mode for nsecure items. + * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void) +{ + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV); +} + +/** + * @brief Disable privileged mode for nsecure items. + * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void) +{ + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV); +} + +/** + * @brief Check if privileged mode for nsecure items is enabled. + * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void) +{ + return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV) == PWR_PRIVCFGR_PRIV) ? 1UL : 0UL); +} +#endif /* RCC_PRIVCFGR_NSPRIV */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable privileged mode for secure items. + * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void) +{ + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); +} + +/** + * @brief Disable privileged mode for secure items. + * @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void) +{ + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined (PWR_PRIVCFGR_SPRIV) +/** + * @brief Check if privileged mode for secure items is enabled. + * @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void) +{ + return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL); +} +#endif /* PWR_PRIVCFGR_SPRIV */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure secure attribute mode. + * @note This API can be executed only by CPU in secure mode. + * @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP6SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP7SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP8SEC LL_PWR_ConfigSecure\n + * SECCFGR RETSEC LL_PWR_ConfigSecure\n + * SECCFGR LPMSEC LL_PWR_ConfigSecure\n + * SECCFGR VDMSEC LL_PWR_ConfigSecure\n + * SECCFGR VBSEC LL_PWR_ConfigSecure\n + * SECCFGR APCSEC LL_PWR_ConfigSecure + * @param SecureConfig This parameter can be the full combination + * of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC + * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC + * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC + * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC + * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC + * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC + * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC + * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC + * @arg @ref LL_PWR_RET_NSEC or LL_PWR_RET_SEC + * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC + * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC + * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC + * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC + * @retval None. + */ +__STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig) +{ + WRITE_REG(PWR->SECCFGR, SecureConfig); +} + +/** + * @brief Get secure attribute configuration. + * @note This API can be executed only by CPU in secure mode. + * @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n + * SECCFGR RETSEC LL_PWR_ConfigSecure\n + * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n + * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n + * SECCFGR VBSEC LL_PWR_GetConfigSecure\n + * SECCFGR APCSEC LL_PWR_GetConfigSecure + * @retval Returned value is the combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC + * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC + * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC + * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC + * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC + * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC + * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC + * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC + * @arg @ref LL_PWR_RET_NSEC or LL_PWR_RET_SEC + * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC + * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC + * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC + * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC + */ +__STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void) +{ + return (READ_REG(PWR->SECCFGR)); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* defined (USE_FULL_LL_DRIVER) */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32H5xx_LL_PWR_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h new file mode 100644 index 00000000..9e28cf8e --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h @@ -0,0 +1,7029 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H5xx_LL_RCC_H +#define __STM32H5xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Constants RCC Private Constants + * @{ + */ +/* Defines used for security configuration extension */ +#if defined(RCC_CR_PLL3ON) +#define RCC_SECURE_MASK 0x3BFFU +#else +#define RCC_SECURE_MASK 0x39FFU +#endif /* RCC_CR_PLL3ON */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if !defined(UNUSED) +#define UNUSED(x) ((void)(x)) +#endif /* !UNUSED */ + +/* 32 24 16 8 0 + -------------------------------------------------------- + | Mask | ClkSource | Bit | Register | + | | Config | Position | Offset | + --------------------------------------------------------*/ + +/* Clock source register offset */ +#define CCIPR1_OFFSET 0x00UL +#define CCIPR2_OFFSET 0x04UL +#define CCIPR3_OFFSET 0x08UL +#define CCIPR4_OFFSET 0x0CUL +#define CCIPR5_OFFSET 0x10UL + +#define LL_RCC_REG_SHIFT 0U +#define LL_RCC_POS_SHIFT 8U +#define LL_RCC_CONFIG_SHIFT 16U +#define LL_RCC_MASK_SHIFT 24U + +#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL) + +#define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) &\ + 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) + +#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) &\ + 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) + +#define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL) + +#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \ + (( __POS__ ) << LL_RCC_POS_SHIFT) | \ + (( __REG__ ) << LL_RCC_REG_SHIFT) | \ + (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT))) + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ + uint32_t PCLK3_Frequency; /*!< PCLK3 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @brief PLL Clocks Frequency Structure + */ +typedef struct +{ + uint32_t PLL_P_Frequency; + uint32_t PLL_Q_Frequency; + uint32_t PLL_R_Frequency; +} LL_PLL_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (CSI_VALUE) +#define CSI_VALUE 4000000U /*!< Value of the CSI oscillator in Hz */ +#endif /* CSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ + +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/** + * @} + */ +#if defined(PWR_USBSCR_OTGHSEN) +#define OTGHS_CLK48_VALUE 48000000U /*!< Value of the OTGHS_CLK48 in Hz */ +#endif /* PWR_USBSCR_OTGHSEN */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider + * @{ + */ +#define LL_RCC_HSI_DIV_1 0x00000000U /*!< HSI_DIV1 clock activation */ +#define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 /*!< HSI_DIV2 clock activation */ +#define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 /*!< HSI_DIV4 clock activation */ +#define LL_RCC_HSI_DIV_8 RCC_CR_HSIDIV /*!< HSI_DIV8 clock activation */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#if !defined(STM32H5E5xx) || !defined(STM32H5E4xx) || !defined(STM32H5F5xx) || !defined(STM32H5F4xx) +#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ +#endif /* !defined(STM32H5E5xx) || !defined(STM32H5E4xx) || !defined(STM32H5F5xx) || !defined(STM32H5F4xx) */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U /*!< HSI oscillator selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR1_SW_0 /*!< CSI oscillator selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE oscillator selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL1 (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL1 selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR1_SWS_0 /*!< CSI oscillator used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE oscillator used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1 used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSEEXT EXTERNAL HSE clock Type + * @{ + */ +#define LL_RCC_HSE_ANALOG_TYPE 0U /*!< ANALOG clock used as HSE external clock source */ +#define LL_RCC_HSE_DIGITAL_TYPE RCC_CR_HSEEXT /*!< DIGITAL clock used as HSE external clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEEXT EXTERNAL LSE clock Type + * @{ + */ +#if !defined(STM32H5E5xx) || !defined(STM32H5E4xx) || !defined(STM32H5F5xx) || !defined(STM32H5F4xx) +#define LL_RCC_LSE_ANALOG_TYPE 0U /*!< ANALOG clock used as LSE external clock source */ +#endif /* !defined(STM32H5E5xx) || !defined(STM32H5E4xx) || !defined(STM32H5F5xx) || !defined(STM32H5F4xx) */ +#define LL_RCC_LSE_DIGITAL_TYPE RCC_BDCR_LSEEXT /*!< DIGITAL clock used as LSE external clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection + * @{ + */ +#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */ +#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 (0x00000000U) /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_DIV_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_DIV_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB3_DIV APB high-speed prescaler (APB3) + * @{ + */ +#define LL_RCC_APB3_DIV_1 0x00000000U /*!< HCLK not divided */ +#define LL_RCC_APB3_DIV_2 RCC_CFGR2_PPRE3_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB3_DIV_4 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB3_DIV_8 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB3_DIV_16 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_1 | RCC_CFGR2_PPRE3_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_AHB1_PERIPH AHB1 peripherals clock branch disable + * @{ + */ +#define LL_RCC_AHB1_PERIPH_DIS RCC_CFGR2_AHB1DIS /*!< Clock Branch disable for all AHB1 peripherals */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_AHB2_PERIPH AHB2 peripherals clock branch disable + * @{ + */ +#define LL_RCC_AHB2_PERIPH_DIS RCC_CFGR2_AHB2DIS /*!< Clock Branch disable for all AHB2 peripherals */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_AHB4_PERIPH AHB4 peripherals clock branch disable + * @{ + */ +#define LL_RCC_AHB4_PERIPH_DIS RCC_CFGR2_AHB4DIS /*!< Clock Branch disable for all AHB4 peripherals */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_PERIPH APB1 peripherals clock branch disable + * @{ + */ +#define LL_RCC_APB1_PERIPH_DIS RCC_CFGR2_APB1DIS /*!< Clock Branch disable for all APB1 peripherals */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_PERIPH APB2 peripherals clock branch disable + * @{ + */ +#define LL_RCC_APB2_PERIPH_DIS RCC_CFGR2_APB2DIS /*!< Clock Branch disable for all APB2 peripherals */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB3_PERIPH APB3 peripherals clock branch disable + * @{ + */ +#define LL_RCC_APB3_PERIPH_DIS RCC_CFGR2_APB3DIS /*!< Clock Branch disable for all APB3 peripherals */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection + * @{ + */ +#define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0x00000000U /*!< HCLKDIV8 clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR4_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR4_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup from stop and CSS backup clock selection + * @{ + */ +#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock after wake-up from STOP */ +#define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI RCC_CFGR1_STOPWUCK /*!< CSI selection as system clock after wake-up from STOP */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE Kernel wakeup from stop clock source + * @{ + */ +#define LL_RCC_KERWAKEUP_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as kernel clock after wake-up from STOP */ +#define LL_RCC_KERWAKEUP_CLKSOURCE_CSI RCC_CFGR1_STOPKERWUCK /*!< CSI selection as kernel clock after wake-up from STOP */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler + * @{ + */ +#define LL_RCC_RTC_HSE_NOCLOCK (0x00000000U) +#define LL_RCC_RTC_HSE_DIV_2 (0x00000200U) +#define LL_RCC_RTC_HSE_DIV_3 (0x00000300U) +#define LL_RCC_RTC_HSE_DIV_4 (0x00000400U) +#define LL_RCC_RTC_HSE_DIV_5 (0x00000500U) +#define LL_RCC_RTC_HSE_DIV_6 (0x00000600U) +#define LL_RCC_RTC_HSE_DIV_7 (0x00000700U) +#define LL_RCC_RTC_HSE_DIV_8 (0x00000800U) +#define LL_RCC_RTC_HSE_DIV_9 (0x00000900U) +#define LL_RCC_RTC_HSE_DIV_10 (0x00000A00U) +#define LL_RCC_RTC_HSE_DIV_11 (0x00000B00U) +#define LL_RCC_RTC_HSE_DIV_12 (0x00000C00U) +#define LL_RCC_RTC_HSE_DIV_13 (0x00000D00U) +#define LL_RCC_RTC_HSE_DIV_14 (0x00000E00U) +#define LL_RCC_RTC_HSE_DIV_15 (0x00000F00U) +#define LL_RCC_RTC_HSE_DIV_16 (0x00001000U) +#define LL_RCC_RTC_HSE_DIV_17 (0x00001100U) +#define LL_RCC_RTC_HSE_DIV_18 (0x00001200U) +#define LL_RCC_RTC_HSE_DIV_19 (0x00001300U) +#define LL_RCC_RTC_HSE_DIV_20 (0x00001400U) +#define LL_RCC_RTC_HSE_DIV_21 (0x00001500U) +#define LL_RCC_RTC_HSE_DIV_22 (0x00001600U) +#define LL_RCC_RTC_HSE_DIV_23 (0x00001700U) +#define LL_RCC_RTC_HSE_DIV_24 (0x00001800U) +#define LL_RCC_RTC_HSE_DIV_25 (0x00001900U) +#define LL_RCC_RTC_HSE_DIV_26 (0x00001A00U) +#define LL_RCC_RTC_HSE_DIV_27 (0x00001B00U) +#define LL_RCC_RTC_HSE_DIV_28 (0x00001C00U) +#define LL_RCC_RTC_HSE_DIV_29 (0x00001D00U) +#define LL_RCC_RTC_HSE_DIV_30 (0x00001E00U) +#define LL_RCC_RTC_HSE_DIV_31 (0x00001F00U) +#define LL_RCC_RTC_HSE_DIV_32 (0x00002000U) +#define LL_RCC_RTC_HSE_DIV_33 (0x00002100U) +#define LL_RCC_RTC_HSE_DIV_34 (0x00002200U) +#define LL_RCC_RTC_HSE_DIV_35 (0x00002300U) +#define LL_RCC_RTC_HSE_DIV_36 (0x00002400U) +#define LL_RCC_RTC_HSE_DIV_37 (0x00002500U) +#define LL_RCC_RTC_HSE_DIV_38 (0x00002600U) +#define LL_RCC_RTC_HSE_DIV_39 (0x00002700U) +#define LL_RCC_RTC_HSE_DIV_40 (0x00002800U) +#define LL_RCC_RTC_HSE_DIV_41 (0x00002900U) +#define LL_RCC_RTC_HSE_DIV_42 (0x00002A00U) +#define LL_RCC_RTC_HSE_DIV_43 (0x00002B00U) +#define LL_RCC_RTC_HSE_DIV_44 (0x00002C00U) +#define LL_RCC_RTC_HSE_DIV_45 (0x00002D00U) +#define LL_RCC_RTC_HSE_DIV_46 (0x00002E00U) +#define LL_RCC_RTC_HSE_DIV_47 (0x00002F00U) +#define LL_RCC_RTC_HSE_DIV_48 (0x00003000U) +#define LL_RCC_RTC_HSE_DIV_49 (0x00003100U) +#define LL_RCC_RTC_HSE_DIV_50 (0x00003200U) +#define LL_RCC_RTC_HSE_DIV_51 (0x00003300U) +#define LL_RCC_RTC_HSE_DIV_52 (0x00003400U) +#define LL_RCC_RTC_HSE_DIV_53 (0x00003500U) +#define LL_RCC_RTC_HSE_DIV_54 (0x00003600U) +#define LL_RCC_RTC_HSE_DIV_55 (0x00003700U) +#define LL_RCC_RTC_HSE_DIV_56 (0x00003800U) +#define LL_RCC_RTC_HSE_DIV_57 (0x00003900U) +#define LL_RCC_RTC_HSE_DIV_58 (0x00003A00U) +#define LL_RCC_RTC_HSE_DIV_59 (0x00003B00U) +#define LL_RCC_RTC_HSE_DIV_60 (0x00003C00U) +#define LL_RCC_RTC_HSE_DIV_61 (0x00003D00U) +#define LL_RCC_RTC_HSE_DIV_62 (0x00003E00U) +#define LL_RCC_RTC_HSE_DIV_63 (0x00003F00U) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection + * @{ + */ +#define LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U) +#define LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR1_TIMPRE) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOxSOURCE MCO SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | 0x00000000U) +#define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_0) +#define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_1) +#define LL_RCC_MCO1SOURCE_PLL1Q (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) |\ + RCC_CFGR1_MCO1SEL_1|RCC_CFGR1_MCO1SEL_0) +#define LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_2) +#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | 0x00000000U) +#define LL_RCC_MCO2SOURCE_PLL2P (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_0) +#define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_1) +#define LL_RCC_MCO2SOURCE_PLL1P (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) |\ + RCC_CFGR1_MCO2SEL_1|RCC_CFGR1_MCO2SEL_0) +#define LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_2) +#define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) |\ + RCC_CFGR1_MCO2SEL_2|RCC_CFGR1_MCO2SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_0) +#define LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\ + RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\ + RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\ + RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\ + RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\ + RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\ + RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\ + RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\ + RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\ + RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\ + RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE) +#define LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_0) +#define LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\ + RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\ + RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\ + RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\ + RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\ + RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\ + RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\ + RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\ + RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\ + RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\ + RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE) +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +#if defined (RCC_CCIPR4_OTGPDCTRL) +/** @defgroup RCC_LL_EC_OTGPD_SUSPEND OTG PHY Suspend Power State + * @{ + */ +#define LL_RCC_OTGPD_SUSPEND_POWERDOWN ((uint32_t)0x00000000U) /*!< Power down the PHY state machine, bias, and PLL in SUSPEND mode. */ +#define LL_RCC_OTGPD_SUSPEND_POWERON RCC_CCIPR4_OTGPDCTRL /*!< Keep the PHY powered in SUSPEND mode (default after reset). */ +/** + * @} + */ +#endif /* RCC_CCIPR4_OTGPDCTRL */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by RTCPRE used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, 0x00000000U) /*!< PCLK2 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_0) /*!< PLL2 Q clock used as USART1 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_USART1_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_1) /*!< PLL3 Q clock used as USART1 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_USART1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_1 | RCC_CCIPR1_USART1SEL_0) /*!< HSI clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_2) /*!< CSI clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_2 | RCC_CCIPR1_USART1SEL_0) /*!< LSE clock used as USART1 clock source */ + +#define LL_RCC_USART2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_0) /*!< PLL2 Q clock used as USART2 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_USART2_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_1) /*!< PLL3 Q clock used as USART2 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_USART2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_1 | RCC_CCIPR1_USART2SEL_0) /*!< HSI clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_2) /*!< CSI clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_2 | RCC_CCIPR1_USART2SEL_0) /*!< LSE clock used as USART2 clock source */ + +#define LL_RCC_USART3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_0) /*!< PLL2 Q clock used as USART3 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_USART3_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_1) /*!< PLL3 Q clock used as USART3 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_USART3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_1 | RCC_CCIPR1_USART3SEL_0) /*!< HSI clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_2) /*!< CSI clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_2 | RCC_CCIPR1_USART3SEL_0) /*!< LSE clock used as USART3 clock source */ + +#if defined(USART6) +#define LL_RCC_USART6_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_0) /*!< PLL2 Q clock used as USART6 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_USART6_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_1) /*!< PLL3 Q clock used as USART6 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_USART6_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_1 | RCC_CCIPR1_USART6SEL_0) /*!< HSI clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_2) /*!< CSI clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_2 | RCC_CCIPR1_USART6SEL_0) /*!< LSE clock used as USART6 clock source */ +#endif /* USART6 */ + +#if defined(USART10) +#define LL_RCC_USART10_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART10 clock source */ +#define LL_RCC_USART10_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_0) /*!< PLL2 Q clock used as USART10 clock source */ +#define LL_RCC_USART10_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_1) /*!< PLL3 Q clock used as USART10 clock source */ +#define LL_RCC_USART10_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_1 | RCC_CCIPR1_USART10SEL_0) /*!< HSI clock used as USART10 clock source */ +#define LL_RCC_USART10_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_2) /*!< CSI clock used as USART10 clock source */ +#define LL_RCC_USART10_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_2 | RCC_CCIPR1_USART10SEL_0) /*!< LSE clock used as USART10 clock source */ +#endif /* USART10 */ + +#if defined(USART11) +#define LL_RCC_USART11_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART11 clock source */ +#define LL_RCC_USART11_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_0) /*!< PLL2 Q clock used as USART11 clock source */ +#define LL_RCC_USART11_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_1) /*!< PLL3 Q clock used as USART11 clock source */ +#define LL_RCC_USART11_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_1 | RCC_CCIPR2_USART11SEL_0) /*!< HSI clock used as USART11 clock source */ +#define LL_RCC_USART11_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_2) /*!< CSI clock used as USART11 clock source */ +#define LL_RCC_USART11_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_2 | RCC_CCIPR2_USART11SEL_0) /*!< LSE clock used as USART11 clock source */ +#endif /* USART11 */ +/** + * @} + */ + +#if defined(UART4) +/** @defgroup RCC_LL_EC_UART_CLKSOURCE Peripheral UARTx clock source selection + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_0) /*!< PLL2 Q clock used as UART4 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_UART4_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_1) /*!< PLL3 Q clock used as UART4 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_UART4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_1 | RCC_CCIPR1_UART4SEL_0) /*!< HSI clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_2) /*!< CSI clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_2 | RCC_CCIPR1_UART4SEL_0) /*!< LSE clock used as UART4 clock source */ + +#define LL_RCC_UART5_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_0) /*!< PLL2 Q clock used as UART5 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_UART5_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_1) /*!< PLL3 Q clock used as UART5 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_UART5_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_1 | RCC_CCIPR1_UART5SEL_0) /*!< HSI clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_2) /*!< CSI clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_2 | RCC_CCIPR1_UART5SEL_0) /*!< LSE clock used as UART5 clock source */ + +#define LL_RCC_UART7_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART7 clock source */ +#define LL_RCC_UART7_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_0) /*!< PLL2 Q clock used as UART7 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_UART7_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_1) /*!< PLL3 Q clock used as UART7 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_UART7_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_1 | RCC_CCIPR1_UART7SEL_0) /*!< HSI clock used as UART7 clock source */ +#define LL_RCC_UART7_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_2) /*!< CSI clock used as UART7 clock source */ +#define LL_RCC_UART7_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_2 | RCC_CCIPR1_UART7SEL_0) /*!< LSE clock used as UART7 clock source */ + +#define LL_RCC_UART8_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART8 clock source */ +#define LL_RCC_UART8_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_0) /*!< PLL2 Q clock used as UART8 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_UART8_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_1) /*!< PLL3 Q clock used as UART8 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_UART8_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_1 | RCC_CCIPR1_UART8SEL_0) /*!< HSI clock used as UART8 clock source */ +#define LL_RCC_UART8_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_2) /*!< CSI clock used as UART8 clock source */ +#define LL_RCC_UART8_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_2 | RCC_CCIPR1_UART8SEL_0) /*!< LSE clock used as UART8 clock source */ + +#define LL_RCC_UART9_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART9 clock source */ +#define LL_RCC_UART9_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_0) /*!< PLL2 Q clock used as UART9 clock source */ +#define LL_RCC_UART9_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_1) /*!< PLL3 Q clock used as UART9 clock source */ +#define LL_RCC_UART9_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_1 | RCC_CCIPR1_UART9SEL_0) /*!< HSI clock used as UART9 clock source */ +#define LL_RCC_UART9_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_2) /*!< CSI clock used as UART9 clock source */ +#define LL_RCC_UART9_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_2 | RCC_CCIPR1_UART9SEL_0) /*!< LSE clock used as UART9 clock source */ + +#define LL_RCC_UART12_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART12 clock source */ +#define LL_RCC_UART12_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_0) /*!< PLL2 Q clock used as UART12 clock source */ +#define LL_RCC_UART12_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_1) /*!< PLL3 Q clock used as UART12 clock source */ +#define LL_RCC_UART12_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_1 | RCC_CCIPR2_UART12SEL_0) /*!< HSI clock used as UART12 clock source */ +#define LL_RCC_UART12_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_2) /*!< CSI clock used as UART12 clock source */ +#define LL_RCC_UART12_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_2 | RCC_CCIPR2_UART12SEL_0) /*!< LSE clock used as UART12 clock source */ +/** + * @} + */ +#endif /* UART4 */ + +/** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE_PCLK3 0x00000000U /*!< PCLK3 clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q RCC_CCIPR3_LPUART1SEL_0 /*!< PLL2Q clock used as LPUART1 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q RCC_CCIPR3_LPUART1SEL_1 /*!< PLL3Q clock used as LPUART1 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) /*!< HSI clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_CSI RCC_CCIPR3_LPUART1SEL_2 /*!< CSI clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_2) /*!< LSE clock used as LPUART1 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_I2C1_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, RCC_CCIPR4_I2C1SEL_0) /*!< PLL3 R clock used as I2C1 clock source */ +#else +#define LL_RCC_I2C1_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, RCC_CCIPR4_I2C1SEL_0) /*!< PLL2 R clock used as I2C1 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_I2C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, RCC_CCIPR4_I2C1SEL_1) /*!< HSI clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, RCC_CCIPR4_I2C1SEL) /*!< CSI clock used as I2C1 clock source */ + +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_I2C2_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, RCC_CCIPR4_I2C2SEL_0) /*!< PLL3 R clock used as I2C2 clock source */ +#else +#define LL_RCC_I2C2_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, RCC_CCIPR4_I2C2SEL_0) /*!< PLL2 R clock used as I2C2 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_I2C2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, RCC_CCIPR4_I2C2SEL_1) /*!< HSI clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, RCC_CCIPR4_I2C2SEL) /*!< CSI clock used as I2C2 clock source */ + +#if defined(I2C3) +#define LL_RCC_I2C3_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as I2C3 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_I2C3_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, RCC_CCIPR4_I2C3SEL_0) /*!< PLL3 R clock used as I2C3 clock source */ +#else +#define LL_RCC_I2C3_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, RCC_CCIPR4_I2C3SEL_0) /*!< PLL2 R clock used as I2C3 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_I2C3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, RCC_CCIPR4_I2C3SEL_1) /*!< HSI clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, RCC_CCIPR4_I2C3SEL) /*!< CSI clock used as I2C3 clock source */ +#endif /* I2C3 */ + +#if defined(I2C4) +#define LL_RCC_I2C4_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, RCC_CCIPR4_I2C4SEL_0) /*!< PLL3 R clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, RCC_CCIPR4_I2C4SEL_1) /*!< HSI clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, RCC_CCIPR4_I2C4SEL) /*!< CSI clock used as I2C4 clock source */ +#endif /* I2C4 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I3C_CLKSOURCE Peripheral I3Cx clock source selection + * @{ + */ +#define LL_RCC_I3C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as I3C1 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_I3C1_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR4_I3C1SEL_0) /*!< PLL3 R clock used as I3C1 clock source */ +#else +#define LL_RCC_I3C1_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR4_I3C1SEL_0) /*!< PLL2 R clock used as I3C1 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_I3C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR4_I3C1SEL_1) /*!< HSI clock used as I3C1 clock source */ +#define LL_RCC_I3C1_CLKSOURCE_NONE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR4_I3C1SEL) /*!< NONE clock used as I3C1 clock source */ + +#if defined(I3C2) +#define LL_RCC_I3C2_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as I3C2 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_I3C2_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL_0) /*!< PLL3 R clock used as I3C2 clock source */ +#else +#define LL_RCC_I3C2_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL_0) /*!< PLL2 R clock used as I3C2 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_I3C2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL_1) /*!< HSI clock used as I3C2 clock source */ +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) +#define LL_RCC_I3C2_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL_0 |RCC_CCIPR4_I3C2SEL_1) /*!< CSI clock used as I3C2 clock source */ +#else +#define LL_RCC_I3C2_CLKSOURCE_NONE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL) /*!< NONE clock used as I3C2 clock source */ +#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */ +#endif /* I3C2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPIx clock source selection + * @{ + */ +#define LL_RCC_SPI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SPI1 clock source */ +#define LL_RCC_SPI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_0) /*!< PLL2 P clock used as SPI1 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_SPI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_1) /*!< PLL3 P clock used as SPI1 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_SPI1_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_1 | RCC_CCIPR3_SPI1SEL_0) /*!< PIN clock used as SPI1 clock source */ +#define LL_RCC_SPI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_2) /*!< CLKP clock used as SPI1 clock source */ + +#define LL_RCC_SPI2_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SPI2 clock source */ +#define LL_RCC_SPI2_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, RCC_CCIPR3_SPI2SEL_0) /*!< PLL2 P clock used as SPI2 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_SPI2_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, RCC_CCIPR3_SPI2SEL_1) /*!< PLL3 P clock used as SPI2 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_SPI2_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, RCC_CCIPR3_SPI2SEL_1 | RCC_CCIPR3_SPI2SEL_0) /*!< PIN clock used as SPI2 clock source */ +#define LL_RCC_SPI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, RCC_CCIPR3_SPI2SEL_2) /*!< CLKP clock used as SPI2 clock source */ + +#define LL_RCC_SPI3_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SPI3 clock source */ +#define LL_RCC_SPI3_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, RCC_CCIPR3_SPI3SEL_0) /*!< PLL2 P clock used as SPI3 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_SPI3_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, RCC_CCIPR3_SPI3SEL_1) /*!< PLL3 P clock used as SPI3 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_SPI3_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, RCC_CCIPR3_SPI3SEL_1 | RCC_CCIPR3_SPI3SEL_0) /*!< PIN clock used as SPI3 clock source */ +#define LL_RCC_SPI3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, RCC_CCIPR3_SPI3SEL_2) /*!< CLKP clock used as SPI3 clock source */ + +#if defined(SPI4) +#define LL_RCC_SPI4_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, 0x00000000U) /*!< PCLK2 clock used as SPI4 clock source */ +#define LL_RCC_SPI4_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_0) /*!< PLL2 Q clock used as SPI4 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_SPI4_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_1) /*!< PLL3 Q clock used as SPI4 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_SPI4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_1 | RCC_CCIPR3_SPI4SEL_0) /*!< HSI clock used as SPI4 clock source */ +#define LL_RCC_SPI4_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_2) /*!< CSI clock used as SPI4 clock source */ +#define LL_RCC_SPI4_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_2 | RCC_CCIPR3_SPI4SEL_0) /*!< HSE clock used as SPI4 clock source */ +#endif /* SPI4 */ + +#if defined(SPI5) +#define LL_RCC_SPI5_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, 0x00000000U) /*!< PCLK2 clock used as SPI5 clock source */ +#define LL_RCC_SPI5_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_0) /*!< PLL2 Q clock used as SPI5 clock source */ +#define LL_RCC_SPI5_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_1) /*!< PLL3 Q clock used as SPI5 clock source */ +#define LL_RCC_SPI5_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_1 | RCC_CCIPR3_SPI5SEL_0) /*!< HSI clock used as SPI5 clock source */ +#define LL_RCC_SPI5_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_2) /*!< CSI clock used as SPI5 clock source */ +#define LL_RCC_SPI5_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_2 | RCC_CCIPR3_SPI5SEL_0) /*!< HSE clock used as SPI5 clock source */ +#endif /* SPI5 */ + +#if defined(SPI6) +#define LL_RCC_SPI6_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, 0x00000000U) /*!< PCLK2 clock used as SPI6 clock source */ +#define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_0) /*!< PLL2 Q clock used as SPI6 clock source */ +#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_1) /*!< PLL3 Q clock used as SPI6 clock source */ +#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_1 | RCC_CCIPR3_SPI6SEL_0) /*!< HSI clock used as SPI6 clock source */ +#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_2) /*!< CSI clock used as SPI6 clock source */ +#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_2 | RCC_CCIPR3_SPI6SEL_0) /*!< HSE clock used as SPI6 clock source */ +#endif /* SPI6 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIMx clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_0) /*!< PLL2 P clock used as LPTIM1 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_1) /*!< PLL3 R clock used as LPTIM1 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_0 | RCC_CCIPR2_LPTIM1SEL_1) /*!< LSE clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_2) /*!< LSI clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_0 | RCC_CCIPR2_LPTIM1SEL_2) /*!< CLKP clock used as LPTIM1 clock source */ + +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as LPTIM2 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_0) /*!< PLL2 P clock used as LPTIM2 clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_1) /*!< PLL3 R clock used as LPTIM2 clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_0 | RCC_CCIPR2_LPTIM2SEL_1) /*!< LSE clock used as LPTIM2 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_2) /*!< LSI clock used as LPTIM2 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_0 | RCC_CCIPR2_LPTIM2SEL_2) /*!< CLKP clock used as LPTIM2 clock source */ + +#if defined(LPTIM3) +#define LL_RCC_LPTIM3_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM3 clock source */ +#define LL_RCC_LPTIM3_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_0) /*!< PLL2 P clock used as LPTIM3 clock source */ +#define LL_RCC_LPTIM3_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_1) /*!< PLL3 R clock used as LPTIM3 clock source */ +#define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_0 | RCC_CCIPR2_LPTIM3SEL_1) /*!< LSE clock used as LPTIM3 clock source */ +#define LL_RCC_LPTIM3_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_2) /*!< LSI clock used as LPTIM3 clock source */ +#define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_0 | RCC_CCIPR2_LPTIM3SEL_2) /*!< CLKP clock used as LPTIM3 clock source */ +#endif /* LPTIM3 */ + +#if defined(LPTIM4) +#define LL_RCC_LPTIM4_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM4 clock source */ +#define LL_RCC_LPTIM4_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_0) /*!< PLL2 P clock used as LPTIM4 clock source */ +#define LL_RCC_LPTIM4_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_1) /*!< PLL3 R clock used as LPTIM4 clock source */ +#define LL_RCC_LPTIM4_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_0 | RCC_CCIPR2_LPTIM4SEL_1) /*!< LSE clock used as LPTIM4 clock source */ +#define LL_RCC_LPTIM4_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_2) /*!< LSI clock used as LPTIM4 clock source */ +#define LL_RCC_LPTIM4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_0 | RCC_CCIPR2_LPTIM4SEL_2) /*!< CLKP clock used as LPTIM4 clock source */ +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +#define LL_RCC_LPTIM5_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM5 clock source */ +#define LL_RCC_LPTIM5_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_0) /*!< PLL2 P clock used as LPTIM5 clock source */ +#define LL_RCC_LPTIM5_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_1) /*!< PLL3 R clock used as LPTIM5 clock source */ +#define LL_RCC_LPTIM5_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_0 | RCC_CCIPR2_LPTIM5SEL_1) /*!< LSE clock used as LPTIM5 clock source */ +#define LL_RCC_LPTIM5_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_2) /*!< LSI clock used as LPTIM5 clock source */ +#define LL_RCC_LPTIM5_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_0 | RCC_CCIPR2_LPTIM5SEL_2) /*!< CLKP clock used as LPTIM5 clock source */ +#endif /* LPTIM5 */ + +#if defined(LPTIM6) +#define LL_RCC_LPTIM6_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM6 clock source */ +#define LL_RCC_LPTIM6_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_0) /*!< PLL2 P clock used as LPTIM6 clock source */ +#define LL_RCC_LPTIM6_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_1) /*!< PLL3 R clock used as LPTIM6 clock source */ +#define LL_RCC_LPTIM6_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_0 | RCC_CCIPR2_LPTIM6SEL_1) /*!< LSE clock used as LPTIM6 clock source */ +#define LL_RCC_LPTIM6_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_2) /*!< LSI clock used as LPTIM6 clock source */ +#define LL_RCC_LPTIM6_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_0 | RCC_CCIPR2_LPTIM6SEL_2) /*!< CLKP clock used as LPTIM6 clock source */ +#endif /* LPTIM6 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN kernel clock source selection + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U /*!< HSE clock used as FDCAN kernel clock source */ +#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q RCC_CCIPR5_FDCANSEL_0 /*!< PLL1 Q clock used as FDCAN kernel clock source */ +#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q RCC_CCIPR5_FDCANSEL_1 /*!< PLL2 Q clock used as FDCAN kernel clock source */ +#define LL_RCC_FDCAN_CLKSOURCE_NONE RCC_CCIPR5_FDCANSEL /*!< NO clock used as FDCAN kernel clock source */ +/** + * @} + */ + +#if defined(SAI1) +/** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAIx clock source selection + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, RCC_CCIPR5_SAI1SEL_0) /*!< PLL2 P clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, RCC_CCIPR5_SAI1SEL_1) /*!< PLL3 P clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, RCC_CCIPR5_SAI1SEL_1 | RCC_CCIPR5_SAI1SEL_0) /*!< External input clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, RCC_CCIPR5_SAI1SEL_2) /*!< CLKP clock used as SAI1 clock source */ + +#define LL_RCC_SAI2_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, RCC_CCIPR5_SAI2SEL_0) /*!< PLL2 P clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, RCC_CCIPR5_SAI2SEL_1) /*!< PLL3 P clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, RCC_CCIPR5_SAI2SEL_1 | RCC_CCIPR5_SAI2SEL_0) /*!< External input clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, RCC_CCIPR5_SAI2SEL_2) /*!< CLKP clock used as SAI2 clock source */ +/** + * @} + */ +#endif /* SAI1 */ + +#if defined(SDMMC1) +/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMCx kernel clock source selection + * @{ + */ +#define LL_RCC_SDMMC1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC1SEL, RCC_CCIPR4_SDMMC1SEL_Pos, 0x00000000U) /*!< PLL1 Q used as SDMMC1 clock source */ +#define LL_RCC_SDMMC1_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC1SEL, RCC_CCIPR4_SDMMC1SEL_Pos, RCC_CCIPR4_SDMMC1SEL) /*!< PLL2 R used as SDMMC1 clock source */ +#if defined(SDMMC2) +#define LL_RCC_SDMMC2_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC2SEL, RCC_CCIPR4_SDMMC2SEL_Pos, 0x00000000U) /*!< PLL1 Q used as SDMMC2 clock source */ +#define LL_RCC_SDMMC2_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC2SEL, RCC_CCIPR4_SDMMC2SEL_Pos, RCC_CCIPR4_SDMMC2SEL) /*!< PLL2 R used as SDMMC2 clock source */ +#endif /*SDMMC2*/ +/** + * @} + */ +#endif /* SDMMC1 */ + +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */ +#define LL_RCC_RNG_CLKSOURCE_PLL1Q RCC_CCIPR5_RNGSEL_0 /*!< PLL1 Q clock used as RNG clock source */ +#define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR5_RNGSEL_1 /*!< LSE clock used as RNG clock source */ +#define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR5_RNGSEL /*!< LSI clock used as RNG clock source */ +/** + * @} + */ + +#if defined(USB_DRD_FS) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /*!< No clock used as USB clock source */ +#define LL_RCC_USB_CLKSOURCE_PLL1Q RCC_CCIPR4_USBSEL_0 /*!< PLL1 Q clock used as USB clock source */ +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_USB_CLKSOURCE_PLL3Q RCC_CCIPR4_USBSEL_1 /*!< PLL3 Q clock used as USB clock source */ +#else +#define LL_RCC_USB_CLKSOURCE_PLL2Q RCC_CCIPR4_USBSEL_1 /*!< PLL2 Q clock used as USB clock source */ +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CCIPR4_USBSEL /*!< HSI48 clock used as USB clock source */ +/** + * @} + */ +#endif /* USB_DRD_FS */ + +/** @defgroup RCC_LL_EC_ADCDAC_CLKSOURCE Peripheral ADCDAC clock source selection + * @{ + */ +#define LL_RCC_ADCDAC_CLKSOURCE_HCLK 0x00000000U /*!< AHB clock used as ADCDAC clock source */ +#define LL_RCC_ADCDAC_CLKSOURCE_SYSCLK RCC_CCIPR5_ADCDACSEL_0 /*!< SYSCLK clock used as ADCDAC clock source */ +#define LL_RCC_ADCDAC_CLKSOURCE_PLL2R RCC_CCIPR5_ADCDACSEL_1 /*!< PLL2 R clock used as ADCDAC clock source */ +#define LL_RCC_ADCDAC_CLKSOURCE_HSE (RCC_CCIPR5_ADCDACSEL_0 | RCC_CCIPR5_ADCDACSEL_1) /*!< HSE clock used as ADCDAC clock source */ +#define LL_RCC_ADCDAC_CLKSOURCE_HSI RCC_CCIPR5_ADCDACSEL_2 /*!< HSI clock used as ADCDAC clock source */ +#define LL_RCC_ADCDAC_CLKSOURCE_CSI (RCC_CCIPR5_ADCDACSEL_0 | RCC_CCIPR5_ADCDACSEL_2) /*!< CSI clock used as ADCDAC clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DAC_CLKSOURCE Peripheral DAC low-power clock source selection + * @{ + */ +#define LL_RCC_DAC_LP_CLKSOURCE_LSE 0x00000000U /*!< LSE clock used as DAC low-power clock */ +#define LL_RCC_DAC_LP_CLKSOURCE_LSI RCC_CCIPR5_DACSEL /*!< LSI clock used as DAC low-power clock */ +/** + * @} + */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE_LSE 0x00000000U /*!< LSE clock used as CEC clock */ +#define LL_RCC_CEC_CLKSOURCE_LSI RCC_CCIPR5_CECSEL_0 /*!< LSI clock used as CEC clock */ +#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 RCC_CCIPR5_CECSEL_1 /*!< CSI clock divied by 122 used as CEC clock */ +#define LL_RCC_CEC_CLKSOURCE_NONE RCC_CCIPR5_CECSEL /*!< NO clock used as CEC clock source */ +/** + * @} + */ +#endif /* CEC */ + +#if defined(OCTOSPI1) +/** @defgroup RCC_LL_EC_OCTOSPI_CLKSOURCE Peripheral OCTOSPI kernel clock source selection + * @{ + */ +#define LL_RCC_OSPI_CLKSOURCE_HCLK 0x00000000U /*!< AHB clock used as OctoSPI kernel clock source */ +#define LL_RCC_OSPI_CLKSOURCE_PLL1Q RCC_CCIPR4_OCTOSPISEL_0 /*!< PLL1 Q clock used as OctoSPI kernel clock source */ +#define LL_RCC_OSPI_CLKSOURCE_PLL2R RCC_CCIPR4_OCTOSPISEL_1 /*!< PLL2 R clock used as OctoSPI kernel clock source */ +#define LL_RCC_OSPI_CLKSOURCE_CLKP RCC_CCIPR4_OCTOSPISEL /*!< CLKP clock used as OctoSPI clock source */ +/** + * @} + */ +#endif /* OCTOSPI1 */ + +#if defined(PLAY1) +/** @defgroup RCC_LL_EC_PLAY1_CLKSOURCE Peripheral PLAY1 clock source selection + * @{ + */ +#define LL_RCC_PLAY1_CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) +#define LL_RCC_PLAY1_CLKSOURCE_PLL2P RCC_CCIPR3_PLAY1SEL_0 +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_PLAY1_CLKSOURCE_PLL3R RCC_CCIPR3_PLAY1SEL_1 +#endif /* RCC_CR_PLL3ON */ +#define LL_RCC_PLAY1_CLKSOURCE_LSE (RCC_CCIPR3_PLAY1SEL_0 | RCC_CCIPR3_PLAY1SEL_1) +#define LL_RCC_PLAY1_CLKSOURCE_LSI RCC_CCIPR3_PLAY1SEL_2 +#define LL_RCC_PLAY1_CLKSOURCE_CLKP (RCC_CCIPR3_PLAY1SEL_0 | RCC_CCIPR3_PLAY1SEL_2) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLAY1_CLKDIVIDER Peripheral PLAY1 clock divider selection + * @{ + */ +#define LL_RCC_PLAY1_CLK_DIV_1 ((uint32_t)0x00000000U) /*!< PLAY1 not divided (default) */ +#define LL_RCC_PLAY1_CLK_DIV_2 RCC_CCIPR3_PLAY1DIV_0 /*!< PLAY1 divided by 2 */ +#define LL_RCC_PLAY1_CLK_DIV_4 RCC_CCIPR3_PLAY1DIV_1 /*!< PLAY1 divided by 4 */ +#define LL_RCC_PLAY1_CLK_DIV_8 (RCC_CCIPR3_PLAY1DIV_0 | RCC_CCIPR3_PLAY1DIV_1) /*!< PLAY1 divided by 8 */ +#define LL_RCC_PLAY1_CLK_DIV_16 RCC_CCIPR3_PLAY1DIV_2 /*!< PLAY1 divided by 16 */ +#define LL_RCC_PLAY1_CLK_DIV_32 (RCC_CCIPR3_PLAY1DIV_2 | RCC_CCIPR3_PLAY1DIV_0) /*!< PLAY1 divided by 32 */ +#define LL_RCC_PLAY1_CLK_DIV_64 (RCC_CCIPR3_PLAY1DIV_2 | RCC_CCIPR3_PLAY1DIV_1) /*!< PLAY1 divided by 64 */ +#define LL_RCC_PLAY1_CLK_DIV_128 (RCC_CCIPR3_PLAY1DIV_2 | RCC_CCIPR3_PLAY1DIV_1 | RCC_CCIPR3_PLAY1DIV_0) /*!< PLAY1 divided by 128 */ +#define LL_RCC_PLAY1_CLK_DIV_256 RCC_CCIPR3_PLAY1DIV_3 /*!< PLAY1 divided by 256 */ +#define LL_RCC_PLAY1_CLK_DIV_512 (RCC_CCIPR3_PLAY1DIV_3 | RCC_CCIPR3_PLAY1DIV_0) /*!< PLAY1 divided by 512 */ +#define LL_RCC_PLAY1_CLK_DIV_1024 (RCC_CCIPR3_PLAY1DIV_3 | RCC_CCIPR3_PLAY1DIV_1) /*!< PLAY1 divided by 1024 */ +#define LL_RCC_PLAY1_CLK_DIV_2048 (RCC_CCIPR3_PLAY1DIV_3 | RCC_CCIPR3_PLAY1DIV_1 | RCC_CCIPR3_PLAY1DIV_0) /*!< PLAY1 divided by 2048 */ +#define LL_RCC_PLAY1_CLK_DIV_4096 (RCC_CCIPR3_PLAY1DIV_3 | RCC_CCIPR3_PLAY1DIV_2) /*!< PLAY1 divided by 4096 */ +#define LL_RCC_PLAY1_CLK_DIV_8192 (RCC_CCIPR3_PLAY1DIV_3 | RCC_CCIPR3_PLAY1DIV_2 | RCC_CCIPR3_PLAY1DIV_0) /*!< PLAY1 divided by 8192 */ +#define LL_RCC_PLAY1_CLK_DIV_16384 (RCC_CCIPR3_PLAY1DIV_3 | RCC_CCIPR3_PLAY1DIV_2 | RCC_CCIPR3_PLAY1DIV_1) /*!< PLAY1 divided by 16384 */ +#define LL_RCC_PLAY1_CLK_DIV_32768 (RCC_CCIPR3_PLAY1DIV_3 | RCC_CCIPR3_PLAY1DIV_2 | RCC_CCIPR3_PLAY1DIV_1 | \ + RCC_CCIPR3_PLAY1DIV_0) /*!< PLAY1 divided by 32768 */ +/** + * @} + */ +#endif /* PLAY1 */ + +#if defined(USB_OTG_FS) +/** @defgroup RCC_LL_EC_USB_OTG_FS_CLKSOURCE Peripheral USB_OTG_FS clock source selection + * @{ + */ +#define LL_RCC_OTGFS_CLKSOURCE_HSI48 ((uint32_t)0x00000000U) +#define LL_RCC_OTGFS_CLKSOURCE_PLL1Q RCC_CCIPR4_OTGFSSEL_0 +#define LL_RCC_OTGFS_CLKSOURCE_PLL3Q RCC_CCIPR4_OTGFSSEL_1 +#if defined (PWR_USBSCR_OTGHSEN) +#define LL_RCC_OTGFS_CLKSOURCE_CLK48 (RCC_CCIPR4_OTGFSSEL_0 | RCC_CCIPR4_OTGFSSEL_1 ) +#endif /* PWR_USBSCR_OTGHSEN */ +/** + * @} + */ +#endif /* USB_OTG_FS */ + +#if defined(USB_OTG_HS) +/** @defgroup RCC_LL_EC_USB_OTG_HS_CLKSOURCE Peripheral USB_OTG_HS clock source selection + * @{ + */ +#define LL_RCC_OTGHS_CLKSOURCE_HSE ((uint32_t)0x00000000U) +#define LL_RCC_OTGHS_CLKSOURCE_PLL3Q RCC_CCIPR4_OTGHSSEL_0 +#define LL_RCC_OTGHS_CLKSOURCE_HSE_DIV2 RCC_CCIPR4_OTGHSSEL_1 +#define LL_RCC_OTGHS_CLKSOURCE_PLL1Q_DIV2 (RCC_CCIPR4_OTGHSSEL_0 | RCC_CCIPR4_OTGHSSEL_1) +/** + * @} + */ +#endif /* USB_OTG_HS */ + +#if defined(RCC_CCIPR4_OTGPHYREFCKSEL) +/** @defgroup RCC_LL_EC_OTGPHYREFCK_CLKSOURCE Peripheral OTGPHYREFCK clock source selection + * @{ + */ +#define LL_RCC_OTGPHYREFCKCLKSOURCE_16M (RCC_CCIPR4_OTGPHYREFCKSEL_0 | RCC_CCIPR4_OTGPHYREFCKSEL_1 ) +#define LL_RCC_OTGPHYREFCKCLKSOURCE_19_2M RCC_CCIPR4_OTGPHYREFCKSEL_3 +#define LL_RCC_OTGPHYREFCKCLKSOURCE_20M (RCC_CCIPR4_OTGPHYREFCKSEL_3 | RCC_CCIPR4_OTGPHYREFCKSEL_0 ) +#define LL_RCC_OTGPHYREFCKCLKSOURCE_24M (RCC_CCIPR4_OTGPHYREFCKSEL_3 | RCC_CCIPR4_OTGPHYREFCKSEL_1 ) +#define LL_RCC_OTGPHYREFCKCLKSOURCE_26M (RCC_CCIPR4_OTGPHYREFCKSEL_3 |\ + RCC_CCIPR4_OTGPHYREFCKSEL_2 | RCC_CCIPR4_OTGPHYREFCKSEL_1) +#define LL_RCC_OTGPHYREFCKCLKSOURCE_32M (RCC_CCIPR4_OTGPHYREFCKSEL_3 |\ + RCC_CCIPR4_OTGPHYREFCKSEL_1 | RCC_CCIPR4_OTGPHYREFCKSEL_0) + +/** + * @} + */ +#endif /* RCC_CCIPR4_OTGPHYREFCKSEL */ + +#if defined(OCTOSPI2) +/** @defgroup RCC_LL_EC_OCTOSPI2_CLKSOURCE Peripheral OCTOSPI2 kernel clock source selection + * @{ + */ +#define LL_RCC_OSPI2_CLKSOURCE_HCLK 0x00000000U /*!< AHB clock used as OctoSPI2 kernel clock source */ +#define LL_RCC_OSPI2_CLKSOURCE_PLL1Q RCC_CCIPR5_OCTOSPI2SEL_0 /*!< PLL1 Q clock used as OctoSPI2 kernel clock source */ +#define LL_RCC_OSPI2_CLKSOURCE_PLL2R RCC_CCIPR5_OCTOSPI2SEL_1 /*!< PLL2 R clock used as OctoSPI2 kernel clock source */ +#define LL_RCC_OSPI2_CLKSOURCE_CLKP (RCC_CCIPR5_OCTOSPI2SEL_0 | RCC_CCIPR5_OCTOSPI2SEL_1) /*!< CLKP clock used as OctoSPI2 clock source */ +/** + * @} + */ +#endif /* OCTOSPI2 */ + +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) +/** @defgroup RCC_LL_EC_ETHPTP_CLKSOURCE Peripheral ETHPTP kernel clock source selection + * @{ + */ +#define LL_RCC_ETHPTP_CLKSOURCE_HCLK ((uint32_t)0x00000000U) +#define LL_RCC_ETHPTP_CLKSOURCE_PLL1R RCC_CCIPR5_ETHPTPCLKSEL_0 +#define LL_RCC_ETHPTP_CLKSOURCE_PLL1Q RCC_CCIPR5_ETHPTPCLKSEL_1 +#if defined(RCC_CR_PLL3ON) +#define LL_RCC_ETHPTP_CLKSOURCE_PLL3P (RCC_CCIPR5_ETHPTPCLKSEL_0 | RCC_CCIPR5_ETHPTPCLKSEL_1) +#endif /* RCC_CR_PLL3ON */ + +/** + * @} + */ +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + +#if defined(RCC_CCIPR4_ETHPTPDIV) +/** @defgroup RCC_LL_ETHPTP_CLK_Divider Peripheral ETHPTP Clock Divider selection + * @{ + */ +#define LL_RCC_ETHPTP_CLK_DIV_1 ((uint32_t)0x00000000U) /*!< ETHPTP not divided (default) */ +#define LL_RCC_ETHPTP_CLK_DIV_2 RCC_CCIPR4_ETHPTPDIV_0 /*!< ETHPTP divided by 2 */ +#define LL_RCC_ETHPTP_CLK_DIV_3 RCC_CCIPR4_ETHPTPDIV_1 /*!< ETHPTP divided by 3 */ +#define LL_RCC_ETHPTP_CLK_DIV_4 (RCC_CCIPR4_ETHPTPDIV_0 | RCC_CCIPR4_ETHPTPDIV_1) /*!< ETHPTP divided by 4 */ +#define LL_RCC_ETHPTP_CLK_DIV_5 RCC_CCIPR4_ETHPTPDIV_2 /*!< ETHPTP divided by 5 */ +#define LL_RCC_ETHPTP_CLK_DIV_6 (RCC_CCIPR4_ETHPTPDIV_2 | RCC_CCIPR4_ETHPTPDIV_0) /*!< ETHPTP divided by 6 */ +#define LL_RCC_ETHPTP_CLK_DIV_7 (RCC_CCIPR4_ETHPTPDIV_2 | RCC_CCIPR4_ETHPTPDIV_1) /*!< ETHPTP divided by 7 */ +#define LL_RCC_ETHPTP_CLK_DIV_8 (RCC_CCIPR4_ETHPTPDIV_2 | RCC_CCIPR4_ETHPTPDIV_1 | RCC_CCIPR4_ETHPTPDIV_0) /*!< ETHPTP divided by 8 */ +#define LL_RCC_ETHPTP_CLK_DIV_9 RCC_CCIPR4_ETHPTPDIV_3 /*!< ETHPTP divided by 9 */ +#define LL_RCC_ETHPTP_CLK_DIV_10 (RCC_CCIPR4_ETHPTPDIV_3 | RCC_CCIPR4_ETHPTPDIV_0) /*!< ETHPTP divided by 10 */ +#define LL_RCC_ETHPTP_CLK_DIV_11 (RCC_CCIPR4_ETHPTPDIV_3 | RCC_CCIPR4_ETHPTPDIV_1) /*!< ETHPTP divided by 11 */ +#define LL_RCC_ETHPTP_CLK_DIV_12 (RCC_CCIPR4_ETHPTPDIV_3 | RCC_CCIPR4_ETHPTPDIV_1 | RCC_CCIPR4_ETHPTPDIV_0) /*!< ETHPTP divided by 12 */ +#define LL_RCC_ETHPTP_CLK_DIV_13 (RCC_CCIPR4_ETHPTPDIV_3 | RCC_CCIPR4_ETHPTPDIV_2) /*!< ETHPTP divided by 13 */ +#define LL_RCC_ETHPTP_CLK_DIV_14 (RCC_CCIPR4_ETHPTPDIV_3 | RCC_CCIPR4_ETHPTPDIV_2 | RCC_CCIPR4_ETHPTPDIV_0) /*!< ETHPTP divided by 14 */ +#define LL_RCC_ETHPTP_CLK_DIV_15 (RCC_CCIPR4_ETHPTPDIV_3 | RCC_CCIPR4_ETHPTPDIV_2 | RCC_CCIPR4_ETHPTPDIV_1) /*!< ETHPTP divided by 15 */ +#define LL_RCC_ETHPTP_CLK_DIV_16 (RCC_CCIPR4_ETHPTPDIV_3 | RCC_CCIPR4_ETHPTPDIV_2 | \ + RCC_CCIPR4_ETHPTPDIV_1 | RCC_CCIPR4_ETHPTPDIV_0) /*!< ETHPTP divided by 16 */ +#endif /* RCC_CCIPR4_ETHPTPDIV */ + +#if defined(RCC_CCIPR4_ETHCLKSEL) +/** @defgroup RCC_LL_EC_ETH_CLKSOURCE Peripheral ETH kernel clock source selection + * @{ + */ +#define LL_RCC_ETH_CLKSOURCE_HSE ((uint32_t)0x00000000U) +#define LL_RCC_ETH_CLKSOURCE_PLL1Q RCC_CCIPR4_ETHCLKSEL +/** + * @} + */ +#endif /* RCC_CCIPR4_ETHCLKSEL */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC kernel clock source selection + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE_PLL3R ((uint32_t)0x00000000U) +#define LL_RCC_LTDC_CLKSOURCE_PLL2R RCC_CCIPR5_LTDCSEL + +/** + * @} + */ +#endif /* LTDC */ + +#if defined(RCC_CCIPR5_ETHREFCLKSEL) +/** @defgroup RCC_LL_EC_ETHREF_CLKSOURCE Peripheral ETHREF kernel clock source selection + * @{ + */ +#define LL_RCC_ETHREF_CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) +#define LL_RCC_ETHREF_CLKSOURCE_PLL1R RCC_CCIPR5_ETHREFCLKSEL + +/** + * @} + */ +#endif /* RCC_CCIPR5_ETHREFCLKSEL */ + +#if defined(ADF1) +/** @defgroup RCC_LL_EC_ADF1_CLKSOURCE Peripheral ADF1 kernel clock source selection + * @{ + */ +#define LL_RCC_ADF1_CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) +#define LL_RCC_ADF1_CLKSOURCE_PLL2P RCC_CCIPR5_ADF1SEL_0 +#define LL_RCC_ADF1_CLKSOURCE_PLL3P RCC_CCIPR5_ADF1SEL_1 +#define LL_RCC_ADF1_CLKSOURCE_PIN (RCC_CCIPR5_ADF1SEL_0 | RCC_CCIPR5_ADF1SEL_1) +#define LL_RCC_ADF1_CLKSOURCE_CLKP RCC_CCIPR5_ADF1SEL_2 +/** + * @} + */ +#endif /* ADF1 */ + +#if defined(MDF1) +/** @defgroup RCC_LL_EC_MDF1_CLKSOURCE Peripheral MDF1 kernel clock source selection + * @{ + */ +#define LL_RCC_MDF1_CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) +#define LL_RCC_MDF1_CLKSOURCE_PLL2P RCC_CCIPR5_MDF1SEL_0 +#define LL_RCC_MDF1_CLKSOURCE_PLL3P RCC_CCIPR5_MDF1SEL_1 +#define LL_RCC_MDF1_CLKSOURCE_PIN (RCC_CCIPR5_MDF1SEL_0 | RCC_CCIPR5_MDF1SEL_1) +#define LL_RCC_MDF1_CLKSOURCE_CLKP RCC_CCIPR5_MDF1SEL_2 +/** + * @} + */ +#endif /* MDF1 */ + +/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection + * @{ + */ +#define LL_RCC_CLKP_CLKSOURCE_HSI 0x00000000U /*!< HSI clock used as CLKP clock source */ +#define LL_RCC_CLKP_CLKSOURCE_CSI RCC_CCIPR5_CKERPSEL_0 /*!< CSI clock used as CLKP clock source */ +#define LL_RCC_CLKP_CLKSOURCE_HSE RCC_CCIPR5_CKERPSEL_1 /*!< HSE clock used as CLKP clock source */ +#define LL_RCC_CLKP_CLKSOURCE_NONE RCC_CCIPR5_CKERPSEL /*!< No clock selected as CLKP clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, 0x00000000UL) /*!< USART1 Clock source selection */ +#define LL_RCC_USART2_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, 0x00000000UL) /*!< USART2 Clock source selection */ +#define LL_RCC_USART3_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, 0x00000000UL) /*!< USART3 Clock source selection */ +#if defined(USART6) +#define LL_RCC_USART6_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, 0x00000000UL) /*!< USART6 Clock source selection */ +#endif /* USART6 */ +#if defined(USART10) +#define LL_RCC_USART10_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, 0x00000000UL) /*!< USART10 Clock source selection */ +#endif /* USART10 */ +#if defined(USART11) +#define LL_RCC_USART11_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, 0x00000000UL) /*!< USART11 Clock source selection */ +#endif /* USART11 */ +/** + * @} + */ + +#if defined(UART4) +/** @defgroup RCC_LL_EC_UART Peripheral UARTx get clock source + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, 0x00000000UL) /*!< UART4 Clock source selection */ +#define LL_RCC_UART5_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, 0x00000000UL) /*!< UART5 Clock source selection */ +#define LL_RCC_UART7_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, 0x00000000UL) /*!< UART7 Clock source selection */ +#define LL_RCC_UART8_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, 0x00000000UL) /*!< UART8 Clock source selection */ +#define LL_RCC_UART9_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, 0x00000000UL) /*!< UART9 Clock source selection */ +#define LL_RCC_UART12_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, 0x00000000UL) /*!< UART12 Clock source selection */ +/** + * @} + */ +#endif /*UART4*/ + +/** @defgroup RCC_LL_EC_SPI Peripheral SPIx get clock source + * @{ + */ +#define LL_RCC_SPI1_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0x00000000UL) /*!< SPI1 Clock source selection */ +#define LL_RCC_SPI2_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, 0x00000000UL) /*!< SPI2 Clock source selection */ +#define LL_RCC_SPI3_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, 0x00000000UL) /*!< SPI3 Clock source selection */ +#if defined(SPI4) +#define LL_RCC_SPI4_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, 0x00000000UL) /*!< SPI4 Clock source selection */ +#endif /* SPI4 */ +#if defined(SPI5) +#define LL_RCC_SPI5_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, 0x00000000UL) /*!< SPI5 Clock source selection */ +#endif /* SPI5 */ +#if defined(SPI6) +#define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, 0x00000000UL) /*!< SPI6 Clock source selection */ +#endif /* SPI6 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUART Peripheral LPUARTx get clock source + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR3_LPUART1SEL /*!< LPUART1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0x00000000UL) /*!< I2C1 Clock source selection */ +#define LL_RCC_I2C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0x00000000UL) /*!< I2C2 Clock source selection */ +#if defined(I2C3) +#define LL_RCC_I2C3_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0x00000000UL) /*!< I2C3 Clock source selection */ +#endif /* I2C3 */ +#if defined(I2C4) +#define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0x00000000UL) /*!< I2C4 Clock source selection */ +#endif /* I2C4 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I3C Peripheral I3Cx get clock source + * @{ + */ +#define LL_RCC_I3C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0x00000000UL) /*!< I3C1 Clock source selection */ +#if defined(I3C2) +#define LL_RCC_I3C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0x00000000UL) /*!< I3C2 Clock source selection */ +#endif /* I3C2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIMx get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0x00000000UL) /*!< LPTIM1 Clock source selection */ +#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, 0x00000000UL) /*!< LPTIM2 Clock source selection */ +#if defined(LPTIM3) +#define LL_RCC_LPTIM3_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, 0x00000000UL) /*!< LPTIM3 Clock source selection */ +#endif /* LPTIM3 */ +#if defined(LPTIM4) +#define LL_RCC_LPTIM4_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, 0x00000000UL) /*!< LPTIM4 Clock source selection */ +#endif /* LPTIM4 */ +#if defined(LPTIM5) +#define LL_RCC_LPTIM5_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, 0x00000000UL) /*!< LPTIM5 Clock source selection */ +#endif /* LPTIM5 */ +#if defined(LPTIM6) +#define LL_RCC_LPTIM6_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, 0x00000000UL) /*!< LPTIM6 Clock source selection */ +#endif /* LPTIM6 */ +/** + * @} + */ + +#if defined(SAI1) +/** @defgroup RCC_LL_EC_SAI Peripheral SAIx get clock source + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, 0x00000000UL) /*!< SAI1 Clock source selection */ +#define LL_RCC_SAI2_CLKSOURCE LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, 0x00000000UL) /*!< SAI2 Clock source selection */ +/** + * @} + */ +#endif /* SAI1 */ + +#if defined(SDMMC1) +/** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source + * @{ + */ +#define LL_RCC_SDMMC1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC1SEL, RCC_CCIPR4_SDMMC1SEL_Pos, 0x00000000UL) /*!< SDMMC1 Kernel Clock source selection */ +#if defined(SDMMC2) +#define LL_RCC_SDMMC2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC2SEL, RCC_CCIPR4_SDMMC2SEL_Pos, 0x00000000UL) /*!< SDMMC2 Kernel Clock source selection */ +#endif /*SDMMC2*/ +/** + * @} + */ +#endif /* SDMMC1 */ + +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR5_RNGSEL /*!< RNG Clock source selection */ +/** + * @} + */ + +#if defined(USB_DRD_FS) +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE RCC_CCIPR4_USBSEL /*!< USB Clock source selection */ +/** + * @} + */ +#endif /* USB_DRD_FS */ + +/** @defgroup RCC_LL_EC_ADCDAC Peripheral ADCDAC get clock source + * @{ + */ +#define LL_RCC_ADCDAC_CLKSOURCE RCC_CCIPR5_ADCDACSEL /*!< ADCDACs Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DAC Peripheral DAC get low-power clock source + * @{ + */ +#define LL_RCC_DAC_LP_CLKSOURCE RCC_CCIPR5_DACSEL /*!< DAC low-power Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE RCC_CCIPR5_CECSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get kernel clock source + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR5_FDCANSEL /*!< FDCAN kernel Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source + * @{ + */ +#define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR4_OCTOSPISEL /*!< OctoSPI Clock source selection */ +/** + * @} + */ + +#if defined(PLAY1) +/** @defgroup RCC_LL_EC_PLAY1_SRC Peripheral PLAY1 get clock source + * @{ + */ +#define LL_RCC_PLAY1_CLKSOURCE RCC_CCIPR3_PLAY1SEL /*!< PLAY1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLAY1_DIV Peripheral PLAY1 get clock divider + * @{ + */ +#define LL_RCC_PLAY1_CLKDIVIDER RCC_CCIPR3_PLAY1DIV /*!< PLAY1 Clock divider selection */ +/** + * @} + */ +#endif /* PLAY1 */ + +#if defined(USB_OTG_FS) +/** @defgroup RCC_LL_EC_OTGFS Peripheral OTGFS get clock source + * @{ + */ +#define LL_RCC_OTGFS_CLKSOURCE RCC_CCIPR4_OTGFSSEL /*!< OTGFS Clock source selection */ +/** + * @} + */ +#endif /* USB_OTG_FS */ + +#if defined(USB_OTG_HS) +/** @defgroup RCC_LL_EC_OTGHS Peripheral OTGHS get clock source + * @{ + */ +#define LL_RCC_OTGHS_CLKSOURCE RCC_CCIPR4_OTGHSSEL /*!< OTGHS Clock source selection */ +/** + * @} + */ +#endif /* USB_OTG_HS */ + +#if defined(RCC_CCIPR4_OTGPHYREFCKSEL) +/** @defgroup RCC_LL_EC_OTGPHY Peripheral OTGPHY get clock source + * @{ + */ +#define LL_RCC_OTGPHY_CLKSOURCE RCC_CCIPR4_OTGPHYREFCKSEL /*!< OTGPHY Clock source selection */ +/** + * @} + */ +#endif /* RCC_CCIPR4_OTGPHYREFCKSEL */ + +#if defined(RCC_CCIPR4_ETHCLKSEL) +/** @defgroup RCC_LL_EC_ETH Peripheral ETH get clock source + * @{ + */ +#define LL_RCC_ETH_CLKSOURCE RCC_CCIPR4_ETHCLKSEL /*!< ETH Clock source selection */ +/** + * @} + */ +#endif /* RCC_CCIPR4_ETHCLKSEL */ + +#if defined(OCTOSPI2) +/** @defgroup RCC_LL_EC_OCTOSPI2 Peripheral OCTOSPI2 get clock source + * @{ + */ +#define LL_RCC_OCTOSPI2_CLKSOURCE RCC_CCIPR5_OCTOSPI2SEL /*!< OctoSPI2 Clock source selection */ +/** + * @} + */ +#endif /* OCTOSOI2 */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR5_LTDCSEL /*!< LTDC Clock source selection */ +/** + * @} + */ +#endif /* LTDC */ + +#if defined(ADF1) +/** @defgroup RCC_LL_EC_ADF1 Peripheral ADF1 get clock source + * @{ + */ +#define LL_RCC_ADF1_CLKSOURCE RCC_CCIPR5_ADF1SEL /*!< ADF1 Clock source selection */ +/** + * @} + */ +#endif /* ADF1 */ + +#if defined(MDF1) +/** @defgroup RCC_LL_EC_MDF1 Peripheral MDF1 get clock source + * @{ + */ +#define LL_RCC_MDF1_CLKSOURCE RCC_CCIPR5_MDF1SEL /*!< MDF1 Clock source selection */ +/** + * @} + */ +#endif /* MDF1 */ + +/** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source + * @{ + */ +#define LL_RCC_CLKP_CLKSOURCE RCC_CCIPR5_CKERPSEL /*!< CLKP Clock source selection */ +/** + * @} + */ + +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) +/** @defgroup RCC_LL_EC_ETHPTP_SRC Peripheral ETHPTP get clock source + * @{ + */ +#define LL_RCC_ETHPTP_CLKSOURCE RCC_CCIPR5_ETHPTPCLKSEL /*!< ETHPTP Clock source selection */ +/** + * @} + */ +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + +#if defined(RCC_CCIPR4_ETHPTPDIV) +/** @defgroup RCC_LL_EC_ETHPTP_DIV Peripheral ETHPTP get clock divider + * @{ + */ +#define LL_RCC_ETHPTP_CLKDIVIDER RCC_CCIPR4_ETHPTPDIV /*!< ETHPTP Clock divider selection */ +/** + * @} + */ + +#endif /* RCC_CCIPR4_ETHPTPDIV */ + +#if defined(RCC_CCIPR5_ETHREFCLKSEL) +/** @defgroup RCC_LL_EC_ETHREF Peripheral ETHREF get clock source + * @{ + */ +#define LL_RCC_ETHREF_CLKSOURCE RCC_CCIPR5_ETHREFCLKSEL /*!< ETHREF Clock source selection */ +/** + * @} + */ +#endif /* RCC_CCIPR5_ETHREFCLKSEL */ + +/** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source + * @{ + */ +#define LL_RCC_PLL1SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL1 entry clock source */ +#define LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_0 /*!< HSI clock selected as main PLL1 entry clock source */ +#define LL_RCC_PLL1SOURCE_CSI RCC_PLL1CFGR_PLL1SRC_1 /*!< CSI clock selected as main PLL1 entry clock source */ +#define LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) /*!< HSE clock selected as main PLL1 entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input ranges + * @{ + */ +#define LL_RCC_PLLINPUTRANGE_1_2 0x00000000U /*!< VCO input range: 1 to 2 MHz */ +#define LL_RCC_PLLINPUTRANGE_2_4 0x00000001U /*!< VCO input range: 2 to 4 MHz */ +#define LL_RCC_PLLINPUTRANGE_4_8 0x00000002U /*!< VCO input range: 4 to 8 MHz */ +#define LL_RCC_PLLINPUTRANGE_8_16 0x00000003U /*!< VCO input range: 8 to 16 MHz */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLOUTPUTRANGE All PLLs output ranges + * @{ + */ +#define LL_RCC_PLLVCORANGE_WIDE 0x00000000U /*!< VCO output range: 192 to 836 MHz */ +#define LL_RCC_PLLVCORANGE_MEDIUM 0x00000001U /*!< VCO output range: 150 to 420 MHz */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL2SOURCE PLL2 entry clock source + * @{ + */ +#define LL_RCC_PLL2SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL2 entry clock source */ +#define LL_RCC_PLL2SOURCE_HSI RCC_PLL2CFGR_PLL2SRC_0 /*!< HSI clock selected as main PLL2 entry clock source */ +#define LL_RCC_PLL2SOURCE_CSI RCC_PLL2CFGR_PLL2SRC_1 /*!< CSI clock selected as main PLL2 entry clock source */ +#define LL_RCC_PLL2SOURCE_HSE (RCC_PLL2CFGR_PLL2SRC_0 | RCC_PLL2CFGR_PLL2SRC_1) /*!< HSE clock selected as main PLL2 entry clock source */ +/** + * @} + */ +#if defined(RCC_CR_PLL3ON) +/** @defgroup RCC_LL_EC_PLL3SOURCE PLL3 entry clock source + * @{ + */ +#define LL_RCC_PLL3SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL3 entry clock source */ +#define LL_RCC_PLL3SOURCE_HSI RCC_PLL3CFGR_PLL3SRC_0 /*!< HSI clock selected as main PLL3 entry clock source */ +#define LL_RCC_PLL3SOURCE_CSI RCC_PLL3CFGR_PLL3SRC_1 /*!< CSI clock selected as main PLL3 entry clock source */ +#define LL_RCC_PLL3SOURCE_HSE (RCC_PLL3CFGR_PLL3SRC_0 | RCC_PLL3CFGR_PLL3SRC_1) /*!< HSE clock selected as main PLL3 entry clock source */ +/** + * @} + */ +#endif /* RCC_CR_PLL3ON */ +#if defined(RCC_SECCFGR_HSISEC) +/** @defgroup RCC_LL_EC_SECURE_ATTRIBUTES Secure attributes + * @note Only available when system implements security (TZEN=1) + * @{ + */ +#define LL_RCC_ALL_SEC RCC_SECURE_MASK /*!< Security on all RCC resources */ +#define LL_RCC_ALL_NSEC 0U /*!< No security on RCC resources (default) */ + +#define LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC /*!< HSI clock configuration secure-only access */ +#define LL_RCC_HSI_NSEC 0U /*!< HSI clock configuration secure/non-secure access */ +#define LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC /*!< HSE clock configuration secure-only access */ +#define LL_RCC_HSE_NSEC 0U /*!< HSE clock configuration secure/non-secure access */ +#define LL_RCC_CSI_SEC RCC_SECCFGR_CSISEC /*!< CSI clock configuration secure-only access */ +#define LL_RCC_CSI_NSEC 0U /*!< CSI clock configuration secure/non-secure access */ +#define LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC /*!< LSI clock configuration secure-only access */ +#define LL_RCC_LSI_NSEC 0U /*!< LSI clock configuration secure/non-secure access */ +#define LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC /*!< LSE clock configuration secure-only access */ +#define LL_RCC_LSE_NSEC 0U /*!< LSE clock configuration secure/non-secure access */ +#define LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure-only access */ +#define LL_RCC_SYSCLK_NSEC 0U /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access */ +#define LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration secure-only access */ +#define LL_RCC_PRESCALERS_NSEC 0U /*!< AHBx/APBx prescaler configuration secure/non-secure access */ +#define LL_RCC_PLL1_SEC RCC_SECCFGR_PLL1SEC /*!< main PLL clock configuration secure-only access */ +#define LL_RCC_PLL1_NSEC 0U /*!< main PLL clock configuration secure/non-secure access */ +#define LL_RCC_PLL2_SEC RCC_SECCFGR_PLL2SEC /*!< PLL2 clock configuration secure-only access */ +#define LL_RCC_PLL2_NSEC 0U /*!< PLL2 clock configuration secure/non-secure access */ +#define LL_RCC_PLL3_SEC RCC_SECCFGR_PLL3SEC /*!< PLL3 clock configuration secure-only access */ +#define LL_RCC_PLL3_NSEC 0U /*!< PLL3 clock configuration secure/non-secure access */ +#define LL_RCC_HSI48_SEC RCC_SECCFGR_HSI48SEC /*!< HSI48 clock configuration secure-only access */ +#define LL_RCC_HSI48_NSEC 0U /*!< HSI48 clock configuration secure/non-secure access */ +#define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag secure-ony access */ +#define LL_RCC_RESET_FLAGS_NSEC 0U /*!< Remove reset flag secure/non-secure access */ +#define LL_RCC_CKPERSEL_SEC RCC_SECCFGR_CKPERSELSEC /*!< Periph clock configuration secure-ony access */ +#define LL_RCC_CKPERSEL_NSEC 0U /*!< Periph clock configuration secure/non-secure access */ +/** + * @} + */ +#endif /* RCC_SECCFGR_HSISEC */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the PLL1P clock frequency + * @note ex: @ref __LL_RCC_CALC_PLL1CLK_P_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetM (), + * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetP ()); + * @param __INPUTFREQ__ PLL1 Input frequency (based on HSI/HSE/CSI) + * @param __PLL1M__ parameter can be a value between 1 and 63 + * @param __PLL1N__ parameter can be a value between 4 and 512 + * @param __PLL1P__ parameter can be a value between 1 and 128 (odd values not allowed) + * @retval PLL1P clock frequency (in Hz) + */ + +#define __LL_RCC_CALC_PLL1CLK_P_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1P__) \ + ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1P__)) + +/** + * @brief Helper macro to calculate the PLL1Q clock frequency + * @note ex: @ref __LL_RCC_CALC_PLL1CLK_Q_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetM (), + * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetQ ()); + * @param __INPUTFREQ__ PLL1 Input frequency (based on HSI/HSE/CSI) + * @param __PLL1M__ parameter can be a value between 1 and 63 + * @param __PLL1N__ parameter can be a value between 4 and 512 + * @param __PLL1Q__ parameter can be a value between 2 and 128 + * @retval PLL1Q clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL1CLK_Q_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1Q__) \ + ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1Q__)) + +/** + * @brief Helper macro to calculate the PLL1R clock frequency + * @note ex: @ref __LL_RCC_CALC_PLL1CLK_R_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetM (), + * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetN ()); + * @param __INPUTFREQ__ PLL1 Input frequency (based on HSI/HSE/CSI) + * @param __PLL1M__ parameter can be a value between 1 and 63 + * @param __PLL1N__ parameter can be a value between 4 and 512 + * @param __PLL1R__ parameter can be a value between 1 and 128 + * @retval PLL1R clock frequency (in Hz) + */ + +#define __LL_RCC_CALC_PLL1CLK_R_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1R__) \ + ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1R__)) + +/** + * @brief Helper macro to calculate the PLL2P clock frequency + * @note ex: @ref __LL_RCC_CALC_PLL2CLK_P_FREQ (HSE_ALUE,@ref LL_RCC_PLL2_GetM (), + * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSI/HSE/CSI) + * @param __PLL2M__ parameter can be a value between 1 and 63 + * @param __PLL2N__ parameter can be a value between 4 and 512 + * @param __PLL2P__ parameter can be a value between 2 and 128 + * @retval PLL2P clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL2CLK_P_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2P__) \ + ((((__INPUTFREQ__) /(__PLL2M__)) * (__PLL2N__)) / (__PLL2P__)) + +/** + * @brief Helper macro to calculate the PLL2Q clock frequency + * @note ex: @ref __LL_RCC_CALC_PLL2CLK_Q_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetM (), + * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSI/HSE/CSI) + * @param __PLL2M__ parameter can be a value between 1 and 63 + * @param __PLL2N__ parameter can be a value between 4 and 512 + * @param __PLL2Q__ parameter can be a value between 1 and 128 + * @retval PLL2Q clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL2CLK_Q_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2Q__) \ + ((((__INPUTFREQ__) /(__PLL2M__)) * (__PLL2N__)) / (__PLL2Q__)) + +/** + * @brief Helper macro to calculate the PLL2R clock frequency + * @note ex: @ref __LL_RCC_CALC_PLL2CLK_R_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetM (), + * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetR ()); + * @param __INPUTFREQ__ PLL2 Input frequency (based on HSI/HSE/CSI) + * @param __PLL2M__ parameter can be a value between 1 and 63 + * @param __PLL2N__ parameter can be a value between 4 and 512 + * @param __PLL2R__ parameter can be a value between 1 and 128 + * @retval PLL2R clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL2CLK_R_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2R__) \ + ((((__INPUTFREQ__) /(__PLL2M__)) * (__PLL2N__)) / (__PLL2R__)) +#if defined(RCC_CR_PLL3ON) +/** + * @brief Helper macro to calculate the PLL3P clock frequency + * @note ex: @ref __LL_RCC_CALC_PLL3CLK_P_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetM (), + * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetP ()); + * @param __INPUTFREQ__ PLL3 Input frequency (based on HSI/HSE/CSI) + * @param __PLL3M__ parameter can be a value between 1 and 63 + * @param __PLL3N__ parameter can be a value between 4 and 512 + * @param __PLL3P__ parameter can be a value between 2 and 128 + * @retval PLL3P clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL3CLK_P_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3P__) \ + ((((__INPUTFREQ__) /(__PLL3M__)) * (__PLL3N__)) / (__PLL3P__)) + +/** + * @brief Helper macro to calculate the PLL3 frequency + * @note ex: @ref __LL_RCC_CALC_PLL3CLK_Q_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetM (), + * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetQ ()); + * @param __INPUTFREQ__ PLL3 Input frequency (based on HSI/HSE/CSI) + * @param __PLL3M__ parameter can be a value between 1 and 63 + * @param __PLL3N__ parameter can be a value between 4 and 512 + * @param __PLL3Q__ parameter can be a value between 1 and 128 + * @retval PLL3Q clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL3CLK_Q_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3Q__) \ + ((((__INPUTFREQ__) /(__PLL3M__)) * (__PLL3N__)) / (__PLL3Q__)) + +/** + * @brief Helper macro to calculate the PLL3 frequency + * @note ex: @ref __LL_RCC_CALC_PLL3CLK_R_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetM (), + * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetR ()); + * @param __INPUTFREQ__ PLL3 Input frequency (based on HSI/HSE/CSI) + * @param __PLL3M__ parameter can be a value between 1 and 63 + * @param __PLL3N__ parameter can be a value between 4 and 512 + * @param __PLL3R__ parameter can be a value between 1 and 128 + * @retval PLL3R clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL3CLK_R_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3R__) \ + ((((__INPUTFREQ__) /(__PLL3M__)) * (__PLL3N__)) / (__PLL3R__)) +#endif /* RCC_CR_PLL3ON */ +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSI/HSE/CSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) \ + ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (APB1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \ + ((__HCLKFREQ__) >> (APBPrescTable[((__APB1PRESCALER__) & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos])) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (APB2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) \ + ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR2_PPRE2_Pos]) + + +/** + * @brief Helper macro to calculate the PCLK3 frequency (APB3) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB3PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + * @retval PCLK3 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) \ + ((__HCLKFREQ__) >> APBPrescTable[(__APB3PRESCALER__) >> RCC_CFGR2_PPRE3_Pos]) + +/** + * @brief Helper macro to calculate the HSI frequency + * @param __HSIDIV__ This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @retval HSI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE >> ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the HSE Clock Security System. + * @rmtoll CR HSECSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSECSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); +} + +/** + * @brief Set external HSE clock type in Bypass mode + * @note This bit can be written only if the HSE oscillator is disabled + * @rmtoll CR HSEEXT LL_RCC_HSE_SetExternalClockType + * @param HSEClockMode This parameter can be one of the following values: + * @arg @ref LL_RCC_HSE_ANALOG_TYPE + * @arg @ref LL_RCC_HSE_DIGITAL_TYPE + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SetExternalClockType(uint32_t HSEClockMode) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSEEXT, HSEClockMode); +} + +/** + * @brief Get external HSE clock type in Bypass mode + * @rmtoll CR HSEEXT LL_RCC_HSE_GetExternalClockType + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HSE_ANALOG_TYPE + * @arg @ref LL_RCC_HSE_DIGITAL_TYPE + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_GetExternalClockType(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSEEXT)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL); +} + +/** + * @brief Enable HSI even in stop mode for some peripherals kernel + * @note HSI oscillator is forced ON even in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Disable HSI in stop mode for some peripherals kernel + * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Check if HSI is enabled in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI new divider applied and ready + * @rmtoll CR HSIDIVF LL_RCC_HSI_IsDividerReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF)) ? 1UL : 0UL); +} + +/** + * @brief Set HSI divider + * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @retval None. + */ +__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider); +} + +/** + * @brief Get HSI divider + * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider + * @retval can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIDIV)); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration + * @retval A value between 0 and 4095 (0xFFF) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 64, which, when added to the HSICAL value, + * should trim the HSI to 64 MHz +/- 1 % + * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value can be a value between Min_Data = 0 and Max_Data = 127 (0x7F) + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll ICSC3R HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval A value between Min_Data = 0 and Max_Data = 127 (0x7F) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_CSI CSI + * @{ + */ + +/** + * @brief Enable CSI oscillator + * @rmtoll CR CSION LL_RCC_CSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSION); +} + +/** + * @brief Disable CSI oscillator + * @rmtoll CR CSION LL_RCC_CSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSION); +} + +/** + * @brief Check if CSI clock is ready + * @rmtoll CR CSIRDY LL_RCC_CSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable CSI oscillator in Stop mode for some peripherals kernel clock + * @rmtoll CR CSIKERON LL_RCC_CSI_EnableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_EnableInStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSIKERON); +} + +/** + * @brief Disable CSI oscillator in Stop mode for some peripherals kernel clock + * @rmtoll CR CSIKERON LL_RCC_CSI_DisableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_DisableInStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON); +} + +/** + * @brief Check if CSI is enabled in stop mode + * @rmtoll CR CSIKERON LL_RCC_CSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_IsEnabledInStopMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_CSIKERON) == RCC_CR_CSIKERON) ? 1UL : 0UL); +} + +/** + * @brief Get CSI Calibration value + * @note When CSITRIM is written, CSICAL is updated with the sum of + * CSITRIM and the factory trim value + * @rmtoll CSICFGR CSICAL LL_RCC_CSI_GetCalibration + * @retval A value between 0 and 255 (0xFF) + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos); +} + +/** + * @brief Set CSI Calibration trimming + * @note user-programmable trimming value that is added to the CSICAL + * @note Default value is 16, which, when added to the CSICAL value, + * should trim the CSI to 4 MHz +/- 1 % + * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_SetCalibTrimming + * @param Value can be a value between Min_Data = 0 and Max_Data = 63 (0x3F) + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos); +} + +/** + * @brief Get CSI Calibration trimming + * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_GetCalibTrimming + * @retval A value between 0 and 63 (0x3F) + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 + * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Disable HSI48 + * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Check if HSI48 oscillator Ready + * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL); +} + +/** + * @brief Get HSI48 Calibration value + * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration + * @retval A value between 0 and 1023 (0x3FF) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Set external LSE clock type in Bypass mode + * @note This bit can be written only if the LSE oscillator is disabled + * @rmtoll BDCR LSEEXT LL_RCC_LSE_SetExternalClockType + * @param LSEClockMode This parameter can be one of the following values: + * @arg @ref LL_RCC_LSE_ANALOG_TYPE + * @arg @ref LL_RCC_LSE_DIGITAL_TYPE (*) + * @retval None + * + * (*) not to be used if RTC is active + */ +__STATIC_INLINE void LL_RCC_LSE_SetExternalClockType(uint32_t LSEClockMode) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEEXT, LSEClockMode); +} + +/** + * @brief Get external LSE clock type in Bypass mode + * @rmtoll BDCR LSEEXT LL_RCC_LSE_GetExternalClockType + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSE_ANALOG_TYPE + * @arg @ref LL_RCC_LSE_DIGITAL_TYPE + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetExternalClockType(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEEXT)); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Enable Clock security system on LSE. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Disable Clock security system on LSE. + * @note Clock security system can be disabled only after a LSE + * failure detection. In that case it MUST be disabled by software. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Check if CSS on LSE failure Detection + * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll BDCR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll BDCR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll BDCR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == RCC_BDCR_LSIRDY) ? 1UL : 0UL); +} + + +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_LSCO LSCO + * @{ + */ + +/** + * @brief Enable Low Speed Microcontroller Clock Output + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} + +/** + * @brief Disable Low Speed Microcontroller Clock Output + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} + +/** + * @brief Configure Low Speed Microcontroller Clock Output selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); +} + +/** + * @brief Get Low Speed Microcontroller Clock Output selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR1 SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_CSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR1 SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler); +} + +/** + * @brief Set Systick clock source + * @rmtoll CCIPR4 SYSTICKSEL LL_RCC_SetSystickClockSource + * @param SystickSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL, SystickSource); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler); +} + +/** + * @brief Set APB3 prescaler + * @rmtoll CFGR3 PPRE3 LL_RCC_SetAPB3Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE3, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE)); +} + +/** + * @brief Get Sysctick clock source + * @rmtoll CCIPR4 SYSTICKSEL LL_RCC_SetSystickClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2)); +} + +/** + * @brief Get APB3 prescaler + * @rmtoll CFGR3 PPRE3 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE3)); +} + +/** + * @brief Set System Clock After Wake-Up From Stop mode + * @rmtoll CFGR1 STOPWUCK LL_RCC_SetClkAfterWakeFromStop + * @param Clock This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, Clock); +} + +/** + * @brief Get System Clock After Wake-Up From Stop mode + * @rmtoll CFGR1 STOPWUCK LL_RCC_GetClkAfterWakeFromStop + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPWUCK)); +} +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCO1 (pin PA8) or MCO2 (pin PC9) + * @rmtoll CFGR1 MCO1 LL_RCC_ConfigMCO\n + * CFGR1 MCO1PRE LL_RCC_ConfigMCO\n + * CFGR1 MCO2 LL_RCC_ConfigMCO\n + * CFGR1 MCO2PRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLL1Q + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 + * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO2SOURCE_PLL2P + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_PLL1P + * @arg @ref LL_RCC_MCO2SOURCE_CSI + * @arg @ref LL_RCC_MCO2SOURCE_LSI + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_3 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_5 + * @arg @ref LL_RCC_MCO1_DIV_6 + * @arg @ref LL_RCC_MCO1_DIV_7 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_9 + * @arg @ref LL_RCC_MCO1_DIV_10 + * @arg @ref LL_RCC_MCO1_DIV_11 + * @arg @ref LL_RCC_MCO1_DIV_12 + * @arg @ref LL_RCC_MCO1_DIV_13 + * @arg @ref LL_RCC_MCO1_DIV_14 + * @arg @ref LL_RCC_MCO1_DIV_15 + * @arg @ref LL_RCC_MCO2_DIV_1 + * @arg @ref LL_RCC_MCO2_DIV_2 + * @arg @ref LL_RCC_MCO2_DIV_3 + * @arg @ref LL_RCC_MCO2_DIV_4 + * @arg @ref LL_RCC_MCO2_DIV_5 + * @arg @ref LL_RCC_MCO2_DIV_6 + * @arg @ref LL_RCC_MCO2_DIV_7 + * @arg @ref LL_RCC_MCO2_DIV_8 + * @arg @ref LL_RCC_MCO2_DIV_9 + * @arg @ref LL_RCC_MCO2_DIV_10 + * @arg @ref LL_RCC_MCO2_DIV_11 + * @arg @ref LL_RCC_MCO2_DIV_12 + * @arg @ref LL_RCC_MCO2_DIV_13 + * @arg @ref LL_RCC_MCO2_DIV_14 + * @arg @ref LL_RCC_MCO2_DIV_15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR1, (MCOxSource << 16U) | (MCOxPrescaler << 16U), \ + (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U)); +} + +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure periph clock source + * @rmtoll CCIPR1 * LL_RCC_SetClockSource\n + * CCIPR2 * LL_RCC_SetClockSource\n + * CCIPR3 * LL_RCC_SetClockSource\n + * CCIPR4 * LL_RCC_SetClockSource\n + * CCIPR5 * LL_RCC_SetClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_UART4_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_UART5_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_UART9_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_UART12_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_UART12_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**) + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PIN + * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PIN + * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*) + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL2R (*) + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL2R (*) + * + * (*) value not defined in all devices. + * (**) : For stm32h503xx family line only. + * + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource) +{ + uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CCIPR1 + LL_CLKSOURCE_REG(ClkSource)); + MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource)); +} + + +/** + * @brief Configure USARTx kernel clock source + * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n + * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n + * CCIPR1 USART3SEL LL_RCC_SetUSARTClockSource\n + * CCIPR1 USART6SEL LL_RCC_SetUSARTClockSource\n + * CCIPR1 USART10SEL LL_RCC_SetUSARTClockSource\n + * CCIPR2 USART11SEL LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_LSE (*) + * + * (*) : For stm32h56xxx and stm32h57xxx family lines only. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + LL_RCC_SetClockSource(USARTxSource); +} + +#if defined(UART4) +/** + * @brief Configure UARTx kernel clock source + * @rmtoll CCIPR1 UART4SEL LL_RCC_SetUARTClockSource\n + * CCIPR1 UART5SEL LL_RCC_SetUARTClockSource\n + * CCIPR1 UART7SEL LL_RCC_SetUARTClockSource\n + * CCIPR1 UART8SEL LL_RCC_SetUARTClockSource\n + * CCIPR1 UART9SEL LL_RCC_SetUARTClockSource\n + * CCIPR2 UART12SEL LL_RCC_SetUARTClockSource + * @param UARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_CSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_CSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART9_CLKSOURCE_CSI + * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART12_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART12_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI + * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) +{ + LL_RCC_SetClockSource(UARTxSource); +} +#endif /* UART4 */ + +/** + * @brief Configure LPUARTx kernel clock source + * @rmtoll CCIPR3 LPUART1SEL LL_RCC_SetLPUARTClockSource + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * + * (*) : For stm32h56xxx and stm32h57xxx family lines only. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) +{ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, LPUARTxSource); +} + +/** + * @brief Configure I2Cx kernel clock source + * @rmtoll CCIPR4 I2C1SEL LL_RCC_SetI2CClockSource\n + * CCIPR4 I2C2SEL LL_RCC_SetI2CClockSource\n + * CCIPR4 I2C3SEL LL_RCC_SetI2CClockSource\n + * CCIPR4 I2C4SEL LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI (*) + * + * (*) : For stm32h56xxx and stm32h57xxx family lines only. + * (**) : For stm32h503xx family line only. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + LL_RCC_SetClockSource(I2CxSource); +} + +/** + * @brief Configure I3Cx kernel clock source + * @rmtoll CCIPR4 I3C1SEL LL_RCC_SetI3CClockSource\n + * CCIPR4 I3C2SEL LL_RCC_SetI3CClockSource + * @param I3CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 (***) + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (**) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (**) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_CSI (***) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**) + * @retval None + * + * (*) : For stm32h56xxx, stm32h57xxx, stm32h5exxx and stm32h5fxxx family lines. + * (**) : For stm32h503xx family line. + * (***) : For stm32h5exxx and stm32h5fxxx family lines. + */ +__STATIC_INLINE void LL_RCC_SetI3CClockSource(uint32_t I3CxSource) +{ + LL_RCC_SetClockSource(I3CxSource); +} + +/** + * @brief Configure SPIx kernel clock source + * @rmtoll CCIPR3 SPI1SEL LL_RCC_SetSPIClockSource\n + * CCIPR3 SPI2SEL LL_RCC_SetSPIClockSource\n + * CCIPR3 SPI3SEL LL_RCC_SetSPIClockSource\n + * CCIPR3 SPI4SEL LL_RCC_SetSPIClockSource\n + * CCIPR3 SPI5SEL LL_RCC_SetSPIClockSource\n + * CCIPR3 SPI6SEL LL_RCC_SetSPIClockSource + * @param SPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PIN + * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PIN + * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*) + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource) +{ + LL_RCC_SetClockSource(SPIxSource); +} + +/** + * @brief Configure LPTIMx kernel clock source + * @rmtoll CCIPR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR2 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR2 LPTIM3SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR2 LPTIM4SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR2 LPTIM5SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR2 LPTIM6SEL LL_RCC_SetLPTIMClockSource + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_CLKP (*) + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +{ + LL_RCC_SetClockSource(LPTIMxSource); +} + +/** + * @brief Configure FDCAN kernel clock source + * @rmtoll CCIPR5 FDCANSEL LL_RCC_SetFDCANClockSource + * @param FDCANxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q + * @retval None + * + */ +__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_FDCANSEL, FDCANxSource); +} + +#if defined(SAI1) +/** + * @brief Configure SAIx kernel clock source + * @rmtoll CCIPR2 SAI1SEL LL_RCC_SetSAIClockSource\n + * CCIPR2 SAI2SEL LL_RCC_SetSAIClockSource + * @param SAIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) +{ + LL_RCC_SetClockSource(SAIxSource); +} +#endif /* SAI1 */ + +#if defined(SDMMC1) +/** + * @brief Configure SDMMCx kernel clock source + * @rmtoll CCIPR4 SDMMC1SEL LL_RCC_SetSDMMCClockSource + * @rmtoll CCIPR4 SDMMC2SEL LL_RCC_SetSDMMCClockSource + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL2R + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) +{ + LL_RCC_SetClockSource(SDMMCxSource); +} +#endif /* SDMMC1 */ + +/** + * @brief Configure RNG kernel clock source + * @rmtoll CCIPR5 RNGSEL LL_RCC_SetRNGClockSource + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_RNGSEL, RNGxSource); +} + +#if defined(USB_DRD_FS) +/** + * @brief Configure USB clock source + * @rmtoll CCIPR4 USBSEL LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_NONE + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + * + * (*) : Available in some STM32H5 lines only. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_USBSEL, USBxSource); +} +#endif /* USB_DRD_FS */ + +/** + * @brief Configure ADCx kernel clock source + * @rmtoll CCIPR5 ADCDACSEL LL_RCC_SetADCDACClockSource + * @param ADCDACxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSI + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCDACClockSource(uint32_t ADCDACxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ADCDACSEL, ADCDACxSource); +} + +/** + * @brief Configure DAC low-power kernel clock source + * @rmtoll CCIPR5 DACSEL LL_RCC_SetDACLPClockSource + * @param DACLPxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DAC_LP_CLKSOURCE_LSE + * @arg @ref LL_RCC_DAC_LP_CLKSOURCE_LSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDACLPClockSource(uint32_t DACLPxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_DACSEL, DACLPxSource); +} + +#if defined(CEC) +/** + * @brief Configure CECx kernel clock source + * @rmtoll CCIPR5 CECSEL LL_RCC_SetCECClockSource + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI + * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CECSEL, CECxSource); +} +#endif /* CEC */ + +#if defined(OCTOSPI1) +/** + * @brief Configure OCTOSPIx kernel clock source + * @rmtoll CCIPR4 OCTOSPISEL LL_RCC_SetOCTOSPIClockSource + * @param OCTOSPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t OCTOSPIxSource) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OCTOSPISEL, OCTOSPIxSource); +} +#endif /* OCTOSPI1 */ + +#if defined(PLAY1) +/** + * @brief Configure PLAY1 kernel clock source + * @rmtoll CCIPR3 PLAY1SEL LL_RCC_SetPLAY1ClockSource + * @param PLAYxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_LSE + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_LSI + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetPLAY1ClockSource(uint32_t PLAYxSource) +{ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_PLAY1SEL, PLAYxSource); +} +#endif /* PLAY1 */ + +#if defined(USB_OTG_FS) +/** + * @brief Configure OTGFSx kernel clock source + * @rmtoll CCIPR4 OTGFSSEL LL_RCC_SetOTGFSClockSource + * @param OTGFSxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_CLK48 (*) + * @retval None + * + * (*) : Available only on STM32H5E5x/STM32H5F5x when OTG_HS PHY is enabled. + */ +__STATIC_INLINE void LL_RCC_SetOTGFSClockSource(uint32_t OTGFSxSource) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OTGFSSEL, OTGFSxSource); +} +#endif /* USB_OTG_FS */ + +#if defined(USB_OTG_HS) +/** + * @brief Configure OTGHSx kernel clock source + * @rmtoll CCIPR4 OTGHSSEL LL_RCC_SetOTGHSClockSource + * @param OTGHSxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGHS_CLKSOURCE_HSE + * @arg @ref LL_RCC_OTGHS_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_OTGHS_CLKSOURCE_HSE_DIV2 + * @arg @ref LL_RCC_OTGHS_CLKSOURCE_PLL1Q_DIV2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOTGHSClockSource(uint32_t OTGHSxSource) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OTGHSSEL, OTGHSxSource); +} +#endif /* USB_OTG_HS */ + +#if defined(RCC_CCIPR4_OTGPHYREFCKSEL) +/** + * @brief Configure OTGPHYx kernel clock source + * @rmtoll CCIPR4 OTGPHYREFCKSEL LL_RCC_SetOTGPHYClockSource + * @param OTGPHYxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_16M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_19_2M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_20M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_24M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_26M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_32M + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOTGPHYClockSource(uint32_t OTGPHYxSource) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OTGPHYREFCKSEL, OTGPHYxSource); +} +#endif /* RCC_CCIPR4_OTGPHYREFCKSEL */ + +#if defined(OCTOSPI2) +/** + * @brief Configure OCTOSPI2 kernel clock source + * @rmtoll CCIPR5 OCTOSPI2SEL LL_RCC_SetOCTOSPI2ClockSource + * @param OCTOSPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OSPI2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_OSPI2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OSPI2_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_OSPI2_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOCTOSPI2ClockSource(uint32_t OCTOSPIxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_OCTOSPI2SEL, OCTOSPIxSource); +} +#endif /* OCTOSPI2 */ + +#if defined(LTDC) +/** + * @brief Configure LTDCx kernel clock source + * @rmtoll CCIPR5 LTDCSEL LL_RCC_SetLTDCClockSource + * @param LTDCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL2R + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t LTDCxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_LTDCSEL, LTDCxSource); +} +#endif /* LTDC */ + +#if defined(ADF1) +/** + * @brief Configure ADF1 kernel clock source + * @rmtoll CCIPR5 ADF1SEL LL_RCC_SetADF1ClockSource + * @param ADFxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PIN + * @arg @ref LL_RCC_ADF1_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADF1ClockSource(uint32_t ADFxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ADF1SEL, ADFxSource); +} +#endif /* ADF1 */ + +#if defined(MDF1) +/** + * @brief Configure MDF1 kernel clock source + * @rmtoll CCIPR5 MDF1SEL LL_RCC_SetMDF1ClockSource + * @param MDFxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PIN + * @arg @ref LL_RCC_MDF1_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetMDF1ClockSource(uint32_t MDFxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_MDF1SEL, MDFxSource); +} +#endif /* MDF1 */ + +#if defined(RCC_CCIPR4_ETHCLKSEL) +/** + * @brief Configure ETH kernel clock source + * @rmtoll CCIPR4 ETHSEL LL_RCC_SetETHClockSource + * @param ETHxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH_CLKSOURCE_HSE + * @arg @ref LL_RCC_ETH_CLKSOURCE_PLL1Q + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHClockSource(uint32_t ETHxSource) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_ETHCLKSEL, ETHxSource); +} +#endif /* RCC_CCIPR4_ETHCLKSEL */ + +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) +/** + * @brief Configure ETHPTP kernel clock source + * @rmtoll CCIPR5 ETHPTPSEL LL_RCC_SetETHPTPClockSource + * @param ETHPTPxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETHPTP_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ETHPTP_CLKSOURCE_PLL1R + * @arg @ref LL_RCC_ETHPTP_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_ETHPTP_CLKSOURCE_PLL3P + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHPTPClockSource(uint32_t ETHPTPxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ETHPTPCLKSEL, ETHPTPxSource); +} +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + +#if defined(RCC_CCIPR5_ETHREFCLKSEL) +/** + * @brief Configure ETHREF kernel clock source + * @rmtoll CCIPR5 ETHREFSEL LL_RCC_SetETHREFClockSource + * @param ETHREFxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETHREF_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_ETHREF_CLKSOURCE_PLL1R + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHREFClockSource(uint32_t ETHREFxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ETHREFCLKSEL, ETHREFxSource); +} +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + +/** + * @brief Configure CLKP Kernel clock source + * @rmtoll CCIPR5 CKPERSEL LL_RCC_SetCLKPClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE + * @arg @ref LL_RCC_CLKP_CLKSOURCE_NONE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CKERPSEL, ClkSource); +} + +#if defined(PLAY1) +/** + * @brief Configure PLAY1 kernel clock divider + * @rmtoll CCIPR3 PLAY1DIV LL_RCC_SetPLAY1ClockDivider + * @param PLAYxDivider This parameter can be one of the following values: + * @arg @ref LL_RCC_PLAY1_CLK_DIV_1 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_2 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_4 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_8 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_16 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_32 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_64 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_128 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_256 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_512 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_1024 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_2048 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_4096 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_8192 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_16384 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_32768 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetPLAY1ClockDivider(uint32_t PLAYxDivider) +{ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_PLAY1DIV, PLAYxDivider); +} +#endif /* PLAY1 */ + +#if defined(RCC_CCIPR4_ETHPTPDIV) +/** + * @brief Configure ETHPTP kernel clock divider + * @rmtoll CCIPR4 ETHPTPDIV LL_RCC_SetETHPTPClockDivider + * @param ETHPTPxDivider This parameter can be one of the following values: + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_1 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_2 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_3 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_4 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_5 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_6 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_7 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_8 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_9 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_10 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_11 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_12 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_13 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_14 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_15 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHPTPClockDivider(uint32_t ETHPTPxDivider) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_ETHPTPDIV, ETHPTPxDivider); +} +#endif /* RCC_CCIPR4_ETHPTPDIV */ + +/** + * @brief Get periph clock source + * @rmtoll CCIPR1 * LL_RCC_GetClockSource\n + * CCIPR2 * LL_RCC_GetClockSource\n + * CCIPR3 * LL_RCC_GetClockSource\n + * CCIPR4 * LL_RCC_GetClockSource\n + * CCIPR5 * LL_RCC_GetClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @arg @ref LL_RCC_USART3_CLKSOURCE + * @arg @ref LL_RCC_USART6_CLKSOURCE (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE (*) + * @arg @ref LL_RCC_UART4_CLKSOURCE (*) + * @arg @ref LL_RCC_UART5_CLKSOURCE (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE (*) + * @arg @ref LL_RCC_UART8_CLKSOURCE (*) + * @arg @ref LL_RCC_UART9_CLKSOURCE (*) + * @arg @ref LL_RCC_UART12_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI1_CLKSOURCE + * @arg @ref LL_RCC_SPI2_CLKSOURCE + * @arg @ref LL_RCC_SPI3_CLKSOURCE + * @arg @ref LL_RCC_SPI4_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE (*) + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C2_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) + * @arg @ref LL_RCC_I3C1_CLKSOURCE + * @arg @ref LL_RCC_I3C2_CLKSOURCE (*) + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*) + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_UART4_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_UART5_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_UART9_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_UART12_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_UART12_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**) + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PIN + * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PIN + * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*) + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL2R (*) + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL2R (*) + * + * (*) value not defined in all devices. + * (**) : For stm32h503xx family line only. + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph) +{ + const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CCIPR1) + LL_CLKSOURCE_REG(Periph))); + return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> \ + LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT)); +} + +/** + * @brief Get USARTx kernel clock source + * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n + * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n + * CCIPR1 USART3SEL LL_RCC_GetUSARTClockSource\n + * CCIPR1 USART6SEL LL_RCC_GetUSARTClockSource\n + * CCIPR1 USART10SEL LL_RCC_GetUSARTClockSource\n + * CCIPR2 USART11SEL LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @arg @ref LL_RCC_USART3_CLKSOURCE + * @arg @ref LL_RCC_USART6_CLKSOURCE (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_USART11_CLKSOURCE_LSE (*) + * + * (*) : For stm32h56xxx and stm32h57xxx family lines only. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return LL_RCC_GetClockSource(USARTx); +} + +#if defined(UART4) +/** + * @brief Get UARTx kernel clock source + * @rmtoll CCIPR1 UART4SEL LL_RCC_GetUARTClockSource\n + * CCIPR1 UART5SEL LL_RCC_GetUARTClockSource\n + * CCIPR1 UART7SEL LL_RCC_GetUARTClockSource\n + * CCIPR1 UART8SEL LL_RCC_GetUARTClockSource\n + * CCIPR1 UART9SEL LL_RCC_GetUARTClockSource\n + * CCIPR2 UART12SEL LL_RCC_GetUARTClockSource + * @param UARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE + * @arg @ref LL_RCC_UART5_CLKSOURCE + * @arg @ref LL_RCC_UART7_CLKSOURCE + * @arg @ref LL_RCC_UART8_CLKSOURCE + * @arg @ref LL_RCC_UART9_CLKSOURCE + * @arg @ref LL_RCC_UART12_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_CSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_CSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART9_CLKSOURCE_CSI + * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART12_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_UART12_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI + * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) +{ + return LL_RCC_GetClockSource(UARTx); +} +#endif /* UART4 */ + +/** + * @brief Get LPUARTx kernel clock source + * @rmtoll CCIPR3 LPUART1SEL LL_RCC_GetLPUARTClockSource + * @param LPUARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * + * (*) : For stm32h56xxx and stm32h57xxx family lines only. + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR3, LPUARTx)); +} + +/** + * @brief Get I2Cx kernel clock source + * @rmtoll CCIPR4 I2C1SEL LL_RCC_GetI2CClockSource\n + * CCIPR4 I2C2SEL LL_RCC_GetI2CClockSource\n + * CCIPR4 I2C3SEL LL_RCC_GetI2CClockSource\n + * CCIPR4 I2C4SEL LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C2_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI (*) + * + * (*) : For stm32h56xxx and stm32h57xxx family lines only. + * (**) : For stm32h503xx family line only. + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + return LL_RCC_GetClockSource(I2Cx); +} + +/** + * @brief Get I3Cx kernel clock source + * @rmtoll CCIPR4 I3C1SEL LL_RCC_GetI3CClockSource\n + * CCIPR4 I3C2SEL LL_RCC_GetI3CClockSource + * @param I3Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE + * @arg @ref LL_RCC_I3C2_CLKSOURCE (**) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (**) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (**) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (**) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_CSI (***) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**) + * + * (*) : For stm32h56xxx, stm32h57xxx, stm32h5exxx and stm32h5fxxx family lines. + * (**) : For stm32h503xx family line. + * (***) : For stm32h5exxx and stm32h5fxxx family lines. + */ +__STATIC_INLINE uint32_t LL_RCC_GetI3CClockSource(uint32_t I3Cx) +{ + return LL_RCC_GetClockSource(I3Cx); +} + +/** + * @brief Get SPIx kernel clock source + * @rmtoll CCIPR3 SPI1SEL LL_RCC_GetSPIClockSource\n + * CCIPR3 SPI2SEL LL_RCC_GetSPIClockSource\n + * CCIPR3 SPI3SEL LL_RCC_GetSPIClockSource\n + * CCIPR3 SPI4SEL LL_RCC_GetSPIClockSource\n + * CCIPR3 SPI5SEL LL_RCC_GetSPIClockSource\n + * CCIPR3 SPI6SEL LL_RCC_GetSPIClockSource + * @param SPIx This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE + * @arg @ref LL_RCC_SPI2_CLKSOURCE + * @arg @ref LL_RCC_SPI3_CLKSOURCE + * @arg @ref LL_RCC_SPI4_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SPI2_CLKSOURCE_PIN + * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PIN + * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*) + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t SPIx) +{ + return LL_RCC_GetClockSource(SPIx); +} + +/** + * @brief Get LPTIMx kernel clock source + * @rmtoll CCIPR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR2 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR2 LPTIM3SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR2 LPTIM4SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR2 LPTIM5SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR2 LPTIM6SEL LL_RCC_GetLPTIMClockSource + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL3R (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSI (*) + * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_CLKP (*) + * + * (*) : For stm32h56xxx and stm32h57xxx family lines. + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +{ + return LL_RCC_GetClockSource(LPTIMx); +} + +/** + * @brief Enable TIM2,15 and LPTIM2 Input capture clock source + * @rmtoll CCIPR1 TIMICSEL LL_RCC_TIMIC_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_TIMIC_Enable(void) +{ + SET_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL); +} + +/** + * @brief Disable TIM2,15 and LPTIM2 Input capture clock source + * @rmtoll CCIPR1 TIMICSEL LL_RCC_TIMIC_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_TIMIC_Disable(void) +{ + CLEAR_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL); +} + +#if defined(RCC_CCIPR4_OTGPDCTRL) + +/** + * @brief Set the power state of the OTG PHY in SUSPEND mode. + * @rmtoll CCIPR4 OTGPDCTRL LL_RCC_OTGPD_Enable + * @param PwrState Specifies the power state to set for the OTG PHY in SUSPEND mode. + * This parameter can be one of the following values: + * @arg RCC_OTGPD_SUSPEND_POWERON: Keep the PHY powered in SUSPEND mode (default after reset). + * @arg RCC_OTGPD_SUSPEND_POWERDOWN: Power down the PHY state machine, bias, and PLL in SUSPEND mode. + * @retval None + */ +__STATIC_INLINE void LL_RCC_OTGPD_SetPWRSuspend(uint32_t PwrState) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OTGPDCTRL, PwrState); +} +#endif /* RCC_CCIPR4_OTGPDCTRL */ +/** + * @brief Get FDCAN kernel clock source + * @rmtoll CCIPR5 FDCANSEL LL_RCC_GetFDCANClockSource + * @param FDCANx This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q + */ +__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR5, FDCANx)); +} + +#if defined(SAI1) +/** + * @brief Get SAIx kernel clock source + * @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n + * CCIPR2 SAI2SEL LL_RCC_GetSAIClockSource + * @param SAIx This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) +{ + return LL_RCC_GetClockSource(SAIx); +} +#endif /* SAI1 */ + +#if defined(SDMMC1) +/** + * @brief Get SDMMCx kernel clock source + * @rmtoll CCIPR4 SDMMC1SEL LL_RCC_GetSDMMCClockSource + * CCIPR4 SDMMC2SEL LL_RCC_GetSDMMCClockSource + * @param SDMMCx This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL2R (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) +{ + return LL_RCC_GetClockSource(SDMMCx); +} +#endif /* SDMMC1 */ + +/** + * @brief Get RNGx kernel clock source + * @rmtoll CCIPR5 RNGSEL LL_RCC_GetRNGClockSource + * @param RNGx This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR5, RNGx)); +} + +#if defined(USB_DRD_FS) +/** + * @brief Get USB clock source + * @rmtoll CCIPR4 USBSEL LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_NONE + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2Q (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + * + * (*) : Available in some STM32H5 lines only. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR4, USBx)); +} +#endif /* USB_DRD_FS */ + +/** + * @brief Get ADCDACx kernel clock source + * @rmtoll CCIPR5 ADCDACSEL LL_RCC_GetADCDACClockSource + * @param ADCDACx This parameter can be one of the following values: + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSI + * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCDACClockSource(uint32_t ADCDACx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR5, ADCDACx)); +} + +/** + * @brief Get DAC low-power kernel Clock Source + * @rmtoll CCIPR5 DACSEL LL_RCC_GetDACLPClockSource + * @param DACLPx This parameter can be one of the following values: + * @arg @ref LL_RCC_DAC_LP_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DAC_LP_CLKSOURCE_LSE + * @arg @ref LL_RCC_DAC_LP_CLKSOURCE_LSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetDACLPClockSource(uint32_t DACLPx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR5, DACLPx)); +} + +/** + * @brief Get CECx kernel clock source + * @rmtoll CCIPR5 CECSEL LL_RCC_GetCECClockSource + * @param CECx This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI + * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122 + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR5, CECx)); +} + +#if defined(OCTOSPI1) +/** + * @brief Get OCTOSPI kernel clock source + * @rmtoll CCIPR4 OCTOSPISEL LL_RCC_GetOCTOSPIClockSource + * @param OCTOSPIx This parameter can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR4, OCTOSPIx)); +} +#endif /* OCTOSPI1 */ + +#if defined(PLAY1) +/** + * @brief Get PLAY1 kernel clock source + * @rmtoll CCIPR3 PLAY1SEL LL_RCC_GetPLAY1ClockSource + * @param PLAYx This parameter can be one of the following values: + * @arg @ref LL_RCC_PLAY1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_LSE + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_LSI + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetPLAY1ClockSource(uint32_t PLAYx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR3, PLAYx)); +} +#endif /* PLAY1 */ + +#if defined(USB_OTG_FS) +/** + * @brief Get OTGFS kernel clock source + * @rmtoll CCIPR4 OTGFSSEL LL_RCC_GetOTGFSClockSource + * @param OTGFSx This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGFS_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_CLK48 (*) + * + * (*) : Available only on STM32H5E5x/STM32H5F5x when OTG_HS PHY is enabled. + */ +__STATIC_INLINE uint32_t LL_RCC_GetOTGFSClockSource(uint32_t OTGFSx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR4, OTGFSx)); +} +#endif /* USB_OTG_FS */ + +#if defined(USB_OTG_HS) +/** + * @brief Get OTGHS kernel clock source + * @rmtoll CCIPR4 OTGHSSEL LL_RCC_GetOTGHSClockSource + * @param OTGHSx This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGHS_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OTGHS_CLKSOURCE_HSE + * @arg @ref LL_RCC_OTGHS_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_OTGHS_CLKSOURCE_HSE_DIV2 + * @arg @ref LL_RCC_OTGHS_CLKSOURCE_PLL1Q_DIV2 + */ +__STATIC_INLINE uint32_t LL_RCC_GetOTGHSClockSource(uint32_t OTGHSx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR4, OTGHSx)); +} +#endif /* USB_OTG_HS */ + +#if defined(RCC_CCIPR4_OTGPHYREFCKSEL) +/** + * @brief Get OTGPHY kernel clock source + * @rmtoll CCIPR4 OTGPHYREFCKSEL LL_RCC_GetOTGPHYClockSource + * @param OTGPHYx This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGPHY_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_16M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_19_2M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_20M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_24M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_26M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_32M + */ +__STATIC_INLINE uint32_t LL_RCC_GetOTGPHYClockSource(uint32_t OTGPHYx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR4, OTGPHYx)); +} +#endif /* RCC_CCIPR4_OTGPHYREFCKSEL */ + +#if defined(OCTOSPI2) +/** + * @brief Get OCTOSPI2 kernel clock source + * @rmtoll CCIPR5 OCTOSPI2SEL LL_RCC_GetOCTOSPI2ClockSource + * @param OCTOSPIx This parameter can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OSPI2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_OSPI2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OSPI2_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_OSPI2_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPI2ClockSource(uint32_t OCTOSPIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR5, OCTOSPIx)); +} +#endif /* OCTOSPI2 */ + +#if defined(LTDC) +/** + * @brief Get LTDC kernel clock source + * @rmtoll CCIPR5 LTDCSEL LL_RCC_GetLTDCClockSource + * @param LTDCx This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL2R + */ +__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR5, LTDCx)); +} +#endif /* LTDC */ + +#if defined(ADF1) +/** + * @brief Get ADF1 kernel clock source + * @rmtoll CCIPR5 ADF1SEL LL_RCC_GetADF1ClockSource + * @param ADFx This parameter can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PIN + * @arg @ref LL_RCC_ADF1_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetADF1ClockSource(uint32_t ADFx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR5, ADFx)); +} +#endif /* ADF1 */ + +#if defined(MDF1) +/** + * @brief Get MDF1 kernel clock source + * @rmtoll CCIPR5 MDF1SEL LL_RCC_GetMDF1ClockSource + * @param MDFx This parameter can be one of the following values: + * @arg @ref LL_RCC_MDF1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PIN + * @arg @ref LL_RCC_MDF1_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetMDF1ClockSource(uint32_t MDFx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR5, MDFx)); +} +#endif /* MDF1 */ + +#if defined(RCC_CCIPR4_ETHCLKSEL) +/* + * @brief Get ETH kernel clock source + * @rmtoll CCIPR4 ETHSEL LL_RCC_GetETHClockSource + * @param ETHx This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ETH_CLKSOURCE_HSE + * @arg @ref LL_RCC_ETH_CLKSOURCE_PLL1Q + */ +__STATIC_INLINE uint32_t LL_RCC_GetETHClockSource(uint32_t ETHx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR4, ETHx)); +} +#endif /* RCC_CCIPR4_ETHCLKSEL */ + +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) +/* + * @brief Get ETHPTP kernel clock source + * @rmtoll CCIPR5 ETHPTPSEL LL_RCC_GetETHPTPClockSource + * @param ETHPTPx This parameter can be one of the following values: + * @arg @ref LL_RCC_ETHPTP_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ETHPTP_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ETHPTP_CLKSOURCE_PLL1R + * @arg @ref LL_RCC_ETHPTP_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_ETHPTP_CLKSOURCE_PLL3P + */ +__STATIC_INLINE uint32_t LL_RCC_GetETHPTPClockSource(uint32_t ETHPTPx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR5, ETHPTPx)); +} +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + +#if defined(RCC_CCIPR5_ETHREFCLKSEL) +/* + * @brief Get ETHREF kernel clock source + * @rmtoll CCIPR5 ETHREFSEL LL_RCC_GetETHREFClockSource + * @param ETHREFx This parameter can be one of the following values: + * @arg @ref LL_RCC_ETHREF_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ETHREF_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_ETHREF_CLKSOURCE_PLL1R + */ +__STATIC_INLINE uint32_t LL_RCC_GetETHREFClockSource(uint32_t ETHREFx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR5, ETHREFx)); +} +#endif /* RCC_CCIPR5_ETHREFCLKSEL */ + +/** + * @brief Get CLKP kernel clock source + * @rmtoll CCIPR5 CKPERSEL LL_RCC_GetCLKPClockSource + * @param CLKPx This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE + * @arg @ref LL_RCC_CLKP_CLKSOURCE_NONE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t CLKPx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR5, CLKPx)); +} + +#if defined(PLAY1) +/** + * @brief Get PLAY1 kernel clock divider + * @rmtoll CCIPR3 PLAY1DIV LL_RCC_GetPLAY1ClockDivider + * @param PLAYx This parameter can be one of the following values: + * @arg @ref LL_RCC_PLAY1_CLKDIVIDER + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLAY1_CLK_DIV_1 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_2 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_4 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_8 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_16 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_32 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_64 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_128 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_256 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_512 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_1024 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_2048 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_4096 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_8192 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_16384 + * @arg @ref LL_RCC_PLAY1_CLK_DIV_32768 + */ +__STATIC_INLINE uint32_t LL_RCC_GetPLAY1ClockDivider(uint32_t PLAYx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR3, PLAYx)); +} +#endif /* PLAY1 */ + +#if defined(RCC_CCIPR4_ETHPTPDIV) +/** + * @brief Get ETHPTP kernel clock divider + * @rmtoll CCIPR4 ETHPTPDIV LL_RCC_GetETHPTPClockDivider + * @param ETHPTPx This parameter can be one of the following values: + * @arg @ref LL_RCC_ETHPTP_CLKDIVIDER + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_1 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_2 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_3 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_4 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_5 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_6 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_7 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_8 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_9 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_10 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_11 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_12 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_13 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_14 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_15 + * @arg @ref LL_RCC_ETHPTP_CLK_DIV_16 + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetETHPTPClockDivider(uint32_t ETHPTPx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR4, ETHPTPx)); +} +#endif /* RCC_CCIPR4_ETHPTPDIV */ +/** + * @brief Configure the Kernel wakeup clock source + * @rmtoll CFGR1 STOPKERWUCK LL_RCC_SetKerWakeUpClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, Source); +} + +/** + * @brief Get the Kernel wakeup clock source + * @rmtoll CFGR1 STOPKERWUCK LL_RCC_GetKerWakeUpClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST); +} + +/** + * @brief Set HSE Prescalers for RTC Clock + * @rmtoll CFGR1 RTCPRE LL_RCC_SetRTC_HSEPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_HSE_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @arg @ref LL_RCC_RTC_HSE_DIV_32 + * @arg @ref LL_RCC_RTC_HSE_DIV_33 + * @arg @ref LL_RCC_RTC_HSE_DIV_34 + * @arg @ref LL_RCC_RTC_HSE_DIV_35 + * @arg @ref LL_RCC_RTC_HSE_DIV_36 + * @arg @ref LL_RCC_RTC_HSE_DIV_37 + * @arg @ref LL_RCC_RTC_HSE_DIV_38 + * @arg @ref LL_RCC_RTC_HSE_DIV_39 + * @arg @ref LL_RCC_RTC_HSE_DIV_40 + * @arg @ref LL_RCC_RTC_HSE_DIV_41 + * @arg @ref LL_RCC_RTC_HSE_DIV_42 + * @arg @ref LL_RCC_RTC_HSE_DIV_43 + * @arg @ref LL_RCC_RTC_HSE_DIV_44 + * @arg @ref LL_RCC_RTC_HSE_DIV_45 + * @arg @ref LL_RCC_RTC_HSE_DIV_46 + * @arg @ref LL_RCC_RTC_HSE_DIV_47 + * @arg @ref LL_RCC_RTC_HSE_DIV_48 + * @arg @ref LL_RCC_RTC_HSE_DIV_49 + * @arg @ref LL_RCC_RTC_HSE_DIV_50 + * @arg @ref LL_RCC_RTC_HSE_DIV_51 + * @arg @ref LL_RCC_RTC_HSE_DIV_52 + * @arg @ref LL_RCC_RTC_HSE_DIV_53 + * @arg @ref LL_RCC_RTC_HSE_DIV_54 + * @arg @ref LL_RCC_RTC_HSE_DIV_55 + * @arg @ref LL_RCC_RTC_HSE_DIV_56 + * @arg @ref LL_RCC_RTC_HSE_DIV_57 + * @arg @ref LL_RCC_RTC_HSE_DIV_58 + * @arg @ref LL_RCC_RTC_HSE_DIV_59 + * @arg @ref LL_RCC_RTC_HSE_DIV_60 + * @arg @ref LL_RCC_RTC_HSE_DIV_61 + * @arg @ref LL_RCC_RTC_HSE_DIV_62 + * @arg @ref LL_RCC_RTC_HSE_DIV_63 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_RTCPRE, Prescaler); +} + +/** + * @brief Get HSE Prescalers for RTC Clock + * @rmtoll CFGR1 RTCPRE LL_RCC_GetRTC_HSEPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_HSE_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @arg @ref LL_RCC_RTC_HSE_DIV_32 + * @arg @ref LL_RCC_RTC_HSE_DIV_33 + * @arg @ref LL_RCC_RTC_HSE_DIV_34 + * @arg @ref LL_RCC_RTC_HSE_DIV_35 + * @arg @ref LL_RCC_RTC_HSE_DIV_36 + * @arg @ref LL_RCC_RTC_HSE_DIV_37 + * @arg @ref LL_RCC_RTC_HSE_DIV_38 + * @arg @ref LL_RCC_RTC_HSE_DIV_39 + * @arg @ref LL_RCC_RTC_HSE_DIV_40 + * @arg @ref LL_RCC_RTC_HSE_DIV_41 + * @arg @ref LL_RCC_RTC_HSE_DIV_42 + * @arg @ref LL_RCC_RTC_HSE_DIV_43 + * @arg @ref LL_RCC_RTC_HSE_DIV_44 + * @arg @ref LL_RCC_RTC_HSE_DIV_45 + * @arg @ref LL_RCC_RTC_HSE_DIV_46 + * @arg @ref LL_RCC_RTC_HSE_DIV_47 + * @arg @ref LL_RCC_RTC_HSE_DIV_48 + * @arg @ref LL_RCC_RTC_HSE_DIV_49 + * @arg @ref LL_RCC_RTC_HSE_DIV_50 + * @arg @ref LL_RCC_RTC_HSE_DIV_51 + * @arg @ref LL_RCC_RTC_HSE_DIV_52 + * @arg @ref LL_RCC_RTC_HSE_DIV_53 + * @arg @ref LL_RCC_RTC_HSE_DIV_54 + * @arg @ref LL_RCC_RTC_HSE_DIV_55 + * @arg @ref LL_RCC_RTC_HSE_DIV_56 + * @arg @ref LL_RCC_RTC_HSE_DIV_57 + * @arg @ref LL_RCC_RTC_HSE_DIV_58 + * @arg @ref LL_RCC_RTC_HSE_DIV_59 + * @arg @ref LL_RCC_RTC_HSE_DIV_60 + * @arg @ref LL_RCC_RTC_HSE_DIV_61 + * @arg @ref LL_RCC_RTC_HSE_DIV_62 + * @arg @ref LL_RCC_RTC_HSE_DIV_63 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE)); +} + + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM + * @{ + */ + +/** + * @brief Set Timers Clock Prescalers + * @rmtoll CFGR1 TIMPRE LL_RCC_SetTIMPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_TIMPRE, Prescaler); +} + +/** + * @brief Get Timers Clock Prescalers + * @rmtoll CFGR1 TIMPRE LL_RCC_GetTIMPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_TIMPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL1 PLL1 + * @{ + */ + +/** + * @brief Enable PLL1 + * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL1ON); +} + +/** + * @brief Disable PLL1 + * @note Cannot be disabled if the PLL1 clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL1_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); +} + +/** + * @brief Check if PLL1 Ready + * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == RCC_CR_PLL1RDY) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL1 P output mapped to SYSCLK + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1P_Enable(void) +{ + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); +} + +/** + * @brief Disable PLL1 P output mapped to SYSCLK + * @note Cannot be disabled if the PLL1 clock is used as the system + * clock + * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1P_Disable(void) +{ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); +} + +/** + * @brief Enable PLL1 Q output + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1Q_Enable(void) +{ + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); +} + +/** + * @brief Disable PLL1 Q output + * @note In order to save power, when the PLL1 Q output of the PLL1 is + * not used, PLL1Q should be 0 + * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1Q_Disable(void) +{ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); +} + +/** + * @brief Enable PLL1 R output + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1R_Enable(void) +{ + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); +} + +/** + * @brief Disable PLL1 R output + * @note In order to save power, when the PLL1 R output of the PLL1 is + * not used, PLL1R should be 0 + * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1R_Disable(void) +{ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); +} + +/** + * @brief Check if PLL1 P is enabled + * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == RCC_PLL1CFGR_PLL1PEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 Q is enabled + * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN) == RCC_PLL1CFGR_PLL1QEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 R is enabled + * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == RCC_PLL1CFGR_PLL1REN) ? 1UL : 0UL); +} + +/** + * @brief Configure PLL1 used for SYSCLK + * @note PLL1 Source, PLL1M, PLL1N and PLL1P can be written only when PLL1 is disabled. + * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_SYS\n + * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_SYS\n + * PLL1CFGR PLL1N LL_RCC_PLL1_ConfigDomain_SYS\n + * PLL1CFGR PLL1R LL_RCC_PLL1_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL1SOURCE_NONE + * @arg @ref LL_RCC_PLL1SOURCE_HSI + * @arg @ref LL_RCC_PLL1SOURCE_CSI + * @arg @ref LL_RCC_PLL1SOURCE_HSE + * @param PLL1M parameter can be a value between 1 and 63 + * @param PLL1P parameter can be a value between 1 and 128 (odd values not allowed) + * @param PLL1N parameter can be a value between 4 and 512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source, uint32_t PLL1M, uint32_t PLL1N, uint32_t PLL1P) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | (PLL1M << RCC_PLL1CFGR_PLL1M_Pos)); + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P, \ + ((PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos)); +} + +/** + * @brief Configure PLL clock source + * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_SetSource + * @param PLL1Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL1SOURCE_NONE + * @arg @ref LL_RCC_PLL1SOURCE_HSI + * @arg @ref LL_RCC_PLL1SOURCE_CSI + * @arg @ref LL_RCC_PLL1SOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetSource(uint32_t PLL1Source) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLL1Source); +} + +/** + * @brief Get the oscillator used as PLL1 clock source. + * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL1SOURCE_NONE + * @arg @ref LL_RCC_PLL1SOURCE_CSI + * @arg @ref LL_RCC_PLL1SOURCE_HSI + * @arg @ref LL_RCC_PLL1SOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC)); +} + +/** + * @brief Set Main PLL1 multiplication factor for VCO + * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_SetN + * @param PLL1N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t PLL1N) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N, (PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos); +} + +/** + * @brief Get Main PLL1 multiplication factor for VCO + * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_GetN + * @retval Between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1UL); +} + +/** + * @brief Set Main PLL1 division factor for PLL1P + * @note Used for System clock + * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_SetP + * @param PLL1P parameter can be a value between 2 and 128 (odd value not allowed) + */ +__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t PLL1P) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos); +} + +/** + * @brief Get PLL1 division factor for PLL1P + * @note Used for System clock + * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_GetP + * @retval Between 2 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL); +} + + +/** + * @brief Set PLL1 division factor for PLL1Q + * @note Used for peripherals clocks + * @rmtoll PLLCFGR PLL1Q LL_RCC_PLL1_SetQ + * @param PLL1Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t PLL1Q) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q, (PLL1Q - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos); +} + +/** + * @brief Get PLL1 division factor for PLL1Q + * @note Used for peripherals clocks + * @rmtoll PLL1CFGR PLL1Q LL_RCC_PLL1_GetQ + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1UL); +} + +/** + * @brief Set PLL1 division factor for PLL1R + * @note Used for trace + * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_SetR + * @param PLL1R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t PLL1R) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos); +} + +/** + * @brief Get Main PLL1 division factor for PLL1R + * @note Used for trace + * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_GetR + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL); +} + +/** + * @brief Set Division factor for the main PLL and other PLL + * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_SetM + * @param PLL1M parameter can be a value between 1 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t PLL1M) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, PLL1M << RCC_PLL1CFGR_PLL1M_Pos); +} + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_GetM + * @retval Between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); +} + +/** + * @brief Enable PLL1 FRACN + * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void) +{ + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN); +} + +/** + * @brief Check if PLL1 FRACN is enabled + * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) == RCC_PLL1CFGR_PLL1FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL1 FRACN + * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN); +} + +/** + * @brief Set PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN, FRACN << RCC_PLL1FRACR_PLL1FRACN_Pos); +} + +/** + * @brief Get PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos); +} + +/** + * @brief Set PLL1 VCO Input Range + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange << RCC_PLL1CFGR_PLL1RGE_Pos); +} + +/** + * @brief Set PLL1 VCO OutputRange + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOutputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1VCOSEL, VCORange << RCC_PLL1CFGR_PLL1VCOSEL_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL2 PLL2 + * @{ + */ + +/** + * @brief Enable PLL2 + * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Disable PLL2 + * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Check if PLL2 Ready + * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == RCC_CR_PLL2RDY) ? 1UL : 0UL); +} + +/** + * @brief Configure PLL2 clock source + * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_SetSource + * @param PLL2Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL2SOURCE_NONE + * @arg @ref LL_RCC_PLL2SOURCE_CSI + * @arg @ref LL_RCC_PLL2SOURCE_HSI + * @arg @ref LL_RCC_PLL2SOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetSource(uint32_t PLL2Source) +{ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, PLL2Source); +} + +/** + * @brief Get the oscillator used as PLL2 clock source. + * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL2SOURCE_NONE + * @arg @ref LL_RCC_PLL2SOURCE_CSI + * @arg @ref LL_RCC_PLL2SOURCE_HSI + * @arg @ref LL_RCC_PLL2SOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC)); +} + +/** + * @brief Set PLL2 Division factor M + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_SetM + * @param PLL2M parameter can be a value between 1 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t PLL2M) +{ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M, PLL2M << RCC_PLL2CFGR_PLL2M_Pos); +} + +/** + * @brief Get PLL2 division factor M + * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_GetM + * @retval Between 1 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos); +} + +/** + * @brief Set PLL2 multiplication factor N + * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_SetN + * @param PLL2N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t PLL2N) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N, (PLL2N - 1UL) << RCC_PLL2DIVR_PLL2N_Pos); +} + +/** + * @brief Get PLL2 multiplication factor N + * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_GetN + * @retval Between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1UL); +} + +/** + * @brief Set PLL2 division factor P + * @note Used for peripherals clocks + * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_SetP + * @param PLL2P parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t PLL2P) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P, (PLL2P - 1UL) << RCC_PLL2DIVR_PLL2P_Pos); +} + +/** + * @brief Get PLL2 division factor P + * @note Used for peripherals clocks + * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_GetP + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1UL); +} + + +/** + * @brief Set PLL2 division factor Q + * @note Used for peripherals clocks + * @rmtoll PLLCFGR PLL2Q LL_RCC_PLL2_SetQ + * @param PLL2Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t PLL2Q) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q, (PLL2Q - 1UL) << RCC_PLL2DIVR_PLL2Q_Pos); +} + +/** + * @brief Get PLL2 division factor Q + * @note Used for peripherals clocks + * @rmtoll PLL2CFGR PLL2Q LL_RCC_PLL2_GetQ + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1UL); +} + +/** + * @brief Set PLL2 division factor R + * @note Used for PLL2CLK selected for peripherals clocks + * @rmtoll PLL2CFGR PLL2Q LL_RCC_PLL2_SetR + * @param PLL2R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t PLL2R) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2R, (PLL2R - 1UL) << RCC_PLL2DIVR_PLL2R_Pos); +} + +/** + * @brief Get PLL2 division factor R + * @note Used for PLL2CLK (system clock) + * @rmtoll PLL2DIVR PLL2R LL_RCC_PLL2_GetR + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + 1UL); +} + +/** + * @brief Enable PLL2 P output + * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2P_Enable(void) +{ + SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); +} + +/** + * @brief Disable PLL2 P output + * @note In order to save power, when PLL2P output is + * not used, it should be disabled (at any time) + * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2P_Disable(void) +{ + CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); +} + +/** + * @brief Enable PLL2 Q output + * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2Q_Enable(void) +{ + SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN); +} + +/** + * @brief Disable PLL2 Q output + * @note In order to save power, when PLL2Q output is + * not used, it should be disabled (at any time) + * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2Q_Disable(void) +{ + CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN); +} + +/** + * @brief Enable PLL2 R output + * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2R_Enable(void) +{ + SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); +} + +/** + * @brief Disable PLL2 R output + * @note In order to save power, when PLL2R output is + * not used, it should be disabled (at any time) + * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2R_Disable(void) +{ + CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); +} + +/** + * @brief Check if PLL2 P is enabled + * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN) == RCC_PLL2CFGR_PLL2PEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 Q is enabled + * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN) == RCC_PLL2CFGR_PLL2QEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 R is enabled + * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN) == RCC_PLL2CFGR_PLL2REN) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL2 FRACN + * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void) +{ + SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN); +} + +/** + * @brief Check if PLL2 FRACN is enabled + * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) == RCC_PLL2CFGR_PLL2FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL2 FRACN + * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN); +} + +/** + * @brief Set PLL2 FRACN Coefficient + * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN, FRACN << RCC_PLL2FRACR_PLL2FRACN_Pos); +} + +/** + * @brief Get PLL2 FRACN Coefficient + * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN) >> RCC_PLL2FRACR_PLL2FRACN_Pos); +} + +/** + * @brief Set PLL2 VCO Input Range + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, InputRange << RCC_PLL2CFGR_PLL2RGE_Pos); +} + +/** + * @brief Set PLL2 VCO OutputRange + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2CFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOutputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2VCOSEL, VCORange << RCC_PLL2CFGR_PLL2VCOSEL_Pos); +} + +/** + * @} + */ + +#if defined(RCC_CR_PLL3ON) +/** @defgroup RCC_LL_EF_PLL3 PLL3 + * @{ + */ + +/** + * @brief Enable PLL3 + * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Disable PLL3 + * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Check if PLL3 is Ready + * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == RCC_CR_PLL3RDY) ? 1UL : 0UL); +} + + +/** + * @brief Configure PLL3 clock source + * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_SetSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL3SOURCE_NONE + * @arg @ref LL_RCC_PLL3SOURCE_CSI + * @arg @ref LL_RCC_PLL3SOURCE_HSI + * @arg @ref LL_RCC_PLL3SOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL3 clock source. + * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL3SOURCE_NONE + * @arg @ref LL_RCC_PLL3SOURCE_CSI + * @arg @ref LL_RCC_PLL3SOURCE_HSI + * @arg @ref LL_RCC_PLL3SOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC)); +} + +/** + * @brief Set PLL3 multiplication factor N + * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_SetN + * @param PLL3N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t PLL3N) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N, (PLL3N - 1UL) << RCC_PLL3DIVR_PLL3N_Pos); +} + +/** + * @brief Get PLL3 multiplication factor N + * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_GetN + * @retval Between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1UL); +} + +/** + * @brief Set PLL3 division factor P + * @note Used for peripherals clocks + * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_SetP + * @param PLL3P parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t PLL3P) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P, (PLL3P - 1UL) << RCC_PLL3DIVR_PLL3P_Pos); +} + +/** + * @brief Get PLL3 division factor P + * @note Used for peripherals clocks + * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_GetP + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1UL); +} + +/** + * @brief Set PLL3 division factor Q + * @note Used for peripherals clocks + * @rmtoll PLLCFGR PLL3Q LL_RCC_PLL3_SetQ + * @param PLL3Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t PLL3Q) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q, (PLL3Q - 1UL) << RCC_PLL3DIVR_PLL3Q_Pos); +} + +/** + * @brief Get PLL3 division factor Q + * @note Used for peripherals clocks + * @rmtoll PLL3CFGR PLL3Q LL_RCC_PLL3_GetQ + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1UL); +} + +/** + * @brief Set PLL3 division factor R + * @note Used for peripherals clocks + * @rmtoll PLL3CFGR PLL3Q LL_RCC_PLL3_SetR + * @param PLL3R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t PLL3R) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R, (PLL3R - 1UL) << RCC_PLL3DIVR_PLL3R_Pos); +} + +/** + * @brief Get PLL3 division factor R + * @note Used for PLL3CLK (system clock) + * @rmtoll PLL3DIVR PLL3R LL_RCC_PLL3_GetR + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1UL); +} + +/** + * @brief Set PLL3 Division factor M + * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_SetM + * @param PLL3M parameter can be a value between 1 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t PLL3M) +{ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M, PLL3M << RCC_PLL3CFGR_PLL3M_Pos); +} + +/** + * @brief Get PLL3 Division factor M + * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_GetM + * @retval Between 1 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos); +} + +/** + * @brief Enable PLL3 P output + * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3P_Enable(void) +{ + SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN); +} + +/** + * @brief Disable PLL3 P output + * @note In order to save power, when PLL3P output is + * not used, it should be disabled (at any time) + * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3P_Disable(void) +{ + CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN); +} + +/** + * @brief Enable PLL3 Q output + * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3Q_Enable(void) +{ + SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); +} + +/** + * @brief Disable PLL3 Q output + * @note In order to save power, when PLL3Q output is + * not used, it should be disabled (at any time) + * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3Q_Disable(void) +{ + CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); +} + +/** + * @brief Enable PLL3 R output + * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3R_Enable(void) +{ + SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); +} + +/** + * @brief Disable PLL3 R output + * @note In order to save power, when PLL3R output is + * not used, it should be disabled (at any time) + * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3R_Disable(void) +{ + CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); +} + +/** + * @brief Check if PLL3 P is enabled + * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN) == RCC_PLL3CFGR_PLL3PEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 Q is enabled + * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN) == RCC_PLL3CFGR_PLL3QEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 R is enabled + * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN) == RCC_PLL3CFGR_PLL3REN) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL3 FRACN + * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void) +{ + SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN); +} + +/** + * @brief Check if PLL3 FRACN is enabled + * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) == RCC_PLL3CFGR_PLL3FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL3 FRACN + * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN); +} + +/** + * @brief Set PLL3 FRACN Coefficient + * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, FRACN << RCC_PLL3FRACR_PLL3FRACN_Pos); +} + +/** + * @brief Get PLL3 FRACN Coefficient + * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN) >> RCC_PLL3FRACR_PLL3FRACN_Pos); +} + +/** + * @brief Set PLL3 VCO Input Range + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, InputRange << RCC_PLL3CFGR_PLL3RGE_Pos); +} + +/** + * @brief Set PLL3 VCO OutputRange + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3CFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOutputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3VCOSEL, VCORange << RCC_PLL3CFGR_PLL3VCOSEL_Pos); +} + +/** + * @} + */ +#endif /* RCC_CR_PLL3ON */ + +/** @defgroup RCC_LL_EF_PRIV Privileged mode + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable Secure Privileged mode + * @rmtoll PRIVCFGR SPRIV LL_RCC_EnableSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableSecPrivilegedMode(void) +{ + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); +} + +/** + * @brief Disable Secure Privileged mode + * @rmtoll PRIVCFGR SPRIV LL_RCC_DisableSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableSecPrivilegedMode(void) +{ + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); +} + +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined(RCC_PRIVCFGR_NSPRIV) +/** + * @brief Enable Non Secure Privileged mode + * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnableNSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableNSecPrivilegedMode(void) +{ + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); +} + +/** + * @brief Disable Non Secure Privileged mode + * @rmtoll PRIVCFGR NSPRIV LL_RCC_DisableNSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableNSecPrivilegedMode(void) +{ + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); +} + +/** + * @brief Check if Secure Privileged mode has been enabled or not + * @rmtoll PRIVCFGR SPRIV LL_RCC_IsEnabledSecPrivilegedMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledSecPrivilegedMode(void) +{ + return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL); +} + +/** + * @brief Check if Non Secure Privileged mode has been enabled or not + * @rmtoll PRIVCFGR NSPRIV LL_RCC_IsEnabledNSecPrivilegedMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledNSecPrivilegedMode(void) +{ + return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL); +} + +#else +/** + * @brief Enable Privileged mode + * @rmtoll PRIVCFGR PRIV LL_RCC_EnablePrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnablePrivilegedMode(void) +{ + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_PRIV); +} + +/** + * @brief Disable Privileged mode + * @rmtoll PRIVCFGR PRIV LL_RCC_DisablePrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisablePrivilegedMode(void) +{ + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_PRIV); +} + +/** + * @brief Check if Privileged mode has been enabled or not + * @rmtoll PRIVCFGR PRIV LL_RCC_IsEnabledPrivilegedMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledPrivilegedMode(void) +{ + return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_PRIV) == RCC_PRIVCFGR_PRIV) ? 1UL : 0UL); +} + +#endif /* RCC_PRIVCFGR_NSPRIV */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} + +/** + * @brief Clear CSI ready interrupt flag + * @rmtoll CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} + + +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); +} + +/** + * @brief Clear PLL1 ready interrupt flag + * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC); +} + +/** + * @brief Clear PLL2 ready interrupt flag + * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC); +} + +#if defined(RCC_CR_PLL3ON) +/** + * @brief Clear PLL3 ready interrupt flag + * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC); +} +#endif /* RCC_CR_PLL3ON */ + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSECSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if CSI ready interrupt occurred or not + * @rmtoll CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == RCC_CIFR_CSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL); +} +/** + * @brief Check if PLL1 ready interrupt occurred or not + * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 ready interrupt occurred or not + * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == RCC_CIFR_PLL2RDYF) ? 1UL : 0UL); +} + +#if defined(RCC_CR_PLL3ON) +/** + * @brief Check if PLL3 ready interrupt occurred or not + * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == RCC_CIFR_PLL3RDYF) ? 1UL : 0UL); +} +#endif /* RCC_CR_PLL3ON */ + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == RCC_CIFR_HSECSSF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll RSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_IWDGRSTF) == RCC_RSR_IWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == RCC_RSR_LPWRRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == RCC_RSR_PINRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == RCC_RSR_SFTRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll RSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_WWDGRSTF) == RCC_RSR_WWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == RCC_RSR_BORRSTF) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll RSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable CSI ready interrupt + * @rmtoll CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} + +/** + * @brief Enable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Enable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +#if defined(RCC_CR_PLL3ON) +/** + * @brief Enable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} +#endif /* RCC_CR_PLL3ON */ + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable CSI ready interrupt + * @rmtoll CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} + +/** + * @brief Disable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Disable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +#if defined(RCC_CR_PLL3ON) +/** + * @brief Disable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} +#endif /* RCC_CR_PLL3ON */ + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if CSI ready interrupt source is enabled or disabled. + * @rmtoll CIER CSIRDYIE LL_RCC_IsEnabledIT_CSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_CSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); +} +/** + * @brief Checks if PLL1 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL2 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL); +} + +#if defined(RCC_CR_PLL3ON) +/** + * @brief Checks if PLL3 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnabledIT_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL); +} +#endif /* RCC_CR_PLL3ON */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Security_Services Security Services + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure RCC resources security + * @note Only available from secure state when system implements security (TZEN=1) + * @rmtoll SECCFGR HSISEC LL_RCC_ConfigSecure\n + * SECCFGR HSESEC LL_RCC_ConfigSecure\n + * SECCFGR CSISEC LL_RCC_ConfigSecure\n + * SECCFGR LSISEC LL_RCC_ConfigSecure\n + * SECCFGR LSESEC LL_RCC_ConfigSecure\n + * SECCFGR SYSCLKSEC LL_RCC_ConfigSecure\n + * SECCFGR PRESCSEC LL_RCC_ConfigSecure\n + * SECCFGR PLL1SEC LL_RCC_ConfigSecure\n + * SECCFGR PLL2SEC LL_RCC_ConfigSecure\n + * SECCFGR PLL3SEC LL_RCC_ConfigSecure\n + * SECCFGR HSI48SEC LL_RCC_ConfigSecure\n + * SECCFGR RMVFSEC LL_RCC_ConfigSecure\n + * SECCFGR CKPERSELSEC LL_RCC_ConfigSecure + * @param Configuration This parameter shall be the full combination of the following values: + * @arg @ref LL_RCC_ALL_SEC or LL_RCC_ALL_NSEC + * @arg @ref LL_RCC_HSI_SEC or LL_RCC_HSI_NSEC + * @arg @ref LL_RCC_HSE_SEC or LL_RCC_HSE_NSEC + * @arg @ref LL_RCC_CSI_SEC or LL_RCC_CSI_NSEC + * @arg @ref LL_RCC_LSE_SEC or LL_RCC_LSE_NSEC + * @arg @ref LL_RCC_LSI_SEC or LL_RCC_LSI_NSEC + * @arg @ref LL_RCC_SYSCLK_SEC or LL_RCC_SYSCLK_NSEC + * @arg @ref LL_RCC_PRESCALERS_SEC or LL_RCC_PRESCALERS_NSEC + * @arg @ref LL_RCC_PLL1_SEC or LL_RCC_PLL1_NSEC + * @arg @ref LL_RCC_PLL2_SEC or LL_RCC_PLL2_NSEC + * @arg @ref LL_RCC_PLL3_SEC or LL_RCC_PLL3_NSEC + * @arg @ref LL_RCC_HSI48_SEC or LL_RCC_HSI48_NSEC + * @arg @ref LL_RCC_RESET_FLAGS_SEC or LL_RCC_RESET_FLAGS_NSEC + * @arg @ref LL_RCC_CKPERSEL_SEC or LL_RCC_CKPERSEL_NSEC + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigSecure(uint32_t Configuration) +{ + WRITE_REG(RCC->SECCFGR, Configuration); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined(RCC_SECCFGR_HSISEC) +/** + * @brief Get RCC resources security status + * @note Only available from secure state when system implements security (TZEN=1) + * @rmtoll SECCFGR HSISEC LL_RCC_GetConfigSecure\n + * SECCFGR HSESEC LL_RCC_GetConfigSecure\n + * SECCFGR CSISEC LL_RCC_GetConfigSecure\n + * SECCFGR LSISEC LL_RCC_GetConfigSecure\n + * SECCFGR LSESEC LL_RCC_GetConfigSecure\n + * SECCFGR SYSCLKSEC LL_RCC_GetConfigSecure\n + * SECCFGR PRESCSEC LL_RCC_GetConfigSecure\n + * SECCFGR PLL1SEC LL_RCC_GetConfigSecure\n + * SECCFGR PLL2SEC LL_RCC_GetConfigSecure\n + * SECCFGR PLL3SEC LL_RCC_GetConfigSecure\n + * SECCFGR HSI48SEC LL_RCC_GetConfigSecure\n + * SECCFGR RMVFSEC LL_RCC_GetConfigSecure\n + * SECCFGR CKPERSELSEC LL_RCC_GetConfigSecure + * @retval Returned value is the combination of the following values: + * @arg @ref LL_RCC_ALL_SEC or LL_RCC_ALL_NSEC + * @arg @ref LL_RCC_HSI_SEC or LL_RCC_HSI_NSEC + * @arg @ref LL_RCC_HSE_SEC or LL_RCC_HSE_NSEC + * @arg @ref LL_RCC_CSI_SEC or LL_RCC_CSI_NSEC + * @arg @ref LL_RCC_LSE_SEC or LL_RCC_LSE_NSEC + * @arg @ref LL_RCC_LSI_SEC or LL_RCC_LSI_NSEC + * @arg @ref LL_RCC_SYSCLK_SEC or LL_RCC_SYSCLK_NSEC + * @arg @ref LL_RCC_PRESCALERS_SEC or LL_RCC_PRESCALERS_NSEC + * @arg @ref LL_RCC_PLL1_SEC or LL_RCC_PLL1_NSEC + * @arg @ref LL_RCC_PLL2_SEC or LL_RCC_PLL2_NSEC + * @arg @ref LL_RCC_PLL3_SEC or LL_RCC_PLL3_NSEC + * @arg @ref LL_RCC_HSI48_SEC or LL_RCC_HSI48_NSEC + * @arg @ref LL_RCC_RESET_FLAGS_SEC or LL_RCC_RESET_FLAGS_NSEC + * @arg @ref LL_RCC_CKPERSEL_SEC or LL_RCC_CKPERSEL_NSEC + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetConfigSecure(void) +{ + return (uint32_t)(READ_BIT(RCC->SECCFGR, RCC_SECURE_MASK)); +} +#endif /* RCC_SECCFGR_HSISEC */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ + +uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR); + +void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks); +void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks); +#if defined(RCC_CR_PLL3ON) +void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks); +#endif /* PLL3 */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *pRCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +#if defined(UART4) +uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); +#endif /* UART4 */ +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource); +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); +#if defined (SAI1) +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +#endif /* SAI1 */ +#if defined(SDMMC1) +uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); +#endif /* SDMMC1 */ +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +#if defined(USB_DRD_FS) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* USB_DRD_FS */ +uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCDACxSource); +uint32_t LL_RCC_GetDACLPClockFreq(uint32_t DACLPxSource); +#if defined(OCTOSPI1) +uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource); +#endif /* OCTOSPI1 */ +uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); +#if defined(CEC) +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +#endif /* CEC */ +#if defined(PLAY1) +uint32_t LL_RCC_GetPLAY1ClockFreq(uint32_t PLAYxSource); +#endif /* PLAY1 */ +#if defined(USB_OTG_FS) +uint32_t LL_RCC_GetOTGFSClockFreq(uint32_t OTGFSxSource); +#endif /* USB_OTG_FS */ +#if defined(USB_OTG_HS) +uint32_t LL_RCC_GetOTGHSClockFreq(uint32_t OTGHSxSource); +#endif /* USB_OTG_HS */ +#if defined(OCTOSPI2) +uint32_t LL_RCC_GetOCTOSPI2ClockFreq(uint32_t OCTOSPIxSource); +#endif /* OCTOSPI2 */ +#if defined(LTDC) +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); +#endif /* LTDC */ +#if defined(ADF1) +uint32_t LL_RCC_GetADF1ClockFreq(uint32_t ADFxSource); +#endif /* ADF1 */ +#if defined(MDF1) +uint32_t LL_RCC_GetMDF1ClockFreq(uint32_t MDFxSource); +#endif /* MDF1 */ +#if defined(RCC_CCIPR4_ETHCLKSEL) +uint32_t LL_RCC_GetETHClockFreq(uint32_t ETHxSource); +#endif /* RCC_CCIPR4_ETHCLKSEL */ +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) +uint32_t LL_RCC_GetETHPTPClockFreq(uint32_t ETHPTPxSource); +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ +#if defined(RCC_CCIPR5_ETHREFCLKSEL) +uint32_t LL_RCC_GetETHREFClockFreq(uint32_t ETHREFxSource); +#endif /* RCC_CCIPR5_ETHREFCLKSEL */ +uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource); +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H5xx_LL_RCC_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h new file mode 100644 index 00000000..adc6168c --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h @@ -0,0 +1,1934 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SBS registers + (+) Access to VREFBUF registers + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_LL_SYSTEM_H +#define STM32H5xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SBS) || defined (DBGMCU) || defined (VREFBUF) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ +#define LL_SBS_HDPL_INCREMENT_VALUE 0x6AU /*!< Define used for the HDPL increment */ +#define LL_SBS_DBG_UNLOCK (0xB4UL << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< Define used to unlock debug */ +#define LL_SBS_ACCESS_PORT_UNLOCK 0xB4U /*!< Define used to unlock access port */ +#define LL_SBS_DBG_CONFIG_LOCK 0xC3U /*!< Define used to lock debug configuration */ +#define LL_SBS_DBG_CONFIG_UNLOCK 0xB4U /*!< Define used to unlock debug configuration */ +#define LL_SBS_DEBUG_SEC_NSEC 0xB4U /*!< Define used to open debug for secure and non-secure */ +#define LL_SBS_DEBUG_NSEC 0x3CU /*!< Define used to open debug for non-secure only */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_SBS_EC_FASTMODEPLUS SBS FASTMODEPLUS + * @{ + */ +#define LL_SBS_FASTMODEPLUS_PB6 SBS_PMCR_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define LL_SBS_FASTMODEPLUS_PB7 SBS_PMCR_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define LL_SBS_FASTMODEPLUS_PB8 SBS_PMCR_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#if defined(SBS_PMCR_PB9_FMP) +#define LL_SBS_FASTMODEPLUS_PB9 SBS_PMCR_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#endif /* SBS_PMCR_PB9_FMP */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_SBS_EC_CS1 SBS Vdd compensation cell Code selection + * @{ + */ +#define LL_SBS_VDD_CELL_CODE 0x0UL /*!< VDD I/Os code from the cell (available in the SBS_CCVALR) */ +#define LL_SBS_VDD_REGISTER_CODE SBS_CCCSR_CS1 /*!< VDD I/Os code from the SBS compensation cell code register (SBS_CCSWCR) */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_SBS_EC_CS2 SBS VddIO compensation cell Code selection + * @{ + */ +#define LL_SBS_VDDIO_CELL_CODE 0x0UL /*!< VDDIO I/Os code from the cell (available in the SBS_CCVALR)*/ +#define LL_SBS_VDDIO_REGISTER_CODE SBS_CCCSR_CS2 /*!< VDDIO I/Os code from the SBS compensation cell code register (SBS_CCSWCR)*/ +/** + * @} + */ + +#if defined(SBS_PMCR_ETH_SEL_PHY) +/** @defgroup SYSTEM_LL_SBS_ETHERNET_CONFIG ETHENET CONFIG + * @{ + */ +#define LL_SBS_ETH_MII 0x0UL /*!< Select the Media Independent Interface (MII) or GMII */ +#define LL_SBS_ETH_RMII SBS_PMCR_ETH_SEL_PHY_2 /*!< Select the Reduced Media Independent Interface (RMII) */ + +/** + * @} + */ +#endif /* SBS_PMCR_ETH_SEL_PHY */ + +/** @defgroup SYSTEM_Memories_Erase_Flag_Status Memories Erase Flags Status + * @{ + */ +#define LL_SBS_MEMORIES_ERASE_MCLR_ON_GOING 0x0UL /*!< Erase after Power-on Reset of SRAM2, BKPRAM, ICACHE, DCACHE and PKA RAMs on going or cleared by SW */ +#define LL_SBS_MEMORIES_ERASE_MCLR_ENDED SBS_MESR_MCLR /*!< Erase after Power-on Reset of SRAM2, BKPRAM, ICACHE, DCACHE and PKA RAMs done */ +#define LL_SBS_MEMORIES_ERASE_IPMEE_ON_GOING 0x0UL /*!< Erase after Power-on Reset or Tamper detection for ICACHE and PKA RAMs on going or cleared by SW */ +#define LL_SBS_MEMORIES_ERASE_IPMEE_ENDED SBS_MESR_IPMEE /*!< Erase after Power-on Reset or Tamper detection for ICACHE and PKA RAMs done */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_SBS_EC_TIMBREAK SBS TIMER BREAK + * @{ + */ +#define LL_SBS_TIMBREAK_ECC SBS_CFGR2_ECCL /*!< Enables and locks the Flash ECC double error signal + with Break Input of TIM1/8/15/16/17 */ +#define LL_SBS_TIMBREAK_PVD SBS_CFGR2_PVDL /*!< Enables and locks the PVD connection + with TIM1/8/15/16/17 Break Input and also the PVDE + and PLS bits of the Power Control Interface */ +#define LL_SBS_TIMBREAK_SRAM_ECC SBS_CFGR2_SEL /*!< Enables and locks the SRAM ECC double error signal + with Break Input of TIM1/8/15/16/17 */ +#define LL_SBS_TIMBREAK_LOCKUP SBS_CFGR2_CLL /*!< Enables and locks the LOCKUP (Hardfault) output of + Cortex-M33 with Break Input of TIM1/15/16/17 */ +/** + * @} + */ + + +/** @defgroup SYSTEM_LL_SBS_EPOCH_Selection EPOCH Selection + * @{ + */ +#define LL_SBS_EPOCH_SEL_NONSECURE 0x0UL /*!< EPOCH non secure selected */ +#define LL_SBS_EPOCH_SEL_SECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH secure selected */ +#define LL_SBS_EPOCH_SEL_PUFCHECK SBS_EPOCHSELCR_EPOCH_SEL_1 /*!< EPOCH all zeros for PUF integrity check */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_SBS_NextHDPL_Selection Next HDPL Selection + * @{ + */ +#define LL_SBS_OBKHDPL_INCR_0 0x00000000U /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define LL_SBS_OBKHDPL_INCR_1 SBS_NEXTHDPLCR_NEXTHDPL_0 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define LL_SBS_OBKHDPL_INCR_2 SBS_NEXTHDPLCR_NEXTHDPL_1 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +#define LL_SBS_OBKHDPL_INCR_3 SBS_NEXTHDPLCR_NEXTHDPL /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_SBS_HDPL_Value HDPL Value + * @{ + */ +#define LL_SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */ +#define LL_SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 1 */ +#define LL_SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 2 */ +#define LL_SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 3 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_SBS_NS_Lock_items Lock items + * @brief SBS non secure items to set lock on + * @{ + */ +#define LL_SBS_MPU_NSEC SBS_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ +#define LL_SBS_VTOR_NSEC SBS_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ +#define LL_SBS_LOCK_ALL_NSEC (LL_SBS_MPU_NSEC | LL_SBS_VTOR_NSEC) /*!< lock all Non-secure (privileged secure or non-secure only) */ +/** + * @} + */ +#if defined(SBS_OTGHSPHYTUNER2_SQRXTUNE) +/** @defgroup SYSTEM_LL_SBS_OTG_SQUELSH OTG High-speed (HS) PHY Squelch threshold adjustment + * @{ + */ +#define LL_SBS_OTGHSPHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ +#define LL_SBS_OTGHSPHY_SQUELCH_0PERCENT (SBS_OTGHSPHYTUNER2_SQRXTUNE_0 | SBS_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ +/** + * @} + */ +#endif /* SBS_OTGHSPHYTUNER2_SQRXTUNE */ + +#if defined(SBS_OTGHSPHYTUNER2_COMPDISTUNE) +/** @defgroup SYSTEM_LL_SBS_OTG_PHYTUNER_DISCONNECT_THRESTHOLD OTG High-speed (HS) PHYTUNER disconnect threshold + * @{ + */ +#define LL_SBS_OTGHSPHY_DISCONNECT_5_9PERCENT SBS_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ +#define LL_SBS_OTGHSPHY_DISCONNECT_0PERCENT SBS_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ +/** + * @} + */ +#endif /* SBS_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE) +/** @defgroup SYSTEM_LL_SBS_OTG_TRANSMITTER_PREEMPHASIS_CURRENT OTG High-speed (HS) transmitter preemphasis current control + * @{ + */ +#define LL_SBS_OTGHSPHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ +#define LL_SBS_OTGHSPHY_PREEMP_1X SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ +#define LL_SBS_OTGHSPHY_PREEMP_2X SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ +#define LL_SBS_OTGHSPHY_PREEMP_3X (SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | \ + SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ +/** + * @} + */ +#endif /* SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** @defgroup SYSTEM_LL_SBS_S_Lock_items SBS Lock items + * @brief SBS secure items to set lock on + * @{ + */ +#define LL_SBS_SAU SBS_CSLCKR_LOCKSAU /*!< SAU lock (privileged secure code only) */ +#define LL_SBS_MPU_SEC SBS_CSLCKR_LOCKSMPU /*!< Secure MPU lock (privileged secure code only) */ +#define LL_SBS_VTOR_AIRCR_SEC SBS_CSLCKR_LOCKSVTAIRCR /*!< VTOR_S and AIRCR lock (privileged secure code only) */ +#define LL_SBS_LOCK_ALL_SEC (LL_SBS_SAU | LL_SBS_MPU_SEC | LL_SBS_VTOR_AIRCR_SEC) /*!< lock all secure (privileged secure only) */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_SBS_EC_SECURE_ATTRIBUTES Secure attributes + * @note Only available when system implements security (TZEN=1) + * @{ + */ +#define LL_SBS_CLOCK_SEC SBS_SECCFGR_SBSSEC /*!< SBS clock configuration secure-only access */ +#define LL_SBS_CLOCK_NSEC 0U /*!< SBS clock configuration secure/non-secure access */ +#define LL_SBS_CLASSB_SEC SBS_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */ +#define LL_SBS_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */ +#define LL_SBS_FPU_SEC SBS_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */ +#define LL_SBS_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */ +/** + * @} + */ +#endif /* __ARM_FEATURE_CMSE */ + +/** @defgroup SYSTEM_LL_DBGMCU_EC_TRACE DBGMCU TRACE Pin Assignment + * @{ + */ +#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ +#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_DBGMCU_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/ +#if defined(TIM4) +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/ +#endif /* TIM4 */ +#if defined(TIM5) +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/ +#endif /* TIM5 */ +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/ +#if defined(TIM12) +#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1FZR1_DBG_TIM12_STOP /*!< The counter clock of TIM12 is stopped when the core is halted*/ +#endif /* TIM12 */ +#if defined(TIM13) +#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1FZR1_DBG_TIM13_STOP /*!< The counter clock of TIM13 is stopped when the core is halted*/ +#endif /* TIM13 */ +#if defined(TIM14) +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1FZR1_DBG_TIM14_STOP /*!< The counter clock of TIM14 is stopped when the core is halted*/ +#endif /* TIM14 */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/ +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/ +#define LL_DBGMCU_APB1_GRP1_I3C1_STOP DBGMCU_APB1FZR1_DBG_I3C1_STOP /*!< The I3C1 SMBus timeout is frozen*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_DBGMCU_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_DBGMCU_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/ +#if defined(TIM8) +#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/ +#endif /* TIM8 */ +#if defined(TIM15) +#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/ +#endif /* TIM15 */ +#if defined(TIM16) +#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/ +#endif /* TIM16 */ +#if defined(TIM17) +#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/ +#endif /* TIM17 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_DBGMCU_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP + * @{ + */ +#if defined(I2C3) +#define LL_DBGMCU_APB3_GRP1_I2C3_STOP DBGMCU_APB3FZR_DBG_I2C3_STOP /*!< The counter clock of I2C3 is stopped when the core is halted*/ +#endif /* I2C3 */ +#if defined(I2C4) +#define LL_DBGMCU_APB3_GRP1_I2C4_STOP DBGMCU_APB3FZR_DBG_I2C4_STOP /*!< The counter clock of I2C4 is stopped when the core is halted*/ +#endif /* I2C4 */ +#if defined(I3C2) +#define LL_DBGMCU_APB3_GRP1_I3C2_STOP DBGMCU_APB3FZR_DBG_I3C2_STOP /*!< The counter clock of I3C2 is stopped when the core is halted*/ +#endif /* I3C2 */ +#define LL_DBGMCU_APB3_GRP1_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/ +#if defined(LPTIM3) +#define LL_DBGMCU_APB3_GRP1_LPTIM3_STOP DBGMCU_APB3FZR_DBG_LPTIM3_STOP /*!< The counter clock of LPTIM3 is stopped when the core is halted*/ +#endif /* LPTIM3 */ +#if defined(LPTIM4) +#define LL_DBGMCU_APB3_GRP1_LPTIM4_STOP DBGMCU_APB3FZR_DBG_LPTIM4_STOP /*!< The counter clock of LPTIM4 is stopped when the core is halted*/ +#endif /* LPTIM4 */ +#if defined(LPTIM5) +#define LL_DBGMCU_APB3_GRP1_LPTIM5_STOP DBGMCU_APB3FZR_DBG_LPTIM5_STOP /*!< The counter clock of LPTIM5 is stopped when the core is halted*/ +#endif /* LPTIM5 */ +#if defined(LPTIM6) +#define LL_DBGMCU_APB3_GRP1_LPTIM6_STOP DBGMCU_APB3FZR_DBG_LPTIM6_STOP /*!< The counter clock of LPTIM6 is stopped when the core is halted*/ +#endif /* LPTIM6 */ +#define LL_DBGMCU_APB3_GRP1_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP /*!< The counter clock of RTC is stopped when the core is halted*/ +/** + * @} + */ + + +#if defined(VREFBUF) +/** @defgroup SYSTEM_LL_VREFBUF_EC_VOLTAGE VREFBUF VOLTAGE + * @{ + */ +#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define LL_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSTEM_LL_FLASH_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH zero wait state */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH one wait state */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH two wait states */ +#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH three wait states */ +#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH four wait states */ +#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait states */ +#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ +#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ +#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ +#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ +#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ +#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ +#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ +#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ +#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ +#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SBS SBS + * @{ + */ + +#if defined(SBS_PMCR_ETH_SEL_PHY) +/** + * @brief Select Ethernet PHY interface + * @rmtoll PMCR EPIS_SEL LL_SBS_SetPHYInterface + * @param Interface This parameter can be one of the following values: + * @arg @ref LL_SBS_ETH_MII + * @arg @ref LL_SBS_ETH_RMII + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetPHYInterface(uint32_t Interface) +{ + MODIFY_REG(SBS->PMCR, SBS_PMCR_ETH_SEL_PHY, Interface); +} + +/** + * @brief Get Ethernet PHY interface + * @rmtoll PMCR EPIS_SEL LL_SBS_GetPHYInterface + * @retval Returned value can be one of the following values: + * @arg @ref LL_SBS_ETH_MII + * @arg @ref LL_SBS_ETH_RMII + */ +__STATIC_INLINE uint32_t LL_SBS_GetPHYInterface(void) +{ + return (uint32_t)(READ_BIT(SBS->PMCR, SBS_PMCR_ETH_SEL_PHY)); +} +#endif /* SBS_PMCR_ETH_SEL_PHY */ + +/** + * @brief Enable the fast mode plus driving capability. + * @rmtoll PMCR PBx_FMP LL_SBS_EnableFastModePlus\n + * PMCR PBx_FMP LL_SBS_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SBS_FASTMODEPLUS_PB6 + * @arg @ref LL_SBS_FASTMODEPLUS_PB7 + * @arg @ref LL_SBS_FASTMODEPLUS_PB8 + * @arg @ref LL_SBS_FASTMODEPLUS_PB9 + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SBS->PMCR, ConfigFastModePlus); +} + +/** + * @brief Disable the fast mode plus driving capability. + * @rmtoll PMCR PBx_FMP LL_SBS_DisableFastModePlus\n + * PMCR PBx_FMP LL_SBS_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SBS_FASTMODEPLUS_PB6 + * @arg @ref LL_SBS_FASTMODEPLUS_PB7 + * @arg @ref LL_SBS_FASTMODEPLUS_PB8 + * @arg @ref LL_SBS_FASTMODEPLUS_PB9 + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SBS->PMCR, ConfigFastModePlus); +} + +/** + * @brief Enable Floating Point Unit Invalid operation Interrupt + * @rmtoll FPUIMR FPU_IE_0 LL_SBS_EnableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_IOC(void) +{ + SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0); +} + +/** + * @brief Enable Floating Point Unit Divide-by-zero Interrupt + * @rmtoll FPUIMR FPU_IE_1 LL_SBS_EnableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_DZC(void) +{ + SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1); +} + +/** + * @brief Enable Floating Point Unit Underflow Interrupt + * @rmtoll FPUIMR FPU_IE_2 LL_SBS_EnableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_UFC(void) +{ + SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2); +} + +/** + * @brief Enable Floating Point Unit Overflow Interrupt + * @rmtoll FPUIMR FPU_IE_3 LL_SBS_EnableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_OFC(void) +{ + SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3); +} + +/** + * @brief Enable Floating Point Unit Input denormal Interrupt + * @rmtoll FPUIMR FPU_IE_4 LL_SBS_EnableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_IDC(void) +{ + SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4); +} + +/** + * @brief Enable Floating Point Unit Inexact Interrupt + * @rmtoll FPUIMR FPU_IE_5 LL_SBS_EnableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_IXC(void) +{ + SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5); +} + +/** + * @brief Disable Floating Point Unit Invalid operation Interrupt + * @rmtoll FPUIMR FPU_IE_0 LL_SBS_DisableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_IOC(void) +{ + CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0); +} + +/** + * @brief Disable Floating Point Unit Divide-by-zero Interrupt + * @rmtoll FPUIMR FPU_IE_1 LL_SBS_DisableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_DZC(void) +{ + CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1); +} + +/** + * @brief Disable Floating Point Unit Underflow Interrupt + * @rmtoll FPUIMR FPU_IE_2 LL_SBS_DisableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_UFC(void) +{ + CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2); +} + +/** + * @brief Disable Floating Point Unit Overflow Interrupt + * @rmtoll FPUIMR FPU_IE_3 LL_SBS_DisableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_OFC(void) +{ + CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3); +} + +/** + * @brief Disable Floating Point Unit Input denormal Interrupt + * @rmtoll FPUIMR FPU_IE_4 LL_SBS_DisableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_IDC(void) +{ + CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4); +} + +/** + * @brief Disable Floating Point Unit Inexact Interrupt + * @rmtoll FPUIMR FPU_IE_5 LL_SBS_DisableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_IXC(void) +{ + CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5); +} + +/** + * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled. + * @rmtoll FPUIMR FPU_IE_0 LL_SBS_IsEnabledIT_FPU_IOC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IOC(void) +{ + return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0) == SBS_FPUIMR_FPU_IE_0) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled. + * @rmtoll FPUIMR FPU_IE_1 LL_SBS_IsEnabledIT_FPU_DZC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_DZC(void) +{ + return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1) == SBS_FPUIMR_FPU_IE_1) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled. + * @rmtoll FPUIMR FPU_IE_2 LL_SBS_IsEnabledIT_FPU_UFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_UFC(void) +{ + return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2) == SBS_FPUIMR_FPU_IE_2) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled. + * @rmtoll FPUIMR FPU_IE_3 LL_SBS_IsEnabledIT_FPU_OFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_OFC(void) +{ + return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3) == SBS_FPUIMR_FPU_IE_3) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled. + * @rmtoll FPUIMR FPU_IE_4 LL_SBS_IsEnabledIT_FPU_IDC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IDC(void) +{ + return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4) == SBS_FPUIMR_FPU_IE_4) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled. + * @rmtoll FPUIMR FPU_IE_5 LL_SBS_IsEnabledIT_FPU_IXC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IXC(void) +{ + return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5) == SBS_FPUIMR_FPU_IE_5) ? 1UL : 0UL); +} + +/** + * @brief Set connections to TIM1/8/15/16/17 Break inputs + * @rmtoll CFGR2 CLL LL_SBS_SetTIMBreakInputs\n + * CFGR2 SEL LL_SBS_SetTIMBreakInputs\n + * CFGR2 PVDL LL_SBS_SetTIMBreakInputs\n + * CFGR2 ECCL LL_SBS_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * where non selected TIMBREAK input is disconnected. + * @arg @ref LL_SBS_TIMBREAK_ECC + * @arg @ref LL_SBS_TIMBREAK_PVD + * @arg @ref LL_SBS_TIMBREAK_SRAM_ECC + * @arg @ref LL_SBS_TIMBREAK_LOCKUP + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetTIMBreakInputs(uint32_t Break) +{ + MODIFY_REG(SBS->CFGR2, SBS_CFGR2_CLL | SBS_CFGR2_SEL | SBS_CFGR2_PVDL | SBS_CFGR2_ECCL, Break); +} + +/** + * @brief Get connections to TIM1/8/15/16/17 Break inputs + * @rmtoll CFGR2 CLL LL_SBS_GetTIMBreakInputs\n + * CFGR2 SEL LL_SBS_GetTIMBreakInputs\n + * CFGR2 PVDL LL_SBS_GetTIMBreakInputs\n + * CFGR2 ECCL LL_SBS_GetTIMBreakInputs + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_SBS_TIMBREAK_ECC + * @arg @ref LL_SBS_TIMBREAK_PVD + * @arg @ref LL_SBS_TIMBREAK_SRAM_ECC + * @arg @ref LL_SBS_TIMBREAK_LOCKUP + */ +__STATIC_INLINE uint32_t LL_SBS_GetTIMBreakInputs(void) +{ + return (uint32_t)(READ_BIT(SBS->CFGR2, SBS_CFGR2_CLL | SBS_CFGR2_SEL | SBS_CFGR2_PVDL | SBS_CFGR2_ECCL)); +} + +#if defined(SBS_EPOCHSELCR_EPOCH_SEL) +/** + * @brief Select EPOCH security sent to SAES IP to encrypt/decrypt keys + * @rmtoll EPOCHSELCR EPOCH_SEL LL_SBS_EPOCHSelection + * @param Epoch_Selection: Select EPOCH security + * This parameter can be one of the following values: + * @arg LL_SBS_EPOCH_SEL_SECURE : EPOCH secure selected. + * @arg LL_SBS_EPOCH_SEL_NONSECURE : EPOCH non secure selected. + * @arg LL_SBS_EPOCH_SEL_PUFCHECK : EPOCH all zeros for PUF integrity check. + * @retval None + */ +__STATIC_INLINE void LL_SBS_EPOCHSelection(uint32_t Epoch_Selection) +{ + MODIFY_REG(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL, (uint32_t)(Epoch_Selection)); +} + +/** + * @brief Get EPOCH security selection + * @rmtoll EPOCHSELCR EPOCH_SEL LL_SBS_GetEPOCHSelection + * @retval Returned value can be one of the following values: + * @arg LL_SBS_EPOCH_SEL_SECURE : EPOCH secure selected. + * @arg LL_SBS_EPOCH_SEL_NONSECURE : EPOCH non secure selected. + * @arg LL_SBS_EPOCH_SEL_PUFCHECK : EPOCH all zeros for PUF integrity check. + */ +__STATIC_INLINE uint32_t LL_SBS_GetEPOCHSelection(void) +{ + return (uint32_t)(READ_BIT(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL)); +} +#endif /* SBS_EPOCHSELCR_EPOCH_SEL */ + +/** + * @brief Disable the NMI in case of double ECC error in FLASH Interface. + * @rmtoll ECCNMIR SBS_ECCNMIR_ECCNMI_MASK_EN LL_SBS_FLASH_DisableECCNMI + * @retval None + */ +__STATIC_INLINE void LL_SBS_FLASH_DisableECCNMI(void) +{ + SET_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN); +} + +/** + * @brief Enable the NMI in case of double ECC error in FLASH Interface. + * @rmtoll ECCNMIR SBS_ECCNMIR_ECCNMI_MASK_EN LL_SBS_FLASH_EnableECCNMI + * @retval None + */ +__STATIC_INLINE void LL_SBS_FLASH_EnableECCNMI(void) +{ + CLEAR_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN); +} + +/** @defgroup SYSTEM_LL_SBS_EF_HDPL_Management HDPL Management + * @{ + */ + +/** + * @brief Increment by 1 the HDPL value + * @rmtoll HDPLCR HDPL_INCR LL_SBS_IncrementHDPLValue + * @retval None + */ +__STATIC_INLINE void LL_SBS_IncrementHDPLValue(void) +{ + MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, LL_SBS_HDPL_INCREMENT_VALUE); +} + +/** + * @brief Get the HDPL Value. + * @rmtoll HDPLSR HDPL LL_SBS_GetHDPLValue + * @retval Returns the HDPL value + * This return value can be one of the following values: + * @arg LL_SBS_HDPL_VALUE_0: HDPL0 + * @arg LL_SBS_HDPL_VALUE_1: HDPL1 + * @arg LL_SBS_HDPL_VALUE_2: HDPL2 + * @arg LL_SBS_HDPL_VALUE_3: HDPL3 + */ +__STATIC_INLINE uint32_t LL_SBS_GetHDPLValue(void) +{ + return (uint32_t)(READ_BIT(SBS->HDPLSR, SBS_HDPLSR_HDPL)); +} + +#if defined(SBS_NEXTHDPLCR_NEXTHDPL) +/** + * @brief Set the OBK-HDPL Value. + * @rmtoll NEXTHDPLCR NEXTHDPL LL_SBS_SetOBKHDPL + * @param OBKHDPL_Value Value of increment to add to HDPL value to generate the OBK-HDPL. + * This parameter can be one of the following values: + * @arg LL_SBS_OBKHDPL_INCR_0 : HDPL + * @arg LL_SBS_OBKHDPL_INCR_1 : HDPL + 1 + * @arg LL_SBS_OBKHDPL_INCR_2 : HDPL + 2 + * @arg LL_SBS_OBKHDPL_INCR_3 : HDPL + 3 + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value) +{ + MODIFY_REG(SBS->NEXTHDPLCR, SBS_NEXTHDPLCR_NEXTHDPL, (uint32_t)(OBKHDPL_Value)); +} + +/** + * @brief Get the OBK-HDPL Value. + * @rmtoll NEXTHDPLCR NEXTHDPL LL_SBS_GetOBKHDPL + * @retval Returns the incremement to add to HDPL value to generate OBK-HDPL + * This return value can be one of the following values: + * @arg LL_SBS_OBKHDPL_INCR_0: HDPL + * @arg LL_SBS_OBKHDPL_INCR_1: HDPL + 1 + * @arg LL_SBS_OBKHDPL_INCR_2: HDPL + 2 + * @arg LL_SBS_OBKHDPL_INCR_3: HDPL + 3 + */ +__STATIC_INLINE uint32_t LL_SBS_GetOBKHDPL(void) +{ + return (uint32_t)(READ_BIT(SBS->NEXTHDPLCR, SBS_NEXTHDPLCR_NEXTHDPL)); +} +#endif /* SBS_NEXTHDPLCR_NEXTHDPL */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_SBS_EF_Debug_Control Debug Control + * @{ + */ + +/** + * @brief Set the authenticated debug hide protection level + * @rmtoll SBS_DBGCR DBG_AUTH_HDPL LL_SBS_SetAuthDbgHDPL + * @param Level This parameter can be one of the following values: + * @arg @ref LL_SBS_HDPL_VALUE_1 + * @arg @ref LL_SBS_HDPL_VALUE_2 + * @arg @ref LL_SBS_HDPL_VALUE_3 + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetAuthDbgHDPL(uint32_t Level) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL, (Level << SBS_DBGCR_DBG_AUTH_HDPL_Pos)); +} + +/** + * @brief Get current hide protection level + * @rmtoll SBS_DBGCR DBG_AUTH_HDPL LL_SBS_GetAuthDbgHDPL + * @retval Returned value is the hide protection level where the authenticated debug is opened: + * @arg @ref LL_SBS_HDPL_VALUE_1 + * @arg @ref LL_SBS_HDPL_VALUE_2 + * @arg @ref LL_SBS_HDPL_VALUE_3 + */ +__STATIC_INLINE uint32_t LL_SBS_GetAuthDbgHDPL(void) +{ + return (uint32_t)(READ_BIT(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL) >> SBS_DBGCR_DBG_AUTH_HDPL_Pos); +} + +#if defined(SBS_DBGCR_DBG_AUTH_SEC) +/** + * @brief Configure the authenticated debug security access. + * @rmtoll SBS_DBGCR DBG_AUTH_SEC LL_SBS_SetAuthDbgSec + * @param Security debug opening secure/non-secure or non-secure only + * This parameter can be one of the following values: + * @arg LL_SBS_DEBUG_SEC_NSEC: debug opening for secure and non-secure. + * @arg LL_SBS_DEBUG_NSEC: debug opening for non-secure only. + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetAuthDbgSec(uint32_t Security) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_SEC, (Security << SBS_DBGCR_DBG_AUTH_SEC_Pos)); +} + +/** + * @brief Get the current value of the hide protection level. + * @rmtoll SBS_DBGCR DBG_AUTH_SEC LL_SBS_GetAuthDbgSec + * @note This function can be only used when device state is Closed. + * @retval Returned value can be one of the following values: + * @arg SBS_DEBUG_SEC_NSEC: debug opening for secure and non-secure. + * @arg any other value: debug opening for non-secure only. + */ +__STATIC_INLINE uint32_t LL_SBS_GetAuthDbgSec(void) +{ + return ((SBS->DBGCR & SBS_DBGCR_DBG_AUTH_SEC) >> SBS_DBGCR_DBG_AUTH_SEC_Pos); +} +#endif /* SBS_DBGCR_DBG_AUTH_SEC */ + +/** + * @brief Unlock the debug + * @rmtoll SBS_DBGCR DBG_UNLOCK LL_SBS_UnlockDebug + * @retval None + */ +__STATIC_INLINE void LL_SBS_UnlockDebug(void) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK, LL_SBS_DBG_UNLOCK); +} + +/** + * @brief Check if the debug is unlocked + * @rmtoll SBS_DBGCR DBG_UNLOCK LL_SBS_IsUnlockedDebug + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsUnlockedDebug(void) +{ + return ((READ_BIT(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK) == LL_SBS_DBG_UNLOCK) ? 1UL : 0UL); +} + +/** + * @brief Unlock the access port + * @rmtoll SBS_DBGCR AP_UNLOCK LL_SBS_UnlockAccessPort + * @retval None + */ +__STATIC_INLINE void LL_SBS_UnlockAccessPort(void) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK, LL_SBS_ACCESS_PORT_UNLOCK); +} + +/** + * @brief Check if the access port is unlocked + * @rmtoll SBS_DBGCR AP_UNLOCK LL_SBS_IsUnlockedAccessPort + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsUnlockedAccessPort(void) +{ + return ((READ_BIT(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK) == LL_SBS_ACCESS_PORT_UNLOCK) ? 1UL : 0UL); +} + +/** + * @brief Lock the debug configuration + * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK LL_SBS_LockDebugConfig + * @retval None + */ +__STATIC_INLINE void LL_SBS_LockDebugConfig(void) +{ + MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, LL_SBS_DBG_CONFIG_LOCK); +} + +/** + * @brief Check if the debug configuration is locked + * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK LL_SBS_IsLockedDebugConfig + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsLockedDebugConfig(void) +{ + return ((READ_BIT(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK) != LL_SBS_DBG_CONFIG_UNLOCK) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_SBS_EF_lock_Management lock Management + * @{ + */ + +/** + * @brief Non-secure Lock of SBS item(s). + * @note Setting lock(s) depends on privilege mode in secure/non-secure code + * Lock(s) cleared only at system reset + * @rmtoll CNSLCKR LOCKNSVTOR LL_SBS_NonSecureLock\n + * CNSLCKR LOCKNSMPU LL_SBS_NonSecureLock + * @param Item Item(s) to set lock on. + * This parameter can be one of the following values : + * @arg LL_SBS_VTOR_NSEC : VTOR_NS register lock + * @arg LL_SBS_MPU_NSEC : Non-secure MPU registers lock + * @arg LL_SBS_LOCK_ALL_NSEC : Non-secure MPU and VTOR_NS lock + * @retval None + */ +__STATIC_INLINE void LL_SBS_NonSecureLock(uint32_t Item) +{ + /* Privilege secure/non-secure locks */ + SBS->CNSLCKR = Item; +} + +/** + * @brief Get the non secure lock state of SBS items. + * @note Getting lock(s) depends on privilege mode in secure/non-secure code + * @rmtoll CNSLCKR LOCKNSVTOR LL_SBS_NonSecureLock\n + * CNSLCKR LOCKNSMPU LL_SBS_NonSecureLock + * @retval the return value can be one of the following values : + * @arg LL_SBS_VTOR_NSEC : VTOR_NS register lock + * @arg LL_SBS_MPU_NSEC : Non-secure MPU registers lock + * @arg LL_SBS_LOCK_ALL_NSEC : VTOR_NS and Non-secure MPU registers lock + */ +__STATIC_INLINE uint32_t LL_SBS_GetNonSecureLock(void) +{ + return (uint32_t)(READ_BIT(SBS->CNSLCKR, LL_SBS_LOCK_ALL_NSEC)); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Secure Lock of System item(s). + * @note Setting lock(s) depends on privilege mode in secure code + * Lock(s) cleared only at system reset + * @rmtoll CSLCKR LOCKSVTAIRCR LL_SBS_SecureLock\n + * CSLCKR LOCKSMPU LL_SBS_SecureLock\n + * CSLCKR LOCKSAU LL_SBS_SecureLock + * @param Item Item(s) to set lock on. + * This parameter can be a combination of the following values : + * @arg LL_SBS_VTOR_AIRCR_SEC : VTOR_S and AIRCR registers lock + * @arg LL_SBS_MPU_SEC : Secure MPU registers lock + * @arg LL_SBS_SAU : SAU registers lock + * @arg LL_SBS_LOCK_ALL_SEC : VTOR_S, AIRCR, Secure MPU and SAU registers lock + * @retval None + */ +__STATIC_INLINE void LL_SBS_SecureLock(uint32_t Item) +{ + /* Privilege secure only locks */ + SBS->CSLCKR = Item; +} + +/** + * @brief Get the secure lock state of System items. + * @note Getting lock(s) depends on privilege mode in secure code + * @rmtoll CSLCKR LOCKSVTAIRCR LL_SBS_GetSecureLock\n + * CSLCKR LOCKSMPU LL_SBS_GetSecureLock\n + * CSLCKR LOCKSAU LL_SBS_GetSecureLock + * @retval the return value is a combination of the following values : + * @arg LL_SBS_VTOR_AIRCR_SEC : VTOR_S and AIRCR registers lock + * @arg LL_SBS_MPU_SEC : Secure MPU registers lock + * @arg LL_SBS_SAU : SAU registers lock + * @arg LL_SBS_LOCK_ALL_SEC : VTOR_S, AIRCR, Secure MPU and SAU registers lock + */ +__STATIC_INLINE uint32_t LL_SBS_GetSecureLock(void) +{ + return (uint32_t)(READ_BIT(SBS->CSLCKR, LL_SBS_LOCK_ALL_SEC)); +} +#endif /* __ARM_FEATURE_CMSE && __ARM_FEATURE_CMSE == 3U */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_SBS_EF_Secure_Management Secure Management + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure Secure mode + * @note Only available from secure state when system implements security (TZEN=1) + * @rmtoll SECCFGR SBSSEC LL_SBS_ConfigSecure\n + * SECCFGR CLASSBSEC LL_SBS_ConfigSecure\n + * SECCFGR FPUSEC LL_SBS_ConfigSecure + * @param Configuration This parameter shall be the full combination + * of the following values: + * @arg @ref LL_SBS_CLOCK_SEC or LL_SBS_CLOCK_NSEC + * @arg @ref LL_SBS_CLASSB_SEC or LL_SBS_CLASSB_NSEC + * @arg @ref LL_SBS_FPU_SEC or LL_SBS_FPU_NSEC + * @retval None + */ +__STATIC_INLINE void LL_SBS_ConfigSecure(uint32_t Configuration) +{ + WRITE_REG(SBS->SECCFGR, Configuration); +} + +/** + * @brief Get Secure mode configuration + * @note Only available when system implements security (TZEN=1) + * @rmtoll SECCFGR SBSSEC LL_SBS_ConfigSecure\n + * SECCFGR CLASSBSEC LL_SBS_ConfigSecure\n + * SECCFGR FPUSEC LL_SBS_ConfigSecure + * @retval Returned value is the combination of the following values: + * @arg @ref LL_SBS_CLOCK_SEC or LL_SBS_CLOCK_NSEC + * @arg @ref LL_SBS_CLASSB_SEC or LL_SBS_CLASSB_NSEC + * @arg @ref LL_SBS_FPU_SEC or LL_SBS_FPU_NSEC + */ +__STATIC_INLINE uint32_t LL_SBS_GetConfigSecure(void) +{ + return (uint32_t)(READ_BIT(SBS->SECCFGR, LL_SBS_CLOCK_SEC | LL_SBS_CLASSB_SEC | LL_SBS_FPU_SEC)); +} +#endif /* __ARM_FEATURE_CMSE && __ARM_FEATURE_CMSE == 3U */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_SBS_EF_COMPENSATION Compensation Cell Control + * @{ + */ + +/** + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD + * @rmtoll CCVALR APSRC1 LL_SBS_GetPMOSVddCompensationValue + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SBS_GetPMOSVddCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_APSRC1)); +} + +/** + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD + * @rmtoll CCVALR ANSRC1 LL_SBS_GetNMOSVddCompensationValue + * @retval Returned value is the NMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SBS_GetNMOSVddCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_ANSRC1)); +} + +/** + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2 + * @rmtoll CCVALR APSRC2 LL_SBS_GetPMOSVddIO2CompensationValue + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SBS_GetPMOSVddIO2CompensationValue(void) +{ + return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_APSRC2)); +} + +/** + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2 + * @rmtoll CCVALR ANSRC2 LL_SBS_GetNMOSVddIO2CompensationValue + * @retval Returned value is the NMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SBS_GetNMOSVddIO2CompensationValue(void) +{ + return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_ANSRC2)); +} + +/** + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD + * @rmtoll CCSWCR SW_APSRC1 LL_SBS_SetPMOSVddCompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the PMOS compensation cell when the CS1 bit of the + * SBS_CCCSR is set + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetPMOSVddCompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC1, PMOSCode << SBS_CCSWCR_SW_APSRC1_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD + * @rmtoll CCSWCR SW_APSRC1 LL_SBS_GetPMOSVddCompensationCode + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SBS_GetPMOSVddCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC1)); +} + +/** + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO + * @rmtoll CCSWCR SW_APSRC2 LL_SBS_SetPMOSVddIOCompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the PMOS compensation cell when the CS2 bit of the + * SBS_CCCSR is set + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetPMOSVddIOCompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC2, PMOSCode << SBS_CCSWCR_SW_APSRC2_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO + * @rmtoll CCSWCR SW_APSRC2 LL_SBS_GetPMOSVddIOCompensationCode + * @retval Returned value is the PMOS compensation + */ +__STATIC_INLINE uint32_t LL_SBS_GetPMOSVddIOCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC2)); +} + +/** + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD + * @rmtoll CCSWCR PCC2 LL_SBS_SetNMOSVddCompensationCode + * @param NMOSCode NMOS compensation code + * This code is applied to the NMOS compensation cell when the CS2 bit of the + * SBS_CCCSR is set + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetNMOSVddCompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC1, NMOSCode << SBS_CCSWCR_SW_ANSRC1_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD + * @rmtoll CCSWCR NCC1 LL_SBS_GetNMOSVddCompensationCode + * @retval Returned value is the Vdd compensation cell code for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SBS_GetNMOSVddCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC1)); +} + +/** + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO + * @rmtoll CCSWCR NCC2 LL_SBS_SetNMOSVddIOCompensationCode + * @param NMOSCode NMOS compensation cell code + * This code is applied to the NMOS compensation cell when the CS2 bit of the + * SBS_CCCSR is set + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetNMOSVddIOCompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC2, NMOSCode << SBS_CCSWCR_SW_ANSRC2_Pos); +} + + +/** + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO + * @rmtoll CCSWCR NCC2 LL_SBS_GetNMOSVddIOCompensationCode + * @retval Returned value is the NMOS compensation cell code + */ +__STATIC_INLINE uint32_t LL_SBS_GetNMOSVddIOCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC2)); +} + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDD + * @rmtoll CCCSR EN1 LL_SBS_EnableVddCompensationCell + * @note The vdd compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableVddCompensationCell(void) +{ + SET_BIT(SBS->CCCSR, SBS_CCCSR_EN1); +} + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDDIO + * @rmtoll CCCSR EN2 LL_SBS_EnableVddIOCompensationCell + * @note The Vdd I/O compensation cell can be used only when the device supply + * voltage ranges from 1.08 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableVddIOCompensationCell(void) +{ + SET_BIT(SBS->CCCSR, SBS_CCCSR_EN2); +} + +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDD + * @rmtoll CCCSR EN1 LL_SBS_DisableVddCompensationCell + * @note The Vdd compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableVddCompensationCell(void) +{ + CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_EN1); +} + +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDDIO + * @rmtoll CCCSR EN2 LL_SBS_DisableVddIOCompensationCell + * @note The Vdd I/O compensation cell can be used only when the device supply + * voltage ranges from 1.08 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableVddIOCompensationCell(void) +{ + CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_EN2); +} + +/** + * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable + * @rmtoll CCCSR EN1 LL_SBS_IsEnabled_VddCompensationCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabled_VddCompensationCell(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_EN1) == SBS_CCCSR_EN1) ? 1UL : 0UL); +} + +/** + * @brief Check if the Compensation Cell of GPIO supplied by VDDIO is enable + * @rmtoll CCCSR EN2 LL_SBS_IsEnabled_VddIOCompensationCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabled_VddIOCompensationCell(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_EN2) == SBS_CCCSR_EN2) ? 1UL : 0UL); +} + +/** + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD + * @rmtoll CCCSR RDY1 LL_SBS_IsActiveFlag_VddCMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsActiveFlag_VddCMPCR(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_RDY1) == (SBS_CCCSR_RDY1)) ? 1UL : 0UL); +} + +/** + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO + * @rmtoll CCCSR RDY2 LL_SBS_IsActiveFlag_VddIOCMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsActiveFlag_VddIOCMPCR(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_RDY2) == (SBS_CCCSR_RDY2)) ? 1UL : 0UL); +} + + +/** + * @brief Set the compensation cell code selection of GPIO supplied by VDD + * @rmtoll CCCSR CS1 LL_SBS_SetVddCellCompensationCode + * @param CompCode: Selects the code to be applied for the Vdd compensation cell + * This parameter can be one of the following values: + * @arg LL_SBS_VDD_CELL_CODE : Select Code from the cell (available in the SBS_CCVALR) + * @arg LL_SBS_VDD_REGISTER_CODE: Select Code from the SBS compensation cell code register (SBS_CCSWCR) + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetVddCellCompensationCode(uint32_t CompCode) +{ + SET_BIT(SBS->CCCSR, CompCode); +} + +/** + * @brief Set the compensation cell code selection of GPIO supplied by VDDIO + * @rmtoll CCCSR CS2 LL_SBS_SetVddIOCellCompensationCode + * @param CompCode: Selects the code to be applied for the VddIO compensation cell + * This parameter can be one of the following values: + * @arg LL_SBS_VDDIO_CELL_CODE : Select Code from the cell (available in the SBS_CCVALR) + * @arg LL_SBS_VDDIO_REGISTER_CODE: Select Code from the SBS compensation cell code register (SBS_CCSWCR) + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetVddIOCellCompensationCode(uint32_t CompCode) +{ + SET_BIT(SBS->CCCSR, CompCode); +} + +/** + * @brief Get the compensation cell code selection of GPIO supplied by VDD + * @rmtoll CCCSR CS1 LL_SBS_GetVddCellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SBS_VDD_CELL_CODE : Selected Code is from the cell (available in the SBS_CCVALR) + * @arg LL_SBS_VDD_REGISTER_CODE: Selected Code is from the SBS compensation cell code register (SBS_CCSWCR) + */ +__STATIC_INLINE uint32_t LL_SBS_GetVddCellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SBS->CCCSR, SBS_CCCSR_CS1)); +} + +/** + * @brief Get the compensation cell code selection of GPIO supplied by VDDIO + * @rmtoll CCCSR CS2 LL_SBS_GetVddIOCellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SBS_VDDIO_CELL_CODE : Selected Code is from the cell (available in the SBS_CCVALR) + * @arg LL_SBS_VDDIO_REGISTER_CODE: Selected Code is from the SBS compensation cell code register (SBS_CCSWCR) + */ +__STATIC_INLINE uint32_t LL_SBS_GetVddIOCellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SBS->CCCSR, SBS_CCCSR_CS2)); +} + +#if defined(SBS_OTGHSPHYTUNER2_COMPDISTUNE) +/** + * @brief Set the OTG high-speed PHY disconnect threshold adjustment. + * @rmtoll SBS_OTGHSPHYTUNER2 COMPDISTUNE LL_SBS_SetOTGPHYDisconnectThresholdAdjustment + * @param DisconnectThreshold This parameter can be one of the following values: + * @arg @ref LL_SBS_OTGHSPHY_DISCONNECT_5_9PERCENT + * @arg @ref LL_SBS_OTGHSPHY_DISCONNECT_0PERCENT + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetOTGPHYDisconnectThresholdAdjustment(uint32_t DisconnectThreshold) +{ + MODIFY_REG(SBS->OTGHSPHYTUNER2, SBS_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold); +} + +/** + * @brief Get the OTG high-speed PHY disconnect threshold adjustment. + * @rmtoll SBS_OTGHSPHYTUNER2 COMPDISTUNE LL_SBS_GetOTGPHYDisconnectThresholdAdjustment + * @retval Returned value can be one of the following values: + * @arg @ref LL_SBS_OTGHSPHY_DISCONNECT_5_9PERCENT + * @arg @ref LL_SBS_OTGHSPHY_DISCONNECT_0PERCENT + */ +__STATIC_INLINE uint32_t LL_SBS_GetOTGPHYDisconnectThresholdAdjustment(void) +{ + return (uint32_t)(READ_BIT(SBS->OTGHSPHYTUNER2, SBS_OTGHSPHYTUNER2_COMPDISTUNE)); +} +#endif /* SBS_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SBS_OTGHSPHYTUNER2_SQRXTUNE) +/** + * @brief Set the voltage level for the threshold used to detect valid high-speed data. + * @rmtoll SBS_OTGHSPHYTUNER2 SQRXTUNE LL_SBS_SetOTGPHYSquelchThresholdAdjustment + * @param SquelchThreshold This parameter can be one of the following values: + * @arg @ref LL_SBS_OTGHSPHY_SQUELCH_15PERCENT + * @arg @ref LL_SBS_OTGHSPHY_SQUELCH_0PERCENT + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetOTGPHYSquelchThresholdAdjustment(uint32_t SquelchThreshold) +{ + MODIFY_REG(SBS->OTGHSPHYTUNER2, SBS_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold); +} + +/** + * @brief Get the voltage level for the threshold used to detect valid high-speed data. + * @rmtoll SBS_OTGHSPHYTUNER2 SQRXTUNE LL_SBS_GetOTGPHYSquelchThresholdAdjustment + * @retval Returned value can be one of the following values: + * @arg @ref LL_SBS_OTGHSPHY_SQUELCH_15PERCENT + * @arg @ref LL_SBS_OTGHSPHY_SQUELCH_0PERCENT + */ +__STATIC_INLINE uint32_t LL_SBS_GetOTGPHYSquelchThresholdAdjustment(void) +{ + return (uint32_t)(READ_BIT(SBS->OTGHSPHYTUNER2, SBS_OTGHSPHYTUNER2_SQRXTUNE)); +} +#endif /* SBS_OTGHSPHYTUNER2_SQRXTUNE */ + +#if defined(SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE) +/** + * @brief Set the OTG high-speed PHY transmitter preemphasis current control. + * @rmtoll SBS_OTGHSPHYTUNER2 TXPREEMPAMPTUNE LL_SBS_SetOTGPHYTransmitterPreemphasisCurrent + * @param PreemphasisCurrent This parameter can be one of the following values: + * @arg @ref LL_SBS_OTGHSPHY_PREEMP_DISABLED + * @arg @ref LL_SBS_OTGHSPHY_PREEMP_1X + * @arg @ref LL_SBS_OTGHSPHY_PREEMP_2X + * @arg @ref LL_SBS_OTGHSPHY_PREEMP_3X + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetOTGPHYTransmitterPreemphasisCurrent(uint32_t PreemphasisCurrent) +{ + MODIFY_REG(SBS->OTGHSPHYTUNER2, SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent); +} + +/** + * @brief Get the OTG high-speed PHY transmitter preemphasis current control. + * @rmtoll SBS_OTGHSPHYTUNER2 TXPREEMPAMPTUNE LL_SBS_GetOTGPHYTransmitterPreemphasisCurrent + * @retval Returned value can be one of the following values: + * @arg @ref LL_SBS_OTGHSPHY_PREEMP_DISABLED + * @arg @ref LL_SBS_OTGHSPHY_PREEMP_1X + * @arg @ref LL_SBS_OTGHSPHY_PREEMP_2X + * @arg @ref LL_SBS_OTGHSPHY_PREEMP_3X + */ +__STATIC_INLINE uint32_t LL_SBS_GetOTGPHYTransmitterPreemphasisCurrent(void) +{ + return (uint32_t)(READ_BIT(SBS->OTGHSPHYTUNER2, SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE)); +} +#endif /* SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_DBGMCU_EF DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415) + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + + +/** + * @brief Enable the Debug Clock Trace + * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN); +} + +/** + * @brief Disable the Debug Clock Trace + * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_DisableTraceClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN); +} + + +/** + * @brief Check if clock trace is enabled or disabled. + * @rmtoll DBGMCU_CR_TRACE_CLKEN LL_DBGMCU_IsEnabledTraceClock + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void) +{ + return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN) == DBGMCU_CR_TRACE_CLKEN) ? 1UL : 0UL); +} + +/** + * @brief Set Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment + * @param PinAssignment This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); +} + +/** + * @brief Get Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZR1, Periphs); +} + +/** + * @brief Freeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZR2, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZR1, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZR2, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZR, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZR, Periphs); +} + +/** + * @brief Freeze APB3 peripherals + * @rmtoll DBGMCU_APB3FZ DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_I2C4_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB3FZR, Periphs); +} + +/** + * @brief Unfreeze APB3 peripherals + * @rmtoll DBGMCU_APB3FZR DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_I2C4_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB3FZR, Periphs); +} + +/** + * @} + */ + +#if defined(VREFBUF) +/** @defgroup SYSTEM_LL_VREFBUF_EF VREFBUF + * @{ + */ + +/** + * @brief Enable Internal voltage reference + * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_Enable(void) +{ + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +/** + * @brief Disable Internal voltage reference + * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_Disable(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +/** + * @brief Enable high impedance (VREF+pin is high impedance) + * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void) +{ + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); +} + +/** + * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output) + * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); +} + +/** + * @brief Set the Voltage reference scale + * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling + * @param Scale This parameter can be one of the following values: + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3 + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale) +{ + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale); +} + +/** + * @brief Get the Voltage reference scale + * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3 + */ +__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS)); +} + +/** + * @brief Check if Voltage reference buffer is ready + * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void) +{ + return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == VREFBUF_CSR_VRR) ? 1UL : 0UL); +} + +/** + * @brief Get the trimming code for VREFBUF calibration + * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming + * @retval Between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) +{ + return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM)); +} + +/** + * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage) + * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming + * @param Value Between 0 and 0x3F + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) +{ + WRITE_REG(VREFBUF->CCR, Value); +} + +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSTEM_LL_FLASH_EF FLASH + * @{ + */ +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @} + */ + + +/** @defgroup SYSTEM_LL_SBS_EF_ERASE_MEMORY_STATUS_CLEAR Erase Memory Status + * @{ + */ + +/** + * @brief Clear Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SBS_ClearEraseEndStatus + * @retval None + */ +__STATIC_INLINE void LL_SBS_ClearEraseEndStatus(void) +{ + WRITE_REG(SBS->MESR, SBS_MESR_IPMEE); +} + +/** + * @brief Get Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SBS_GetEraseEndStatus + * @retval Returned value can be one of the following values: + * @arg LL_SBS_MEMORIES_ERASE_IPMEE_ON_GOING : Erase of ICACHE and PKA RAMs on going or flag cleared by SW + * @arg LL_SBS_MEMORIES_ERASE_IPMEE_ENDED: Erase of ICACHE and PKA RAMs ended + */ +__STATIC_INLINE uint32_t LL_SBS_GetEraseEndStatus(void) +{ + return (uint32_t)(READ_BIT(SBS->MESR, SBS_MESR_IPMEE)); +} + +/** + * @brief Clear Status of End of Erase after Power-on Reset for SRAM2, BKPRAM, ICACHE, DCACHE and PKA RAMs + * @rmtoll MESR MCLR LL_SBS_ClearEraseAfterResetStatus + * @retval None + */ +__STATIC_INLINE void LL_SBS_ClearEraseAfterResetStatus(void) +{ + WRITE_REG(SBS->MESR, SBS_MESR_MCLR); +} + +/** + * @brief Get Status of End of Erase after Power-on Reset for SRAM2, BKPRAM, ICACHE, DCACHE and PKA RAMs + * @rmtoll MESR MCLR LL_SBS_GetEraseAfterResetStatus + * @retval Returned value can be one of the following values: + * @arg LL_SBS_MEMORIES_ERASE_MCLR_ON_GOING : Erase of memories on going or flag cleared by SW + * @arg LL_SBS_MEMORIES_ERASE_MCLR_ENDED: Erase of memories ended + */ +__STATIC_INLINE uint32_t LL_SBS_GetEraseAfterResetStatus(void) +{ + return (uint32_t)(READ_BIT(SBS->MESR, SBS_MESR_MCLR)); +} +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SBS) || defined (DBGMCU) || defined (VREFBUF) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_LL_SYSTEM_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h new file mode 100644 index 00000000..9caf80fe --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h @@ -0,0 +1,376 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H5xx_LL_UTILS_H +#define __STM32H5xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ + +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 63 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetM(). */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetN(). */ + + uint32_t PLLP; /*!< Division for the main system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + odd division factors are not allowed + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetP(). */ + + uint32_t FRACN; /*!< Fractional part of the multiplication factor for PLL VCO. + This parameter can be a value between 0 and 8191 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetFRACN(). */ + + uint32_t VCO_Input; /*!< PLL clock Input range. + This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetVCOInputRange(). */ + + uint32_t VCO_Output; /*!< PLL clock Output range. + This parameter can be a value of @ref RCC_LL_EC_PLLOUTPUTRANGE + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetVCOOutputRange(). */ + +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t SYSCLKDivider; /*!< The System clock (SYSCLK) divider. This clock is derived from the System clock. + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + + uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB3_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB3Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass Analog is enabled */ +#define LL_UTILS_HSEBYPASS_DIGITAL_ON 0x00000002U /*!< HSE Bypass Digital is enabled */ +/** + * @} + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ +#define LL_UTILS_PACKAGETYPE_VFQFPN68 0x00000001U /*!< VFQFPN68 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176 0x00000003U /*!< UFBGA176+25 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP48 0x00000005U /*!< LQFP48 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000006U /*!< UFBGA169 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176 0x00000007U /*!< LQFP176 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000009U /*!< UFQFPN32 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x0000000AU /*!< LQFP100 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000BU /*!< UFBGA176+25 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x0000000DU /*!< LQFP176 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000EU /*!< UFBGA169 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP25 0x0000000FU /*!< WLCSP25 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x00000010U /*!< UFQFPN48 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP39 0x00000011U /*!< WLCSP39 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA100 0x00000014U /*!< UFBGA100 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144 0x00000015U /*!< UFBGA144 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144_SMPS 0x00000016U /*!< UFBGA144 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP100_SMPS_USBPHY 0x00000018U /*!< WLCSP100 with internal SMPS USBPHY package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_25_SMPS_USBPHY 0x00000019U /*!< UFBGA176+25 with internal SMPS USBPHY package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS_USBPHY 0x0000001AU /*!< LQFP176 with internal SMPS USBPHY package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA255_SMPS_USBPHY 0x0000001BU /*!< TFBGA1255 with internal SMPS USBPHY package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_USBPHY 0x0000001CU /*!< LQFP144 with USBPHY package type */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); +} + +/** + * @brief Get Package type + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 + * @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48 + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176 + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP25 + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP39 + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100 + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144 + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP100_SMPS_USBPHY + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS_USBPHY + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA255_SMPS_USBPHY + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_USBPHY + * @note Refer to product datasheet for availability of package on a specific device + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ + return (uint32_t)(READ_REG(*((uint16_t *)PACKAGE_BASE_ADDRESS))); +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency); +void LL_Init1msTick_LSE(void); +void LL_Init1msTick_LSI(void); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_PLL_ConfigSystemClock_CSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, + uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H5xx_LL_UTILS_H */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/LICENSE.txt b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/LICENSE.txt new file mode 100644 index 00000000..3edc4d14 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c new file mode 100644 index 00000000..10db2568 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c @@ -0,0 +1,1423 @@ +/** + ********************************************************************************************************************** + * @file stm32h5xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ====================================================================================================================== + ##### How to use this driver ##### + ====================================================================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/* Private define ----------------------------------------------------------------------------------------------------*/ +/** + * @brief STM32H5xx HAL Driver version number 1.6.0 + */ +#define __STM32H5XX_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32H5XX_HAL_VERSION_SUB1 (0x06UL) /*!< [23:16] sub1 version */ +#define __STM32H5XX_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ +#define __STM32H5XX_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ +#define __STM32H5XX_HAL_VERSION ((__STM32H5XX_HAL_VERSION_MAIN << 24U)\ + |(__STM32H5XX_HAL_VERSION_SUB1 << 16U)\ + |(__STM32H5XX_HAL_VERSION_SUB2 << 8U )\ + |(__STM32H5XX_HAL_VERSION_RC)) + +#if defined(VREFBUF) +#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */ +#endif /* VREFBUF */ + +/* Value used to increment hide protection level */ +#define SBS_HDPL_INCREMENT_VALUE (uint8_t)0x6A + +/* Value used to lock/unlock debug functionalities */ +#define SBS_DEBUG_LOCK_VALUE (uint8_t)0xC3 +#define SBS_DEBUG_UNLOCK_VALUE (uint8_t)0xB4 + +/* Private macro -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Exported variables ------------------------------------------------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + ======================================================================================================================= + ##### Initialization and de-initialization functions ##### + ======================================================================================================================= + [..] This section provides functions allowing to: + (+) Initializes the Flash interface the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) De-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief Configure the Flash prefetch, the time base source, NVIC and any required global low + * level hardware by calling the HAL_MspInit() callback function to be optionally defined + * in user file stm32h5xx_hal_msp.c. + * + * @note HAL_Init() function is called at the beginning of program after reset and before + * the clock configuration. + * + * @note In the default implementation the System Timer (SysTick) is used as source of time base. + * The SysTick configuration is based on HSI clock, as HSI is the clock + * used after a system Reset and the NVIC configuration is set to Priority group 4. + * Once done, time base tick starts incrementing: the tick variable counter is incremented + * each 1ms in the SysTick_Handler() interrupt handler. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; + + /* Select HCLK as SysTick clock source */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_APB3_FORCE_RESET(); + __HAL_RCC_APB3_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + +#if defined(AHB4PERIPH_BASE) + __HAL_RCC_AHB4_FORCE_RESET(); + __HAL_RCC_AHB4_RELEASE_RESET(); +#endif /* AHB4PERIPH_BASE */ + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + uint32_t ticknumber = 0U; + uint32_t systicksel; + + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ + if ((uint32_t)uwTickFreq == 0UL) + { + return HAL_ERROR; + } + + /* Check Clock source to calculate the tickNumber */ + if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) == SysTick_CTRL_CLKSOURCE_Msk) + { + /* HCLK selected as SysTick clock source */ + ticknumber = SystemCoreClock / (1000UL / (uint32_t)uwTickFreq); + } + else + { + systicksel = HAL_SYSTICK_GetCLKSourceConfig(); + switch (systicksel) + { + /* HCLK_DIV8 selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_HCLK_DIV8: + /* Calculate tick value */ + ticknumber = (SystemCoreClock / (8000UL / (uint32_t)uwTickFreq)); + break; + /* LSI selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_LSI: + /* Calculate tick value */ + ticknumber = (LSI_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + /* LSE selected as SysTick clock source */ + case SYSTICK_CLKSOURCE_LSE: + /* Calculate tick value */ + ticknumber = (LSE_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + default: + /* Nothing to do */ + break; + } + } + + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(ticknumber) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + ======================================================================================================================= + ##### HAL Control functions ##### + ======================================================================================================================= + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32H5XX_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); +} + +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @} + */ + + +/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions + * @brief HAL Debug functions + * +@verbatim + ======================================================================================================================= + ##### HAL Debug functions ##### + ======================================================================================================================= + [..] This section provides functions allowing to: + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Debug Module during STOP mode. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group4 HAL VREFBUF Control functions + * @brief HAL VREFBUF Control functions + * +@verbatim + ======================================================================================================================= + ##### HAL VREFBUF Control functions ##### + ======================================================================================================================= + [..] This section provides functions allowing to: + (+) Configure the Voltage reference buffer + (+) Enable/Disable the Voltage reference buffer + +@endverbatim + * @{ + */ + +#if defined(VREFBUF) +/** + * @brief Configure the internal voltage reference buffer voltage scale. + * @param VoltageScaling: specifies the output voltage to achieve + * This parameter can be one of the following values: + * @arg VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.5 V. + * This requires VDDA equal to or higher than 2.8 V. + * @arg VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.048 V. + * This requires VDDA equal to or higher than 2.4 V. + * @arg VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.8 V. + * This requires VDDA equal to or higher than 2.1 V. + * @arg VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.5 V. + * This requires VDDA equal to or higher than 1.8 V. + * @retval None + */ +void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param(IS_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); +} + +/** + * @brief Configure the internal voltage reference buffer high impedance mode. + * @param Mode: specifies the high impedance mode + * This parameter can be one of the following values: + * @arg VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. + * @arg VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. + * @retval None + */ +void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode) +{ + /* Check the parameters */ + assert_param(IS_VREFBUF_HIGH_IMPEDANCE(Mode)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); +} + +/** + * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + * @retval None + */ +void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) +{ + /* Check the parameters */ + assert_param(IS_VREFBUF_TRIMMING(TrimmingValue)); + + MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); +} + +/** + * @brief Enable the Internal Voltage Reference buffer (VREFBUF). + * @retval HAL_OK/HAL_TIMEOUT + */ +HAL_StatusTypeDef HAL_EnableVREFBUF(void) +{ + uint32_t tickstart; + + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for VRR bit */ + while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL) + { + if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Internal Voltage Reference buffer (VREFBUF). + * + * @retval None + */ +void HAL_DisableVREFBUF(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} +#endif /* VREFBUF */ + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group5 HAL SBS configuration functions + * @brief HAL SBS configuration functions + * +@verbatim + ======================================================================================================================= + ##### HAL SBS configuration functions ##### + ======================================================================================================================= + [..] This section provides functions allowing to: + (+) Select the Ethernet PHY Interface + (+) Enable/Disable the VDD I/Os Compensation Cell + (+) Code selection/configuration for the VDD I/O Compensation cell + (+) Get ready flag status of VDD I/Os Compensation cell + (+) Get PMOS/NMOS compensation value of the I/Os supplied by VDD + (+) Enable/Disable the NMI in case of double ECC error in FLASH Interface + +@endverbatim + * @{ + */ + +#if defined(SBS_PMCR_ETH_SEL_PHY) +/** + * @brief Ethernet PHY Interface Selection either MII or RMII + * @param SBS_ETHInterface: Selects the Ethernet PHY interface + * This parameter can be one of the following values: + * @arg SBS_ETH_MII : Select the Media Independent Interface + * @arg SBS_ETH_RMII: Select the Reduced Media Independent Interface + * @retval None + */ +void HAL_SBS_ETHInterfaceSelect(uint32_t SBS_ETHInterface) +{ + /* Check the parameter */ + assert_param(IS_SBS_ETHERNET_CONFIG(SBS_ETHInterface)); + + MODIFY_REG(SBS->PMCR, SBS_PMCR_ETH_SEL_PHY, (uint32_t)(SBS_ETHInterface)); +} +#endif /* SBS_PMCR_ETH_SEL_PHY */ + +/** + * @brief Enables the VDD I/Os Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_SBS_EnableVddIO1CompensationCell(void) +{ + SET_BIT(SBS->CCCSR, SBS_CCCSR_EN1) ; +} + +/** + * @brief Power-down the VDD I/Os Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_SBS_DisableVddIO1CompensationCell(void) +{ + CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_EN1); +} + +/** + * @brief Enables the VDDIO2 I/Os Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_SBS_EnableVddIO2CompensationCell(void) +{ + SET_BIT(SBS->CCCSR, SBS_CCCSR_EN2) ; +} + +/** + * @brief Power-down the VDDIO2 I/Os Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_SBS_DisableVddIO2CompensationCell(void) +{ + CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_EN2); +} + +/** + * @brief Code selection for the VDD I/O Compensation cell + * @param SBS_CompCode: Selects the code to be applied for the I/O compensation cell + * This parameter can be one of the following values: + * @arg SBS_VDD_CELL_CODE : Select Code from the cell (available in the SBS_CCVALR) + * @arg SBS_VDD_REGISTER_CODE: Select Code from the SBS compensation cell code register (SBS_CCSWCR) + * @retval None + */ +void HAL_SBS_VDDCompensationCodeSelect(uint32_t SBS_CompCode) +{ + /* Check the parameter */ + assert_param(IS_SBS_VDD_CODE_SELECT(SBS_CompCode)); + MODIFY_REG(SBS->CCCSR, SBS_CCCSR_CS1, (uint32_t)(SBS_CompCode)); +} + +/** + * @brief Code selection for the VDDIO I/O Compensation cell + * @param SBS_CompCode: Selects the code to be applied for the I/O compensation cell + * This parameter can be one of the following values: + * @arg SBS_VDDIO_CELL_CODE : Select Code from the cell (available in the SBS_CCVALR) + * @arg SBS_VDDIO_REGISTER_CODE: Select Code from the SBS compensation cell code register (SBS_CCSWCR) + * @retval None + */ +void HAL_SBS_VDDIOCompensationCodeSelect(uint32_t SBS_CompCode) +{ + /* Check the parameter */ + assert_param(IS_SBS_VDDIO_CODE_SELECT(SBS_CompCode)); + MODIFY_REG(SBS->CCCSR, SBS_CCCSR_CS2, (uint32_t)(SBS_CompCode)); +} + +/** + * @brief VDDIO1 I/O Compensation cell get ready flag status + * @retval State of bit (1 or 0). + */ +uint32_t HAL_SBS_GetVddIO1CompensationCellReadyFlag(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_RDY1) == SBS_CCCSR_RDY1) ? 1UL : 0UL); +} + +/** + * @brief VDDIO2 I/O Compensation cell get ready flag status + * @retval State of bit (1 or 0). + */ +uint32_t HAL_SBS_GetVddIO2CompensationCellReadyFlag(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_RDY2) == SBS_CCCSR_RDY2) ? 1UL : 0UL); +} + +/** + * @brief Code configuration for the VDD I/O Compensation cell + * @param SBS_PMOSCode: PMOS compensation code + * This code is applied to the VDD I/O compensation cell when the CS1 bit of the + * SBS_CCSR is set + * @param SBS_NMOSCode: NMOS compensation code + * This code is applied to the VDD I/O compensation cell when the CS1 bit of the + * SBS_CCSR is set + * @retval None + */ +void HAL_SBS_VDDCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode) +{ + /* Check the parameter */ + assert_param(IS_SBS_CODE_CONFIG(SBS_PMOSCode)); + assert_param(IS_SBS_CODE_CONFIG(SBS_NMOSCode)); + MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC1 | SBS_CCSWCR_SW_APSRC1, (((uint32_t)(SBS_PMOSCode) << 4) | \ + (uint32_t)(SBS_NMOSCode))); +} + +/** + * @brief Code configuration for the VDDIO I/O Compensation cell + * @param SBS_PMOSCode: PMOS compensation code + * This code is applied to the VDDIO I/O compensation cell when the CS2 bit of the + * SBS_CCSR is set + * @param SBS_NMOSCode: NMOS compensation code + * This code is applied to the VDDIO I/O compensation cell when the CS2 bit of the + * SBS_CCSR is set + * @retval None + */ +void HAL_SBS_VDDIOCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode) +{ + /* Check the parameter */ + assert_param(IS_SBS_CODE_CONFIG(SBS_PMOSCode)); + assert_param(IS_SBS_CODE_CONFIG(SBS_NMOSCode)); + MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC2 | SBS_CCSWCR_SW_APSRC2, (((uint32_t)(SBS_PMOSCode) << 12) | \ + ((uint32_t)(SBS_NMOSCode) << 8))); +} + +/** + * @brief Get NMOS compensation value of the I/Os supplied by VDD + * @retval None + */ +uint32_t HAL_SBS_GetNMOSVddCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_ANSRC1)); +} + +/** + * @brief Get PMOS compensation value of the I/Os supplied by VDD + * @retval None + */ +uint32_t HAL_SBS_GetPMOSVddCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_APSRC1) >> SBS_CCVALR_APSRC1_Pos); +} + +/** + * @brief Get NMOS compensation value of the I/Os supplied by VDDIO2 + * @retval None + */ +uint32_t HAL_SBS_GetNMOSVddIO2CompensationValue(void) +{ + return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_ANSRC2) >> SBS_CCVALR_ANSRC2_Pos); +} + + +/** + * @brief Get PMOS compensation value of the I/Os supplied by VDDIO2 + * @retval None + */ +uint32_t HAL_SBS_GetPMOSVddIO2CompensationValue(void) +{ + return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_APSRC2) >> SBS_CCVALR_APSRC2_Pos); +} + +/** + * @brief Disable the NMI in case of double ECC error in FLASH Interface. + * + * @retval None + */ +void HAL_SBS_FLASH_DisableECCNMI(void) +{ + SET_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN); +} + +/** + * @brief Enable the NMI in case of double ECC error in FLASH Interface. + * + * @retval None + */ +void HAL_SBS_FLASH_EnableECCNMI(void) +{ + CLEAR_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN); +} + +/** + * @brief Check if the NMI is Enabled in case of double ECC error in FLASH Interface. + * + * @retval State of bit (1 or 0). + */ +uint32_t HAL_SBS_FLASH_ECCNMI_IsDisabled(void) +{ + return ((READ_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN) == SBS_ECCNMIR_ECCNMI_MASK_EN) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group6 HAL SBS Boot control functions + * @brief HAL SBS Boot functions + * +@verbatim + ======================================================================================================================= + ##### HAL SBS Boot control functions ##### + ======================================================================================================================= + [..] This section provides functions allowing to: + (+) Increment the HDPL value + (+) Get the HDPL value + +@endverbatim + * @{ + */ + +/** + * @brief Increment by 1 the HDPL value + * @retval None + */ +void HAL_SBS_IncrementHDPLValue(void) +{ + MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, SBS_HDPL_INCREMENT_VALUE); +} + +/** + * @brief Get the HDPL Value. + * + * @retval Returns the HDPL value + * This return value can be one of the following values: + * @arg SBS_HDPL_VALUE_0: HDPL0 + * @arg SBS_HDPL_VALUE_1: HDPL1 + * @arg SBS_HDPL_VALUE_2: HDPL2 + * @arg SBS_HDPL_VALUE_3: HDPL3 + */ +uint32_t HAL_SBS_GetHDPLValue(void) +{ + return (uint32_t)(READ_BIT(SBS->HDPLSR, SBS_HDPLSR_HDPL)); +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group7 HAL SBS Hardware secure storage control functions + * @brief HAL SBS Hardware secure storage functions + * +@verbatim + ======================================================================================================================= + ##### HAL SBS Hardware secure storage control functions ##### + ======================================================================================================================= + [..] This section provides functions allowing to: + (+) Select EPOCH security sent to SAES IP + (+) Set/Get EPOCH security selection + (+) Set/Get the OBK-HDPL Value + +@endverbatim + * @{ + */ + +#if defined(SBS_EPOCHSELCR_EPOCH_SEL) +/** + * @brief Select EPOCH security sent to SAES IP to encrypt/decrypt keys + * @param Epoch_Selection: Select EPOCH security + * This parameter can be one of the following values: + * @arg SBS_EPOCH_SEL_SECURE : EPOCH secure selected. + * @arg SBS_EPOCH_SEL_NONSECURE : EPOCH non secure selected. + * @arg SBS_EPOCH_SEL_PUFCHECK : EPOCH all zeros for PUF integrity check. + * @retval None + */ +void HAL_SBS_EPOCHSelection(uint32_t Epoch_Selection) +{ + /* Check the parameter */ + assert_param(IS_SBS_EPOCH_SELECTION(Epoch_Selection)); + + MODIFY_REG(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL, (uint32_t)(Epoch_Selection)); +} + +/** + * @brief Get EPOCH security selection + * @retval Returned value can be one of the following values: + * @arg SBS_EPOCH_SEL_SECURE : EPOCH secure selected. + * @arg SBS_EPOCH_SEL_NONSECURE : EPOCH non secure selected. + * @arg SBS_EPOCH_SEL_PUFCHECK : EPOCH all zeros for PUF integrity check. + */ +uint32_t HAL_SBS_GetEPOCHSelection(void) +{ + return (uint32_t)(READ_BIT(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL)); +} +#endif /* SBS_EPOCHSELCR_EPOCH_SEL */ + +#if defined(SBS_NEXTHDPLCR_NEXTHDPL) +/** + * @brief Set the OBK-HDPL Value. + * @param OBKHDPL_Value Value of the increment to add to HDPL value to generate the OBK-HDPL. + * This parameter can be one of the following values: + * @arg SBS_OBKHDPL_INCR_0 : HDPL + * @arg SBS_OBKHDPL_INCR_1 : HDPL + 1 + * @arg SBS_OBKHDPL_INCR_2 : HDPL + 2 + * @arg SBS_OBKHDPL_INCR_3 : HDPL + 3 + * @retval None + */ +void HAL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value) +{ + /* Check the parameter */ + assert_param(IS_SBS_OBKHDPL_SELECTION(OBKHDPL_Value)); + + MODIFY_REG(SBS->NEXTHDPLCR, SBS_NEXTHDPLCR_NEXTHDPL, (uint32_t)(OBKHDPL_Value)); +} + +/** + * @brief Get the OBK-HDPL Value. + * @retval Returns the incremement to add to HDPL value to generate OBK-HDPL + * This return value can be one of the following values: + * @arg SBS_OBKHDPL_INCR_0: HDPL + * @arg SBS_OBKHDPL_INCR_1: HDPL + 1 + * @arg SBS_OBKHDPL_INCR_2: HDPL + 2 + * @arg SBS_OBKHDPL_INCR_3: HDPL + 3 + */ +uint32_t HAL_SBS_GetOBKHDPL(void) +{ + return (uint32_t)(READ_BIT(SBS->NEXTHDPLCR, SBS_NEXTHDPLCR_NEXTHDPL)); +} +#endif /* SBS_NEXTHDPLCR_NEXTHDPL */ + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group8 HAL SBS Debug control functions + * @brief HAL SBS Debug functions + * +@verbatim + ======================================================================================================================= + ##### SBS Debug control functions ##### + ======================================================================================================================= + [..] This section provides functions allowing to: + (+) Open the device access port + (+) Open the debug + (+) Configure the authenticated debug HDPL + (+) Get the current value of the hide protection level + (+) Lock the access to the debug control register + (+) Configure/Get the authenticated debug security access + +@endverbatim + * @{ + */ + +/** + * @brief Open the device access port. + * @note This function can be only used when device state is Closed. + * @retval None + */ +void HAL_SBS_OpenAccessPort(void) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK, SBS_DEBUG_UNLOCK_VALUE); +} + +/** + * @brief Open the debug when the hide protection level is authorized. + * @note This function can be only used when device state is Closed. + * @retval None + */ +void HAL_SBS_OpenDebug(void) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK, ((uint32_t)SBS_DEBUG_UNLOCK_VALUE << SBS_DBGCR_DBG_UNLOCK_Pos)); +} + +/** + * @brief Configure the authenticated debug hide protection level. + * @note This function can be only used when device state is Closed. + * @param Level Hide protection level where the authenticated debug opens + * This value is one of @ref SBS_HDPL_Value (except SBS_HDPL_VALUE_0) + * @retval HAL_OK if parameter is correct + * HAL_ERROR otherwise + */ +HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level) +{ + /* Check the parameter */ + assert_param(IS_SBS_HDPL(Level)); + + if (Level != SBS_HDPL_VALUE_0) + { + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL, (Level << SBS_DBGCR_DBG_AUTH_HDPL_Pos)); + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Get the current value of the hide protection level. + * @note This function can be only used when device state is Closed. + * @retval Current hide protection level + * This value is one of @ref SBS_HDPL_Value + */ +uint32_t HAL_SBS_GetDebugLevel(void) +{ + return ((SBS->DBGCR & SBS_DBGCR_DBG_AUTH_HDPL) >> SBS_DBGCR_DBG_AUTH_HDPL_Pos); +} + +/** + * @brief Lock the access to the debug control register. + * @note This function can be only used when device state is Closed. + * @note locking the current debug configuration is released only by a reset. + * @retval None + */ +void HAL_SBS_LockDebugConfig(void) +{ + MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, SBS_DEBUG_LOCK_VALUE); +} + +#if defined(SBS_DBGCR_DBG_AUTH_SEC) +/** + * @brief Configure the authenticated debug security access. + * @param Security debug opening secure/non-secure or non-secure only + * This parameter can be one of the following values: + * @arg SBS_DEBUG_SEC_NSEC: debug opening for secure and non-secure. + * @arg SBS_DEBUG_NSEC: debug opening for non-secure only. + * @retval None + */ +void HAL_SBS_ConfigDebugSecurity(uint32_t Security) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_SEC, (Security << SBS_DBGCR_DBG_AUTH_SEC_Pos)); +} + +/** + * @brief Get the current value of the hide protection level. + * @note This function can be only used when device state is Closed. + * @retval Returned value can be one of the following values: + * @arg SBS_DEBUG_SEC_NSEC: debug opening for secure and non-secure. + * @arg SBS_DEBUG_NSEC: debug opening for non-secure only. + */ +uint32_t HAL_SBS_GetDebugSecurity(void) +{ + return ((SBS->DBGCR & SBS_DBGCR_DBG_AUTH_SEC) >> SBS_DBGCR_DBG_AUTH_SEC_Pos); +} +#endif /* SBS_DBGCR_DBG_AUTH_SEC */ + +#if defined(SBS_OTGHSPHYTUNER2_COMPDISTUNE) +/** + * @brief Set the OTG PHY Disconnect Threshold. + * @param DisconnectThreshold Defines the voltage level for the threshold used to detect a disconnect event. + * This parameter can be one of the following values: + * @arg SBS_OTG_HS_PHY_DISCONNECT_5_9PERCENT: +5.9% (recommended value) + * @arg SBS_OTG_HS_PHY_DISCONNECT_0PERCENT: 0% (default value) + * @retval None + */ + +void HAL_SBS_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold) +{ + /* Check the parameter */ + assert_param(IS_SBS_OTGPHY_DISCONNECT(DisconnectThreshold)); + + MODIFY_REG(SBS->OTGHSPHYTUNER2, SBS_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold); +} + +/** + * @brief Get the current voltage level for the threshold used to detect a disconnect event. + * @retval The returned value can be one of the following values: + * @arg SBS_OTG_HS_PHY_DISCONNECT_5_9PERCENT: +5.9% (recommended value) + * @arg SBS_OTG_HS_PHY_DISCONNECT_0PERCENT: 0% (default value) + */ +uint32_t HAL_SBS_GetOTGPHYDisconnectThreshold(void) +{ + return (uint32_t)(READ_BIT(SBS->OTGHSPHYTUNER2, SBS_OTGHSPHYTUNER2_COMPDISTUNE)); +} +#endif /* SBS_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SBS_OTGHSPHYTUNER2_SQRXTUNE) +/** + * @brief Adjust the voltage level for the threshold used to detect valid high speed data. + * @param SquelchThreshold Defines the voltage level. + * This parameter can be one of the following values: + * @arg SBS_OTG_HS_PHY_SQUELCH_15PERCENT: +15% (recommended value) + * @arg SBS_OTG_HS_PHY_SQUELCH_0PERCENT: 0% (default value) + * @retval None + */ + +void HAL_SBS_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold) +{ + /* Check the parameter */ + assert_param(IS_SBS_OTGPHY_SQUELCH(SquelchThreshold)); + + MODIFY_REG(SBS->OTGHSPHYTUNER2, SBS_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold); +} + +/** + * @brief Get the current voltage level for the threshold used to detect a squelch event. + * @retval The returned value can be one of the following values: + * @arg SBS_OTG_HS_PHY_SQUELCH_15PERCENT: +15% (recommended value) + * @arg SBS_OTG_HS_PHY_SQUELCH_0PERCENT: 0% (default value) + */ +uint32_t HAL_SBS_GetOTGPHYSquelchThreshold(void) +{ + return (uint32_t)(READ_BIT(SBS->OTGHSPHYTUNER2, SBS_OTGHSPHYTUNER2_SQRXTUNE)); +} +#endif /* SBS_OTGHSPHYTUNER2_SQRXTUNE */ + +#if defined(SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE) +/** + * @brief Set the OTG PHY Current config. + * @param PreemphasisCurrent Defines the current configuration. + * This parameter can be one of the following values: + * @arg SBS_OTG_HS_PHY_PREEMP_DISABLED: HS transmitter preemphasis circuit disabled + * @arg SBS_OTG_HS_PHY_PREEMP_1X: HS transmitter preemphasis circuit sources 1x preemphasis current + * @arg SBS_OTG_HS_PHY_PREEMP_2X: HS transmitter preemphasis circuit sources 2x preemphasis current + * @arg SBS_OTG_HS_PHY_PREEMP_3X: HS transmitter preemphasis circuit sources 3x preemphasis current + * @retval None + */ + +void HAL_SBS_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent) +{ + /* Check the parameter */ + assert_param(IS_SBS_OTGPHY_PREEMPHASIS(PreemphasisCurrent)); + + MODIFY_REG(SBS->OTGHSPHYTUNER2, SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent); +} + +/** + * @brief Get the current level for the preemphasis. + * @retval The returned value can be one of the following values: + * @arg SBS_OTG_HS_PHY_PREEMP_DISABLED: HS transmitter preemphasis circuit disabled + * @arg SBS_OTG_HS_PHY_PREEMP_1X: HS transmitter preemphasis circuit sources 1x preemphasis current + * @arg SBS_OTG_HS_PHY_PREEMP_2X: HS transmitter preemphasis circuit sources 2x preemphasis current + * @arg SBS_OTG_HS_PHY_PREEMP_3X: HS transmitter preemphasis circuit sources 3x preemphasis current + */ +uint32_t HAL_SBS_GetOTGPHYPreemphasisCurrent(void) +{ + return (uint32_t)(READ_BIT(SBS->OTGHSPHYTUNER2, SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE)); +} +#endif /* SBS_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */ + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group9 HAL SBS lock management functions + * @brief SBS lock management functions. + * +@verbatim + ======================================================================================================================= + ##### SBS lock functions ##### + ======================================================================================================================= + +@endverbatim + * @{ + */ + +/** + * @brief Lock the SBS item(s). + * @note Setting lock(s) depends on privilege mode in secure/non-secure code + * Lock(s) cleared only at system reset + * @param Item Item(s) to set lock on. + * This parameter can be a combination of @ref SBS_Lock_items + * @retval None + */ +void HAL_SBS_Lock(uint32_t Item) +{ + /* Check the parameters */ + assert_param(IS_SBS_LOCK_ITEMS(Item)); + + /* Privilege secure/non-secure locks */ + SBS->CNSLCKR = (0xFFFFU & Item); /* non-secure lock item in 16 lowest bits */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Privilege secure only locks */ + SBS->CSLCKR = ((0xFFFF0000U & Item) >> 16U); /* Secure-only lock item in 16 highest bits */ +#endif /* __ARM_FEATURE_CMSE */ +} + +/** + * @brief Get the lock state of SBS items. + * @note Getting lock(s) depends on privilege mode in secure/non-secure code + * @param pItem pointer to return locked items + * the return value can be a combination of @ref SBS_Lock_items + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SBS_GetLock(uint32_t *pItem) +{ + uint32_t tmp_lock; + + /* Check null pointer */ + if (pItem == NULL) + { + return HAL_ERROR; + } + + /* Get the non-secure lock state */ + tmp_lock = SBS->CNSLCKR; + + /* Get the secure lock state in secure code */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + tmp_lock |= (SBS->CSLCKR << 16U); +#endif /* __ARM_FEATURE_CMSE */ + + /* Return overall lock status */ + *pItem = tmp_lock; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group10 HAL SBS attributes management functions + * @brief SBS attributes management functions. + * +@verbatim + ======================================================================================================================= + ##### SBS attributes functions ##### + ======================================================================================================================= + +@endverbatim + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure the SBS item attribute(s). + * @note Available attributes are to secure SBS items, so this function is + * only available in secure. + * SBS_FPU item attribute is only configurable through PRIVILEGE transaction. + * @param Item Item(s) to set attributes on. + * This parameter can be a one or a combination of @ref SBS_Attributes_items + * @param Attributes specifies the secure/non-secure attributes. + * @retval None + */ +void HAL_SBS_ConfigAttributes(uint32_t Item, uint32_t Attributes) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_SBS_ITEMS_ATTRIBUTES(Item)); + assert_param(IS_SBS_ATTRIBUTES(Attributes)); + + tmp = SBS->SECCFGR; + + /* Set or reset Item */ + if ((Attributes & SBS_SEC) != 0x00U) + { + tmp |= Item; + } + else + { + tmp &= ~Item; + } + + /* Set secure attributes */ + SBS->SECCFGR = tmp; +} + + +/** + * @brief Get the attribute of a SBS items. + * @note Available attributes have read restrictions, so this function is + * only available in secure + * @param Item Single item to get secure/non-secure attribute from. + * @param pAttributes pointer to return the attribute. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SBS_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) +{ + /* Check null pointer */ + if (pAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SBS_ITEMS_ATTRIBUTES(Item)); + + /* Get the secure attribute state */ + if ((SBS->SECCFGR & Item) != 0U) + { + *pAttributes = SBS_SEC; + } + else + { + *pAttributes = SBS_NSEC; + } + + return HAL_OK; +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c new file mode 100644 index 00000000..28ab504a --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c @@ -0,0 +1,873 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and Configuration functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M33 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest pre-emption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure SysTick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32h5xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + [..] + *** How to configure MPU regions using CORTEX HAL driver *** + ============================================================ + [..] + This section provides functions allowing to configure the Memory Protection Unit (MPU). + + (#) Disable the MPU using HAL_MPU_Disable(). + (#) Configure the necessary MPU memory attributes using HAL_MPU_ConfigMemoryAttributes(). + (#) Configure the necessary MPU regions using HAL_MPU_ConfigRegion() ennsuring that the MPU region configuration + link to the right MPU attributes number. + (#) Enable the MPU using HAL_MPU_Enable() function. + + -@- The memory management fault exception is enabled in HAL_MPU_Enable() function and the system will enter + the memory management fault handler MemManage_Handler() when an illegal memory access is performed. + -@- If the MPU has previously been programmed, disable the unused regions to prevent any previous region + configuration from affecting the new MPU configuration. + -@- MPU APIs ending with '_NS' allow to control the non-secure Memory Protection Unit (MPU_NS) from the + secure context. + + @endverbatim + ****************************************************************************** + + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. + +======================================================================================================================== + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description +======================================================================================================================== + NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority + | | | 4 bits for subpriority +------------------------------------------------------------------------------------------------------------------------ + NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority + | | | 3 bits for subpriority +------------------------------------------------------------------------------------------------------------------------ + NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority +------------------------------------------------------------------------------------------------------------------------ + NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bit for subpriority +------------------------------------------------------------------------------------------------------------------------ + NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bit for subpriority +======================================================================================================================== + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Functions CORTEX Private Functions + * @{ + */ +static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit); +static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @brief NVIC functions + * +@verbatim + ============================================================================== + ##### NVIC functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions for NVIC functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Set the priority grouping field (pre-emption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup: The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, + * 0 bit for subpriority + * @note When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Set the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32h5xxxx.h)) + * @param PreemptPriority: The pre-emption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority: the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enable a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32h5xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disable a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32h5xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiate a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Get the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Get the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32h5xxxx.h)) + * @param PriorityGroup: the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, + * 0 bit for subpriority + * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, + uint32_t *const pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Set Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32h5xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Get Pending Interrupt (read the pending register in the NVIC + * and return the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32h5xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clear the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32h5xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Get active interrupt (read the active register in NVIC and return the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate + * CMSIS device file (stm32h5xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @} + */ + + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @brief SYSTICK functions + * +@verbatim + ============================================================================== + ##### SYSTICK functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions for SYSTICK functionalities + + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + if ((TicksNumb - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + /* Reload value impossible */ + return (1UL); + } + + /* Set reload register */ + WRITE_REG(SysTick->LOAD, (uint32_t)(TicksNumb - 1UL)); + + /* Load the SysTick Counter Value */ + WRITE_REG(SysTick->VAL, 0UL); + + /* Enable SysTick IRQ and SysTick Timer */ + SET_BIT(SysTick->CTRL, (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk)); + + /* Function successful */ + return (0UL); +} + +/** + * @brief Configure the SysTick clock source. + * @param CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + switch (CLKSource) + { + /* Select HCLK as Systick clock source */ + case SYSTICK_CLKSOURCE_HCLK: + SET_BIT(SysTick->CTRL, SYSTICK_CLKSOURCE_HCLK); + break; + /* Select HCLK_DIV8 as Systick clock source */ + case SYSTICK_CLKSOURCE_HCLK_DIV8: + CLEAR_BIT(SysTick->CTRL, SYSTICK_CLKSOURCE_HCLK); + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL, (0x00000000U)); + break; + /* Select LSI as Systick clock source */ + case SYSTICK_CLKSOURCE_LSI: + CLEAR_BIT(SysTick->CTRL, SYSTICK_CLKSOURCE_HCLK); + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL, RCC_CCIPR4_SYSTICKSEL_0); + break; + /* Select LSE as Systick clock source */ + case SYSTICK_CLKSOURCE_LSE: + CLEAR_BIT(SysTick->CTRL, SYSTICK_CLKSOURCE_HCLK); + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL, RCC_CCIPR4_SYSTICKSEL_1); + break; + default: + /* Nothing to do */ + break; + } +} + +/** + * @brief Get the SysTick clock source configuration. + * @retval SysTick clock source that can be one of the following values: + * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + */ +uint32_t HAL_SYSTICK_GetCLKSourceConfig(void) +{ + uint32_t systick_source; + uint32_t systick_rcc_source; + + /* Read SysTick->CTRL register for internal or external clock source */ + if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) != 0U) + { + /* Internal clock source */ + systick_source = SYSTICK_CLKSOURCE_HCLK; + } + else + { + /* External clock source, check the selected one in RCC */ + systick_rcc_source = READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL); + + switch (systick_rcc_source) + { + case (0x00000000U): + systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; + break; + + case (RCC_CCIPR4_SYSTICKSEL_0): + systick_source = SYSTICK_CLKSOURCE_LSI; + break; + + case (RCC_CCIPR4_SYSTICKSEL_1): + systick_source = SYSTICK_CLKSOURCE_LSE; + break; + + default: + systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; + break; + } + } + return systick_source; +} + +/** + * @brief Handle SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group3 + * @brief MPU functions + * +@verbatim + ============================================================================== + ##### MPU functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions for MPU functionalities + + +@endverbatim + * @{ + */ + +/** + * @brief Enable the MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the non-secure MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + + /* Enable the MPU */ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU */ + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable the non-secure MPU. + * @retval None + */ +void HAL_MPU_Disable_NS(void) +{ + __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + + /* Disable fault exceptions */ + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU */ + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Enable the MPU Region. + * @param RegionNumber Specifies the index of the region to enable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the MPU_NS Region. + * @param RegionNumber Specifies the index of the region to enable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + * @retval None + */ +void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER_NS(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Disable the MPU Region. + * @param RegionNumber Specifies the index of the region to disable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable the MPU_NS Region. + * @param RegionNumber Specifies the index of the region to disable. + * this parameter can be a value of @ref CORTEX_MPU_Region_Number + * @retval None + */ +void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER_NS(RegionNumber)); + + /* Set the Region number */ + MPU_NS->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Initialize and configure the Region and the memory to be protected. + * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit) +{ + MPU_ConfigRegion(MPU, pMPU_RegionInit); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Initialize and configure the Region and the memory to be protected for non-secure MPU. + * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit) +{ + MPU_ConfigRegion(MPU_NS, pMPU_RegionInit); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Initialize and configure the memory attributes. + * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit) +{ + MPU_ConfigMemoryAttributes(MPU, pMPU_AttributesInit); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Initialize and configure the memory attributes for non-secure MPU. + * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit) +{ + MPU_ConfigMemoryAttributes(MPU_NS, pMPU_AttributesInit); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CORTEX_Private_Functions + * @{ + */ +/** + * @brief Initialize and configure the Region and the memory to be protected for MPU. + * @param MPUx: Pointer to MPU_Type structure + * This parameter can be one of the following values: + * @arg MPU + * @arg MPU_NS + * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit) +{ + /* Check the parameters */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + assert_param(IS_MPU_INSTANCE(MPUx)); +#endif /* __ARM_FEATURE_CMSE */ + assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number)); + assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission)); + assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable)); + + /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */ + __DMB(); + + /* Set the Region number */ + MPUx->RNR = pMPU_RegionInit->Number; + + /* Disable the Region */ + CLEAR_BIT(MPUx->RLAR, MPU_RLAR_EN_Msk); + + MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) | + ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | + ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | + ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); + + MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) | + ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | + ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); +} + +/** + * @brief Initialize and configure the memory attributes for MPU. + * @param MPUx: Pointer to MPU_Type structure + * This parameter can be one of the following values: + * @arg MPU + * @arg MPU_NS + * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit) +{ + __IO uint32_t *p_mair; + uint32_t attr_values; + uint32_t attr_number; + + /* Check the parameters */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + assert_param(IS_MPU_INSTANCE(MPUx)); +#endif /* __ARM_FEATURE_CMSE */ + assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_AttributesInit->Number)); + /* No need to check Attributes value as all 0x0..0xFF possible */ + + /* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */ + __DMB(); + + if (pMPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4) + { + /* Program MPU_MAIR0 */ + p_mair = &(MPUx->MAIR0); + attr_number = pMPU_AttributesInit->Number; + } + else + { + /* Program MPU_MAIR1 */ + p_mair = &(MPUx->MAIR1); + attr_number = (uint32_t)pMPU_AttributesInit->Number - 4U; + } + + attr_values = *(p_mair); + attr_values &= ~(0xFFUL << (attr_number * 8U)); + *(p_mair) = attr_values | ((uint32_t)pMPU_AttributesInit->Attributes << (attr_number * 8U)); +} +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c new file mode 100644 index 00000000..cc1ab31e --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c @@ -0,0 +1,1722 @@ +/** + ********************************************************************************************************************** + * @file stm32h5xx_hal_dma.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following functionalities of the Direct Memory Access + * (DMA) peripheral: + * + Initialization/De-Initialization Functions + * + I/O Operation Functions + * + State and Errors Functions + * + DMA Attributes Functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + @verbatim + ====================================================================================================================== + ##### How to use this driver ##### + ====================================================================================================================== + + + [..] + DMA transfer modes are divided to 2 major categories : + (+) Normal transfers (legacy) + (+) Linked-list transfers + + [..] + Normal transfers mode is initialized via the standard module and linked-list mode is configured via the extended + module. + + [..] + Additionally to linked-list capability, all advanced DMA features are managed and configured via the extended + module as extensions to normal mode. + Advanced features are : + (+) Repeated block feature. + (+) Trigger feature. + (+) Data handling feature. + + [..] + DMA Legacy circular transfer, is replaced by circular linked-list configuration. + + + *** Initialization and De-Initialization *** + ============================================ + [..] + For a given channel, enable and configure the peripheral to be connected to the DMA Channel (except for internal + SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between + peripherals and DMA requests. + + [..] + For a given channel, use HAL_DMA_Init function to program the required configuration for normal transfer through + the following parameters: + + (+) Request : Specifies the DMA channel request + Request parameters : + (++) can be a value of DMA_Request_Selection + + (+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel + (++) can be a value of DMA_Block_Request + + (+) Direction : Specifies the transfer direction for DMA channel + (++) can be a value of DMA_Transfer_Direction + + (+) SrcInc : Specifies the source increment mode for the DMA channel + (++) can be a value of DMA_Source_Increment_Mode + + (+) DestInc : Specifies the destination increment mode for the DMA channel + (++) can be a value of DMA_Destination_Increment_Mode + + (+) SrcDataWidth : Specifies the source data width for the DMA channel + (++) can be a value of DMA_Source_Data_Width + + (+) DestDataWidth : Specifies the destination data width for the DMA channel + (++) can be a value of DMA_Destination_Data_Width + + (+) Priority : Specifies the priority for the DMA channel + (++) can be a value of DMA_Priority_Level + + (+) SrcBurstLength : Specifies the source burst length (number of beats) for the DMA channel + (++) can be a value of between 1 and 64 + + (+) DestBurstLength : Specifies the destination burst length (number of beats) for the DMA channel + (++) can be a value of between 1 and 64 + + (+) TransferAllocatedPort : Specifies the source and destination allocated ports + (++) can be a value of DMA_Transfer_Allocated_Port + + (+) TransferEventMode : Specifies the transfer event mode for the DMA channel + (++) can be a value of DMA_Transfer_Event_Mode + + (+) Mode : Specifies the transfer mode for the DMA channel + (++) can be one of the following modes : + (+++) DMA_NORMAL : Normal Mode + (+++) DMA_PFCTRL : Peripheral Flow Control (peripheral early termination) Mode + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start a DMA normal transfer after the configuration of source address, destination + address and the size of data to be transferred. + + (+) Use HAL_DMA_PollForTransfer() to poll for selected transfer level. In this case a fixed Timeout can be + configured by User depending on his application. + Transfer level can be : + (++) HAL_DMA_HALF_TRANSFER + (++) HAL_DMA_FULL_TRANSFER + For circular transfer, this API returns an HAL_ERROR with HAL_DMA_ERROR_NOT_SUPPORTED error code. + + (+) Use HAL_DMA_Abort() function to abort any ongoing DMA transfer in blocking mode. + This API returns HAL_ERROR when there is no ongoing transfer or timeout is reached when disabling the DMA + channel. (This API should not be called from an interrupt service routine) + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + + (+) Use HAL_DMA_RegisterCallback() function to register user callbacks from the following list : + (++) XferCpltCallback : transfer complete callback. + (++) XferHalfCpltCallback : half transfer complete callback. + (++) XferErrorCallback : transfer error callback. + (++) XferAbortCallback : transfer abort complete callback. + (++) XferSuspendCallback : transfer suspend complete callback. + + (+) Use HAL_DMA_Start_IT() to start the DMA transfer after the enable of DMA interrupts and the configuration + of source address,destination address and the size of data to be transferred. + + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() interrupt subroutine to handle any DMA interrupt. + + (+) Use HAL_DMA_Abort_IT() function to abort any on-going DMA transfer in non-blocking mode. + This API will suspend immediately the DMA channel execution. When the transfer is effectively suspended, + an interrupt is generated and HAL_DMA_IRQHandler() will reset the channel and execute the callback + XferAbortCallback. (This API could be called from an interrupt service routine) + + + *** State and errors *** + ======================== + [..] + (+) Use HAL_DMA_GetState() function to get the DMA state. + (+) Use HAL_DMA_GetError() function to get the DMA error code. + + + *** Security and privilege attributes *** + ========================================= + [..] + (+) Use HAL_DMA_ConfigChannelAttributes() function to configure DMA channel security and privilege attributes. + (++) Security : at channel level, at source level and at destination level. + (++) Privilege : at channel level. + (+) Use HAL_DMA_GetConfigChannelAttributes() function to get the DMA channel attributes. + (+) Use HAL_DMA_LockChannelAttributes() function to lock the DMA channel security and privilege attributes + configuration. This API can be called once after each system boot. + If called again, HAL_DMA_ConfigChannelAttributes() API has no effect. + Unlock is done either by a system boot or a by an RCC reset. + (+) Use HAL_DMA_GetLockChannelAttributes() function to get the attributes lock status. + + + *** DMA HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE : Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE : Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG : Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG : Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT : Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT : Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE : Check whether the specified DMA Channel interrupt has occurred or not. + + [..] + (@) You can refer to the header file of the DMA HAL driver for more useful macros. + + @endverbatim + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/* Private macro -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +static void DMA_Init(DMA_HandleTypeDef const *const hdma); + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + ====================================================================================================================== + ##### Initialization and de-initialization functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode. + + [..] + (+) The HAL_DMA_Init() function follows the DMA channel configuration procedures as described in reference manual. + (+) The HAL_DMA_DeInit() function allows to de-initialize the DMA channel. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef and + * create the associated handle. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) + { + assert_param(IS_DMA_REQUEST(hdma->Init.Request)); + } + assert_param(IS_DMA_BLOCK_HW_REQUEST(hdma->Init.BlkHWRequest)); + assert_param(IS_DMA_SOURCE_INC(hdma->Init.SrcInc)); + assert_param(IS_DMA_DESTINATION_INC(hdma->Init.DestInc)); + assert_param(IS_DMA_SOURCE_DATA_WIDTH(hdma->Init.SrcDataWidth)); + assert_param(IS_DMA_DESTINATION_DATA_WIDTH(hdma->Init.DestDataWidth)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + assert_param(IS_DMA_TCEM_EVENT_MODE(hdma->Init.TransferEventMode)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + if (hdma->Init.Mode == DMA_PFCTRL) + { + assert_param(IS_DMA_PFREQ_INSTANCE(hdma->Instance)); + } + /* Check DMA channel instance */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + assert_param(IS_DMA_BURST_LENGTH(hdma->Init.SrcBurstLength)); + assert_param(IS_DMA_BURST_LENGTH(hdma->Init.DestBurstLength)); + assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(hdma->Init.TransferAllocatedPort)); + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Initialize the callbacks */ + if (hdma->State == HAL_DMA_STATE_RESET) + { + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + } + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Initialize the DMA channel registers */ + DMA_Init(hdma); + + /* Update DMA channel operation mode */ + hdma->Mode = hdma->Init.Mode; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA channel when it is configured in normal mode. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) +{ + + DMA_TypeDef *p_dma_instance; + + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Disable the selected DMA Channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset DMA Channel registers */ + hdma->Instance->CLBAR = 0U; + hdma->Instance->CCR = 0U; + hdma->Instance->CTR1 = 0U; + hdma->Instance->CTR2 = 0U; + hdma->Instance->CBR1 = 0U; + hdma->Instance->CSAR = 0U; + hdma->Instance->CDAR = 0U; + hdma->Instance->CLLR = 0U; + + /* Reset 2D Addressing registers */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + hdma->Instance->CTR3 = 0U; + hdma->Instance->CBR2 = 0U; + } + + /* Clear privilege attribute */ + CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Clear secure attribute */ + CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + + /* Clean DMA queue */ + hdma->LinkedListQueue = NULL; + + /* Clean DMA parent */ + if (hdma->Parent != NULL) + { + hdma->Parent = NULL; + } + + /* Update DMA channel operation mode */ + hdma->Mode = DMA_NORMAL; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + ====================================================================================================================== + ##### IO operation functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure the source, destination address and data size and Start DMA transfer in normal mode + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + (+) Register and Unregister DMA callbacks + + [..] + (+) The HAL_DMA_Start() function allows to start the DMA channel transfer in normal mode (Blocking mode). + (+) The HAL_DMA_Start_IT() function allows to start the DMA channel transfer in normal mode (Non-blocking mode). + (+) The HAL_DMA_Abort() function allows to abort any on-going transfer (Blocking mode). + (+) The HAL_DMA_Abort_IT() function allows to abort any on-going transfer (Non-blocking mode). + (+) The HAL_DMA_PollForTransfer() function allows to poll on half transfer and transfer complete (Blocking mode). + This API cannot be used for circular transfers. + (+) The HAL_DMA_IRQHandler() function allows to handle any DMA channel interrupt (Non-blocking mode). + (+) The HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() functions allow respectively to register and + unregister user customized callbacks. + User callbacks are called under HAL_DMA_IRQHandler(). + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA channel transfer in normal mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA Mode is DMA_NORMAL */ + if (hdma->Mode != DMA_NORMAL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); + + /* Process locked */ + __HAL_LOCK(hdma); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source address, destination address, the data size and clear flags */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize); + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Starts the DMA channel transfer in normal mode with interrupts enabled (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA Mode is DMA_NORMAL */ + if (hdma->Mode != DMA_NORMAL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); + + /* Process locked */ + __HAL_LOCK(hdma); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source address, destination address, the data size and clear flags */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize); + + /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* If Half Transfer complete callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + } + + /* Check Half suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* If Transfer suspend callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Abort any on-going DMA channel transfer (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @note After suspending a DMA channel, a wait until the DMA channel is effectively stopped is added. If a channel + * is suspended while a data transfer is on-going, the current data will be transferred and the channel will be + * effectively suspended only after the transfer of any on-going data is finished. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the channel */ + hdma->Instance->CCR |= DMA_CCR_SUSP; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + + /* Check if the DMA Channel is suspended */ + while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Reset the channel */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Clear all status flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + + /* Clear remaining data size to ensure loading linked-list from memory next start */ + hdma->Instance->CBR1 = 0U; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Abort any on-going DMA channel transfer in interrupt mode (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + else + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Suspend the channel and activate suspend interrupt */ + hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer status (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CompleteLevel : Specifies the DMA level complete. + * @param Timeout : Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, + HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + uint32_t level_flag; + uint32_t tmp_csr; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_LEVEL_COMPLETE(CompleteLevel)); + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Polling mode is not supported in circular mode */ + if ((hdma->Mode & DMA_LINKEDLIST_CIRCULAR) == DMA_LINKEDLIST_CIRCULAR) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + level_flag = ((CompleteLevel == HAL_DMA_FULL_TRANSFER) ? DMA_FLAG_IDLE : DMA_FLAG_HT); + + /* Get DMA channel status */ + tmp_csr = hdma->Instance->CSR; + + while ((tmp_csr & level_flag) == 0U) + { + /* Check for the timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* + If timeout, abort the current transfer. + Note that the Abort function will + - Clear all transfer flags. + - Unlock. + - Set the State. + */ + (void)HAL_DMA_Abort(hdma); + + return HAL_ERROR; + } + } + + /* Get a newer CSR register value */ + tmp_csr = hdma->Instance->CSR; + } + + /* Check trigger overrun flag */ + if ((tmp_csr & DMA_FLAG_TO) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TO; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO); + } + + /* Check error flags */ + if ((tmp_csr & (DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE)) != 0U) + { + /* Check the data transfer error flag */ + if ((tmp_csr & DMA_FLAG_DTE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DTE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE); + } + + /* Check the update link error flag */ + if ((tmp_csr & DMA_FLAG_ULE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_ULE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE); + } + + /* Check the user setting error flag */ + if ((tmp_csr & DMA_FLAG_USE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_USE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE); + } + + /* Reset the channel */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Clear the transfer level flag */ + if (CompleteLevel == HAL_DMA_HALF_TRANSFER) + { + /* Clear the Half Transfer flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT); + } + else if (CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the transfer flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT)); + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) +{ + const DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma); + uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Global Interrupt Flag management *********************************************************************************/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U)) +#else + if (global_active_flag_ns == 0U) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + { + return; /* the global interrupt flag for the current channel is down , nothing to do */ + } + + /* Data Transfer Error Interrupt management *************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U) + { + /* Clear the transfer error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DTE; + } + } + + /* Update Linked-list Error Interrupt management ********************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U) + { + /* Clear the update linked-list error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_ULE; + } + } + + /* User Setting Error Interrupt management **************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U) + { + /* Clear the user setting error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_USE; + } + } + + /* Trigger Overrun Interrupt management *****************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U) + { + /* Clear the trigger overrun flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TO; + } + } + + /* Half Transfer Complete Interrupt management **********************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) + { + /* Clear the half transfer flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + + /* Suspend Transfer Interrupt management ****************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U) + { + /* Clear the block transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_SUSP); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_ABORT) + { + /* Disable the suspend transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_SUSP); + + /* Reset the channel internal state and reset the FIFO */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + + /* Clear remaining data size to ensure loading linked-list from memory next start */ + hdma->Instance->CBR1 = 0U; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer abort callback */ + if (hdma->XferAbortCallback != NULL) + { + /* Transfer abort callback */ + hdma->XferAbortCallback(hdma); + } + + return; + } + else + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + + /* Check transfer suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* Transfer suspend callback */ + hdma->XferSuspendCallback(hdma); + } + } + } + } + + /* Transfer Complete Interrupt management ***************************************************************************/ + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) + { + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* If linked-list transfer */ + if (hdma->Instance->CLLR == 0U) + { + if (hdma->Instance->CBR1 == 0U) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + } + } + else + { + /* If normal transfer */ + if (hdma->Instance->CBR1 == 0U) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + } + } + + /* Clear TC and HT transfer flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT)); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer complete callback */ + if (hdma->XferCpltCallback != NULL) + { + /* Channel Transfer Complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + + /* Manage error case ************************************************************************************************/ + if (hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + /* Reset the channel internal state and reset the FIFO */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer error callback */ + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callback according to specified ID. + * @note The HAL_DMA_RegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration. + * @param pCallback : Pointer to private callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID, + void (*const pCallback)(DMA_HandleTypeDef *const _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Check callback ID */ + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + { + /* Register transfer complete callback */ + hdma->XferCpltCallback = pCallback; + break; + } + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + { + /* Register half transfer callback */ + hdma->XferHalfCpltCallback = pCallback; + break; + } + + case HAL_DMA_XFER_ERROR_CB_ID: + { + /* Register transfer error callback */ + hdma->XferErrorCallback = pCallback; + break; + } + + case HAL_DMA_XFER_ABORT_CB_ID: + { + /* Register abort callback */ + hdma->XferAbortCallback = pCallback; + break; + } + + case HAL_DMA_XFER_SUSPEND_CB_ID: + { + /* Register suspend callback */ + hdma->XferSuspendCallback = pCallback; + break; + } + + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + else + { + /* Update error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister callback according to specified ID. + * @note The HAL_DMA_UnRegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to un-register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Check callback ID */ + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + { + /* UnRegister transfer complete callback */ + hdma->XferCpltCallback = NULL; + break; + } + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + { + /* UnRegister half transfer callback */ + hdma->XferHalfCpltCallback = NULL; + break; + } + + case HAL_DMA_XFER_ERROR_CB_ID: + { + /* UnRegister transfer error callback */ + hdma->XferErrorCallback = NULL; + break; + } + + case HAL_DMA_XFER_ABORT_CB_ID: + { + /* UnRegister abort callback */ + hdma->XferAbortCallback = NULL; + break; + } + + case HAL_DMA_XFER_SUSPEND_CB_ID: + { + /* UnRegister suspend callback */ + hdma->XferSuspendCallback = NULL; + break; + } + + case HAL_DMA_XFER_ALL_CB_ID: + { + /* UnRegister all available callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + break; + } + + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + else + { + /* Update error status */ + status = HAL_ERROR; + } + + return status; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + ====================================================================================================================== + ##### State and Errors functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Check the DMA state + (+) Get error code + + [..] + (+) The HAL_DMA_GetState() function allows to get the DMA channel state. + (+) The HAL_DMA_DeInit() function allows to get the DMA channel error code. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA channel state. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval DMA state. + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma) +{ + /* Return the DMA channel state */ + return hdma->State; +} + +/** + * @brief Return the DMA channel error code. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval DMA Error Code. + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma) +{ + /* Return the DMA channel error code */ + return hdma->ErrorCode; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group4 + * +@verbatim + ====================================================================================================================== + ##### DMA Attributes functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure DMA channel secure and privilege attributes. + (+) Get DMA channel secure and privilege attributes. + (+) Lock DMA channel secure and privilege attributes configuration. + (+) Check whether DMA channel secure and privilege attributes configuration is locked or not. + + [..] + (+) The HAL_DMA_ConfigChannelAttributes() function allows to configure DMA channel security and privilege + attributes. + (+) The HAL_DMA_GetConfigChannelAttributes() function allows to get DMA channel security and privilege attributes + configuration. + (+) The HAL_DMA_LockChannelAttributes() function allows to lock the DMA channel security and privilege attributes. + (+) The HAL_DMA_GetLockChannelAttributes() function allows to get the DMA channel security and privilege + attributes lock status. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMA channel security and privilege attribute(s). + * @note These attributes cannot be modified when the corresponding lock state is enabled. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param ChannelAttributes : Specifies the DMA channel secure/privilege attributes. + * This parameter can be a one or a combination of @ref DMA_Channel_Attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, uint32_t ChannelAttributes) +{ + DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes)); + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Check DMA channel privilege attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) == DMA_CHANNEL_ATTR_PRIV_MASK) + { + /* Configure DMA channel privilege attribute */ + if ((ChannelAttributes & DMA_CHANNEL_PRIV) == DMA_CHANNEL_PRIV) + { + p_dma_instance->PRIVCFGR |= channel_idx; + } + else + { + p_dma_instance->PRIVCFGR &= (~channel_idx); + } + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Check DMA channel security attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_MASK) == DMA_CHANNEL_ATTR_SEC_MASK) + { + /* Configure DMA channel security attribute */ + if ((ChannelAttributes & DMA_CHANNEL_SEC) == DMA_CHANNEL_SEC) + { + p_dma_instance->SECCFGR |= channel_idx; + } + else + { + p_dma_instance->SECCFGR &= (~channel_idx); + } + } + + /* Channel source security attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_SRC_MASK) == DMA_CHANNEL_ATTR_SEC_SRC_MASK) + { + /* Configure DMA channel source security attribute */ + if ((ChannelAttributes & DMA_CHANNEL_SRC_SEC) == DMA_CHANNEL_SRC_SEC) + { + hdma->Instance->CTR1 |= DMA_CTR1_SSEC; + } + else + { + hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC); + } + } + + /* Channel destination security attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_DEST_MASK) == DMA_CHANNEL_ATTR_SEC_DEST_MASK) + { + /* Configure DMA channel destination security attribute */ + if ((ChannelAttributes & DMA_CHANNEL_DEST_SEC) == DMA_CHANNEL_DEST_SEC) + { + hdma->Instance->CTR1 |= DMA_CTR1_DSEC; + } + else + { + hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC); + } + } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + return HAL_OK; +} + +/** + * @brief Get the DMA channel security and privilege attributes. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pChannelAttributes : Pointer to the returned attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pChannelAttributes) +{ + const DMA_TypeDef *p_dma_instance; + uint32_t attributes; + uint32_t channel_idx; + + /* Check the DMA peripheral handle and channel attributes parameters */ + if ((hdma == NULL) || (pChannelAttributes == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Get DMA channel privilege attribute */ + attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV; + +#if defined (DMA_SECCFGR_SEC0) + /* Get DMA channel security attribute */ + attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC; + + /* Get DMA channel source security attribute */ + attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_SRC_SEC; + + /* Get DMA channel destination security attribute */ + attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC; +#endif /* DMA_SECCFGR_SEC0 */ + + /* return value */ + *pChannelAttributes = attributes; + + return HAL_OK; +} + + +#if defined (DMA_RCFGLOCKR_LOCK0) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the DMA channel security and privilege attribute(s). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma) +{ + DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Lock the DMA channel privilege and security attributes */ + p_dma_instance->RCFGLOCKR |= channel_idx; + + return HAL_OK; +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get the security and privilege attribute lock state of a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param pLockState : Pointer to lock state (returned value can be DMA_CHANNEL_ATTRIBUTE_UNLOCKED or + * DMA_CHANNEL_ATTRIBUTE_LOCKED). + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState) +{ + const DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle and lock state parameters */ + if ((hdma == NULL) || (pLockState == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Get channel lock attribute state */ + *pLockState = ((p_dma_instance->RCFGLOCKR & channel_idx) == 0U) ? DMA_CHANNEL_ATTRIBUTE_UNLOCKED : \ + DMA_CHANNEL_ATTRIBUTE_LOCKED; + + return HAL_OK; +} +#endif /* DMA_RCFGLOCKR_LOCK0 */ +/** + * @} + */ + +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA Private Functions + * @{ + */ + +/** + * @brief Set the DMA channel normal transfer parameters. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval None. + */ +static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Configure the DMA channel data size */ + MODIFY_REG(hdma->Instance->CBR1, DMA_CBR1_BNDT, (SrcDataSize & DMA_CBR1_BNDT)); + + /* Clear all interrupt flags */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO); + + /* Configure DMA channel source address */ + hdma->Instance->CSAR = SrcAddress; + + /* Configure DMA channel destination address */ + hdma->Instance->CDAR = DstAddress; +} + +/** + * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +static void DMA_Init(DMA_HandleTypeDef const *const hdma) +{ + uint32_t tmpreg; + + /* Prepare DMA Channel Control Register (CCR) value *****************************************************************/ + tmpreg = hdma->Init.Priority; + + /* Write DMA Channel Control Register (CCR) */ + MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); + + /* Prepare DMA Channel Transfer Register (CTR1) value ***************************************************************/ + tmpreg = hdma->Init.DestInc | hdma->Init.DestDataWidth | hdma->Init.SrcInc | hdma->Init.SrcDataWidth; + + /* Add parameters specific to GPDMA */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + tmpreg |= (hdma->Init.TransferAllocatedPort | + (((hdma->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) | + (((hdma->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1)); + } + + /* Write DMA Channel Transfer Register 1 (CTR1) */ +#if defined (DMA_CTR1_SSEC) + MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg); +#else + WRITE_REG(hdma->Instance->CTR1, tmpreg); +#endif /* DMA_CTR1_SSEC */ + + /* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/ + tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode; + + /* Memory to Peripheral Transfer */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + tmpreg |= DMA_CTR2_DREQ; + } + } + /* Memory to Memory Transfer */ + else if ((hdma->Init.Direction) == DMA_MEMORY_TO_MEMORY) + { + tmpreg |= DMA_CTR2_SWREQ; + } + else + { + /* Nothing to do */ + } + + /* Set DMA channel operation mode */ + tmpreg |= hdma->Init.Mode; + + /* Write DMA Channel Transfer Register 2 (CTR2) */ + MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM | + DMA_CTR2_PFREQ | DMA_CTR2_BREQ | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | + DMA_CTR2_REQSEL), tmpreg); + + + /* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/ + WRITE_REG(hdma->Instance->CBR1, 0U); + + /* If 2D Addressing is supported by current channel */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + /* Write DMA Channel Transfer Register 3 (CTR3) *******************************************************************/ + WRITE_REG(hdma->Instance->CTR3, 0U); + + /* Write DMA Channel Block Register 2 (CBR2) **********************************************************************/ + WRITE_REG(hdma->Instance->CBR2, 0U); + } + + /* Write DMA Channel linked-list address register (CLLR) ************************************************************/ + WRITE_REG(hdma->Instance->CLLR, 0U); +} +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c new file mode 100644 index 00000000..e2f57b6c --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c @@ -0,0 +1,4777 @@ +/** + ********************************************************************************************************************** + * @file stm32h5xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following functionalities of the DMA extension + * peripheral: + * + Linked-List Initialization and De-Initialization Functions + * + Linked-List I/O Operation Functions + * + Linked-List Management Functions + * + Data Handling, Repeated Block and Trigger Configuration Functions + * + Suspend and Resume Operation Functions + * + FIFO Status Function + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + @verbatim + ====================================================================================================================== + ##### How to use this driver ##### + ====================================================================================================================== + [..] + Alternatively to the normal programming mode, a DMA channel can be programmed by a list of transfers, known as + linked-list (list of Node items). Each node is defined by its data structure. + Each node specifies a standalone DMA channel. + When enabled, the DMA channel fetch the first linked-list node from SRAM (known as head node). When executed, the + next linked list node will be fetched and executed. This operation is repeated until the end of the whole + linked-list queue. Optionally, the linked-list can be linear where the last linked-list queue node is not linked + to another queue node or circular where the last linked-list node is linked to any linked-list queue node. + + (+) Linear linked-list: + The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node + (tail node) ones. When the last node is completed, the DMA channel remains in idle state and another + transfer can be lunched. + + (+) Circular linked-list: + The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node (tail + node). When last node is executed, the DMA channel fetches the first circular node another time and repeat + the same sequence in an infinite loop (Circular transfer). To stop the DMA channel, an abort operation is + required. This linked-list mode replaces the legacy circular transfers. + + [..] + In order to reduce linked-list queue executing time and power consumption, the DMA channel supports executing the + dynamic linked-list format. In fact, the DMA supports the execution of 2 types of linked-list formats : static and + dynamic. + + (+) Static linked-list: + The static linked-list format refers to the full linked-list node where all DMA channel parameters are + fetched and executed independently of the redundancy of information. + + (+) Dynamic linked-list: + The dynamic linked-list format refer to the customized linked-list node where only DMA channel necessary + parameters are fetched and executed (Example: data size = 20 on previous node, and data size = 20 on the + current node => No need to update it). + + For linked-list transfers, the DMA channel can execute the linked-list queue node by node. This feature is named + link step mode. When activated, enabling the DMA channel first time allows to fetch the head node from memory + then it stops. Then, another DMA channel enable is needed to execute the node. After that, keeping enabling the + DMA channel is needed to execute each node until the end of linked-list queue. When the linked-list queue is + circular, enabling the DMA channel in an infinite loop is required to keep the DMA channel running. This feature + is useful for debug purpose or asynchronously executing queue nodes. + + [..] + Each DMA channel transfer (normal or linked-list), is highly configurable according to DMA channel instance + integrated in devices. These configuration can be : + + (+) Repeated block configuration : + If the feature is supported, the DMA channel can performs a repeated block transfers. Named also 2 + dimension addressing transfers, this feature can transfer n iteration of programmed block transfer (Block + transfer is the legacy data size). Additional to the repeat count of a block, DMA channel addresses can + jump after at burst and block level. The jump length is a programmable parameter defined by DMA user. + (++) Jump at burst level : + The DMA channel keep an empty area, between each 2 consecutive bursts transmitted. + (++) Jump at block level : + The DMA channel keep an empty area, between each 2 consecutive blocks transmitted. + + (+) Trigger : + The DMA channel transfers can be conditioned by hardware signals edges (rising or falling) named hardware + triggers. Trigger condition can be applied at : + (++) Single/Burst level : + Each single/burst data transmission is conditioned by a signal trigger hit. + (++) Block level : + Each block data transmission is conditioned by a signal trigger hit. + (++) Repeated block level : + Each repeated block data transmission is conditioned by a signal trigger hit. + (++) Node level : + Each node execution is conditioned by a signal trigger hit. + The DMA channel can report a trigger overrun when detects more than 2 trigger signal edges before + executing the current transfer. + + (+) Data handling : + The data handling feature is a FIFO capability that can be : + (++) Padding pattern : + Padding selected pattern (zero padding or sign extension) when the source data width is smaller + than the destination data width at single level. + (++) Truncation : + Truncate section from the source data single when the source data width is bigger than the + destination data width. + (++) Pack/Unpack : + Pack a set of data when source data width is smaller than the destination data width. + Unpack a set of data when source data width is bigger than the destination data width. + (++) Exchange : + Exchange data at byte and half-word on the destination and at byte level on the source. + + [..] + Each DMA channel transfer (normal or linked-list) when it is active, can be suspended and resumed at run time + application. When trying to suspend an ongoing transfer, the DMA channel isn't suspended instantly but complete + the current ongoing single/burst then it stops. + When the DMA channel is suspended, the current transfer can be resumed instantly. + + [..] + The DMA channel that supports FIFO, can report in real time the number of beats remains on destination (Output) + FIFO level. + + *** Linked-List Initialization and De-Initialization operation *** + ================================================================== + [..] + Differently from normal transfers, DMA channel initialization and de-initialization need less parameters as the + remaining transfer parameters are defined by linked-list nodes. + + (+) Use HAL_DMAEx_List_Init() to initialize a DMA channel in linked-list mode according to programmed fields. + When called, the DMA channel will be ready to execute linked-list queues. + + (+) Use HAL_DMAEx_List_DeInit() to de-initialize a DMA channel in linked-list mode. + When called, the DMA channel will be in reset. It is mandatory to reinitialize it for next transfer. + + *** Linked-List I/O Operation *** + ================================= + [..] + (+) Use HAL_DMAEx_List_Start() to start a DMA transfer in linked-list mode after the configuration of + linked-list queue base address and offset in polling mode (Blocking mode). + + (+) Use HAL_DMAEx_List_Start_IT() to start a DMA transfer in linked-list mode after the configuration of + linked-list queue base address and offset in interrupt mode (Non-blocking mode). + + *** Linked-List Management *** + ============================== + [..] + The linked-list management is a software processing independently of DMA channel hardware. It allows to reset, + build, create, insert, remove, replace, circularize, convert both nodes and queue in order to perform DMA + channel transfers in linked-list mode. + Linked-list APIs and types are adapted to reduce memory footprint. + + *** Linked-list nodes building *** + [..] + At node level, the operations that can be done are building a new linked-list node or get a linked-list node + information from a built node. The linked-list nodes have two forms according to 2 dimensions addressing + capability. The linear addressing nodes contains the information of all DMA channel features except the 2 + dimension addressing features and the 2 dimensions addressing nodes contain the information of all available + features. + + (+) Use HAL_DMAEx_List_BuildNode() to build the DMA linked-list node according to the specified parameters. + Build operation allow to convert the specified parameter in values known by the DMA channel and place them + in memory. + Placing DMA linked-list in SRAM must be done in accordance to product specification to ensure that the + link access port can access to the specified SRAM. + (++) The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + addressable space. + + (+) Use HAL_DMAEx_List_GetNodeConfig() to get the specified configuration parameter on building node. + This API can be used when need to change few parameter to build new node. + + *** Inserting nodes to linked-list queue *** + [..] + In order to build a sequence of DMA transaction with different configuration, we need to insert built node at + linked-list queue (node present an elementary DMA transaction) in linked-list queue on any position to have the + full flexibility of ordering nodes or extend the sequence of queue transactions. + + (+) Use HAL_DMAEx_List_InsertNode() to insert new built node in any queue position of linked-list queue + according to selecting previous node. When calling this API with previous node parameter is NULL, the + inserted node will be placed at the head of the linked-list queue. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + (++) This API shall be avoided when adding new node at the head or the tail of queue (overhead of + footprint and performance : use HAL_DMAEx_List_InsertNode_Head() or HAL_DMAEx_List_InsertNode_Tail() + instead). + + (+) Use HAL_DMAEx_List_InsertNode_Head() to insert new built node at the head of linked-list queue. The head + node will not be overwritten but will be the second queue node. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_InsertNode_Tail() to insert new built node at the tail of linked-list queue. The tail + node will not be overwritten but will be the penultimate queue node. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + + *** Removing nodes from linked-list queue *** + [..] + There is some cases when removing a node from linked-list queue is needed (need to remove an elementary DMA + transaction). Removing node allows to unlink a node from DMA linked-list queue (NOT DELETED), so the removed node + can be reused for another queue or to be added to the same queue without need to rebuild it in next step. + + (+) Use HAL_DMAEx_List_RemoveNode() to remove any yet built and inserted node from linked-list queue according + to selected node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when removing the head or the tail of linked-list queue (overhead of + footprint and performance : use HAL_DMAEx_List_RemoveNode_Head() or HAL_DMAEx_List_RemoveNode_Tail() + instead). + + (+) Use HAL_DMAEx_List_RemoveNode_Head() to remove the head node from linked-list queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_RemoveNode_Tail() to remove the tail node from linked-list queue. + (++) This API must be called for static queues format. + + *** Replacing nodes on linked-list queue *** + [..] + There is some cases when replacing a node from linked-list queue is needed (need to replace an elementary DMA + transfer, by another one that have not the same configuration). Replacing node allows to unlink the node to be + replaced from DMA linked-list queue (NOT DELETED) and link instead a new node. So the replaced node can be reused + for another queue or to be added to the same queue without need to rebuild it in next step and the new node cannot + be reused except when remove it or replaced in next step. + + (+) Use HAL_DMAEx_List_ReplaceNode() to replace any yet built and inserted node on linked-list queue according + to selected node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when replacing the head or the tail linked-list queue (overhead of + footprint and performance : use HAL_DMAEx_List_ReplaceNode_Head() or + HAL_DMAEx_List_ReplaceNode_Tail() instead). + + (+) Use HAL_DMAEx_List_ReplaceNode_Head() to replace the head node of linked-list queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_ReplaceNode_Tail() to replace the tail node from linked-list queue. + (++) This API must be called for static queues format. + + *** Reset linked-list queue *** + [..] + After finishing using a linked-list queue, it can be reset and cleared and it's content nodes will be + unlinked (NOT DELETED) and reused on another queue. + + (+) Use HAL_DMAEx_List_ResetQ() to reset a linked-list queue and unlink all it's content nodes. + (++) This API must be called for ready state queues. + (++) This API must be called for static queues format. + + *** Inserting linked-list queue *** + [..] + To ensure the flexibility of building linked-list queue by their targeted functionalities (Example: 3 nodes for + action 1 and 5 nodes for action 2), it is possible to build a queue for action 1 that contains action 1 nodes and + a queue for action 2 that contains action 2 nodes then concatenating the 2 queues. So, there are some cases where + the management of linked-list at queue granularity is needed. + + (+) Use HAL_DMAEx_List_InsertQ() to insert source linked-list queue to a destination linked-list queue + according to selecting previous node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when inserting source linked-list queue at the head or the tail of + destination queue (overhead of footprint and performance : use HAL_DMAEx_List_InsertQ_Head() or + HAL_DMAEx_List_InsertQ_Tail() instead). + + (+) Use HAL_DMAEx_List_InsertQ_Head() to insert a source linked-list queue at the head of linked-list + destination queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_InsertQ_Tail() to insert a source linked-list queue at the tail of linked-list + destination queue. + (++) This API must be called for static queues format. + + *** Circularizing linked-list queue *** + [..] + In order to perform tasks in infinite loop with DMA channel, it is possible to circularize the linked-list queues. + Circularizing queue allows to link last linked-list queue node to any previous node of the same queue (This node + is named first circular queue). When the first circular node is the head node, all linked-list queue nodes will be + executed in infinite loop. When the first circular node is not the head nodes, all precedent nodes are executed + once and all remaining nodes are executed in an infinite loop. + + (+) Use HAL_DMAEx_List_SetCircularModeConfig() to circularize the linked-list queue according to first + circular node selected. + (++) This API must be called for static queues format. + (++) This API shall be avoided when first circular node is the head linked-list queue node (overhead of + footprint and performance : use HAL_DMAEx_List_SetCircularMode() instead). + + (+) Use HAL_DMAEx_List_SetCircularMode() to circularize the linked-list queue with linking last queue node + with first queue node. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_ClearCircularMode() to clear any linked-list queue circular configuration. + (++) This API must be called for static queues format. + + + *** Converting linked-list queue *** + [..] + To have the best DMA channel linked-list queue execution, it is recommended to convert yet build linked-list queue + to dynamic format (Static is the default format). When linked-list queue becomes dynamic, all queue nodes are + optimized and only changed parameters will be updated between nodes. So, the DMA will fetch only changes + parameters instead of the whole node. + + (+) Use HAL_DMAEx_List_ConvertQToDynamic() to convert a linked-list queue to dynamic format. + (++) This API must be called for ready state queues. + (++) This API must be called for static queues format. + (++) This API must be called as the last API before starting the DMA channel in linked-list mode. + + (+) Use HAL_DMAEx_List_ConvertQToStatic() to convert a linked-list queue to static format. + (++) This API must be called for ready state queues. + (++) This API must be called for dynamic queues format. + (++) This API must be called as the first API after the full execution of linked-list queue when the + execution mode is linear (not circular) if it is dynamic and a linked-list queue management is + needed. + (++) This API must be called as the first API after the aborting the execution of the current linked-list + queue when the execution mode is linear (not circular) if it is dynamic and a linked-list queue + management is needed. + + [..] + When converting a circular queue to dynamic format and when the first circular node is the last queue node, it is + recommended to duplicate the last circular node in order to ensure the full optimization when calling + HAL_DMAEx_List_ConvertQToDynamic() API. In this case, updated information are only addresses which allow to reduce + 4 words of update for linear nodes per node execution and 6 words update for 2 dimensions addressing nodes per + node execution. + + + *** Linking linked-list queue to DMA channel *** + [..] + In order to have the possibility of the creation of an infinity queues (limited by available memory size), the + building of linked-list queue is fully independent from DMA channels. It is possible to build all needed queues if + their size is less then available memory at startup time, then linking each time when needed a linked-list queue + to an idle DMA channel. + + (+) Use HAL_DMAEx_List_LinkQ() to link a ready linked-list queue to ready DMA channel. + (++) This API supports the two format of linked-list (Static and dynamic). + (++) This API must be called for ready state queues and DMA channels. + + (+) Use HAL_DMAEx_List_ConvertQToStatic() to unlink a ready linked-list queue to ready DMA channel. + (++) This API supports the two format of linked-list (Static and dynamic). + (++) This API must be called for ready state queues and DMA channels. + + *** User sequence *** + [..] + To use cleanly the DMA linked-list library, ensure to apply the following call sequences : + + (+) Linear transfer : + Linked-list queue building + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + . + . + . + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + (++) HAL_DMAEx_List_ConvertQToDynamic() + Linked-list queue execution + (++) HAL_DMAEx_List_Init() + (++) HAL_DMAEx_List_LinkQ() + (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT() + (++) HAL_DMAEx_List_UnLinkQ() + (++) HAL_DMAEx_List_DeInit() + + (+) Circular transfer : + Linked-list queue building + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + . + . + . + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + (++) HAL_DMAEx_List_SetCircularModeConfig() / HAL_DMAEx_List_SetCircularMode() + (++) HAL_DMAEx_List_ConvertQToDynamic() + Linked-list queue execution + (++) HAL_DMAEx_List_Init() + (++) HAL_DMAEx_List_LinkQ() + (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT() + (++) HAL_DMA_Abort() / HAL_DMA_Abort_IT() + (++) HAL_DMAEx_List_UnLinkQ() + (++) HAL_DMAEx_List_DeInit() + + + *** Data Handling *** + ===================== + [..] + In order to avoid some CPU data processing in several cases, the DMA channel provides some features related to + FIFO capabilities titled data handling. + (++) Padding pattern + Padding selected pattern (zero padding or sign extension) when the source data width is smaller + than the destination data width at single level. + Zero padding (Source : 0xABAB ------> Destination : 0xABAB0000) + Sign bit extension (Source : 0x0ABA ------> Destination : 0x00000ABA) + (Source : 0xFABA ------> Destination : 0xFFFFFABA) + (++) Truncation : + Truncate section from the source data single when the source data width is bigger than the + destination data width. + Left truncation (Source : 0xABABCDCD ------> Destination : 0xCDCD) + Right truncation (Source : 0xABABCDCD ------> Destination : 0xABAB) + (++) Pack/Unpack : + Pack a set of data when source data width is smaller than the destination data width. + Unpack a set of data when source data width is bigger than the destination data width. + Pack (Source : 0xAB, 0xCD ------> Destination : 0xABCD) + UnPack (Source : 0xABCD ------> Destination : 0xAB, 0xCD) + (++) Exchange : + Exchange data at byte and half-word on the destination and at byte level on the source. + Considering source and destination are both word type. Exchange operation can be as follows. + In examples below, one exchange setting is enabled at a time. + Source byte exchange only (Source : 0xAB12CD34 ------> Destination : 0xABCD1234) + Destination byte exchange only (Source : 0xAB12CD34 ------> Destination : 0x12AB34CD) + Destination half-word exchange only (Source : 0xAB12CD34 ------> Destination : 0xCD34AB12) + + (+) Use HAL_DMAEx_ConfigDataHandling() to configure data handling features. Previous elementary explained + can be combined according to application needs. + (++) This API is complementary of normal transfers. + (++) This API must not be called for linked-list transfers as data handling information are configured at + node level. + + *** User sequence *** + [..] + To configure cleanly the DMA channel data handling, ensure to apply the following call sequence : + + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigDataHandling() + (++) HAL_DMA_Start() + + *** Repeated Block *** + ====================== + [..] + When available, this feature is used when the data size is higher then 65535 bytes (Maximum block size) or for + scattering / gathering data. + (++) Gather data + Source Destination + 0xAA 0xAA + 0xBB 0xAA + 0xAA ==> 0xAA + 0xCC + 0xAA + (++) Scatter data + Source Destination + 0xAA 0xAA + 0xAA 0xBB + 0xAA ==> 0xAA + 0xBB + 0xAA + + (+) Use HAL_DMAEx_ConfigRepeatBlock() to configure data repeated block feature. Jump addresses and + incrementing or decrementing on source and destination can be combined to have the need application + behavior. + (++) This API is complementary of normal transfers. + (++) This API must not be called for linked-list transfers as repeated block information are configured at + node level. + (++) This API must be called only for DMA channel that supports repeated block feature. + + *** User sequence *** + [..] + To configure cleanly the DMA channel repeated block, ensure to apply the following call sequence : + + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigRepeatBlock() + (++) HAL_DMA_Start() + + *** Trigger Configuration *** + ============================= + [..] + When application needs that DMA transfers are conditioned by internal or external events, the trigger feature can + do that. Trigger signals are a set of device signal that are linked to DMA trigger inputs that allows to start the + DMA transfers. + To setup a trigger transfers, three DMA channel parameters are needed: + + (+) Trigger mode + This parameter specifies the trig level. + (++) Block level + (++) Repeated block level + (++) Node level + (++) Single / Burst level + + (+) Trigger polarity + This parameter specifies the DMA trigger sensitivity (Rising or falling). + + (+) Trigger selection + This parameter specifies the DMA trigger hardware signal. + + (+) Use HAL_DMAEx_ConfigTrigger() to configure trigger feature. + (++) This API is complementary to normal transfers APIs. + (++) This API must not be called for linked-list transfers as trigger information are configured at + node level. + + *** User sequence *** + [..] + To configure cleanly the DMA channel trigger, ensure to apply the following call sequence : + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigTrigger() + (++) HAL_DMA_Start() + + *** Suspend and resume operation *** + ==================================== + [..] + There are several cases when needs to suspend a DMA current transfer (Example: liberate bandwidth for more + priority DMA channel transfer). Suspending DMA channel (same as abort) is available in polling (blocking mode) and + interrupt (non-blocking mode) modes. When suspended, a DMA channel can be instantly resumed. + + (+) Use HAL_DMAEx_Suspend() to suspend an ongoing DMA channel transfer in polling mode (Blocking mode). + + (+) Use HAL_DMAEx_Suspend_IT() to suspend an ongoing DMA channel transfer in interrupt mode (Non-blocking + mode). + + (+) Use HAL_DMAEx_Resume() to resume a suspended DMA channel transfer execution. + + *** FIFO status *** + =================== + [..] + In several cases, the information of FIFO level is useful to inform at application level how to process remaining + data. When not empty, the DMA channel FIFO cannot be flashed only by reset. + + (+) Use HAL_DMAEx_GetFifoLevel() to get the DMA channel FIFO level (available beats in FIFO). + + @endverbatim + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private Constants -------------------------------------------------------------------------------------------------*/ +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +static void DMA_List_Init(DMA_HandleTypeDef const *const hdma); +static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode); +static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode); +static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3); +static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3); +static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, + uint32_t *const cllr_mask, + uint32_t *const cllr_offset); +static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList, + DMA_NodeTypeDef const *const pNode, + DMA_NodeInQInfoTypeDef *const NodeInfo); +static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList, + DMA_NodeInQInfoTypeDef const *const NodeInfo); +static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode, + DMA_NodeTypeDef *const pDestNode); +static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber); +static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber); +static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t LastNode_IsCircular); +static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t operation); +static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode, + uint32_t RegisterIdx, + uint32_t RegisterNumber, + uint32_t Format); +static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode, + uint32_t FirstUnusedField); +static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList); + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + ====================================================================================================================== + ##### Linked-List Initialization and De-Initialization Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the DMA channel in linked-list mode. + [..] + (+) The HAL_DMAEx_List_Init() function follows the DMA channel linked-list mode configuration procedures as + described in reference manual. + (+) The HAL_DMAEx_List_DeInit() function allows to de-initialize the DMA channel in linked-list mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA channel in linked-list mode according to the specified parameters in the + * DMA_InitLinkedListTypeDef and create the associated handle. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA channel handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_PRIORITY(hdma->InitLinkedList.Priority)); + assert_param(IS_DMA_LINK_STEP_MODE(hdma->InitLinkedList.LinkStepMode)); + assert_param(IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(hdma->InitLinkedList.TransferEventMode)); + assert_param(IS_DMA_LINKEDLIST_MODE(hdma->InitLinkedList.LinkedListMode)); + /* Check DMA channel instance */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + assert_param(IS_DMA_LINK_ALLOCATED_PORT(hdma->InitLinkedList.LinkAllocatedPort)); + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Initialize the DMA channel registers */ + DMA_List_Init(hdma); + + /* Update DMA channel operation mode */ + hdma->Mode = hdma->InitLinkedList.LinkedListMode; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA channel when it is configured in linked-list mode. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) +{ + + /* Get DMA instance */ + DMA_TypeDef *p_dma_instance; + + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Disable the selected DMA Channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset DMA Channel registers */ + hdma->Instance->CCR = 0U; + hdma->Instance->CLBAR = 0U; + hdma->Instance->CTR1 = 0U; + hdma->Instance->CTR2 = 0U; + hdma->Instance->CBR1 = 0U; + hdma->Instance->CSAR = 0U; + hdma->Instance->CDAR = 0U; + hdma->Instance->CLLR = 0U; + + /* Reset 2D Addressing registers */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + hdma->Instance->CTR3 = 0U; + hdma->Instance->CBR2 = 0U; + } + + + /* Clear privilege attribute */ + CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Clear secure attribute */ + CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + + /* Check the linked-list queue */ + if (hdma->LinkedListQueue != NULL) + { + /* Update the queue state and error code */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Clean DMA queue */ + hdma->LinkedListQueue = NULL; + } + + /* Clean DMA parent */ + if (hdma->Parent != NULL) + { + hdma->Parent = NULL; + } + + /* Update DMA channel operation mode */ + hdma->Mode = DMA_NORMAL; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group2 + * +@verbatim + ====================================================================================================================== + ##### Linked-List IO Operation Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure to start DMA transfer in linked-list mode. + + [..] + (+) The HAL_DMAEx_List_Start() function allows to start the DMA channel transfer in linked-list mode (Blocking + mode). + (+) The HAL_DMAEx_List_Start_IT() function allows to start the DMA channel transfer in linked-list mode + (Non-blocking mode). + (++) It is mandatory to register a linked-list queue to be executed by a DMA channel before starting + transfer otherwise a HAL_ERROR will be returned. + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA channel transfer in linked-list mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef dma_state; + uint32_t ccr_value; + uint32_t cllr_mask; + + /* Check the DMA peripheral handle and the linked-list queue parameters */ + if ((hdma == NULL) || (hdma->LinkedListQueue == NULL)) + { + return HAL_ERROR; + } + + /* Check the DMA Mode is not DMA_NORMAL */ + if (hdma->Mode == DMA_NORMAL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + dma_state = hdma->State; + ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; + if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U))) + { + /* Check DMA channel state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process locked */ + __HAL_LOCK(hdma); + + /* Update the DMA channel and the queue states */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the DMA channel and the queue error codes */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL); + + /* Update DMA registers for linked-list transfer */ + hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA); + hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Starts the DMA channel transfer in linked-list mode with interrupts enabled (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef dma_state; + uint32_t ccr_value; + uint32_t cllr_mask; + + /* Check the DMA peripheral handle and the linked-list queue parameters */ + if ((hdma == NULL) || (hdma->LinkedListQueue == NULL)) + { + return HAL_ERROR; + } + + /* Check the DMA Mode is not DMA_NORMAL */ + if (hdma->Mode == DMA_NORMAL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + dma_state = hdma->State; + ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; + if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U))) + { + /* Check DMA channel state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process locked */ + __HAL_LOCK(hdma); + + /* Update the DMA channel and the queue states */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the DMA channel and the queue error codes */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* If half transfer complete callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + } + + /* Check suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* If transfer suspend callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); + } + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL); + + /* Update DMA registers for linked-list transfer */ + hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA); + hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group3 + * +@verbatim + ====================================================================================================================== + ##### Linked-List Management Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Build linked-list node. + (+) Get linked-list node configuration. + (+) Insert node to linked-list queue in any queue position. + (+) Remove any node from linked-list queue. + (+) Replace any node from linked-list queue. + (+) Reset linked-list queue. + (+) Insert linked-list queue in any queue position. + (+) Set circular mode configuration to linked-list queue. + (+) Clear circular mode configuration from linked-list queue. + (+) Convert static linked-list queue to dynamic format. + (+) Convert dynamic linked-list queue to static format. + (+) Link linked-list queue to DMA channel. + (+) Unlink linked-list queue from DMA channel. + + [..] + (+) The HAL_DMAEx_List_BuildNode() function allows to build linked-list node. + Node type can be : + (++) 2 dimensions addressing node. + (++) Linear addressing node. + + (+) The HAL_DMAEx_List_GetNodeConfig() function allows to get the linked-list node configuration from built node. + + (+) The HAL_DMAEx_List_InsertNode() function allows to insert built linked-list node to static linked-list queue + according to selected position. + + (+) The HAL_DMAEx_List_InsertNode_Head() and HAL_DMAEx_List_InsertNode_Tail() functions allow to insert built + linked-list node to the head (respectively the tail) of static linked-list queue. + + (+) The HAL_DMAEx_List_RemoveNode() function allows to remove selected built linked-list node from static + linked-list queue. + + (+) The HAL_DMAEx_List_RemoveNode_Head() and HAL_DMAEx_List_RemoveNode_Tail() functions allow to remove the head + (respectively the tail) built linked-list node from static linked-list queue. + + (+) The HAL_DMAEx_List_ReplaceNode() function allows to replace selected built linked-list node from static + linked-list queue. + + (+) The HAL_DMAEx_List_ReplaceNode_Head() and HAL_DMAEx_List_ReplaceNode_Tail() functions allow to replace the + head (respectively the tail) built linked-list node of static linked-list queue. + + (+) The HAL_DMAEx_List_ResetQ() function allows to reset static linked-list queue and unlink all built linked-list + nodes. + + (+) The HAL_DMAEx_List_InsertQ() function allows to insert static linked-list source queue to static linked-list + destination queue according to selected position. + + (+) The HAL_DMAEx_List_InsertQ_Head() and HAL_DMAEx_List_InsertQ_Tail() functions allow to insert static + linked-list source queue to the head (respectively the tail) of static linked-list destination queue. + + (+) The HAL_DMAEx_List_SetCircularModeConfig() function allows to link the last static linked-list queue node to + the selected first circular node. + + (+) The HAL_DMAEx_List_SetCircularMode() function allows to link the last static linked-list queue node to the + first static linked-list queue node. + + (+) The HAL_DMAEx_List_ClearCircularMode() function allows to unlink the last static linked-list queue node from + any first circular node position. + + (+) The HAL_DMAEx_List_ConvertQToDynamic() function allows to convert the static linked-list queue to dynamic + format. (Optimized queue execution) + + (+) The HAL_DMAEx_List_ConvertQToStatic() function allows to convert the dynamic linked-list queue to static + format. (Not optimized queue execution) + + (+) The HAL_DMAEx_List_LinkQ() function allows to link the (Dynamic / Static) linked-list queue to DMA channel to + be executed. + + (+) The HAL_DMAEx_List_UnLinkQ() function allows to unlink the (Dynamic / Static) linked-list queue from DMA + channel when execution is completed. + +@endverbatim + * @{ + */ + +/** + * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @note The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + * addressable space. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode) +{ + /* Check the node configuration and physical node parameters */ + if ((pNodeConfig == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Check node type parameter */ + assert_param(IS_DMA_NODE_TYPE(pNodeConfig->NodeType)); + + /* Check DMA channel basic transfer parameters */ + assert_param(IS_DMA_SOURCE_INC(pNodeConfig->Init.SrcInc)); + assert_param(IS_DMA_DESTINATION_INC(pNodeConfig->Init.DestInc)); + assert_param(IS_DMA_SOURCE_DATA_WIDTH(pNodeConfig->Init.SrcDataWidth)); + assert_param(IS_DMA_DESTINATION_DATA_WIDTH(pNodeConfig->Init.DestDataWidth)); + assert_param(IS_DMA_DATA_ALIGNMENT(pNodeConfig->DataHandlingConfig.DataAlignment)); + assert_param(IS_DMA_REQUEST(pNodeConfig->Init.Request)); + assert_param(IS_DMA_DIRECTION(pNodeConfig->Init.Direction)); + assert_param(IS_DMA_TCEM_EVENT_MODE(pNodeConfig->Init.TransferEventMode)); + assert_param(IS_DMA_BLOCK_HW_REQUEST(pNodeConfig->Init.BlkHWRequest)); + assert_param(IS_DMA_MODE(pNodeConfig->Init.Mode)); + + /* Check DMA channel parameters */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) + { + assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.SrcBurstLength)); + assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.DestBurstLength)); + assert_param(IS_DMA_DATA_EXCHANGE(pNodeConfig->DataHandlingConfig.DataExchange)); + assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(pNodeConfig->Init.TransferAllocatedPort)); + } + + /* Check DMA channel trigger parameters */ + assert_param(IS_DMA_TRIGGER_POLARITY(pNodeConfig->TriggerConfig.TriggerPolarity)); + if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED) + { + assert_param(IS_DMA_TRIGGER_MODE(pNodeConfig->TriggerConfig.TriggerMode)); + assert_param(IS_DMA_TRIGGER_SELECTION(pNodeConfig->TriggerConfig.TriggerSelection)); + } + + /* Check DMA channel repeated block parameters */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + assert_param(IS_DMA_REPEAT_COUNT(pNodeConfig->RepeatBlockConfig.RepeatCount)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); + } + + /* Check DMA channel security and privilege attributes parameters */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->SrcSecure)); + assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->DestSecure)); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Build the DMA channel node */ + DMA_List_BuildNode(pNodeConfig, pNode); + + return HAL_OK; +} + +/** + * @brief Get a DMA channel node configuration. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode) +{ + /* Check the node configuration and physical node parameters */ + if ((pNodeConfig == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Get the DMA channel node configuration */ + DMA_List_GetNodeConfig(pNodeConfig, pNode); + + return HAL_OK; +} + +/** + * @brief Insert new node in any queue position of linked-list queue according to selecting previous node. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pPrevNode, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Empty queue */ + if (pQList->Head == NULL) + { + /* Add only new node to queue */ + if (pPrevNode == NULL) + { + pQList->Head = pNewNode; + pQList->NodeNumber = 1U; + } + /* Add previous node then new node to queue */ + else + { + pQList->Head = pPrevNode; + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + pQList->NodeNumber = 2U; + } + } + /* Not empty queue */ + else + { + /* Add new node at the head of queue */ + if (pPrevNode == NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + pQList->Head = pNewNode; + } + /* Add new node according to selected position */ + else + { + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pPrevNode, &node_info) == 0U) + { + /* Selected node is the last queue node */ + if (node_info.currentnode_pos == pQList->NodeNumber) + { + /* Check if queue is circular */ + if (pQList->FirstCircularNode != NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + /* Selected node is not the last queue node */ + else + { + pNewNode->LinkRegisters[cllr_offset] = pPrevNode->LinkRegisters[cllr_offset]; + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + } + + /* Increment queue node number */ + pQList->NodeNumber++; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Insert new node at the head of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Empty queue */ + if (pQList->Head == NULL) + { + pQList->Head = pNewNode; + } + /* Not empty queue */ + else + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + pQList->Head = pNewNode; + } + + /* Increment queue node number */ + pQList->NodeNumber++; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Insert new node at the tail of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Empty queue */ + if (pQList->Head == NULL) + { + pQList->Head = pNewNode; + } + /* Not empty queue */ + else + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Check if queue is circular */ + if (pQList->FirstCircularNode != NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + + ((DMA_NodeTypeDef *)node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + + /* Increment queue node number */ + pQList->NodeNumber++; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove node from any linked-list queue position. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNode) +{ + uint32_t previousnode_addr; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the node parameters */ + if ((pQList == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNode, NULL, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pNode, &node_info) == 0U) + { + /* Removed node is the head node */ + if (node_info.currentnode_pos == 1U) + { + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Update the queue head node */ + pQList->Head = (DMA_NodeTypeDef *)(((uint32_t)pQList->Head & DMA_CLBAR_LBA) + + (pNode->LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + /* Unlink node to be removed */ + pNode->LinkRegisters[cllr_offset] = 0U; + } + /* Removed node is the last node */ + else if (node_info.currentnode_pos == pQList->NodeNumber) + { + /* Clear CLLR for previous node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear CLLR for last node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + /* Removed node is in the middle */ + else + { + /* Store previous node address to be updated later */ + previousnode_addr = node_info.previousnode_addr; + + /* Check if first circular node queue is the current node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Link previous node */ + ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[cllr_offset] = pNode->LinkRegisters[cllr_offset]; + + /* Unlink node to be removed */ + pNode->LinkRegisters[cllr_offset] = 0U; + } + + /* Decrement node number */ + pQList->NodeNumber--; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove the head node from linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t current_addr; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Queue contains only one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->FirstCircularNode = 0U; + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + } + /* Queue contains more then one node */ + else + { + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == pQList->Head) + { + /* Find last queue node */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + current_addr = pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->Head = ((DMA_NodeTypeDef *)(current_addr + ((uint32_t)pQList->Head & DMA_CLBAR_LBA))); + } + + /* Decrement node number */ + pQList->NodeNumber--; + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove the tail node from linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Queue contains only one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->FirstCircularNode = 0U; + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + } + /* Queue contains more then one node */ + else + { + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear CLLR for previous node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear CLLR for last node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Decrement node number */ + pQList->NodeNumber--; + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace node in linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pOldNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list old node registers + * configurations. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pOldNode, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the nodes parameters */ + if ((pQList == NULL) || (pOldNode == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pOldNode, &node_info) == 0U) + { + /* Replaced node is the head node */ + if (node_info.currentnode_pos == 1U) + { + pNewNode->LinkRegisters[cllr_offset] = + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset]; + pQList->Head = pNewNode; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + } + /* Replaced node is the last */ + else if (node_info.currentnode_pos == pQList->NodeNumber) + { + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the last node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + /* Check if first circular node queue is not the last node */ + else if (pQList->FirstCircularNode != NULL) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + } + /* Replaced node is in the middle */ + else + { + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + pNewNode->LinkRegisters[cllr_offset] = + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset]; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the current node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Find last node and get its position in selected queue */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Link last queue node to new node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + } + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace the head node of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_offset; + uint32_t cllr_mask; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == pQList->Head) + { + /* Find last queue node */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + + /* Replace head node */ + pNewNode->LinkRegisters[cllr_offset] = pQList->Head->LinkRegisters[cllr_offset]; + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->Head = pNewNode; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace the tail node of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find last node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Link previous node to new node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Clear CLLR for current node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the last node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + /* Check if first circular node queue is not the last node */ + else if (pQList->FirstCircularNode != NULL) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check if queue contains one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head = pNewNode; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Reset the linked-list queue and unlink queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check queue state */ + if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Check the queue */ + if (pQList->Head != NULL) + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Reset selected queue nodes */ + node_info.cllr_offset = cllr_offset; + DMA_List_ResetQueueNodes(pQList, &node_info); + } + + /* Reset head node address */ + pQList->Head = NULL; + + /* Reset node number */ + pQList->NodeNumber = 0U; + + /* Reset first circular node */ + pQList->FirstCircularNode = NULL; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue to a destination linked-list queue according to selecting previous node. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, + DMA_NodeTypeDef const *const pPrevNode, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the source queue circularity */ + if (pSrcQList->FirstCircularNode != NULL) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Previous node is empty */ + if (pPrevNode == NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Check if first circular node queue is the first node */ + if (pDestQList->FirstCircularNode == pDestQList->Head) + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Link destination queue tail node to new first circular node */ + ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Set the head node of source queue as the first circular node */ + pDestQList->FirstCircularNode = pSrcQList->Head; + } + + /* Link the last node of source queue to the fist node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + /* Previous node is not empty */ + else + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pDestQList, pPrevNode, &dest_q_node_info) == 0U) + { + /* Selected node is the last destination queue node */ + if (dest_q_node_info.currentnode_pos == pDestQList->NodeNumber) + { + /* Link the first node of source queue to the last node of destination queue */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + + /* Check if first circular node queue is not empty */ + if (pDestQList->FirstCircularNode != NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Find first circular node */ + (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info); + + /* Link last source queue node to first destination queue */ + ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask; + } + } + /* Selected node is not the last destination queue node */ + else + { + /* Link the first node of source queue to the previous node of destination queue */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Link the last node of source queue to the next node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + (dest_q_node_info.nextnode_addr & DMA_CLLR_LA) | cllr_mask; + + /* Update queues counter */ + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + } + else + { + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + } + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + UNUSED(dest_q_node_info); + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue at the head of destination queue. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Check if first circular node queue is the first node */ + if (pDestQList->FirstCircularNode == pDestQList->Head) + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Link destination queue tail node to new first circular node */ + ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Set the head node of source queue as the first circular node */ + pDestQList->FirstCircularNode = pSrcQList->Head; + } + + /* Link the last node of source queue to the fist node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + UNUSED(dest_q_node_info); + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue at the tail of destination queue. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Update source queue last node CLLR to link it with destination first node */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + + /* Check if first circular node queue is not empty */ + if (pDestQList->FirstCircularNode != NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Find first circular node */ + (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info); + + /* Link last source queue node to first destination queue */ + ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask; + } + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + + return HAL_OK; +} + +/** + * @brief Set circular mode configuration for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pFirstCircularNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list first circular node + * registers configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pFirstCircularNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the first circular node parameters */ + if ((pQList == NULL) || (pFirstCircularNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode != NULL) + { + if (pQList->FirstCircularNode == pFirstCircularNode) + { + return HAL_OK; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pFirstCircularNode, &cllr_mask, &cllr_offset); + + /* Find the first circular node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pFirstCircularNode, &node_info) == 0U) + { + /* Find the last queue node and get its position in selected queue */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Set circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pFirstCircularNode & DMA_CLLR_LA) | cllr_mask; + + /* Update first circular node in queue */ + pQList->FirstCircularNode = pFirstCircularNode; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Set circular mode for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode != NULL) + { + if (pQList->FirstCircularNode == pQList->Head) + { + return HAL_OK; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_mask, &cllr_offset); + + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Set circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Update linked-list circular state */ + pQList->FirstCircularNode = pQList->Head; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Clear circular mode for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode == NULL) + { + return HAL_OK; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Update linked-list circular configuration */ + pQList->FirstCircularNode = NULL; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Convert a linked-list queue to dynamic (Optimized DMA queue execution). + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t currentnode_addr; + DMA_NodeTypeDef context_node; + DMA_NodeInQInfoTypeDef node_info = {0U}; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check if queue is dynamic */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + return HAL_OK; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Check queue circularity */ + if (pQList->FirstCircularNode != 0U) + { + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + } + + /* Set current node address */ + currentnode_addr = (uint32_t)pQList->Head; + + /* Store register value */ + DMA_List_FillNode(pQList->Head, &context_node); + + /* Convert all nodes to dyncamic (Bypass head node) */ + for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++) + { + /* Update node address */ + MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + + /* Bypass the first circular node when first circular node isn't the last queue node */ + if (((uint32_t)pQList->FirstCircularNode != 0U) && + ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr) && + ((uint32_t)pQList->FirstCircularNode == currentnode_addr)) + { + /* Copy first circular node to context node */ + DMA_List_FillNode(pQList->FirstCircularNode, &context_node); + } + else + { + /* Convert current node to dynamic */ + DMA_List_ConvertNodeToDynamic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); + } + } + + /* Check if first circular node is the last node queue */ + if (((uint32_t)pQList->FirstCircularNode != 0U) && + ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr)) + { + /* Update all queue nodes CLLR */ + DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_ISNOT_CIRCULAR); + } + else + { + /* Update all queue nodes CLLR */ + DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_IS_CIRCULAR); + } + + /* Set queue type */ + pQList->Type = QUEUE_TYPE_DYNAMIC; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Convert a linked-list queue to static (Not optimized DMA queue execution). + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t currentnode_addr; + DMA_NodeTypeDef context_node; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check if queue is static */ + if (pQList->Type == QUEUE_TYPE_STATIC) + { + return HAL_OK; + } + + /* Set current node address */ + currentnode_addr = (uint32_t)pQList->Head; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Set all CLLR queue nodes to their default positions */ + DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_POSITION); + + /* Convert all nodes to static (Bypass head node) */ + for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++) + { + /* Update context node register values */ + DMA_List_FillNode((DMA_NodeTypeDef *)currentnode_addr, &context_node); + + /* Update node address */ + MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + + /* Convert current node to static */ + DMA_List_ConvertNodeToStatic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); + } + + /* Set all CLLR queue nodes to their default values */ + DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_VALUE); + + /* Set queue type */ + pQList->Type = QUEUE_TYPE_STATIC; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Link linked-list queue to a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, + DMA_QListTypeDef *const pQList) +{ + HAL_DMA_StateTypeDef state; + + /* Check the DMA channel handle and the queue parameters */ + if ((hdma == NULL) || (pQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the DMA Mode is not DMA_NORMAL */ + if (hdma->Mode == DMA_NORMAL) + { + return HAL_ERROR; + } + + /* Get DMA state */ + state = hdma->State; + + /* Check DMA channel state */ + if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Check queue state */ + if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY; + + return HAL_ERROR; + } + + /* Check linearity compatibility */ + if ((IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) == 0U) && + ((pQList->Head->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_UNSUPPORTED; + + return HAL_ERROR; + } + + /* Check circularity compatibility */ + if (hdma->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Check first circular node */ + if (pQList->FirstCircularNode == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + else + { + /* Check first circular node */ + if (pQList->FirstCircularNode != NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Register queue to DMA handle */ + hdma->LinkedListQueue = pQList; + + return HAL_OK; +} + +/** + * @brief Unlink linked-list queue from a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef state; + + /* Check the DMA channel parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA Mode is not DMA_NORMAL */ + if (hdma->Mode == DMA_NORMAL) + { + return HAL_ERROR; + } + + /* Get DMA state */ + state = hdma->State; + + /* Check DMA channel state */ + if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Clear queue information from DMA channel handle */ + hdma->LinkedListQueue = NULL; + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group4 + * +@verbatim + ====================================================================================================================== + ##### Data handling, repeated block and trigger configuration functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure DMA channel data handling. + (+) Configure DMA channel repeated block. + (+) Configure DMA channel trigger. + + [..] + (+) The HAL_DMAEx_ConfigDataHandling() function allows to configure DMA channel data handling. + (++) GPDMA data handling : byte-based reordering, packing/unpacking, padding/truncation, sign extension + and left/right alignment. + + (+) The HAL_DMAEx_ConfigTrigger() function allows to configure DMA channel HW triggers. + + (+) The HAL_DMAEx_ConfigRepeatBlock() function allows to configure DMA channel repeated block. + (++) This feature is available only for channel that supports 2 dimensions addressing capability. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMA channel data handling according to the specified parameters in the + * DMA_DataHandlingConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pConfigDataHandling : Pointer to a DMA_DataHandlingConfTypeDef structure that contains the data handling + * configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, + DMA_DataHandlingConfTypeDef const *const pConfigDataHandling) +{ + /* Check the DMA peripheral handle and data handling parameters */ + if ((hdma == NULL) || (pConfigDataHandling == NULL)) + { + return HAL_ERROR; + } + + /* Check the DMA Mode is DMA_NORMAL */ + if (hdma->Mode != DMA_NORMAL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_DATA_ALIGNMENT(pConfigDataHandling->DataAlignment)); + assert_param(IS_DMA_DATA_EXCHANGE(pConfigDataHandling->DataExchange)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), + (pConfigDataHandling->DataAlignment | pConfigDataHandling->DataExchange)); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the DMA channel trigger according to the specified parameters in the DMA_TriggerConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param pConfigTrigger : Pointer to a DMA_TriggerConfTypeDef structure that contains the trigger configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, + DMA_TriggerConfTypeDef const *const pConfigTrigger) +{ + /* Check the DMA peripheral handle and trigger parameters */ + if ((hdma == NULL) || (pConfigTrigger == NULL)) + { + return HAL_ERROR; + } + + /* Check the DMA Mode is DMA_NORMAL */ + if (hdma->Mode != DMA_NORMAL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_TRIGGER_POLARITY(pConfigTrigger->TriggerPolarity)); + assert_param(IS_DMA_TRIGGER_MODE(pConfigTrigger->TriggerMode)); + assert_param(IS_DMA_TRIGGER_SELECTION(pConfigTrigger->TriggerSelection)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM), + (pConfigTrigger->TriggerPolarity | pConfigTrigger->TriggerMode | + (pConfigTrigger->TriggerSelection << DMA_CTR2_TRIGSEL_Pos))); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the DMA channel repeated block according to the specified parameters in the + * DMA_RepeatBlockConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pConfigRepeatBlock : Pointer to a DMA_RepeatBlockConfTypeDef structure that contains the repeated block + * configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, + DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock) +{ + uint32_t tmpreg1; + uint32_t tmpreg2; + + /* Check the DMA peripheral handle and repeated block parameters */ + if ((hdma == NULL) || (pConfigRepeatBlock == NULL)) + { + return HAL_ERROR; + } + + /* Check the DMA Mode is DMA_NORMAL */ + if (hdma->Mode != DMA_NORMAL) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_REPEAT_COUNT(pConfigRepeatBlock->RepeatCount)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->SrcAddrOffset)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->DestAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkSrcAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkDestAddrOffset)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Store repeat block count */ + tmpreg1 = ((pConfigRepeatBlock->RepeatCount - 1U) << DMA_CBR1_BRC_Pos); + + /* Check the sign of single/burst destination address offset value */ + if (pConfigRepeatBlock->DestAddrOffset < 0) + { + /* Store single/burst destination address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_DDEC; + tmpreg2 = (uint32_t)(- pConfigRepeatBlock->DestAddrOffset); + tmpreg2 = tmpreg2 << DMA_CTR3_DAO_Pos; + } + else + { + /* Store single/burst destination address offset configuration (unsigned case) */ + tmpreg2 = ((uint32_t)pConfigRepeatBlock->DestAddrOffset << DMA_CTR3_DAO_Pos); + } + + /* Check the sign of single/burst source address offset value */ + if (pConfigRepeatBlock->SrcAddrOffset < 0) + { + /* Store single/burst source address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_SDEC; + tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->SrcAddrOffset); + } + else + { + /* Store single/burst source address offset configuration (unsigned case) */ + tmpreg2 |= (uint32_t)pConfigRepeatBlock->SrcAddrOffset; + } + + /* Write DMA Channel Transfer Register 3 (CTR3) */ + WRITE_REG(hdma->Instance->CTR3, tmpreg2); + + /* Check the sign of block destination address offset value */ + if (pConfigRepeatBlock->BlkDestAddrOffset < 0) + { + /* Store block destination address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_BRDDEC; + tmpreg2 = (uint32_t)(- pConfigRepeatBlock->BlkDestAddrOffset); + tmpreg2 = tmpreg2 << DMA_CBR2_BRDAO_Pos; + } + else + { + /* Store block destination address offset configuration (unsigned case) */ + tmpreg2 = ((uint32_t)pConfigRepeatBlock->BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos); + } + + /* Check the sign of block source address offset value */ + if (pConfigRepeatBlock->BlkSrcAddrOffset < 0) + { + /* Store block source address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_BRSDEC; + tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->BlkSrcAddrOffset); + } + else + { + /* Store block source address offset configuration (unsigned case) */ + tmpreg2 |= (uint32_t)pConfigRepeatBlock->BlkSrcAddrOffset; + } + + /* Write DMA Channel block register 2 (CBR2) */ + WRITE_REG(hdma->Instance->CBR2, tmpreg2); + + /* Write DMA Channel block register 1 (CBR1) */ + WRITE_REG(hdma->Instance->CBR1, tmpreg1); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group5 + * +@verbatim + ====================================================================================================================== + ##### Suspend and resume operation functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Suspend any ongoing DMA channel transfer. + (+) Resume any suspended DMA channel transfer. + + [..] + (+) The HAL_DMAEx_Suspend() function allows to suspend any ongoing DMA channel transfer in polling mode (Blocking + mode). + + (+) The HAL_DMAEx_Suspend_IT() function allows to suspend any ongoing DMA channel transfer in interrupt mode + (Non-blocking mode). + + (+) The HAL_DMAEx_Resume() function allows to resume any suspended DMA channel transfer. + +@endverbatim + * @{ + */ + +/** + * @brief Suspend any ongoing DMA channel transfer in polling mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA channel. + * @note After suspending a DMA channel, a check for wait until the DMA channel is effectively suspended is added. If + * a channel is suspended while a data transfer is ongoing, the current data will be transferred and the + * channel will be effectively suspended only after the transfer of this single/burst data is finished. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the channel */ + hdma->Instance->CCR |= DMA_CCR_SUSP; + + /* Check if the DMA channel is suspended */ + while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) + { + /* Check for the timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + } + + return HAL_OK; +} + +/** + * @brief Suspend any ongoing DMA channel transfer in polling mode (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the DMA channel and activate suspend interrupt */ + hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE); + } + + return HAL_OK; +} + +/** + * @brief Resume any suspended DMA channel transfer. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_SUSPEND) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Resume the DMA channel */ + hdma->Instance->CCR &= (~DMA_CCR_SUSP); + + /* Clear the suspend flag */ + hdma->Instance->CFCR |= DMA_CFCR_SUSPF; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group6 + * +@verbatim + ====================================================================================================================== + ##### Fifo status function ##### + ====================================================================================================================== + [..] + This section provides function allowing to get DMA channel FIFO level. + + [..] + (+) The HAL_DMAEx_GetFifoLevel() function allows to return the number of available write beats in the FIFO, in + units of the programmed destination data. + (++) This API is available only for DMA channels that supports FIFO. + +@endverbatim + * @{ + */ + +/** + * @brief Get and returns the DMA channel FIFO level. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval Returns the number of available beats in FIFO. + */ +uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma) +{ + return ((hdma->Instance->CSR & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private Functions + * @{ + */ + +/** + * @brief Initialize the DMA handle according to the specified parameters in the DMA_InitTypeDef. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +static void DMA_List_Init(DMA_HandleTypeDef const *const hdma) +{ + uint32_t tmpreg; + + /* Prepare DMA Channel Control Register (CCR) value */ + tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode; + + /* Check DMA channel instance */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + tmpreg |= hdma->InitLinkedList.LinkAllocatedPort; + } + + /* Write DMA Channel Control Register (CCR) */ + MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); + + /* Write DMA Channel Control Register (CTR1) */ + WRITE_REG(hdma->Instance->CTR1, 0U); + + /* Write DMA Channel Control Register (CTR2) */ + WRITE_REG(hdma->Instance->CTR2, hdma->InitLinkedList.TransferEventMode); + + /* Write DMA Channel Control Register (CBR1) */ + WRITE_REG(hdma->Instance->CBR1, 0U); + + /* Write DMA Channel Control Register (CSAR) */ + WRITE_REG(hdma->Instance->CSAR, 0U); + + /* Write DMA Channel Control Register (CDAR) */ + WRITE_REG(hdma->Instance->CDAR, 0U); + + /* If 2D Addressing is supported by current channel */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + /* Write DMA Channel Control Register (CTR3) */ + WRITE_REG(hdma->Instance->CTR3, 0U); + + /* Write DMA Channel Control Register (CBR2) */ + WRITE_REG(hdma->Instance->CBR2, 0U); + } + + /* Write DMA Channel linked-list address register (CLLR) */ + WRITE_REG(hdma->Instance->CLLR, 0U); +} + +/** + * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval None. + */ +static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode) +{ + int32_t blockoffset; + + /* Update CTR1 register value ***************************************************************************************/ + /* Prepare DMA channel transfer register (CTR1) value */ + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc | + pNodeConfig->Init.DestDataWidth | + pNodeConfig->DataHandlingConfig.DataAlignment | + pNodeConfig->Init.SrcInc | + pNodeConfig->Init.SrcDataWidth; + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* set source channel security attribute */ + if (pNodeConfig->SrcSecure == DMA_CHANNEL_SRC_SEC) + { + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC; + } + + /* set destination channel security attribute */ + if (pNodeConfig->DestSecure == DMA_CHANNEL_DEST_SEC) + { + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC; + } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Add parameters related to DMA configuration */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) + { + /* Prepare DMA channel transfer register (CTR1) value */ + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= + (pNodeConfig->Init.TransferAllocatedPort | pNodeConfig->DataHandlingConfig.DataExchange | + (((pNodeConfig->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) | + (((pNodeConfig->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1)); + } + /*********************************************************************************** CTR1 register value is updated */ + + + /* Update CTR2 register value ***************************************************************************************/ + /* Prepare DMA channel transfer register 2 (CTR2) value */ + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] = pNodeConfig->Init.TransferEventMode | + (pNodeConfig->Init.Request & (DMA_CTR2_REQSEL | DMA_CTR2_SWREQ)); + + /* Check for memory to peripheral transfer */ + if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Check for GPDMA */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) + { + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_DREQ; + } + } + /* Memory to memory transfer */ + else if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_MEMORY) + { + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_SWREQ; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Configure HW Peripheral flow control selection */ + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= pNodeConfig->Init.Mode; + + /* Check if trigger feature is active */ + if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED) + { + /* Prepare DMA channel transfer register 2 (CTR2) value */ + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= + pNodeConfig->TriggerConfig.TriggerMode | pNodeConfig->TriggerConfig.TriggerPolarity | + ((pNodeConfig->TriggerConfig.TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); + } + /*********************************************************************************** CTR2 register value is updated */ + + + /* Update CBR1 register value ***************************************************************************************/ + /* Prepare DMA channel block register 1 (CBR1) value */ + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (pNodeConfig->DataSize & DMA_CBR1_BNDT); + + /* If 2D addressing is supported by the selected DMA channel */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Set the new CBR1 Register value */ + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= + (((pNodeConfig->RepeatBlockConfig.RepeatCount - 1U) << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC); + + /* If the source address offset is negative, set SDEC bit */ + if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_SDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_SDEC); + } + + /* If the destination address offset is negative, set DDEC bit */ + if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_DDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_DDEC); + } + + /* If the repeated block source address offset is negative, set BRSEC bit */ + if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRSDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRSDEC); + } + + /* if the repeated block destination address offset is negative, set BRDEC bit */ + if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRDDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRDDEC); + } + } + /*********************************************************************************** CBR1 register value is updated */ + + + /* Update CSAR register value ***************************************************************************************/ + pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = pNodeConfig->SrcAddress; + /*********************************************************************************** CSAR register value is updated */ + + + /* Update CDAR register value ***************************************************************************************/ + pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pNodeConfig->DstAddress; + /*********************************************************************************** CDAR register value is updated */ + + /* Check if the selected channel is 2D addressing */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Update CTR3 register value *************************************************************************************/ + /* Write new CTR3 Register value : source address offset */ + if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.SrcAddrOffset); + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CTR3_SAO); + } + else + { + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = + ((uint32_t)pNodeConfig->RepeatBlockConfig.SrcAddrOffset & DMA_CTR3_SAO); + } + + /* Write new CTR3 Register value : destination address offset */ + if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.DestAddrOffset); + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |= (((uint32_t)blockoffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO); + } + else + { + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |= + (((uint32_t)pNodeConfig->RepeatBlockConfig.DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO); + } + /********************************************************************************* CTR3 register value is updated */ + + + /* Update CBR2 register value *************************************************************************************/ + /* Write new CBR2 Register value : repeated block source address offset */ + if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset); + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CBR2_BRSAO); + } + else + { + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] = + ((uint32_t)pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset & DMA_CBR2_BRSAO); + } + + /* Write new CBR2 Register value : repeated block destination address offset */ + if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset); + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |= + (((uint32_t)blockoffset & DMA_CBR2_BRSAO) << DMA_CBR2_BRDAO_Pos); + } + else + { + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |= + (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO); + } + /********************************************************************************* CBR2 register value is updated */ + + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_2D_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } + else + { + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_LINEAR_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } + + /* Update node information value ************************************************************************************/ + /* Set node information */ + pNode->NodeInfo = pNodeConfig->NodeType; + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + pNode->NodeInfo |= (NODE_CLLR_2D_DEFAULT_OFFSET << NODE_CLLR_IDX_POS); + } + else + { + pNode->NodeInfo |= (NODE_CLLR_LINEAR_DEFAULT_OFFSET << NODE_CLLR_IDX_POS); + } + /******************************************************************************** Node information value is updated */ +} + +/** + * @brief Get a DMA channel node configuration. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval None. + */ +static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode) +{ + uint16_t offset; + + /* Get node information *********************************************************************************************/ + pNodeConfig->NodeType = (pNode->NodeInfo & NODE_TYPE_MASK); + /*************************************************************************************** Node type value is updated */ + + + /* Get CTR1 fields values *******************************************************************************************/ + pNodeConfig->Init.SrcInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SINC; + pNodeConfig->Init.DestInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DINC; + pNodeConfig->Init.SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SDW_LOG2; + pNodeConfig->Init.DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + pNodeConfig->Init.SrcBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U; + pNodeConfig->Init.DestBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U; + pNodeConfig->Init.TransferAllocatedPort = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + (DMA_CTR1_SAP | DMA_CTR1_DAP); + pNodeConfig->DataHandlingConfig.DataExchange = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + (DMA_CTR1_SBX | DMA_CTR1_DBX | DMA_CTR1_DHX); + pNodeConfig->DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SSEC) != 0U) + { + pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_SEC; + } + else + { + pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_NSEC; + } + + if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DSEC) != 0U) + { + pNodeConfig->DestSecure = DMA_CHANNEL_DEST_SEC; + } + else + { + pNodeConfig->DestSecure = DMA_CHANNEL_DEST_NSEC; + } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + /*********************************************************************************** CTR1 fields values are updated */ + + + /* Get CTR2 fields values *******************************************************************************************/ + if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_SWREQ) != 0U) + { + pNodeConfig->Init.Request = DMA_REQUEST_SW; + pNodeConfig->Init.Direction = DMA_MEMORY_TO_MEMORY; + } + else + { + pNodeConfig->Init.Request = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_REQSEL; + + if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_DREQ) != 0U) + { + pNodeConfig->Init.Direction = DMA_MEMORY_TO_PERIPH; + } + else + { + pNodeConfig->Init.Direction = DMA_PERIPH_TO_MEMORY; + } + } + + pNodeConfig->Init.BlkHWRequest = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_BREQ); + pNodeConfig->TriggerConfig.TriggerMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGM; + pNodeConfig->TriggerConfig.TriggerPolarity = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGPOL; + pNodeConfig->TriggerConfig.TriggerSelection = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & + DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos; + pNodeConfig->Init.TransferEventMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TCEM; + /*********************************************************************************** CTR2 fields values are updated */ + + + /* Get CBR1 fields **************************************************************************************************/ + pNodeConfig->DataSize = pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BNDT; + + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + pNodeConfig->RepeatBlockConfig.RepeatCount = + ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos) + 1U; + } + else + { + pNodeConfig->RepeatBlockConfig.RepeatCount = 1U; + } + /*********************************************************************************** CBR1 fields values are updated */ + + + /* Get CSAR field ***************************************************************************************************/ + pNodeConfig->SrcAddress = pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]; + /************************************************************************************** CSAR field value is updated */ + + + /* Get CDAR field ***************************************************************************************************/ + pNodeConfig->DstAddress = pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]; + /************************************************************************************** CDAR field value is updated */ + + /* Check if the selected channel is 2D addressing */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Get CTR3 field *************************************************************************************************/ + offset = (uint16_t)(pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_SAO); + pNodeConfig->RepeatBlockConfig.SrcAddrOffset = (int32_t)offset; + + offset = (uint16_t)((pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos); + pNodeConfig->RepeatBlockConfig.DestAddrOffset = (int32_t)offset; + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_SDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.SrcAddrOffset *= (-1); + } + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_DDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.DestAddrOffset *= (-1); + } + /************************************************************************************ CTR3 field value is updated */ + + + /* Get CBR2 fields ************************************************************************************************/ + offset = (uint16_t)(pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRSAO); + pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = (int32_t)offset; + + offset = (uint16_t)((pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos); + pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = (int32_t)offset; + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRSDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset *= (-1); + } + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRDDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset *= (-1); + } + /************************************************************************************ CBR2 field value is updated */ + } + else + { + /* Get CTR3 field *************************************************************************************************/ + pNodeConfig->RepeatBlockConfig.SrcAddrOffset = 0; + pNodeConfig->RepeatBlockConfig.DestAddrOffset = 0; + /************************************************************************************ CTR3 field value is updated */ + + + /* Get CBR2 fields ************************************************************************************************/ + pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = 0; + pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = 0; + /************************************************************************************ CBR2 field value is updated */ + } +} + +/** + * @brief Check nodes base addresses compatibility. + * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. + * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. + * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. + * @retval Return 0 when nodes addresses are compatible, 1 otherwise. + */ +static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3) +{ + uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA); + uint32_t ref = 0U; + + /* Check node 1 address */ + if ((uint32_t)pNode1 != 0U) + { + /* Check addresses offset compatibility */ + if (((uint32_t)pNode1 & 0xFFFFU) > 0xFFE0U) + { + return 1U; + } + ref = (uint32_t)pNode1; + } + /* Check node 2 address */ + else if ((uint32_t)pNode2 != 0U) + { + /* Check addresses offset compatibility */ + if (((uint32_t)pNode2 & 0xFFFFU) > 0xFFE0U) + { + return 1U; + } + ref = (uint32_t)pNode2; + } + /* Check node 3 address */ + else if ((uint32_t)pNode3 != 0U) + { + /* Check addresses offset compatibility */ + if (((uint32_t)pNode3 & 0xFFFFU) > 0xFFE0U) + { + return 1U; + } + ref = (uint32_t)pNode3; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check addresses compatibility */ + if (temp != ((uint32_t)ref & DMA_CLBAR_LBA)) + { + return 1U; + } + + return 0U; +} + +/** + * @brief Check nodes types compatibility. + * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. + * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. + * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. + * @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible. + */ +static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3) +{ + uint32_t ref = 0U; + + /* Check node 1 parameter */ + if (pNode1 != NULL) + { + ref = pNode1->NodeInfo & NODE_TYPE_MASK; + } + /* Check node 2 parameter */ + else if (pNode2 != NULL) + { + ref = pNode2->NodeInfo & NODE_TYPE_MASK; + } + /* Check node 3 parameter */ + else if (pNode3 != NULL) + { + ref = pNode3->NodeInfo & NODE_TYPE_MASK; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check node 2 parameter */ + if (pNode2 != NULL) + { + /* Check node type compatibility */ + if (ref != (pNode2->NodeInfo & NODE_TYPE_MASK)) + { + return 2U; + } + } + + /* Check node 3 parameter */ + if (pNode3 != NULL) + { + /* Check node type compatibility */ + if (ref != (pNode3->NodeInfo & NODE_TYPE_MASK)) + { + return 3U; + } + } + + return 0U; +} + +/** + * @brief Check nodes types compatibility. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param cllr_mask : Pointer to CLLR register mask value. + * @param cllr_offset : Pointer to CLLR register offset value. + * @retval None. + */ +static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, + uint32_t *const cllr_mask, + uint32_t *const cllr_offset) +{ + /* Check node type */ + if ((pNode->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Update CLLR register mask value */ + if (cllr_mask != NULL) + { + *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | + DMA_CLLR_UB2 | DMA_CLLR_ULL; + } + + /* Update CLLR register offset */ + if (cllr_offset != NULL) + { + *cllr_offset = NODE_CLLR_2D_DEFAULT_OFFSET; + } + } + /* Update CLLR and register number for linear addressing node */ + else + { + /* Update CLLR register mask value */ + if (cllr_mask != NULL) + { + *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; + } + + /* Update CLLR register offset */ + if (cllr_offset != NULL) + { + *cllr_offset = NODE_CLLR_LINEAR_DEFAULT_OFFSET; + } + } +} + +/** + * @brief Find node in queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers configurations. + * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information. + * @retval Return 0 when node is found in selected queue, otherwise node is not found. + */ +static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList, + DMA_NodeTypeDef const *const pNode, + DMA_NodeInQInfoTypeDef *const NodeInfo) +{ + uint32_t node_idx = 0U; + uint32_t currentnode_address = 0U; + uint32_t previousnode_address = 0U; + uint32_t cllr_offset = NodeInfo->cllr_offset; + + /* Find last node in queue */ + if (pNode == NULL) + { + /* Check that previous node is linked to the selected queue */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Increment node index */ + node_idx++; + } + } + /* Find selected node node in queue */ + else + { + /* Check that previous node is linked to the selected queue */ + while ((node_idx < pQList->NodeNumber) && (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA))) + { + /* Get head node address */ + if (node_idx == 0U) + { + currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Increment node index */ + node_idx++; + } + } + + /* Check stored address */ + if (pNode != NULL) + { + if (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA)) + { + return 1U; + } + } + + /* Update current node position */ + NodeInfo->currentnode_pos = node_idx; + + /* Update previous node address */ + NodeInfo->previousnode_addr = previousnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + + /* Update current node address */ + NodeInfo->currentnode_addr = currentnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + + /* Update next node address */ + if (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] != 0U) + { + NodeInfo->nextnode_addr = (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] & + DMA_CLLR_LA) | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + } + + return 0U; +} + +/** + * @brief Reset queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information. + * @retval None. + */ +static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList, + DMA_NodeInQInfoTypeDef const *const NodeInfo) +{ + uint32_t node_idx = 0U; + uint32_t currentnode_address = 0U; + uint32_t previousnode_address; + uint32_t cllr_offset = NodeInfo->cllr_offset; + + /* Check that previous node is linked to the selected queue */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + previousnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + currentnode_address = (pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA); + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Reset node */ + ((DMA_NodeTypeDef *)(previousnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] = 0U; + + /* Increment node index */ + node_idx++; + } +} + +/** + * @brief Fill source node registers values by destination nodes registers values. + * @param pSrcNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list source node registers + * configurations. + * @param pDestNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list destination node registers + * configurations. + * @retval None. + */ +static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode, + DMA_NodeTypeDef *const pDestNode) +{ + /* Repeat for all register nodes */ + for (uint32_t reg_idx = 0U; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) + { + pDestNode->LinkRegisters[reg_idx] = pSrcNode->LinkRegisters[reg_idx]; + } + + /* Fill node information */ + pDestNode->NodeInfo = pSrcNode->NodeInfo; +} + +/** + * @brief Convert node to dynamic. + * @param ContextNodeAddr : The context node address. + * @param CurrentNodeAddr : The current node address to be converted. + * @param RegisterNumber : The register number to be converted. + * @retval None. + */ +static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber) +{ + uint32_t currentnode_reg_counter = 0U; + uint32_t contextnode_reg_counter = 0U; + uint32_t cllr_idx = RegisterNumber - 1U; + DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; + uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL + }; + + /* Update ULL position according to register number */ + update_link[cllr_idx] = update_link[NODE_MAXIMUM_SIZE - 1U]; + + /* Repeat for all node registers */ + while (contextnode_reg_counter != RegisterNumber) + { + /* Check if register values are equal (exception for CSAR, CDAR and CLLR registers) */ + if ((context_node->LinkRegisters[contextnode_reg_counter] == + current_node->LinkRegisters[currentnode_reg_counter]) && + (contextnode_reg_counter != NODE_CSAR_DEFAULT_OFFSET) && + (contextnode_reg_counter != NODE_CDAR_DEFAULT_OFFSET) && + (contextnode_reg_counter != (RegisterNumber - 1U))) + { + /* Format the node according to unused registers */ + DMA_List_FormatNode(current_node, currentnode_reg_counter, RegisterNumber, NODE_DYNAMIC_FORMAT); + + /* Update CLLR index */ + cllr_idx --; + + /* Update CLLR fields */ + current_node->LinkRegisters[cllr_idx] &= ~update_link[contextnode_reg_counter]; + } + else + { + /* Update context node register fields with new values */ + context_node->LinkRegisters[contextnode_reg_counter] = current_node->LinkRegisters[currentnode_reg_counter]; + + /* Update CLLR fields */ + current_node->LinkRegisters[cllr_idx] |= update_link[contextnode_reg_counter]; + + /* Increment current node number register counter */ + currentnode_reg_counter++; + } + + /* Increment context node number register counter */ + contextnode_reg_counter++; + } + + /* Update node information */ + MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((currentnode_reg_counter - 1U) << NODE_CLLR_IDX_POS)); + + /* Clear unused node fields */ + DMA_List_ClearUnusedFields(current_node, currentnode_reg_counter); +} + +/** + * @brief Convert node to static. + * @param ContextNodeAddr : The context node address. + * @param CurrentNodeAddr : The current node address to be converted. + * @param RegisterNumber : The register number to be converted. + * @retval None. + */ +static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber) +{ + uint32_t contextnode_reg_counter = 0U; + uint32_t cllr_idx; + uint32_t cllr_mask; + const DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; + uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL + }; + + /* Update ULL position according to register number */ + update_link[RegisterNumber - 1U] = update_link[NODE_MAXIMUM_SIZE - 1U]; + + /* Get context node CLLR information */ + cllr_idx = (context_node->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + cllr_mask = context_node->LinkRegisters[cllr_idx]; + + /* Repeat for all node registers */ + while (contextnode_reg_counter != RegisterNumber) + { + /* Check if node field is dynamic */ + if ((cllr_mask & update_link[contextnode_reg_counter]) == 0U) + { + /* Format the node according to unused registers */ + DMA_List_FormatNode(current_node, contextnode_reg_counter, RegisterNumber, NODE_STATIC_FORMAT); + + /* Update node field */ + current_node->LinkRegisters[contextnode_reg_counter] = context_node->LinkRegisters[contextnode_reg_counter]; + } + + /* Increment context node number register counter */ + contextnode_reg_counter++; + } + + /* Update node information */ + MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((RegisterNumber - 1U) << NODE_CLLR_IDX_POS)); +} + +/** + * @brief Format the node according to unused registers. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param RegisterIdx : The first register index to be formatted. + * @param RegisterNumber : The number of node registers. + * @param Format : The format type. + * @retval None. + */ +static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode, + uint32_t RegisterIdx, + uint32_t RegisterNumber, + uint32_t Format) +{ + if (Format == NODE_DYNAMIC_FORMAT) + { + /* Repeat for all registers to be formatted */ + for (uint32_t reg_idx = RegisterIdx; reg_idx < (RegisterNumber - 1U); reg_idx++) + { + pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx + 1U]; + } + } + else + { + /* Repeat for all registers to be formatted */ + for (uint32_t reg_idx = (RegisterNumber - 2U); reg_idx > RegisterIdx; reg_idx--) + { + pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx - 1U]; + } + } +} + +/** + * @brief Clear unused register fields. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param FirstUnusedField : The first unused field to be cleared. + * @retval None. + */ +static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode, + uint32_t FirstUnusedField) +{ + /* Repeat for all unused fields */ + for (uint32_t reg_idx = FirstUnusedField; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) + { + pNode->LinkRegisters[reg_idx] = 0U; + } +} + +/** + * @brief Update CLLR for all dynamic queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param LastNode_IsCircular : The first circular node is the last queue node or not. + * @retval None. + */ +static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t LastNode_IsCircular) +{ + uint32_t previous_cllr_offset; + uint32_t current_cllr_offset = 0U; + uint32_t previousnode_addr; + uint32_t currentnode_addr = (uint32_t)pQList->Head; + uint32_t cllr_mask; + uint32_t node_idx = 0U; + + /* Repeat for all register nodes */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + /* Get current node information */ + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + } + /* Calculate nodes addresses */ + else + { + /* Get previous node information */ + previousnode_addr = currentnode_addr; + previous_cllr_offset = current_cllr_offset; + + /* Get current node information */ + currentnode_addr = (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA) + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + + /* Calculate CLLR register value to be updated */ + cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & ~DMA_CLLR_LA) | + (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA); + + /* Set new CLLR value to previous node */ + ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] = cllr_mask; + } + + /* Increment node index */ + node_idx++; + } + + /* Check queue circularity */ + if (pQList->FirstCircularNode != 0U) + { + /* First circular queue is not last queue node */ + if (LastNode_IsCircular == 0U) + { + /* Get CLLR node information */ + DMA_List_GetCLLRNodeInfo(((DMA_NodeTypeDef *)currentnode_addr), &cllr_mask, NULL); + + /* Update CLLR register for last circular node */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = + ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + } + /* First circular queue is last queue node */ + else + { + /* Disable CLLR updating */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL; + } + } + else + { + /* Clear CLLR register for last node */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = 0U; + } +} + +/** + * @brief Update CLLR for all static queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param operation : The operation type. + * @retval None. + */ +static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t operation) +{ + uint32_t currentnode_addr = (uint32_t)pQList->Head; + uint32_t current_cllr_offset = ((uint32_t)pQList->Head->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + uint32_t cllr_default_offset; + uint32_t cllr_default_mask; + uint32_t cllr_mask; + uint32_t node_idx = 0U; + + /* Get CLLR node information */ + DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_default_mask, &cllr_default_offset); + + /* Repeat for all register nodes (Bypass last queue node) */ + while (node_idx < pQList->NodeNumber) + { + if (operation == UPDATE_CLLR_POSITION) + { + /* Get CLLR value */ + cllr_mask = ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset]; + } + else + { + /* Calculate CLLR value */ + cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & DMA_CLLR_LA) | + cllr_default_mask; + } + + /* Set new CLLR value to default position */ + if ((node_idx == (pQList->NodeNumber - 1U)) && (pQList->FirstCircularNode == NULL)) + { + ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = 0U; + } + else + { + ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = cllr_mask; + } + + /* Update current node address with next node address */ + currentnode_addr = (currentnode_addr & DMA_CLBAR_LBA) | (cllr_mask & DMA_CLLR_LA); + + /* Update current CLLR offset with next CLLR offset */ + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + + /* Increment node index */ + node_idx++; + } +} + +/** + * @brief Clean linked-list queue variable. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval None. + */ +static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList) +{ + /* Clear head node */ + pQList->Head = NULL; + + /* Clear first circular queue node */ + pQList->FirstCircularNode = NULL; + + /* Reset node number */ + pQList->NodeNumber = 0U; + + /* Reset queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_RESET; + + /* Reset queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Reset queue type */ + pQList->Type = QUEUE_TYPE_STATIC; +} +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c new file mode 100644 index 00000000..a6d1f4f9 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c @@ -0,0 +1,874 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two diffenrents + interrupt pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x04U /* 0x10: byte offset between: IMR1/EMR1 and IMR2/EMR2 registers */ +#define EXTI_CONFIG_OFFSET 0x08U /* 0x20: byte offset between Rising1/Falling1 and Rising2/Falling2 + configuration registers */ +#define EXTI_PRIVCFGR_OFFSET 0x08U /* 0x20: byte offset between PRIVCFGR1 and PRIVCFGR2 registers */ +#define EXTI_SECCFGR_OFFSET 0x08U /* 0x20: byte offset between SECCFGR1 and SECCFGR2 registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, const EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0U) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* Configure event mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + + return HAL_OK; +} + + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configiguration structure */ + pExtiConfig->Line = hexti->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + pExtiConfig->GPIOSel = (regval >> (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & EXTI_EXTICR1_EXTI0; + } + } + + return HAL_OK; +} + + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + return HAL_OK; +} + + +/** + * @brief Register callback for a dedicaated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, + void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->RisingCallback = pPendingCbfn; + hexti->FallingCallback = pPendingCbfn; + break; + + case HAL_EXTI_RISING_CB_ID: + hexti->RisingCallback = pPendingCbfn; + break; + + case HAL_EXTI_FALLING_CB_ID: + hexti->FallingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get rising edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0U) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call rising callback */ + if (hexti->RisingCallback != NULL) + { + hexti->RisingCallback(); + } + } + + /* Get falling edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0U) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call rising callback */ + if (hexti->FallingCallback != NULL) + { + hexti->FallingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get rising edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval None. + */ +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get falling edge pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* Clear Pending bit */ + *regaddr = maskline; +} + + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions + * @brief EXTI attributes management functions. + * +@verbatim + =============================================================================== + ##### EXTI attributes functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configure the EXTI line attribute(s). + * @note Available attributes are to secure EXTI line and set EXT line as privileged. + * Default state is not secure and unprivileged access allowed. + * @note Secure and non-secure attributes can only be set from the secure + * state when the system implements the security (TZEN=1). + * @note Security and privilege attributes can be set independently. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @param LineAttributes can be one or a combination of the following values: + * @arg @ref EXTI_LINE_PRIV Privileged-only access + * @arg @ref EXTI_LINE_NPRIV Privileged/Non-privileged access + * @arg @ref EXTI_LINE_SEC Secure-only access + * @arg @ref EXTI_LINE_NSEC Secure/Non-secure access + * @retval None + */ +void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + assert_param(IS_EXTI_LINE_ATTRIBUTES(LineAttributes)); + + /* compute line register offset and line mask */ + offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (ExtiLine & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Configure privilege or non-privilege attributes */ + regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((LineAttributes & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) + { + regval |= maskline; + } + else if ((LineAttributes & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV) + { + regval &= ~maskline; + } + else + { + /* do nothing */ + } + + /* Store privilege or non-privilege attribute */ + *regaddr = regval; + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + + /* Configure secure or non-secure attributes */ + regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((LineAttributes & EXTI_LINE_SEC) == EXTI_LINE_SEC) + { + regval |= maskline; + } + else if ((LineAttributes & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) + { + regval &= ~maskline; + } + else + { + /* do nothing */ + } + + /* Store secure or non-secure attribute */ + *regaddr = regval; + +#endif /* __ARM_FEATURE_CMSE */ +} + +/** + * @brief Get the EXTI line attribute(s). + * @note Secure and non-secure attributes are only available from secure state + * when the system implements the security (TZEN=1) + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @param pLineAttributes: pointer to return line attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes) +{ + const __IO uint32_t *regaddr; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + uint32_t attributes; + + /* Check null pointer */ + if (pLineAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Compute line register offset and line mask */ + offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (ExtiLine & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Get privilege or non-privilege attribute */ + regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset)); + + if ((*regaddr & maskline) != 0U) + { + attributes = EXTI_LINE_PRIV; + } + else + { + attributes = EXTI_LINE_NPRIV; + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + + /* Get secure or non-secure attribute */ + regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset)); + + if ((*regaddr & maskline) != 0U) + { + attributes |= EXTI_LINE_SEC; + } + else + { + attributes |= EXTI_LINE_NSEC; + } + +#endif /* __ARM_FEATURE_CMSE */ + + /* return value */ + *pLineAttributes = attributes; + + return HAL_OK; +} +#if defined (EXTI_LOCKR_LOCK) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the global EXTI security and privilege configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_LockConfigAttributes(void) +{ + EXTI->LOCKR = EXTI_ATTRIBUTES_LOCKED; + + return HAL_OK; +} + +/** + * @brief Get the global EXTI security and privilege lock configuration. + * @param pLockState : Pointer to returned security and privilege configuration + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetLockConfigAttributes(uint32_t *const pLockState) +{ + uint32_t attributes; + const __IO uint32_t *regaddr; + + /* Check null pointer */ + if (pLockState == NULL) + { + return HAL_ERROR; + } + + /* Get security and privilege configuration */ + regaddr = (__IO uint32_t *)(&EXTI->LOCKR); + + if ((*regaddr & EXTI_LOCKR_LOCK) != 0U) + { + attributes = EXTI_ATTRIBUTES_LOCKED; + } + else + { + attributes = EXTI_ATTRIBUTES_UNLOCKED; + } + + /* return value */ + *pLockState = attributes; + + return HAL_OK; +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* defined (EXTI_LOCKR_LOCK) */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c new file mode 100644 index 00000000..fd8e3bfc --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c @@ -0,0 +1,983 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB C-Bus accesses to the Flash memory. + It implements the erase and program Flash memory operations and the read + and write protection mechanisms. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Option bytes programming + (+) TrustZone aware + (+) Watermark-based area protection + (+) Block-based sector protection + (+) Error code correction (ECC) + + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32H5xx devices. + + (#) FLASH Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Flash memory programming by 128 bits (user area, OBKeys) and 16 bits (OTP and Flash high-cycle + data area) + (++) There Two modes of programming : + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions : + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Callback functions are called when the flash operations are finished : + HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise + HAL_FLASH_OperationErrorCallback() + (++) Get error flag status by calling HAL_FLASH_GetError() + + (#) Option bytes management functions : + (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and + HAL_FLASH_OB_Lock() functions + (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function. + In this case, a reset is generated + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + [..] + (@) The contents of the Flash memory are not guaranteed if a device reset occurs during + a Flash memory operation. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/** + * @brief Variable used for Program/Erase sectors under interruption + */ +FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ + .ErrorCode = HAL_FLASH_ERROR_NONE, \ + .ProcedureOnGoing = 0U, \ + .Address = 0U, \ + .Bank = FLASH_BANK_1, \ + .Sector = 0U, \ + .NbSectorsToErase = 0U + }; +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_QuadWord(uint32_t FlashAddress, uint32_t DataAddress); +#if defined (FLASH_SR_OBKERR) +static void FLASH_Program_QuadWord_OBK(uint32_t FlashAddress, uint32_t DataAddress); +#endif /* FLASH_SR_OBKERR */ +static void FLASH_Program_HalfWord(uint32_t FlashAddress, uint32_t DataAddress); +#if defined(FLASH_EDATAR_EDATA_EN) +static void FLASH_Program_Word(uint32_t FlashAddress, uint32_t DataAddress); +#endif /* FLASH_EDATAR_EDATA_EN */ + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Functions FLASH Exported functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program a quad-word at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param FlashAddress specifies the address to be programmed. + * This parameter shall be aligned to the Flash word (128-bit) + * @param DataAddress specifies the address of data to be programmed + * This parameter shall be 32-bit aligned + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + __IO uint32_t *reg_cr; +#if defined (FLASH_SR_OBKERR) + __IO uint32_t *reg_obkcfgr; +#endif /* FLASH_SR_OBKERR */ + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set current operation type */ + pFlash.ProcedureOnGoing = TypeProgram; + + /* Access to SECCR or NSCR depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); +#else + reg_cr = &(FLASH_NS->NSCR); +#endif /* FLASH_OPTSR2_TZEN */ + + if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD) + { + /* Check the parameters */ + assert_param(IS_FLASH_USER_MEM_ADDRESS(FlashAddress)); + + /* Program a quad-word (128-bit) at a specified address */ + FLASH_Program_QuadWord(FlashAddress, DataAddress); + } +#if defined (FLASH_SR_OBKERR) + else if ((TypeProgram == FLASH_TYPEPROGRAM_QUADWORD_OBK) || (TypeProgram == FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT)) + { + /* Check the parameters */ + assert_param(IS_FLASH_OBK_ADDRESS(FlashAddress)); + + /* Program a quad-word (128-bit) of OBK at a specified address */ + FLASH_Program_QuadWord_OBK(FlashAddress, DataAddress); + } +#endif /* FLASH_SR_OBKERR */ +#if defined (FLASH_EDATAR_EDATA_EN) + else if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_HALFWORD_EDATA) + { + /* Check the parameters */ + assert_param(IS_FLASH_EDATA_ADDRESS(FlashAddress)); + + /* Program a Flash high-cycle data half-word at a specified address */ + FLASH_Program_HalfWord(FlashAddress, DataAddress); + } + else if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_WORD_EDATA) + { + /* Check the parameters */ + assert_param(IS_FLASH_EDATA_ADDRESS(FlashAddress)); + + /* Program a Flash high-cycle data half-word at a specified address */ + FLASH_Program_Word(FlashAddress, DataAddress); + } +#endif /* FLASH_EDATAR_EDATA_EN */ + else + { + /* Check the parameters */ + assert_param(IS_FLASH_OTP_ADDRESS(FlashAddress)); + + /* Program an OTP half-word at a specified address */ + FLASH_Program_HalfWord(FlashAddress, DataAddress); + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + +#if defined (FLASH_SR_OBKERR) + /* If the program operation is completed, disable the PG */ + CLEAR_BIT((*reg_cr), (TypeProgram & ~(FLASH_NON_SECURE_MASK | FLASH_OBK | FLASH_OTP | FLASH_OBKCFGR_ALT_SECT))); + + /* Clear alternate sector bit */ + if (TypeProgram == FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT) + { + reg_obkcfgr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECOBKCFGR) : &(FLASH_NS->NSOBKCFGR); + CLEAR_BIT((*reg_obkcfgr), FLASH_OBKCFGR_ALT_SECT); + } +#else + /* If the program operation is completed, disable the PG */ + CLEAR_BIT((*reg_cr), (TypeProgram & ~(FLASH_NON_SECURE_MASK | FLASH_OTP))); +#endif /* FLASH_SR_OBKERR */ + } + /* return status */ + return status; +} + +/** + * @brief Program a quad-word at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param FlashAddress specifies the address to be programmed. + * This parameter shall be aligned to the Flash word (128-bit) + * @param DataAddress specifies the address of data to be programmed + * This parameter shall be 32-bit aligned + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = TypeProgram; + pFlash.Address = FlashAddress; + + /* Access to SECCR or NSCR depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); +#else + reg_cr = &(FLASH_NS->NSCR); +#endif /* FLASH_OPTSR2_TZEN */ + + /* Enable End of Operation and Error interrupts */ +#if defined (FLASH_SR_OBKERR) + (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | \ + FLASH_IT_STRBERR | FLASH_IT_INCERR | FLASH_IT_OBKERR | \ + FLASH_IT_OBKWERR); +#else + (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | \ + FLASH_IT_STRBERR | FLASH_IT_INCERR); +#endif /* FLASH_SR_OBKERR */ + + if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD) + { + /* Check the parameters */ + assert_param(IS_FLASH_USER_MEM_ADDRESS(FlashAddress)); + + /* Program a quad-word (128-bit) at a specified address */ + FLASH_Program_QuadWord(FlashAddress, DataAddress); + } +#if defined (FLASH_SR_OBKERR) + else if (((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD_OBK) || \ + ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT)) + { + /* Check the parameters */ + assert_param(IS_FLASH_OBK_ADDRESS(FlashAddress)); + + /* Program a quad-word (128-bit) of OBK at a specified address */ + FLASH_Program_QuadWord_OBK(FlashAddress, DataAddress); + } +#endif /* FLASH_SR_OBKERR */ +#if defined (FLASH_EDATAR_EDATA_EN) + else if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_HALFWORD_EDATA) + { + /* Check the parameters */ + assert_param(IS_FLASH_EDATA_ADDRESS(FlashAddress)); + + /* Program a Flash high-cycle data half-word at a specified address */ + FLASH_Program_HalfWord(FlashAddress, DataAddress); + } + else if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_WORD_EDATA) + { + /* Check the parameters */ + assert_param(IS_FLASH_EDATA_ADDRESS(FlashAddress)); + + /* Program a Flash high-cycle data word at a specified address */ + FLASH_Program_Word(FlashAddress, DataAddress); + } +#endif /* FLASH_EDATAR_EDATA_EN */ + else + { + /* Check the parameters */ + assert_param(IS_FLASH_OTP_ADDRESS(FlashAddress)); + + /* Program an OTP word at a specified address */ + FLASH_Program_HalfWord(FlashAddress, DataAddress); + } + } + + /* return status */ + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t param = 0U; + uint32_t errorflag; + __IO uint32_t *reg_cr; + __IO uint32_t *reg_ccr; + const __IO uint32_t *reg_sr; + const __IO uint32_t *reg_ecccorr; + + /* Access to CR, CCR and SR registers depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); + reg_ccr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCCR) : &(FLASH_NS->NSCCR); + reg_sr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECSR) : &(FLASH_NS->NSSR); +#else + reg_cr = &(FLASH_NS->NSCR); + reg_ccr = &(FLASH_NS->NSCCR); + reg_sr = &(FLASH_NS->NSSR); +#endif /* FLASH_OPTSR2_TZEN */ + reg_ecccorr = &(FLASH->ECCCORR); + + /* Save Flash errors */ + errorflag = (*reg_sr) & FLASH_FLAG_SR_ERRORS; + /* Add option byte error flag, if any */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + errorflag |= (FLASH->NSSR & FLASH_FLAG_OPTCHANGEERR); +#endif /* __ARM_FEATURE_CMSE */ + + /* Set parameter of the callback */ + if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_SECTORS) + { + param = pFlash.Sector; + } + else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE) + { + param = pFlash.Bank; + } + else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD) + { + param = pFlash.Address; + } + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } + + /* Clear operation bit on the on-going procedure */ + CLEAR_BIT((*reg_cr), (pFlash.ProcedureOnGoing & ~(FLASH_NON_SECURE_MASK))); + + /* Check FLASH operation error flags */ + if (errorflag != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= errorflag; + + /* Clear error programming flags */ + (*reg_ccr) = errorflag & FLASH_FLAG_SR_ERRORS; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((errorflag & FLASH_FLAG_OPTCHANGEERR) != 0U) + { + FLASH->NSCCR = FLASH_FLAG_OPTCHANGEERR; + } +#endif /* __ARM_FEATURE_CMSE */ + + /* Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = 0U; + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(param); + } + + /* Check FLASH End of Operation flag */ + if (((*reg_sr) & FLASH_FLAG_EOP) != 0U) + { + /* Clear FLASH End of Operation pending bit */ + (*reg_ccr) = FLASH_FLAG_EOP; + + if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_SECTORS) + { + /* Nb of sector to erased can be decreased */ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase */ + if (pFlash.NbSectorsToErase != 0U) + { + /* Increment sector number */ + pFlash.Sector++; + FLASH_Erase_Sector(pFlash.Sector, pFlash.Bank); + } + else + { + /* No more sectors to erase */ + /* Reset sector parameter and stop erase sectors procedure */ + param = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = 0U; + } + } + else + { + /* Clear the procedure ongoing */ + pFlash.ProcedureOnGoing = 0U; + } + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(param); + } + + /* Check FLASH ECC correction flag */ + if ((*reg_ecccorr & FLASH_ECCR_ECCC) != 0U) + { + /* Call User callback */ + HAL_FLASHEx_EccCorrectionCallback(); + + /* Clear ECC correction flag in order to allow new ECC error record */ + FLASH->ECCCORR |= FLASH_ECCR_ECCC; + } + + if (pFlash.ProcedureOnGoing == 0U) + { + /* Disable Flash Operation and Error source interrupt */ +#if defined (FLASH_SR_OBKERR) + (*reg_cr) &= ~(FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | \ + FLASH_IT_STRBERR | FLASH_IT_INCERR | FLASH_IT_OBKERR | \ + FLASH_IT_OBKWERR | FLASH_IT_OPTCHANGEERR); +#else + (*reg_cr) &= ~(FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | \ + FLASH_IT_STRBERR | FLASH_IT_INCERR | FLASH_IT_OPTCHANGEERR); +#endif /* FLASH_SR_OBKERR */ + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector which has been erased + * (if 0xFFFFFFFF, it means that all the selected sectors have been erased) + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector number which returned an error + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (READ_BIT(FLASH->NSCR, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Control Register access */ + WRITE_REG(FLASH->NSKEYR, FLASH_KEY1); + WRITE_REG(FLASH->NSKEYR, FLASH_KEY2); + + /* Verify Flash CR is unlocked */ + if (READ_BIT(FLASH->NSCR, FLASH_CR_LOCK) != 0U) + { + status = HAL_ERROR; + } + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (status == HAL_OK) + { + if (READ_BIT(FLASH->SECCR, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Control Register access */ + WRITE_REG(FLASH->SECKEYR, FLASH_KEY1); + WRITE_REG(FLASH->SECKEYR, FLASH_KEY2); + + /* verify Flash CR is unlocked */ + if (READ_BIT(FLASH->SECCR, FLASH_CR_LOCK) != 0U) + { + status = HAL_ERROR; + } + } + } +#endif /* __ARM_FEATURE_CMSE */ + + return status; +} + +/** + * @brief Locks the FLASH control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Set the LOCK Bit to lock the FLASH Control Register access */ + SET_BIT(FLASH->NSCR, FLASH_CR_LOCK); + + /* Verify Flash is locked */ + if (READ_BIT(FLASH->NSCR, FLASH_CR_LOCK) == 0U) + { + status = HAL_ERROR; + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (status == HAL_OK) + { + /* Set the LOCK Bit to lock the FLASH Control Register access */ + SET_BIT(FLASH->SECCR, FLASH_CR_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->SECCR, FLASH_CR_LOCK) == 0U) + { + status = HAL_ERROR; + } + } +#endif /* __ARM_FEATURE_CMSE */ + + return status; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + { + /* Authorizes the Option Byte registers programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2); + + /* Verify that the Option Bytes are unlocked */ + if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK); + + /* Verify that the Option Bytes are locked */ + if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + { + return HAL_OK; + } + + return HAL_ERROR; +} + +/** + * @brief Launch the option bytes loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + HAL_StatusTypeDef status; + + /* Set OPTSTRT Bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART); + + /* Wait for OB change operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + return status; +} + +#if defined(FLASH_CR_PUF_LAUNCH) +/** + * @brief Launch the PUF preparation. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_PUF_Launch(void) +{ + HAL_StatusTypeDef status; + + /* Set PUF_LAUNCH Bit */ + SET_BIT(FLASH->NSCR, FLASH_CR_PUF_LAUNCH); + + /* Wait for OB change operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + return status; +} +#endif /* FLASH_CR_PUF_LAUNCH */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval HAL_FLASH_ERRORCode The returned value can be: + * @arg HAL_FLASH_ERROR_NONE : No error set + * @arg HAL_FLASH_ERROR_WRP : Write Protection Error + * @arg HAL_FLASH_ERROR_PGS : Program Sequence Error + * @arg HAL_FLASH_ERROR_STRB : Strobe Error + * @arg HAL_FLASH_ERROR_INC : Inconsistency Error + * @arg HAL_FLASH_ERROR_OBK : OBK Error + * @arg HAL_FLASH_ERROR_OBKW : OBK Write Error + * @arg HAL_FLASH_ERROR_OB_CHANGE : Option Byte Change Error + * @arg HAL_FLASH_ERROR_ECCC : ECC Single Correction Error + * @arg HAL_FLASH_ERROR_ECCD : ECC Double Detection Error + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY, WBNE and DBNE flags to be reset. + Even if the FLASH operation fails, the BUSY, WBNE and DBNE flags will be reset and an error + flag will be set */ + + uint32_t errorflag; + const __IO uint32_t *reg_sr; + __IO uint32_t *reg_ccr; + + uint32_t tickstart = HAL_GetTick(); + + /* Access to SR register depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_sr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECSR) : &(FLASH_NS->NSSR); +#else + reg_sr = &(FLASH_NS->NSSR); +#endif /* FLASH_OPTSR2_TZEN */ + + /* Wait on BSY, WBNE and DBNE flags to be reset */ + while (((*reg_sr) & (FLASH_FLAG_BSY | FLASH_FLAG_WBNE | FLASH_FLAG_DBNE)) != 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Access to CCR register depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_ccr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCCR) : &(FLASH_NS->NSCCR); +#else + reg_ccr = &(FLASH_NS->NSCCR); +#endif /* FLASH_OPTSR2_TZEN */ + + /* Check FLASH operation error flags */ + errorflag = ((*reg_sr) & FLASH_FLAG_SR_ERRORS); + /* Add option byte error flag, if any */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + errorflag |= (FLASH->NSSR & FLASH_FLAG_OPTCHANGEERR); +#endif /* __ARM_FEATURE_CMSE */ + + /* In case of error reported in Flash SR or OPTSR registers */ + if (errorflag != 0U) + { + /*Save the error code*/ + pFlash.ErrorCode |= errorflag; + + /* Clear error flags */ + (*reg_ccr) = errorflag & FLASH_FLAG_SR_ERRORS; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((errorflag & FLASH_FLAG_OPTCHANGEERR) != 0U) + { + FLASH->NSCCR = FLASH_FLAG_OPTCHANGEERR; + } +#endif /* __ARM_FEATURE_CMSE */ + + return HAL_ERROR; + } + + /* Check FLASH End of Operation flag */ + if (((*reg_sr) & FLASH_FLAG_EOP) != 0U) + { + /* Clear FLASH End of Operation pending bit */ + (*reg_ccr) = FLASH_FLAG_EOP; + } + + /* If there is no error flag set */ + return HAL_OK; +} + +/** + * @brief Program a quad-word (128-bit) at a specified address. + * @param FlashAddress specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_QuadWord(uint32_t FlashAddress, uint32_t DataAddress) +{ + uint8_t index = 4; + uint32_t *dest_addr = (uint32_t *)FlashAddress; + uint32_t *src_addr = (uint32_t *)DataAddress; + uint32_t primask_bit; + __IO uint32_t *reg_cr; + + /* Access to SECCR or NSCR registers depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); +#else + reg_cr = &(FLASH_NS->NSCR); +#endif /* FLASH_OPTSR2_TZEN */ + + /* Set PG bit */ + SET_BIT((*reg_cr), FLASH_CR_PG); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the quad-word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + index--; + } while (index != 0U); + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +#if defined (FLASH_SR_OBKERR) +/** + * @brief Program a quad-word (128-bit) of OBK at a specified address. + * @param FlashAddress specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_QuadWord_OBK(uint32_t FlashAddress, uint32_t DataAddress) +{ + uint8_t index = 4; + uint32_t *dest_addr = (uint32_t *)FlashAddress; + uint32_t *src_addr = (uint32_t *)DataAddress; + uint32_t primask_bit; + __IO uint32_t *reg_cr; + __IO uint32_t *reg_obkcfgr; + + /* Access to SECCR or NSCR registers depends on operation type */ + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); + reg_obkcfgr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECOBKCFGR) : &(FLASH_NS->NSOBKCFGR); + + /* Set PG bit */ + SET_BIT((*reg_cr), FLASH_CR_PG); + + /* Set ALT_SECT bit */ + SET_BIT((*reg_obkcfgr), pFlash.ProcedureOnGoing & FLASH_OBKCFGR_ALT_SECT); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the quad-word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + index--; + } while (index != 0U); + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} +#endif /* FLASH_SR_OBKERR */ + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @param FlashAddress specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t FlashAddress, uint32_t DataAddress) +{ + __IO uint32_t *reg_cr; + + /* Access to SECCR or NSCR registers depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); +#else + reg_cr = &(FLASH_NS->NSCR); +#endif /* FLASH_OPTSR2_TZEN */ + + /* Set HalfWord_PG bit */ + SET_BIT((*reg_cr), FLASH_CR_PG); + + /* Program a halfword word (16 bits) */ + *(__IO uint16_t *)FlashAddress = *(__IO uint16_t *)DataAddress; +} + +#if defined(FLASH_EDATAR_EDATA_EN) +/** + * @brief Program a word (32-bit) at a specified address. + * @param FlashAddress specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_Word(uint32_t FlashAddress, uint32_t DataAddress) +{ + __IO uint32_t *reg_cr; + + /* Access to SECCR or NSCR registers depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); +#else + reg_cr = &(FLASH_NS->NSCR); +#endif /* FLASH_OPTSR2_TZEN */ + + /* Set PG bit */ + SET_BIT((*reg_cr), FLASH_CR_PG); + + *(__IO uint32_t *)FlashAddress = *(__IO uint32_t *)DataAddress; +} +#endif /* FLASH_EDATAR_EDATA_EN */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c new file mode 100644 index 00000000..1eb5b88e --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c @@ -0,0 +1,2161 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extension peripheral: + * + Extended programming operations functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### Flash Extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32H5xx + devices contains the following additional features + + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + capability (RWW) + (+) Dual bank memory organization + (+) Product State protection + (+) Write protection + (+) Secure access only protection + (+) Bank / register swapping (when Dual-Bank) + (+) Watermark-based secure protection + (+) Block-based secure protection + (+) Block-based privilege protection + (+) Hide Protection areas + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32H5xx devices. It includes + (#) FLASH Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Sector erase, bank erase and dual-bank mass erase + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to: + (++) Configure the write protection per bank + (++) Set the Product State + (++) Program the user Option Bytes + (++) Configure the watermark security for each area + (++) Configure the Hide protection areas + (++) Configure the Boot addresses + + (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to: + (++) Get the value of a write protection area + (++) Get the Product State + (++) Get the value of the user Option Bytes + (++) Get the configuration of watermark security areas + (++) Get the configuration of Hide protection areas + (++) Get the value of a boot address + + (#) Block-based secure / privilege area configuration function: Use HAL_FLASHEx_ConfigBBAttributes() + (++) Bit-field allowing to secure or un-secure each sector + (++) Bit-field allowing to privilege or un-privilege each sector + + (#) Get the block-based secure / privilege area configuration function: Use HAL_FLASHEx_GetConfigBBAttributes() + (++) Return the configuration of the block-based security and privilege for all the sectors + + (#) Privilege mode configuration function: Use HAL_FLASHEx_ConfigPrivMode() + (++) FLASH register can be protected against non-privilege accesses + + (#) Get the privilege mode configuration function: Use HAL_FLASHEx_GetPrivMode() + (++) Return if the FLASH registers are protected against non-privilege accesses + + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +static void FLASH_MassErase(uint32_t Banks); +#if defined (FLASH_SR_OBKERR) +static void FLASH_OBKErase(void); +#endif /* FLASH_SR_OBKERR */ +static void FLASH_OB_EnableWRP(uint64_t WRPSector, uint32_t Banks); +static void FLASH_OB_DisableWRP(uint64_t WRPSector, uint32_t Bank); +static void FLASH_OB_GetWRP(uint32_t Bank, uint32_t *WRPState, uint64_t *WRPSector); +static void FLASH_OB_ProdStateConfig(uint32_t ProdStateConfig); +static uint32_t FLASH_OB_GetProdState(void); +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig1, uint32_t UserConfig2); +static void FLASH_OB_GetUser(uint32_t *UserConfig1, uint32_t *UserConfig2); +static void FLASH_OB_BootAddrConfig(uint32_t BootOption, uint32_t BootAddress); +static void FLASH_OB_BootLockConfig(uint32_t BootLockOption, uint32_t BootLockConfig); +static void FLASH_OB_GetBootConfig(uint32_t BootOption, uint32_t *BootAddress, uint32_t *BootLockConfig); +static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block); +static uint32_t FLASH_OB_OTP_GetLock(void); +static void FLASH_OB_HDPConfig(uint32_t Banks, uint32_t HDPStartSector, uint32_t HDPEndSector); +static void FLASH_OB_GetHDP(uint32_t Bank, uint32_t *HDPStartSector, uint32_t *HDPEndSector); +#if defined(FLASH_EDATAR_EDATA_EN) +static void FLASH_OB_EDATAConfig(uint32_t Banks, uint32_t EDATASize); +static void FLASH_OB_GetEDATA(uint32_t Bank, uint32_t *EDATASize); +#endif /* FLASH_EDATAR_EDATA_EN */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +static void FLASH_OB_WMSECConfig(uint32_t Banks, uint32_t WMSecStartSector, uint32_t WMSecEndSector); +static void FLASH_OB_GetWMSEC(uint32_t Bank, uint32_t *WMSecStartSector, uint32_t *WMSecEndSector); +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Extended IO operation functions + * @brief FLASHEx Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + programming operations Operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] SectorError pointer to variable that contains the configuration + * information on faulty sector in case of error (0xFFFFFFFF means that all + * the sectors have been correctly erased). + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) +{ + HAL_StatusTypeDef status; + uint32_t sector_index; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Current operation type */ + pFlash.ProcedureOnGoing = pEraseInit->TypeErase; + + /* Access to SECCR or NSCR depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); +#else + reg_cr = &(FLASH_NS->NSCR); +#endif /* FLASH_OPTSR2_TZEN */ + + if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE) + { + /* Mass erase to be done */ + FLASH_MassErase(pEraseInit->Banks); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } +#if defined (FLASH_SR_OBKERR) + else if (pEraseInit->TypeErase == FLASH_TYPEERASE_OBK_ALT) + { + /* OBK erase to be done */ + FLASH_OBKErase(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_SR_OBKERR */ + else + { + /* Initialization of SectorError variable */ + *SectorError = 0xFFFFFFFFU; + + /* Erase by sector by sector to be done*/ + for (sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); \ + sector_index++) + { + FLASH_Erase_Sector(sector_index, pEraseInit->Banks); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty sector */ + *SectorError = sector_index; + break; + } + } + } + + /* If the erase operation is completed, disable the associated bits */ + CLEAR_BIT((*reg_cr), (pEraseInit->TypeErase) & (~(FLASH_NON_SECURE_MASK))); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + return status; + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = pEraseInit->TypeErase; + pFlash.Bank = pEraseInit->Banks; + + /* Access to SECCR or NSCR depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); +#else + reg_cr = &(FLASH_NS->NSCR); +#endif /* FLASH_OPTSR2_TZEN */ + + /* Enable End of Operation and Error interrupts */ +#if defined (FLASH_SR_OBKERR) + (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | \ + FLASH_IT_STRBERR | FLASH_IT_INCERR | FLASH_IT_OBKERR | \ + FLASH_IT_OBKWERR); +#else + (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | \ + FLASH_IT_STRBERR | FLASH_IT_INCERR); +#endif /* FLASH_SR_OBKERR */ + + if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE) + { + /* Mass erase to be done */ + FLASH_MassErase(pEraseInit->Banks); + } +#if defined (FLASH_SR_OBKERR) + else if (pEraseInit->TypeErase == FLASH_TYPEERASE_OBK_ALT) + { + /* OBK erase to be done */ + FLASH_OBKErase(); + } +#endif /* FLASH_SR_OBKERR */ + else + { + /* Erase by sector to be done */ + pFlash.NbSectorsToErase = pEraseInit->NbSectors; + pFlash.Sector = pEraseInit->Sector; + + /* Erase first sector and wait for IT */ + FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks); + } + } + + return status; +} + +/** + * @brief Program option bytes + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @note To configure any option bytes, the option lock bit OPTLOCK must be + * cleared with the call of HAL_FLASH_OB_Unlock() function. + * @note New option bytes configuration will be taken into account in two cases: + * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() + * - after a power-on reset (BOR reset or exit from Standby/Shutdown modes) + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset Error Code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Current operation type */ + pFlash.ProcedureOnGoing = FLASH_TYPEPROGRAM_OB; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /*Write protection configuration*/ + if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /* Enable write protection on the selected sectors */ + FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks); + } + else + { + /* Disable write protection on the selected sectors */ + FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks); + } + } + + /* Product State configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_PROD_STATE) != 0U) + { + /* Configure the product state */ + FLASH_OB_ProdStateConfig(pOBInit->ProductState); + } + + /* User Configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) + { + /* Configure the user option bytes */ + FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig, pOBInit->USERConfig2); + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Watermark secure configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_WMSEC) != 0U) + { + /* Configure the watermark-based secure area */ + FLASH_OB_WMSECConfig(pOBInit->Banks, pOBInit->WMSecStartSector, pOBInit->WMSecEndSector); + } +#endif /* __ARM_FEATURE_CMSE */ + + /* Boot Address configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_BOOTADDR) != 0U) + { + FLASH_OB_BootAddrConfig(pOBInit->BootConfig, pOBInit->BootAddr); + } + + /* Unique boot entry point configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U) + { + /* Configure the unique boot entry point */ + FLASH_OB_BootLockConfig(pOBInit->BootConfig, pOBInit->BootLock); + } + + /* OTP Block Lock configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) != 0U) + { + FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock); + } + + /* Hide Protection area configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_HDP) != 0U) + { + FLASH_OB_HDPConfig(pOBInit->Banks, pOBInit->HDPStartSector, pOBInit->HDPEndSector); + } + +#if defined(FLASH_EDATAR_EDATA_EN) + /* Flash high-cycle data area configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_EDATA) != 0U) + { + FLASH_OB_EDATAConfig(pOBInit->Banks, pOBInit->EDATASize); + } +#endif /* FLASH_EDATAR_EDATA_EN */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * @note The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2, + * as this parameter is use to get the given Bank WRP, PCROP and secured area configuration. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_PROD_STATE); + + /* Get Product State */ + pOBInit->ProductState = FLASH_OB_GetProdState(); + + /* Get the user option bytes */ + FLASH_OB_GetUser(&(pOBInit->USERConfig), &(pOBInit->USERConfig2)); + + if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2)) + { + /* Get write protection on the selected area */ + pOBInit->OptionType |= OPTIONBYTE_WRP; + FLASH_OB_GetWRP(pOBInit->Banks, &(pOBInit->WRPState), &(pOBInit->WRPSector)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Get the configuration of the watermark secure area for the selected area */ + pOBInit->OptionType |= OPTIONBYTE_WMSEC; + FLASH_OB_GetWMSEC(pOBInit->Banks, &(pOBInit->WMSecStartSector), &(pOBInit->WMSecEndSector)); +#endif /* __ARM_FEATURE_CMSE */ + + /* Get the configuration of the hide protection for the selected area */ + pOBInit->OptionType |= OPTIONBYTE_HDP; + FLASH_OB_GetHDP(pOBInit->Banks, &(pOBInit->HDPStartSector), &(pOBInit->HDPEndSector)); +#if defined (FLASH_EDATAR_EDATA_EN) + /* Get the Flash high-cycle data configuration for the selected area */ + pOBInit->OptionType |= OPTIONBYTE_EDATA; + FLASH_OB_GetEDATA(pOBInit->Banks, &(pOBInit->EDATASize)); +#endif /* FLASH_EDATAR_EDATA_EN */ + } + + /* Get boot configuration */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((pOBInit->BootConfig == OB_BOOT_NS) || (pOBInit->BootConfig == OB_BOOT_SEC)) +#else + if (pOBInit->BootConfig == OB_BOOT_NS) +#endif /* __ARM_FEATURE_CMSE */ + { + pOBInit->OptionType |= OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK; + FLASH_OB_GetBootConfig(pOBInit->BootConfig, &(pOBInit->BootAddr), &(pOBInit->BootLock)); + } + + /* Get OTP Block Lock */ + pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK; + pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock(); +} + +#if defined (FLASH_SR_OBKERR) +/** + * @brief Unlock the FLASH OBK register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBK_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (READ_BIT(FLASH->SECOBKCFGR, FLASH_OBKCFGR_LOCK) != 0U) + { + /* Authorize the FLASH OBK Register access */ + WRITE_REG(FLASH->SECOBKKEYR, FLASH_OBK_KEY1); + WRITE_REG(FLASH->SECOBKKEYR, FLASH_OBK_KEY2); + + /* Verify Flash OBK Register is unlocked */ + if (READ_BIT(FLASH->SECOBKCFGR, FLASH_OBKCFGR_LOCK) != 0U) + { + status = HAL_ERROR; + } + } +#else + if (READ_BIT(FLASH->NSOBKCFGR, FLASH_OBKCFGR_LOCK) != 0U) + { + /* Authorize the FLASH OBK Register access */ + WRITE_REG(FLASH->NSOBKKEYR, FLASH_OBK_KEY1); + WRITE_REG(FLASH->NSOBKKEYR, FLASH_OBK_KEY2); + + /* Verify Flash OBK Register is unlocked */ + if (READ_BIT(FLASH->NSOBKCFGR, FLASH_OBKCFGR_LOCK) != 0U) + { + status = HAL_ERROR; + } + } +#endif /* __ARM_FEATURE_CMSE */ + + return status; +} + +/** + * @brief Locks the FLASH OBK register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBK_Lock(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Set the LOCK Bit to lock the FLASH OBK Register access */ + SET_BIT(FLASH->SECOBKCFGR, FLASH_OBKCFGR_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->SECOBKCFGR, FLASH_OBKCFGR_LOCK) != 0U) + { + status = HAL_OK; + } +#else + /* Set the LOCK Bit to lock the FLASH OBK Register access */ + SET_BIT(FLASH->NSOBKCFGR, FLASH_OBKCFGR_LOCK); + + /* Verify Flash OBK is locked */ + if (READ_BIT(FLASH->NSOBKCFGR, FLASH_OBKCFGR_LOCK) != 0U) + { + status = HAL_OK; + } +#endif /* __ARM_FEATURE_CMSE */ + + return status; +} + +/** + * @brief Swap the FLASH Option Bytes Keys (OBK) + * @param SwapOffset Specifies the number of keys to be swapped. + * This parameter can be a value between 0 (no OBK data swapped) and 511 (all OBK data swapped). + * Typical value are available in @ref FLASH_OBK_SWAP_Offset + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap(uint32_t SwapOffset) +{ + HAL_StatusTypeDef status; + __IO uint32_t *reg_obkcfgr; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Access to SECOBKCFGR or NSOBKCFGR registers depends on operation type */ + reg_obkcfgr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECOBKCFGR) : &(FLASH_NS->NSOBKCFGR); + + /* Set OBK swap offset */ + MODIFY_REG((*reg_obkcfgr), FLASH_OBKCFGR_SWAP_OFFSET, (SwapOffset << FLASH_OBKCFGR_SWAP_OFFSET_Pos)); + + /* Set OBK swap request */ + SET_BIT((*reg_obkcfgr), FLASH_OBKCFGR_SWAP_SECT_REQ); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + + return status; +} +/** + * @brief Swap the FLASH Option Bytes Keys (OBK) with interrupt enabled + * @param SwapOffset Specifies the number of keys to be swapped. + * This parameter can be a value between 0 (no OBK data swapped) and 511 (all OBK data swapped). + * Typical value are available in @ref FLASH_OBK_SWAP_Offset + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap_IT(uint32_t SwapOffset) +{ + HAL_StatusTypeDef status; + __IO uint32_t *reg_obkcfgr; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Access to SECOBKCFGR or NSOBKCFGR registers depends on operation type */ + reg_obkcfgr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECOBKCFGR) : &(FLASH_NS->NSOBKCFGR); + + /* Enable End of Operation and Error interrupts */ + (*reg_obkcfgr) |= (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | FLASH_IT_STRBERR | FLASH_IT_INCERR); + + /* Set OBK swap offset */ + MODIFY_REG((*reg_obkcfgr), FLASH_OBKCFGR_SWAP_OFFSET, (SwapOffset << FLASH_OBKCFGR_SWAP_OFFSET_Pos)); + + /* Set OBK swap request */ + SET_BIT((*reg_obkcfgr), FLASH_OBKCFGR_SWAP_SECT_REQ); + } + + return status; +} +#endif /* FLASH_SR_OBKERR */ + +/** + * @brief Return the on-going Flash Operation. After a system reset, return + * the interrupted Flash operation, if any. + * @param pFlashOperation [out] pointer to a FLASH_OperationTypeDef structure + * that contains the Flash operation information. + * @retval None + */ +void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation) +{ + uint32_t opsr_reg = FLASH->OPSR; + + /* Get Flash operation Type */ + pFlashOperation->OperationType = opsr_reg & FLASH_OPSR_CODE_OP; + + /* Get Flash operation memory */ +#if defined (FLASH_EDATAR_EDATA_EN) + pFlashOperation->FlashArea = opsr_reg & (FLASH_OPSR_DATA_OP | FLASH_OPSR_BK_OP | \ + FLASH_OPSR_SYSF_OP | FLASH_OPSR_OTP_OP); +#else + pFlashOperation->FlashArea = opsr_reg & (FLASH_OPSR_BK_OP | FLASH_OPSR_SYSF_OP | \ + FLASH_OPSR_OTP_OP); +#endif /* FLASH_EDATAR_EDATA_EN */ + /* Get Flash operation address */ + pFlashOperation->Address = opsr_reg & FLASH_OPSR_ADDR_OP; +} + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group2 FLASHEx Extension Protection configuration functions + * @brief Extension Protection configuration functions + * @{ + */ + +/** + * @brief Configure the block-based secure area. + * + * @param pBBAttributes pointer to an FLASH_BBAttributesTypeDef structure that + * contains the configuration information for the programming. + * + * @note The field pBBAttributes->Bank should indicate which area is requested + * for the block-based attributes. + * @note The field pBBAttributes->BBAttributesType should indicate which + * block-base attribute type is requested: Secure or Privilege. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(const FLASH_BBAttributesTypeDef *pBBAttributes) +{ + HAL_StatusTypeDef status; + uint8_t index; + __IO uint32_t *reg; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank)); + assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set the first Block-Based register to write */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (pBBAttributes->BBAttributesType == FLASH_BB_SEC) + { + if (pBBAttributes->Bank == FLASH_BANK_1) + { + reg = &(FLASH->SECBB1R1); + } + else + { + reg = &(FLASH->SECBB2R1); + } + } + else +#endif /* __ARM_FEATURE_CMSE */ + { + if (pBBAttributes->Bank == FLASH_BANK_1) + { + reg = &(FLASH->PRIVBB1R1); + } + else + { + reg = &(FLASH->PRIVBB2R1); + } + } + + /* Modify the register values and check that new attributes are taken in account */ + for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++) + { + *reg = pBBAttributes->BBAttributes_array[index] & FLASH_PRIVBBR_PRIVBB; + if ((*reg) != (pBBAttributes->BBAttributes_array[index] & FLASH_PRIVBBR_PRIVBB)) + { + status = HAL_ERROR; + } + reg++; + } + + /* ISB instruction is called to be sure next instructions are performed with correct attributes */ + __ISB(); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Return the block-based attributes. + * + * @param pBBAttributes [in/out] pointer to an FLASH_BBAttributesTypeDef structure + * that contains the configuration information. + * @note The field pBBAttributes->Bank should indicate which area is requested + * for the block-based attributes. + * @note The field pBBAttributes->BBAttributesType should indicate which + * block-base attribute type is requested: Secure or Privilege. + * + * @retval None + */ +void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes) +{ + uint8_t index; + __IO uint32_t *reg; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank)); + assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType)); + + /* Set the first Block-Based register to read */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (pBBAttributes->BBAttributesType == FLASH_BB_SEC) + { + if (pBBAttributes->Bank == FLASH_BANK_1) + { + reg = &(FLASH->SECBB1R1); + } + else + { + reg = &(FLASH->SECBB2R1); + } + } + else +#endif /* __ARM_FEATURE_CMSE */ + { + if (pBBAttributes->Bank == FLASH_BANK_1) + { + reg = &(FLASH->PRIVBB1R1); + } + else + { + reg = &(FLASH->PRIVBB2R1); + } + } + + /* Read the register values */ + for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++) + { + pBBAttributes->BBAttributes_array[index] = (*reg) & FLASH_PRIVBBR_PRIVBB; + reg++; + } +} + +/** + * @brief Configuration of the privilege attribute. + * + * @param PrivMode indicate privilege mode configuration + * This parameter can be one of the following values: + * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged or unprivileged access + * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied to unprivileged access + * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged or unprivileged access + * @arg FLASH_NSPRIV_DENIED: access to non-secure Flash registers is denied to unprivilege access + * + * @retval None + */ +void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CFGPRIVMODE(PrivMode)); +#if defined (FLASH_PRIVCFGR_SPRIV) + MODIFY_REG(FLASH->PRIVCFGR, (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV), PrivMode); +#else + MODIFY_REG(FLASH->PRIVCFGR, FLASH_PRIVCFGR_NSPRIV, PrivMode); +#endif /* FLASH_PRIVCFGR_SPRIV */ +} + +/** + * @brief Return the value of the privilege attribute. + * + * @retval It indicates the privilege mode configuration. + * This return value can be one of the following values: + * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged or unprivileged access + * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied to unprivileged access + * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged or unprivileged access + * @arg FLASH_NSPRIV_DENIED: access to Flash registers is denied to unprivilege accessP + */ +uint32_t HAL_FLASHEx_GetPrivMode(void) +{ +#if defined (FLASH_PRIVCFGR_SPRIV) + return (FLASH->PRIVCFGR & (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV)); +#else + return (FLASH->PRIVCFGR & FLASH_PRIVCFGR_NSPRIV); +#endif /* FLASH_PRIVCFGR_SPRIV */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configuration of the security inversion. + * + * @param SecInvState indicate the flash security state configuration + * This parameter can be one of the following values: + * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted + * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_CFGSECINV(SecInvState)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + MODIFY_REG(FLASH->SECCR, FLASH_CR_INV, SecInvState); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Return the value of the security inversion. + * + * @retval It indicates the flash security state configuration + * This return value can be one of the following values: + * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted + * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted + */ +uint32_t HAL_FLASHEx_GetSecInversion(void) +{ + return (FLASH->SECCR & FLASH_CR_INV); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure the HDP extension area. + * + * @param pHDPExtension pointer to an FLASH_HDPExtentionTypeDef structure that + * contains the configuration information. + * + * @note The field pHDPExtension->Banks should indicate which area is requested + * for the HDP extension. + * @note The field pHDPExtension->NbSectors should indicate the number of + * sector to be added to the HDP area. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(const FLASH_HDPExtensionTypeDef *pHDPExtension) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(pHDPExtension->Banks)); + assert_param(IS_FLASH_SECTOR(pHDPExtension->NbSectors)); + + /* Set the HDP extension register */ + if (pHDPExtension->Banks == FLASH_BANK_1) + { + MODIFY_REG(FLASH->HDPEXTR, FLASH_HDPEXTR_HDP1_EXT, pHDPExtension->NbSectors); + } + else if (pHDPExtension->Banks == FLASH_BANK_2) + { + MODIFY_REG(FLASH->HDPEXTR, FLASH_HDPEXTR_HDP2_EXT, (pHDPExtension->NbSectors << FLASH_HDPEXTR_HDP2_EXT_Pos)); + } + else + { + FLASH->HDPEXTR = (pHDPExtension->NbSectors << FLASH_HDPEXTR_HDP2_EXT_Pos) | pHDPExtension->NbSectors; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Mass erase of FLASH memory + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * @retval None + */ +static void FLASH_MassErase(uint32_t Banks) +{ + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + + /* Access to SECCR or NSCR registers depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); +#else + reg_cr = &(FLASH_NS->NSCR); +#endif /* FLASH_OPTSR2_TZEN */ + + /* Flash Mass Erase */ + if ((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH) + { + /* Set Mass Erase Bit */ + SET_BIT((*reg_cr), FLASH_CR_MER | FLASH_CR_START); + } + else + { + /* Proceed to erase Flash Bank */ + if ((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Erase Bank1 */ + MODIFY_REG((*reg_cr), (FLASH_CR_BKSEL | FLASH_CR_BER | FLASH_CR_START), (FLASH_CR_BER | FLASH_CR_START)); + } + + if ((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Erase Bank2 */ + SET_BIT((*reg_cr), (FLASH_CR_BER | FLASH_CR_BKSEL | FLASH_CR_START)); + } + } +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * This parameter can be a value of @ref FLASH_Sectors + * @param Banks Bank(s) where the sector will be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Sector in bank 1 to be erased + * @arg FLASH_BANK_2: Sector in bank 2 to be erased + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks) +{ + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); + + /* Access to SECCR or NSCR registers depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); +#else + reg_cr = &(FLASH_NS->NSCR); +#endif /* FLASH_OPTSR2_TZEN */ + + if ((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Reset Sector Number for Bank1 */ + (*reg_cr) &= ~(FLASH_CR_SNB | FLASH_CR_BKSEL); + + (*reg_cr) |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); + } + else + { + /* Reset Sector Number for Bank2 */ + (*reg_cr) &= ~(FLASH_CR_SNB); + + (*reg_cr) |= (FLASH_CR_SER | FLASH_CR_BKSEL | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); + } +} + +#if defined (FLASH_SR_OBKERR) +/** + * @brief Erase of FLASH OBK + * @retval None + */ +static void FLASH_OBKErase() +{ + __IO uint32_t *reg_obkcfgr; + + /* Access to SECOBKCFGR or NSOBKCFGR registers depends on operation type */ + reg_obkcfgr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECOBKCFGR) : &(FLASH_NS->NSOBKCFGR); + + /* Set OBK Erase Bit */ + SET_BIT((*reg_obkcfgr), FLASH_OBKCFGR_ALT_SECT_ERASE); +} +#endif /* FLASH_SR_OBKERR */ + +/** + * @brief Enable the write protection of the desired bank1 or bank 2 sectors + * @param WRPSector specifies the sectors to be write protected. + * This parameter can be a value of @ref FLASH_OB_Write_Protection_Sectors + * + * @param Banks the specific bank to apply WRP sectors + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: enable WRP on specified bank1 sectors + * @arg FLASH_BANK_2: enable WRP on specified bank2 sectors + * @arg FLASH_BANK_BOTH: enable WRP on both bank1 and bank2 specified sectors + * + * @retval None + */ +static void FLASH_OB_EnableWRP(uint64_t WRPSector, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); +#if defined(OB_WRP_SECTOR_128TO131) + uint32_t WRPSector_Group1 = (uint32_t)(WRPSector & 0xFFFFFFFF); + uint32_t WRPSector_Group2 = (uint32_t)((WRPSector >> 32) & 0xFFFFFFFF); + if ((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + if (WRPSector_Group1 != 0) + { + /* Enable Write Protection for bank 1 Group1 */ + FLASH->WRP11R_PRG &= (~(WRPSector_Group1 & FLASH_WRPR_WRPSG)); + } + if (WRPSector_Group2 != 0) + { + /* Enable Write Protection for bank 1 Group2 */ + FLASH->WRP12R_PRG &= (~(WRPSector_Group2 & FLASH_WRPR_WRPSG)); + } + } + if ((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + if (WRPSector_Group1 != 0) + { + /* Enable Write Protection for bank 2 Group1 */ + FLASH->WRP21R_PRG &= (~(WRPSector_Group1 & FLASH_WRPR_WRPSG)); + } + if (WRPSector_Group2 != 0) + { + /* Enable Write Protection for bank 2 Group2 */ + FLASH->WRP22R_PRG &= (~(WRPSector_Group2 & FLASH_WRPR_WRPSG)); + } + } +#else + if ((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Enable Write Protection for bank 1 */ + FLASH->WRP1R_PRG &= (~((uint32_t)(WRPSector & FLASH_WRPR_WRPSG))); + } + + if ((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Enable Write Protection for bank 2 */ + FLASH->WRP2R_PRG &= (~((uint32_t)(WRPSector & FLASH_WRPR_WRPSG))); + } +#endif /* OB_WRP_SECTOR_128TO131 */ +} + +/** + * @brief Disable the write protection of the desired bank1 or bank 2 sectors + * @param WRPSector specifies the sectors to disable write protection. + * This parameter can be a value of @ref FLASH_OB_Write_Protection_Sectors + * + * @param Banks the specific bank to apply WRP sectors + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: disable WRP on specified bank1 sectors + * @arg FLASH_BANK_2: disable WRP on specified bank2 sectors + * @arg FLASH_BANK_BOTH: disable WRP on both bank1 and bank2 specified sectors + * + * @retval None + */ +static void FLASH_OB_DisableWRP(uint64_t WRPSector, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); +#if defined(OB_WRP_SECTOR_128TO131) + uint32_t WRPSector_Group1 = (uint32_t)(WRPSector & 0xFFFFFFFF); + uint32_t WRPSector_Group2 = (uint32_t)((WRPSector >> 32) & 0xFFFFFFFF); + if ((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + if (WRPSector_Group1 != 0) + { + /* Disable Write Protection for bank 1 group1 */ + FLASH->WRP11R_PRG |= (WRPSector_Group1 & FLASH_WRPR_WRPSG); + } + if (WRPSector_Group2 != 0) + { + /* Disable Write Protection for bank 1 group2 */ + FLASH->WRP12R_PRG |= (WRPSector_Group2 & FLASH_WRPR_WRPSG); + } + } + + if ((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + if (WRPSector_Group1 != 0) + { + /* Disable Write Protection for bank 2 group1 */ + FLASH->WRP21R_PRG |= (WRPSector_Group1 & FLASH_WRPR_WRPSG); + } + if (WRPSector_Group2 != 0) + { + /* Disable Write Protection for bank 2 group2 */ + FLASH->WRP22R_PRG |= (WRPSector_Group2 & FLASH_WRPR_WRPSG); + } + } +#else + if ((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Disable Write Protection for bank 1 */ + FLASH->WRP1R_PRG |= (uint32_t)(WRPSector & FLASH_WRPR_WRPSG); + } + + if ((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Disable Write Protection for bank 2 */ + FLASH->WRP2R_PRG |= (uint32_t)(WRPSector & FLASH_WRPR_WRPSG); + } +#endif /* OB_WRP_SECTOR_128TO131 */ +} + +/** + * @brief Get the write protection of the given bank 1 or bank 2 sectors + * @param[in] Bank specifies the bank where to get the write protection sectors. + * This parameter can be exclusively one of the following values: + * @arg FLASH_BANK_1: Get bank1 WRP sectors + * @arg FLASH_BANK_2: Get bank2 WRP sectors + * + * @param[out] WRPState returns the write protection state of the returned sectors. + * This parameter can be one of the following values: + * @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE + + * @param[out] WRPSector returns the write protected sectors on the given bank . + * This parameter can be a value of @ref FLASH_OB_Write_Protection_Sectors + * + * @retval None + */ +static void FLASH_OB_GetWRP(uint32_t Bank, uint32_t *WRPState, uint64_t *WRPSector) +{ + uint32_t regvalue1 = 0U; + +#if defined(OB_WRP_SECTOR_128TO131) + uint32_t regvalue2 = 0U; + + if (Bank == FLASH_BANK_1) + { + regvalue1 = FLASH->WRP11R_CUR; + regvalue2 = FLASH->WRP12R_CUR; + } + + if (Bank == FLASH_BANK_2) + { + regvalue1 = FLASH->WRP21R_CUR; + regvalue2 = FLASH->WRP22R_CUR; + } + + uint64_t wrp_sector_group1 = (~regvalue1) & FLASH_WRPR_WRPSG; + uint64_t wrp_sector_group2 = (~regvalue2) & FLASH_WRPR_WRPSG; + + *WRPSector = (wrp_sector_group2 << 32) | wrp_sector_group1; + + if (*WRPSector == 0U) + { + *WRPState = OB_WRPSTATE_DISABLE; + } + else + { + *WRPState = OB_WRPSTATE_ENABLE; + } +#else + if (Bank == FLASH_BANK_1) + { + regvalue1 = FLASH->WRP1R_CUR; + } + + if (Bank == FLASH_BANK_2) + { + regvalue1 = FLASH->WRP2R_CUR; + } + + *WRPSector = ((uint64_t)(~regvalue1) & (uint64_t)FLASH_WRPR_WRPSG); + + if (*WRPSector == 0U) + { + *WRPState = OB_WRPSTATE_DISABLE; + } + else + { + *WRPState = OB_WRPSTATE_ENABLE; + } +#endif /* OB_WRP_SECTOR_128TO131 */ +} + +/** + * @brief Set the product state. + * + * @note To configure the product state, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @note To validate the product state, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * + * @param ProductState specifies the product state. + * This parameter can be a value of @ref FLASH_OB_Product_State + * + * @retval None + */ +static void FLASH_OB_ProdStateConfig(uint32_t ProductState) +{ + /* Check the parameters */ + assert_param(IS_OB_PRODUCT_STATE(ProductState)); + + /* Configure the Product State in the option bytes register */ + MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_PRODUCT_STATE, ProductState); +} + +/** + * @brief Get the the product state. + * @retval ProductState returns the product state. + * This returned value can a value of @ref FLASH_OB_Product_State + */ +static uint32_t FLASH_OB_GetProdState(void) +{ + return (FLASH->OPTSR_CUR & FLASH_OPTSR_PRODUCT_STATE); +} + +/** + * @brief Program the FLASH User Option Byte. + * + * @note To configure the user option bytes, the option lock bit OPTLOCK must + * be cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @note To validate the user option bytes, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * + * @param UserType specifies The FLASH User Option Bytes to be modified. + * This parameter can be a combination of @ref FLASH_OB_USER_Type + * + * @param UserConfig1 specifies values of the selected User Option Bytes. + * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, + * @ref FLASH_OB_USER_BORH_EN, @ref FLASH_OB_USER_IWDG_SW, + * @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nRST_STOP, + * @ref FLASH_OB_USER_nRST_STANDBY, @ref FLASH_OB_USER_IO_VDD_HSLV, + * @ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_IWDG_STOP, + * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_BOOT_UBE and @ref OB_USER_SWAP_BANK. + * @param UserConfig2 specifies values of the selected User Option Bytes. + * @ref FLASH_OB_USER_SRAM1_3_RST, @ref FLASH_OB_USER_SRAM2_RST, + * @ref FLASH_OB_USER_BKPRAM_ECC, @ref FLASH_OB_USER_SRAM3_ECC, + * @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM1_ECC, + * @ref FLASH_OB_USER_SRAM1_RST and @ref OB_USER_TZEN. + * @retval None + */ +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig1, uint32_t UserConfig2) +{ + uint32_t optr_reg1_val = 0U; + uint32_t optr_reg1_mask = 0U; + uint32_t optr_reg2_val = 0U; + uint32_t optr_reg2_mask = 0U; + + /* Check the parameters */ + assert_param(IS_OB_USER_TYPE(UserType)); + + if ((UserType & OB_USER_BOR_LEV) != 0U) + { + /* BOR level option byte should be modified */ + assert_param(IS_OB_USER_BOR_LEVEL(UserConfig1 & FLASH_OPTSR_BOR_LEV)); + + /* Set value and mask for BOR level option byte */ + optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_BOR_LEV); + optr_reg1_mask |= FLASH_OPTSR_BOR_LEV; + } + + if ((UserType & OB_USER_BORH_EN) != 0U) + { + /* BOR high enable status bit should be modified */ + assert_param(IS_OB_USER_BORH_EN(UserConfig1 & FLASH_OPTSR_BORH_EN)); + + /* Set value and mask for BOR high enable status bit */ + optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_BORH_EN); + optr_reg1_mask |= FLASH_OPTSR_BORH_EN; + } + + if ((UserType & OB_USER_IWDG_SW) != 0U) + { + /* IWDG_SW option byte should be modified */ + assert_param(IS_OB_USER_IWDG(UserConfig1 & FLASH_OPTSR_IWDG_SW)); + + /* Set value and mask for IWDG_SW option byte */ + optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_IWDG_SW); + optr_reg1_mask |= FLASH_OPTSR_IWDG_SW; + } + + if ((UserType & OB_USER_WWDG_SW) != 0U) + { + /* WWDG_SW option byte should be modified */ + assert_param(IS_OB_USER_WWDG(UserConfig1 & FLASH_OPTSR_WWDG_SW)); + + /* Set value and mask for WWDG_SW option byte */ + optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_WWDG_SW); + optr_reg1_mask |= FLASH_OPTSR_WWDG_SW; + } + + if ((UserType & OB_USER_NRST_STOP) != 0U) + { + /* nRST_STOP option byte should be modified */ + assert_param(IS_OB_USER_STOP(UserConfig1 & FLASH_OPTSR_NRST_STOP)); + + /* Set value and mask for nRST_STOP option byte */ + optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_NRST_STOP); + optr_reg1_mask |= FLASH_OPTSR_NRST_STOP; + } + + if ((UserType & OB_USER_NRST_STDBY) != 0U) + { + /* nRST_STDBY option byte should be modified */ + assert_param(IS_OB_USER_STANDBY(UserConfig1 & FLASH_OPTSR_NRST_STDBY)); + + /* Set value and mask for nRST_STDBY option byte */ + optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_NRST_STDBY); + optr_reg1_mask |= FLASH_OPTSR_NRST_STDBY; + } + + if ((UserType & OB_USER_IO_VDD_HSLV) != 0U) + { + /* IO_VDD_HSLV option byte should be modified */ + assert_param(IS_OB_USER_IO_VDD_HSLV(UserConfig1 & FLASH_OPTSR_IO_VDD_HSLV)); + + /* Set value and mask for IO_VDD_HSLV option byte */ + optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_IO_VDD_HSLV); + optr_reg1_mask |= FLASH_OPTSR_IO_VDD_HSLV; + } + + if ((UserType & OB_USER_IO_VDDIO2_HSLV) != 0U) + { + /* IO_VDD_HSLV option byte should be modified */ + assert_param(IS_OB_USER_IO_VDDIO2_HSLV(UserConfig1 & FLASH_OPTSR_IO_VDDIO2_HSLV)); + + /* Set value and mask for IO_VDD_HSLV option byte */ + optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_IO_VDDIO2_HSLV); + optr_reg1_mask |= FLASH_OPTSR_IO_VDDIO2_HSLV; + } + + if ((UserType & OB_USER_IWDG_STOP) != 0U) + { + /* IWDG_STOP option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STOP(UserConfig1 & FLASH_OPTSR_IWDG_STOP)); + + /* Set value and mask for IWDG_STOP option byte */ + optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_IWDG_STOP); + optr_reg1_mask |= FLASH_OPTSR_IWDG_STOP; + } + + if ((UserType & OB_USER_IWDG_STDBY) != 0U) + { + /* IWDG_STDBY option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STDBY(UserConfig1 & FLASH_OPTSR_IWDG_STDBY)); + + /* Set value and mask for IWDG_STDBY option byte */ + optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_IWDG_STDBY); + optr_reg1_mask |= FLASH_OPTSR_IWDG_STDBY; + } + +#if defined (FLASH_OPTSR_BOOT_UBE) + if ((UserType & OB_USER_BOOT_UBE) != 0U) + { + /* SWAP_BANK option byte should be modified */ + assert_param(IS_OB_USER_BOOT_UBE(UserConfig1 & FLASH_OPTSR_BOOT_UBE)); + + /* Set value and mask for BOOT_UBE option byte */ + optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_BOOT_UBE); + optr_reg1_mask |= FLASH_OPTSR_BOOT_UBE; + } +#endif /* FLASH_OPTSR_BOOT_UBE */ + + if ((UserType & OB_USER_SWAP_BANK) != 0U) + { + /* SWAP_BANK option byte should be modified */ + assert_param(IS_OB_USER_SWAP_BANK(UserConfig1 & FLASH_OPTSR_SWAP_BANK)); + + /* Set value and mask for SWAP_BANK option byte */ + optr_reg1_val |= (UserConfig1 & FLASH_OPTSR_SWAP_BANK); + optr_reg1_mask |= FLASH_OPTSR_SWAP_BANK; + } + +#if defined (FLASH_OPTSR2_SRAM1_3_RST) + if ((UserType & OB_USER_SRAM1_3_RST) != 0U) + { + /* SRAM13_RST option byte should be modified */ + assert_param(IS_OB_USER_SRAM1_3_RST(UserConfig2 & FLASH_OPTSR2_SRAM1_3_RST)); + + /* Set value and mask for SRAM13_RST option byte */ + optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_SRAM1_3_RST); + optr_reg2_mask |= FLASH_OPTSR2_SRAM1_3_RST; + } +#elif defined (FLASH_OPTSR2_SRAM1_3_4_5_RST) + if ((UserType & OB_USER_SRAM1_3_4_5_RST) != 0U) + { + /* SRAM13_RST option byte should be modified */ + assert_param(IS_OB_USER_SRAM1_3_4_5_RST(UserConfig2 & FLASH_OPTSR2_SRAM1_3_4_5_RST)); + + /* Set value and mask for SRAM13_RST option byte */ + optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_SRAM1_3_4_5_RST); + optr_reg2_mask |= FLASH_OPTSR2_SRAM1_3_4_5_RST; + } +#endif /* FLASH_OPTSR2_SRAM1_3_RST */ + +#if defined (FLASH_OPTSR2_SRAM1_RST) + if ((UserType & OB_USER_SRAM1_RST) != 0U) + { + /* SRAM1_RST option byte should be modified */ + assert_param(IS_OB_USER_SRAM1_RST(UserConfig2 & FLASH_OPTSR2_SRAM1_RST)); + + /* Set value and mask for SRAM1_RST option byte */ + optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_SRAM1_RST); + optr_reg2_mask |= FLASH_OPTSR2_SRAM1_RST; + } +#endif /* FLASH_OPTSR2_SRAM1_RST */ + + if ((UserType & OB_USER_SRAM2_RST) != 0U) + { + /* SRAM2_RST option byte should be modified */ + assert_param(IS_OB_USER_SRAM2_RST(UserConfig2 & FLASH_OPTSR2_SRAM2_RST)); + + /* Set value and mask for SRAM2_RST option byte */ + optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_SRAM2_RST); + optr_reg2_mask |= FLASH_OPTSR2_SRAM2_RST; + } + + if ((UserType & OB_USER_BKPRAM_ECC) != 0U) + { + /* BKPRAM_ECC option byte should be modified */ + assert_param(IS_OB_USER_BKPRAM_ECC(UserConfig2 & FLASH_OPTSR2_BKPRAM_ECC)); + + /* Set value and mask for BKPRAM_ECC option byte */ + optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_BKPRAM_ECC); + optr_reg2_mask |= FLASH_OPTSR2_BKPRAM_ECC; + } + +#if defined (FLASH_OPTSR2_SRAM3_ECC) + if ((UserType & OB_USER_SRAM3_ECC) != 0U) + { + /* SRAM3_ECC option byte should be modified */ + assert_param(IS_OB_USER_SRAM3_ECC(UserConfig2 & FLASH_OPTSR2_SRAM3_ECC)); + + /* Set value and mask for SRAM3_ECC option byte */ + optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_SRAM3_ECC); + optr_reg2_mask |= FLASH_OPTSR2_SRAM3_ECC; + } +#endif /* FLASH_OPTSR2_SRAM3_ECC */ + + if ((UserType & OB_USER_SRAM2_ECC) != 0U) + { + /* SRAM2_ECC option byte should be modified */ + assert_param(IS_OB_USER_SRAM2_ECC(UserConfig2 & FLASH_OPTSR2_SRAM2_ECC)); + + /* Set value and mask for SRAM2_ECC option byte */ + optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_SRAM2_ECC); + optr_reg2_mask |= FLASH_OPTSR2_SRAM2_ECC; + } + +#if defined (FLASH_OPTSR2_SRAM1_ECC) + if ((UserType & OB_USER_SRAM1_ECC) != 0U) + { + /* SRAM2_ECC option byte should be modified */ + assert_param(IS_OB_USER_SRAM1_ECC(UserConfig2 & FLASH_OPTSR2_SRAM1_ECC)); + + /* Set value and mask for SRAM2_ECC option byte */ + optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_SRAM1_ECC); + optr_reg2_mask |= FLASH_OPTSR2_SRAM1_ECC; + } +#endif /* FLASH_OPTSR2_SRAM1_ECC */ + +#if defined (FLASH_OPTSR2_USBPD_DIS) + if ((UserType & OB_USER_USBPD_DIS) != 0U) + { + /* USBPD_DIS option byte should be modified */ + assert_param(IS_OB_USER_USBPD_DIS(UserConfig2 & FLASH_OPTSR2_USBPD_DIS)); + + /* Set value and mask for USBPD_DIS option byte */ + optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_USBPD_DIS); + optr_reg2_mask |= FLASH_OPTSR2_USBPD_DIS; + } +#endif /* FLASH_OPTSR2_USBPD_DIS */ + +#if defined (FLASH_OPTSR2_TZEN) + if ((UserType & OB_USER_TZEN) != 0U) + { + /* TZEN option byte should be modified */ + assert_param(IS_OB_USER_TZEN(UserConfig2 & FLASH_OPTSR2_TZEN)); + + /* Set value and mask for TZEN option byte */ + optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_TZEN); + optr_reg2_mask |= FLASH_OPTSR2_TZEN; + } +#endif /* FLASH_OPTSR2_TZEN */ +#if defined(FLASH_OPTSR2_HUK_PUF) + if ((UserType & OB_USER_HUK_PUF) != 0U) + { + /* TZEN option byte should be modified */ + assert_param(IS_OB_USER_HUK_PUF(UserConfig2 & FLASH_OPTSR2_HUK_PUF)); + + /* Set value and mask for TZEN option byte */ + optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_HUK_PUF); + optr_reg2_mask |= FLASH_OPTSR2_HUK_PUF; + } +#endif /* FLASH_OPTSR2_HUK_PUF */ + + /* Check to write first User OB register or/and second one */ + if ((UserType & 0xFFFU) != 0U) + { + /* Configure the option bytes register */ + MODIFY_REG(FLASH->OPTSR_PRG, optr_reg1_mask, optr_reg1_val); + } + if ((UserType & 0x1FF000U) != 0U) + { + /* Configure the option bytes register */ + MODIFY_REG(FLASH->OPTSR2_PRG, optr_reg2_mask, optr_reg2_val); + } +} + +/** + * @brief Return the FLASH User Option Byte values. + * @param UserConfig1 FLASH User Option Bytes values + * 2M: IWDG_SW(Bit3), WWDG_SW(Bit4), nRST_STOP(Bit 6), nRST_STDY(Bit 7), + * PRODUCT_STATE(Bit[8:15]), IO_VDD_HSLV(Bit 16), IO_VDDTO2_HSLV(Bit 17), + * IWDG_STOP(Bit 20), IWDG_STDBY (Bit 21), BOOT_UBE(Bit[22:29]) and SWAP_BANK(Bit 31). + * 128K: IWDG_SW(Bit3), WWDG_SW(Bit4), nRST_STOP(Bit 6), nRST_STDY(Bit 7), + * PRODUCT_STATE(Bit[8:15]), IO_VDD_HSLV(Bit16), IO_VDDIO2_HSLV(Bit17), IWDG_STOP(Bit 20), + * IWDG_STDBY (Bit 21) and SWAP_BANK(Bit 31). + * @param UserConfig2 FLASH User Option Bytes values + * 2M: SRAM1_3_RST(Bit2), SRAM2_RST(Bit 3), BKPRAM_ECC(Bit 4), SRAM3_ECC(Bit 5), + * SRAM2_ECC(Bit 6). + * 128K: SRAM2_RST(Bit 3), BKPRAM_ECC(Bit 4), SRAM2_ECC(Bit 6), + * SRAM1_RST(Bit9), SRAM1_ECC(Bit10). + * @retval None + */ +static void FLASH_OB_GetUser(uint32_t *UserConfig1, uint32_t *UserConfig2) +{ + (*UserConfig1) = FLASH->OPTSR_CUR & (~FLASH_OPTSR_PRODUCT_STATE); + + (*UserConfig2) = FLASH->OPTSR2_CUR; +} + +/** + * @brief Configure Boot address + * @param BootOption specifies the Boot address option byte to be programmed. + * This parameter can be one of the following values: + * @arg OB_BOOTADDR_NS: Non-secure boot address + * @arg OB_BOOTADDR_SEC: Secure boot address + * @param BootAddress: specifies the boot address value + * This parameter can be sector number between 0 and 0xFFFFFF00 + * @retval None + */ +static void FLASH_OB_BootAddrConfig(uint32_t BootOption, uint32_t BootAddress) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOT_CONFIG(BootOption)); + + if (BootOption == OB_BOOT_NS) + { + MODIFY_REG(FLASH->NSBOOTR_PRG, FLASH_BOOTR_BOOTADD, BootAddress); + } +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else if (BootOption == OB_BOOT_SEC) + { + MODIFY_REG(FLASH->SECBOOTR_PRG, FLASH_BOOTR_BOOTADD, BootAddress); + } +#endif /* __ARM_FEATURE_CMSE */ + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } +} + +/** + * @brief Configure the boot lock. + * + * @param BootOption select the BOOT_LOCK option: secure or non-secure. + * This parameter can be one of the following values: + * @arg OB_BOOT_LOCK_SEC: Boot Lock mode deactivated + * @arg OB_BOOT_LOCK_NS: Boot Lock mode activated + * + * @param BootLockConfig specifies the activation of the BOOT_LOCK. + * This parameter can be one of the following values: + * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated + * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated + * + * @retval None + */ +static void FLASH_OB_BootLockConfig(uint32_t BootOption, uint32_t BootLockConfig) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOT_CONFIG(BootOption)); + assert_param(IS_OB_BOOT_LOCK(BootLockConfig)); + + /* Configure the option bytes register */ + if (BootOption == OB_BOOT_NS) + { + MODIFY_REG(FLASH->NSBOOTR_PRG, FLASH_BOOTR_BOOT_LOCK, BootLockConfig); + } +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else if (BootOption == OB_BOOT_SEC) + { + MODIFY_REG(FLASH->SECBOOTR_PRG, FLASH_BOOTR_BOOT_LOCK, BootLockConfig); + } +#endif /* __ARM_FEATURE_CMSE */ + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } +} + +/** + * @brief Get the boot configuration + * @param[in] BootOption specifies the boot address option byte to be returned. + * This parameter can be one of the following values: + * @arg OB_BOOT_NS: Non-secure boot address + * @arg OB_BOOT_SEC: Secure boot address + * + * @param[out] BootAddress specifies the boot address value + * + * @param[out] BootLockConfig returns the activation of the BOOT_LOCK. + * This parameter can be one of the following values: + * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated + * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated + * @retval None + */ +static void FLASH_OB_GetBootConfig(uint32_t BootOption, uint32_t *BootAddress, uint32_t *BootLockConfig) +{ + if (BootOption == OB_BOOT_NS) + { + *BootAddress = FLASH->NSBOOTR_CUR & FLASH_BOOTR_BOOTADD; + *BootLockConfig = FLASH->NSBOOTR_CUR & FLASH_BOOTR_BOOT_LOCK; + } +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else if (BootOption == OB_BOOT_SEC) + { + *BootAddress = (FLASH->SECBOOTR_CUR & FLASH_BOOTR_BOOTADD); + *BootLockConfig = (FLASH->SECBOOTR_CUR & FLASH_BOOTR_BOOT_LOCK); + } +#endif /* __ARM_FEATURE_CMSE */ + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } +} + +/** + * @brief Configure the OTP Block Lock. + * @param OTP_Block specifies the OTP Block to lock. + * This parameter can be a value of @ref FLASH_OTP_Blocks + * @retval None + */ +static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block) +{ + /* Configure the OTP Block lock in the option bytes register */ + FLASH->OTPBLR_PRG |= OTP_Block; +} + +/** + * @brief Get the OTP Block Lock. + * @retval OTP_Block specifies the OTP Block to lock. + * This return value can be a value of @ref FLASH_OTP_Blocks + */ +static uint32_t FLASH_OB_OTP_GetLock(void) +{ + return (FLASH->OTPBLR_CUR); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure the watermark-based secure area. + * + * @param Banks specifies the bank where to apply Watermark protection + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: configure Watermark on bank1 + * @arg FLASH_BANK_2: configure Watermark on bank2 + * @arg FLASH_BANK_BOTH: configure Watermark on both bank1 and bank2 + * + * @param WMSecStartSector specifies the start sector of the secure area + * This parameter can be sector number between 0 and (max number of sectors in the bank - 1) + * + * @param WMSecEndSector specifies the end sector of the secure area + * This parameter can be sector number between WMSecStartSector and WMSecEndSector(max number of sectors + * in the bank - 1) + * + * @retval None + */ +static void FLASH_OB_WMSECConfig(uint32_t Banks, uint32_t WMSecStartSector, uint32_t WMSecEndSector) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + assert_param(IS_FLASH_SECTOR(WMSecStartSector)); + assert_param(IS_FLASH_SECTOR(WMSecEndSector)); + + /* Write SECWM registers */ + if ((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Configure Watermark Protection for bank 1 */ + FLASH->SECWM1R_PRG = ((WMSecEndSector << FLASH_SECWMR_SECWM_END_Pos) | WMSecStartSector); + } + + if ((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Configure Watermark Protection for bank 2 */ + FLASH->SECWM2R_PRG = ((WMSecEndSector << FLASH_SECWMR_SECWM_END_Pos) | WMSecStartSector); + } +} + +/** + * @brief Return the watermark-based secure area configuration. + * + * @param Bank [in] specifies the bank where to get the watermark protection. + * This parameter can be exclusively one of the following values: + * @arg FLASH_BANK_1: Get bank1 watermark configuration + * @arg FLASH_BANK_2: Get bank2 watermark configuration + * + * @param WMSecStartSector [out] specifies the start sector of the secure area + * + * @param WMSecEndSector [out] specifies the end sector of the secure area + * + * @retval None + */ +static void FLASH_OB_GetWMSEC(uint32_t Bank, uint32_t *WMSecStartSector, uint32_t *WMSecEndSector) +{ + uint32_t regvalue = 0U; + + /* Read SECWM register */ + if (Bank == FLASH_BANK_1) + { + regvalue = FLASH->SECWM1R_CUR; + } + + if (Bank == FLASH_BANK_2) + { + regvalue = FLASH->SECWM2R_CUR; + } + + /* Get configuration of secure area */ + *WMSecStartSector = (regvalue & FLASH_SECWMR_SECWM_STRT); + *WMSecEndSector = ((regvalue & FLASH_SECWMR_SECWM_END) >> FLASH_SECWMR_SECWM_END_Pos); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure the hide protection area. + * + * @param Banks specifies the bank where to apply hide protection + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: configure HDP on bank1 + * @arg FLASH_BANK_2: configure HDP on bank2 + * @arg FLASH_BANK_BOTH: configure HDP on both bank1 and bank2 + * + * @param HDPStartSector specifies the start sector of the hide protection area + * This parameter can be sector number between 0 and (max number of sectors in the bank - 1) + * + * @param HDPEndSector specifies the end sector of the hide protection area + * This parameter can be sector number between HDPStartSector and HDPEndSector (max number of sectors + * in the bank - 1) + * + * @retval None + */ +static void FLASH_OB_HDPConfig(uint32_t Banks, uint32_t HDPStartSector, uint32_t HDPEndSector) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + assert_param(IS_FLASH_SECTOR(HDPStartSector)); + assert_param(IS_FLASH_SECTOR(HDPEndSector)); + + /* Write HDP registers */ + if ((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Configure hide Protection for bank 1 */ + FLASH->HDP1R_PRG = ((HDPEndSector << FLASH_HDPR_HDP_END_Pos) | HDPStartSector); + } + + if ((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Configure hide Protection for bank 2 */ + FLASH->HDP2R_PRG = ((HDPEndSector << FLASH_HDPR_HDP_END_Pos) | HDPStartSector); + } +} + +/** + * @brief Return the hide protection area configuration. + * + * @param Bank [in] specifies the bank where to get the HDP protection. + * This parameter can be exclusively one of the following values: + * @arg FLASH_BANK_1: Get bank1 HDP configuration + * @arg FLASH_BANK_2: Get bank2 HDP configuration + * + * @param HDPStartSector [out] specifies the start sector of the HDP area + * + * @param HDPEndSector [out] specifies the end sector of the HDP area + * + * @retval None + */ +static void FLASH_OB_GetHDP(uint32_t Bank, uint32_t *HDPStartSector, uint32_t *HDPEndSector) +{ + uint32_t regvalue = 0U; + + /* Read SECWM register */ + if (Bank == FLASH_BANK_1) + { + regvalue = FLASH->HDP1R_CUR; + } + + if (Bank == FLASH_BANK_2) + { + regvalue = FLASH->HDP2R_CUR; + } + + /* Get configuration of HDP area */ + *HDPStartSector = (regvalue & FLASH_HDPR_HDP_STRT); + *HDPEndSector = ((regvalue & FLASH_HDPR_HDP_END) >> FLASH_HDPR_HDP_END_Pos); +} + +#if defined(FLASH_EDATAR_EDATA_EN) +/** + * @brief Configure the Flash high-cycle area. + * + * @param Banks specifies the bank where to apply Flash high-cycle data area + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: configure Flash high-cycle area on bank1 + * @arg FLASH_BANK_2: configure Flash high-cycle area on bank2 + * @arg FLASH_BANK_BOTH: configure Flash high-cycle area on both bank1 and bank2 + * + * @param EDATASize specifies the size (in sectors) of the Flash high-cycle data area + * This parameter can be sectors number between 0 and 8 + * 0: Disable all EDATA sectors. + * 1: The last sector is reserved for flash high-cycle data. + * 2: The two last sectors are reserved for flash high-cycle data. + * 3: The three last sectors are reserved for flash high-cycle data + * 4: The four last sectors is reserved for flash high-cycle data. + * 5: The five last sectors are reserved for flash high-cycle data. + * 6: The six last sectors are reserved for flash high-cycle data. + * 7: The seven last sectors are reserved for flash high-cycle data. + * 8: The eight last sectors are reserved for flash high-cycle data. + * + * @retval None + */ +static void FLASH_OB_EDATAConfig(uint32_t Banks, uint32_t EDATASize) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + assert_param(IS_FLASH_EDATA_SIZE(EDATASize)); + + if (EDATASize != 0U) + { + /* Write EDATA registers */ + if ((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Configure Flash high-cycle data for bank 1 */ + FLASH->EDATA1R_PRG = (FLASH_EDATAR_EDATA_EN | (EDATASize - 1U)); + } + + if ((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Configure Flash high-cycle data for bank 2 */ + FLASH->EDATA2R_PRG = (FLASH_EDATAR_EDATA_EN | (EDATASize - 1U)); + } + } + else + { + /* Write EDATA registers */ + if ((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Disable Flash high-cycle data for bank 1 */ + FLASH->EDATA1R_PRG = 0U; + } + + if ((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Disable Flash high-cycle data for bank 2 */ + FLASH->EDATA2R_PRG = 0U; + } + } +} + +/** + * @brief Return the Flash high-cycle data area configuration. + * + * @param Bank [in] specifies the bank where to get the Flash high-cycle data configuration. + * This parameter can be exclusively one of the following values: + * @arg FLASH_BANK_1: Get bank1 Flash high-cycle data configuration + * @arg FLASH_BANK_2: Get bank2 Flash high-cycle data configuration + * + * @param EDATASize [out] specifies the size (in sectors) of the Flash high-cycle data area + * + * @retval None + */ +static void FLASH_OB_GetEDATA(uint32_t Bank, uint32_t *EDATASize) +{ + uint32_t regvalue = 0U; + + /* Read SECWM register */ + if (Bank == FLASH_BANK_1) + { + regvalue = FLASH->EDATA1R_CUR; + } + + if (Bank == FLASH_BANK_2) + { + regvalue = FLASH->EDATA2R_CUR; + } + + /* Get configuration of secure area */ + if ((regvalue & FLASH_EDATAR_EDATA_EN) != 0U) + { + /* Encoding of Edata Area size is register value + 1 */ + *EDATASize = (regvalue & FLASH_EDATAR_EDATA_STRT) + 1U; + } + else + { + /* No defined Edata area */ + *EDATASize = 0U; + } + +} +#endif /* FLASH_EDATAR_EDATA_EN */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group3 Extended ECC operation functions + * @brief Extended ECC operation functions + * +@verbatim + =============================================================================== + ##### Extended ECC operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + ECC Operations. + +@endverbatim + * @{ + */ +/** + * @brief Enable ECC correction interrupt + * @retval None + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt(void) +{ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ECCC); +} + +/** + * @brief Disable ECC correction interrupt + * @retval None + */ +void HAL_FLASHEx_DisableEccCorrectionInterrupt(void) +{ + __HAL_FLASH_DISABLE_IT(FLASH_IT_ECCC); +} + +/** + * @brief Get the ECC error information. + * @param pData Pointer to an FLASH_EccInfoTypeDef structure that contains the + * ECC error information. + * @note This function should be called before ECC bit is cleared + * (in callback function) + * @retval None + */ +void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData) +{ + uint32_t correction_reg = FLASH->ECCCORR; + uint32_t detection_reg = FLASH->ECCDETR; + uint32_t data_reg = FLASH->ECCDR; + uint32_t addr_reg = 0xFFFFFFFFU; + + /* Check if the operation is a correction or a detection*/ + if ((correction_reg & FLASH_ECCR_ECCC) != 0U) + { + /* Get area and offset address values from ECCCORR register*/ + pData->Area = correction_reg & (~(FLASH_ECCR_ECCIE | FLASH_ECCR_ADDR_ECC | FLASH_ECCR_ECCC)); + addr_reg = (correction_reg & FLASH_ECCR_ADDR_ECC); + } + else if ((detection_reg & FLASH_ECCR_ECCD) != 0U) + { + /* Get area and offset address values from ECCDETR register */ + pData->Area = detection_reg & (~(FLASH_ECCR_ADDR_ECC | FLASH_ECCR_ECCD)); + addr_reg = (detection_reg & FLASH_ECCR_ADDR_ECC); + } + else + { + /* Do nothing */ + } + + /* Check that an ECC single or double error has occurred to continue the calculation of area address */ + if (addr_reg != 0xFFFFFFFFU) + { + /* Get address value according to area value*/ + switch (pData->Area) + { + case FLASH_ECC_AREA_USER_BANK1: + /* + * One error detection/correction or two error detections per 128-bit flash word + * Therefore, the address returned by ECC registers in bank1 represents 128-bit flash word, + * to get the correct address value, we must do a shift by 4 bits + */ + addr_reg = ((uint32_t)addr_reg << 4U) & 0xFFFFFFFFU; + pData->Address = (FLASH_BASE + addr_reg) & 0xFFFFFFFFU; + break; + case FLASH_ECC_AREA_USER_BANK2: + /* + * One error detection/correction or two error detections per 128-bit flash word + * Therefore, the address returned by ECC registers in bank2 represents 128-bit flash word, + * to get the correct address value, we must do a shift by 4 bits + */ + addr_reg = ((uint32_t)addr_reg << 4U) & 0xFFFFFFFFU; + pData->Address = (FLASH_BASE + FLASH_BANK_SIZE + addr_reg) & 0xFFFFFFFFU; + break; + case FLASH_ECC_AREA_SYSTEM: + /* check system flash bank */ + if ((correction_reg & FLASH_ECCR_BK_ECC) == FLASH_ECCR_BK_ECC) + { + pData->Address = (FLASH_SYSTEM_BASE + FLASH_SYSTEM_SIZE + addr_reg) & 0xFFFFFFFFU; + } + else + { + pData->Address = (FLASH_SYSTEM_BASE + addr_reg) & 0xFFFFFFFFU; + } + break; +#if defined (FLASH_SR_OBKERR) + case FLASH_ECC_AREA_OBK: + pData->Address = (FLASH_OBK_BASE + addr_reg) & 0xFFFFFFFFU; + break; +#endif /* FLASH_SR_OBKERR */ +#if defined (FLASH_EDATAR_EDATA_EN) + case FLASH_ECC_AREA_EDATA_BANK1: + /* check flash high-cycle data bank */ + /* + * addr_reg is the address returned by the ECC register along with an offset value depends on area + * To calculate the exact address set by user while an ECC occurred, we must subtract the offset value, + * In addition, the address returned by ECC registers represents 128-bit flash word (multiply by 4), + */ + pData->Address = (FLASH_EDATA_BASE + ((addr_reg - FLASH_ADDRESS_OFFSET_EDATA) * 4U)) & 0xFFFFFFFFU; + break; + case FLASH_ECC_AREA_EDATA_BANK2: + /* check flash high-cycle data bank */ + /* + * addr_reg is the address returned by the ECC register along with an offset value depends on area + * To calculate the exact address set by user while an ECC occurred, we must subtract the offset value, + * In addition, the address returned by ECC registers represents 128-bit flash word (multiply by 4), + */ + pData->Address = (FLASH_EDATA_BASE + FLASH_EDATA_BANK_SIZE + \ + ((addr_reg - FLASH_ADDRESS_OFFSET_EDATA) * 4U)) & 0xFFFFFFFFU; + break; +#endif /* FLASH_EDATAR_EDATA_EN */ + case FLASH_ECC_AREA_OTP: + /* Address returned by the ECC is an halfword, multiply by 4 to get the exact address*/ + pData->Address = (FLASH_OTP_BASE + ((addr_reg - FLASH_ADDRESS_OFFSET_OTP) * 4U)) & 0xFFFFFFFFU; + break; + + default: + /* Do nothing */ + break; + } + } + + pData->Data = data_reg & FLASH_ECCR_ADDR_ECC; +} + +/** + * @brief Handle Flash ECC Detection interrupt request. + * @retval None + */ +void HAL_FLASHEx_ECCD_IRQHandler(void) +{ + /* Check if the ECC double error occurred*/ + if (READ_BIT(FLASH->ECCDETR, FLASH_ECCR_ECCD) != 0U) + { + /* FLASH ECC detection user callback */ + HAL_FLASHEx_EccDetectionCallback(); + + /* Clear ECCD flag + note : this step will clear all the information related to the flash ecc detection + */ + SET_BIT(FLASH->ECCDETR, FLASH_ECCR_ECCD); + } +} + +/** + * @brief FLASH ECC Correction interrupt callback. + * @retval None + */ +__weak void HAL_FLASHEx_EccCorrectionCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASHEx_EccCorrectionCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH ECC Detection interrupt callback. + * @retval None + */ +__weak void HAL_FLASHEx_EccDetectionCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASHEx_EccDetectionCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c new file mode 100644 index 00000000..9fdffd7d --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c @@ -0,0 +1,754 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 39 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To set the level of several pins and reset level of several other pins in + same cycle, use HAL_GPIO_WriteMultipleStatePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup GPIO_Private_Defines GPIO Private Defines + * @{ + */ +#define GPIO_MODE (0x00000003U) +#define EXTI_MODE (0x10000000U) +#define GPIO_MODE_IT (0x00010000U) +#define GPIO_MODE_EVT (0x00020000U) +#define RISING_EDGE (0x00100000U) +#define FALLING_EDGE (0x00200000U) +#define GPIO_OUTPUT_TYPE (0x00000010U) +#define GPIO_NUMBER (16U) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified parameters in the pGPIO_Init. + * @note If GPIOx peripheral pin is used in EXTI_MODE and the pin is secure in case + * the system implements the security (TZEN=1), it is up to the secure application to + * insure that the corresponding EXTI line is set secure. + * @param GPIOx: where x can be (A..I) for stm32h56xxx and stm32h57xxx family lines and + * (A..D or H) for stm32h503xx family line to select the GPIO peripheral for STM32H5 family + * @param pGPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) +{ + uint32_t tmp; + uint32_t iocurrent; + uint32_t position = 0U; + + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(pGPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(pGPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(pGPIO_Init->Pull)); + + /* Configure the port pins */ + while (((pGPIO_Init->Pin) >> position) != 0U) + { + /* Get current io position */ + iocurrent = (pGPIO_Init->Pin) & (1UL << position); + + if (iocurrent != 0U) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(pGPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + tmp = GPIOx->AFR[position >> 3U]; + tmp &= ~(0x0FUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + GPIOx->AFR[position >> 3U] = tmp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + tmp = GPIOx->MODER; + tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); + tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos)); + GPIOx->MODER = tmp; + + /* In case of Output or Alternate function mode selection */ + if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) || + (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(pGPIO_Init->Speed)); + + /* Configure the IO Speed */ + tmp = GPIOx->OSPEEDR; + tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + tmp |= (pGPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + GPIOx->OSPEEDR = tmp; + + /* Configure the IO Output Type */ + tmp = GPIOx->OTYPER; + tmp &= ~(GPIO_OTYPER_OT0 << position) ; + tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + GPIOx->OTYPER = tmp; + } + + if (((pGPIO_Init->Mode & GPIO_MODE) != GPIO_MODE_ANALOG) || + (((pGPIO_Init->Mode & GPIO_MODE) == GPIO_MODE_ANALOG) && (pGPIO_Init->Pull != GPIO_PULLUP))) + { + /* Check the Pull parameters */ + assert_param(IS_GPIO_PULL(pGPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + tmp = GPIOx->PUPDR; + tmp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); + tmp |= ((pGPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos)); + GPIOx->PUPDR = tmp; + } + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + tmp = EXTI->EXTICR[position >> 2U]; + tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + EXTI->EXTICR[position >> 2U] = tmp; + + /* Clear Rising Falling edge configuration */ + tmp = EXTI->RTSR1; + tmp &= ~((uint32_t)iocurrent); + if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + tmp |= iocurrent; + } + EXTI->RTSR1 = tmp; + + tmp = EXTI->FTSR1; + tmp &= ~((uint32_t)iocurrent); + if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + tmp |= iocurrent; + } + EXTI->FTSR1 = tmp; + + /* Clear EXTI line configuration */ + tmp = EXTI->EMR1; + tmp &= ~((uint32_t)iocurrent); + if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + tmp |= iocurrent; + } + EXTI->EMR1 = tmp; + + tmp = EXTI->IMR1; + tmp &= ~((uint32_t)iocurrent); + if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + tmp |= iocurrent; + } + EXTI->IMR1 = tmp; + } + } + + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..I) for stm32h56xxx and stm32h57xxx family lines and + * (A..D or H) for stm32h503xx family line to select the GPIO peripheral for STM32H5 family + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t tmp; + uint32_t iocurrent; + uint32_t position = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0U) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1UL << position); + + if (iocurrent != 0U) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + tmp = EXTI->EXTICR[position >> 2U]; + tmp &= ((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + if (tmp == (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos))) + { + /* Clear EXTI line configuration */ + EXTI->IMR1 &= ~(iocurrent); + EXTI->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR1 &= ~(iocurrent); + EXTI->FTSR1 &= ~(iocurrent); + + tmp = (0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos); + EXTI->EXTICR[position >> 2U] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0x0FUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position); + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); + } + + position++; + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx: where x can be (A..I) for stm32h56xxx and stm32h57xxx family lines and + * (A..D or H) for stm32h503xx family line to select the GPIO peripheral for STM32H5 family + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0U) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Set or clear the selected data port bit. + * + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx: where x can be (A..I) for stm32h56xxx and stm32h57xxx family lines and + * (A..D or H) for stm32h503xx family line to select the GPIO peripheral for STM32H5 family + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState: specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Set and clear several pins of a dedicated port in same cycle. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. + * @param GPIOx: where x can be (A..I) for stm32h56xxx and stm32h57xxx family lines and + * (A..D or H) for stm32h503xx family line to select the GPIO peripheral for STM32H5 family + * @param PinReset specifies the port bits to be reset + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @param PinSet specifies the port bits to be set + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @note Both PinReset and PinSet combinations shall not get any common bit, else + * assert would be triggered. + * @note At least one of the two parameters used to set or reset shall be different from zero. + * @retval None + */ +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet) +{ + uint32_t tmp; + + /* Check the parameters */ + /* Make sure at least one parameter is different from zero and that there is no common pin */ + assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet)); + assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet)); + + tmp = (((uint32_t)PinReset << 16) | PinSet); + GPIOx->BSRR = tmp; +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral for STM32H5 family + * @param GPIO_Pin: specifies the pin to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Lock GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx: where x can be (A..I) for stm32h56xxx and stm32h57xxx family lines and + * (A..D or H) for stm32h503xx family line to select the GPIO peripheral for STM32H5 family + * @param GPIO_Pin: specifies the port bits to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != GPIO_LCKR_LCKK) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Enable speed optimization for several pin of dedicated port. + * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding + * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must + * be kept at reset value. + * @note It must be used only if the I/O supply voltage is below 2.7 V. + * @param GPIOx: where x can be (A..I) for stm32h56xxx and stm32h57xxx family lines and + * (A..D or H) for stm32h503xx family line to select the GPIO peripheral for STM32H5 family + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Set HSLVR gpio pin */ + SET_BIT(GPIOx->HSLVR, GPIO_Pin); +} + +/** + * @brief Disable speed optimization for several pin of dedicated port. + * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding + * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must + * be kept at reset value. + * @note It must be used only if the I/O supply voltage is below 2.7 V. + * @param GPIOx: where x can be (A..I) for stm32h56xxx and stm32h57xxx family lines and + * (A..D or H) for stm32h503xx family line to select the GPIO peripheral for STM32H5 family + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Clear HSLVR gpio pin */ + CLEAR_BIT(GPIOx->HSLVR, GPIO_Pin); +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U) + { + __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); + } + + if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U) + { + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line rising detection callback. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file + */ +} + +/** + * @brief EXTI line falling detection callback. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions + * @brief GPIO attributes management functions. + * +@verbatim + =============================================================================== + ##### IO attributes functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configure the GPIO pins attributes. + * @note Available attributes are to secure GPIO pin(s), so this function is + * only available in secure + * @param GPIOx: where x can be (A..I) for stm32h56xxx and stm32h57xxx family lines and + * (A..D or H) for stm32h503xx family line to select the GPIO peripheral for STM32H5 family + * @param GPIO_Pin: specifies the pin(s) to configure the secure attribute + * @param PinAttributes: specifies the pin(s) to be set in secure mode, other being set non secured. + * @retval None + */ +void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes) +{ + uint32_t tmp; + uint32_t iocurrent; + uint32_t position = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ATTRIBUTES(PinAttributes)); + + tmp = GPIOx->SECCFGR; + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0U) + { + /* Get current io position */ + iocurrent = GPIO_Pin & (1UL << position); + + if (iocurrent != 0U) + { + /* Configure the IO secure attribute */ + tmp &= ~(GPIO_SECCFGR_SEC0 << position); + tmp |= (PinAttributes << position); + } + position++; + } + + /* Set secure attributes */ + GPIOx->SECCFGR = tmp; +} + +/** + * @brief Get the GPIO pins attributes. + * @note Available attributes are to secure GPIO pin(s), so this function is + * only available in secure + * @param GPIOx: where x can be (A..I) for stm32h56xxx and stm32h57xxx family lines and + * (A..D or H) for stm32h503xx family line to select the GPIO peripheral for STM32H5 family + * @param GPIO_Pin: specifies the single pin to get the secure attribute from + * @param pPinAttributes: pointer to return the pin attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, + uint32_t *pPinAttributes) +{ + uint32_t iocurrent; + uint32_t position = 0U; + + /* Check null pointer */ + if (pPinAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin)); + + /* Get secure attribute of the port pin */ + while ((GPIO_Pin >> position) != 0U) + { + /* Get current io position */ + iocurrent = GPIO_Pin & (1UL << position); + + if (iocurrent != 0U) + { + /* Get the IO secure attribute */ + if ((GPIOx->SECCFGR & (GPIO_SECCFGR_SEC0 << position)) != 0U) + { + *pPinAttributes = GPIO_PIN_SEC; + } + else + { + *pPinAttributes = GPIO_PIN_NSEC; + } + + break; + } + position++; + } + + return HAL_OK; +} + +/** + * @} + */ + +#endif /* __ARM_FEATURE_CMSE */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c new file mode 100644 index 00000000..4ce76ea0 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c @@ -0,0 +1,657 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_icache.c + * @author MCD Application Team + * @brief ICACHE HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Instruction Cache (ICACHE). + * + Initialization and Configuration + * + Invalidate functions + * + Monitoring management + * + Memory address remap management + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### ICACHE main features ##### + ============================================================================== + [..] + The Instruction Cache (ICACHE) is introduced on C-AHB code bus of + Cortex-M33 processor to improve performance when fetching instruction + and data from both internal and external memories. It allows close to + zero wait states performance. + + (+) The ICACHE provides two performance counters (Hit and Miss), + cache invalidate maintenance operation, error management and TrustZone + security support. + + (+) The ICACHE provides additionally the possibility to remap input address + falling into up to four memory regions (used to remap aliased code in + external memories to the internal Code region, for execution) + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The ICACHE HAL driver can be used as follows: + + (#) Optionally configure the Instruction Cache mode with + HAL_ICACHE_ConfigAssociativityMode() if the default configuration + does not suit the application requirements. + + (#) Enable and disable the Instruction Cache with respectively + HAL_ICACHE_Enable() and HAL_ICACHE_Disable(). + Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status. + To ensure a deterministic cache behavior after power on, system reset or after + a call to @ref HAL_ICACHE_Disable(), the application must call + @ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset + or cache disable, an automatic cache invalidation procedure is launched and the + cache is bypassed until the operation completes. + + (#) Initiate the cache maintenance invalidation procedure with either + HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT() + (interrupt mode). When interrupt mode is used, the callback function + HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate + procedure is complete. The function HAL_ICACHE_WaitForInvalidateComplete() + may be called to wait for the end of the invalidate procedure automatically + initiated when disabling the Instruction Cache with HAL_ICACHE_Disable(). + The cache operation is bypassed during the invalidation procedure. + + (#) Use the performance monitoring counters for Hit and Miss with the following + functions: HAL_ICACHE_Monitor_Start(), HAL_ICACHE_Monitor_Stop(), + HAL_ICACHE_Monitor_Reset(), HAL_ICACHE_Monitor_GetHitValue() and + HAL_ICACHE_Monitor_GetMissValue() + + (#) Enable and disable up to four regions to remap input address from external + memories to the internal Code region for execution with + HAL_ICACHE_EnableRemapRegion() and HAL_ICACHE_DisableRemapRegion() + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup ICACHE ICACHE + * @brief HAL ICACHE module driver + * @{ + */ +#if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants + * @{ + */ +#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */ +#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ICACHE_Private_Macros ICACHE Private Macros + * @{ + */ + +#define IS_ICACHE_ASSOCIATIVITY_MODE(__MODE__) (((__MODE__) == ICACHE_1WAY) || \ + ((__MODE__) == ICACHE_2WAYS)) + +#define IS_ICACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == ICACHE_MONITOR_HIT_MISS) || \ + ((__TYPE__) == ICACHE_MONITOR_HIT) || \ + ((__TYPE__) == ICACHE_MONITOR_MISS)) + +#if defined(ICACHE_CRRx_REN) +#define IS_ICACHE_REGION_NUMBER(__NUMBER__) ((__NUMBER__) < 4U) + +#define IS_ICACHE_REGION_SIZE(__SIZE__) (((__SIZE__) == ICACHE_REGIONSIZE_2MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_4MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_8MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_16MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_32MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_64MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_128MB)) + +#define IS_ICACHE_REGION_TRAFFIC_ROUTE(__TRAFFICROUTE__) (((__TRAFFICROUTE__) == ICACHE_MASTER1_PORT) || \ + ((__TRAFFICROUTE__) == ICACHE_MASTER2_PORT)) + +#define IS_ICACHE_REGION_OUTPUT_BURST_TYPE(__OUTPUTBURSTTYPE_) (((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_WRAP) || \ + ((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_INCR)) + +#endif /* ICACHE_CRRx_REN */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions + * @{ + */ + +/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions + * @brief Initialization and control functions + * + @verbatim + ============================================================================== + ##### Initialization and control functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize and control the + Instruction Cache (mode, invalidate procedure, performance counters). + @endverbatim + * @{ + */ + +/** + * @brief Configure the Instruction Cache cache associativity mode selection. + * @param AssociativityMode Associativity mode selection + * This parameter can be one of the following values: + * @arg ICACHE_1WAY 1-way cache (direct mapped cache) + * @arg ICACHE_2WAYS 2-ways set associative cache (default) + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ICACHE_ASSOCIATIVITY_MODE(AssociativityMode)); + + /* Check cache is not enabled */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_ERROR; + } + else + { + MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode); + } + + return status; +} + +/** + * @brief DeInitialize the Instruction Cache. + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_DeInit(void) +{ + /* Reset interrupt enable value */ + WRITE_REG(ICACHE->IER, 0U); + + /* Clear any pending flags */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); + + /* Disable cache then set default associative mode value */ + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); + WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL); + + /* Stop monitor and reset monitor values */ + CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS); + SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); + CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); + +#if defined(ICACHE_CRRx_REN) + /* Reset regions configuration values */ + WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); +#endif /* ICACHE_CRRx_REN */ + + return HAL_OK; +} + +/** + * @brief Enable the Instruction Cache. + * @note This function always returns HAL_OK even if there is any ongoing + * cache operation. The Instruction Cache is bypassed until the + * cache operation completes. + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Enable(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_EN); + + return HAL_OK; +} + +/** + * @brief Disable the Instruction Cache. + * @note This function waits for the cache being disabled but + * not for the end of the automatic cache invalidation procedure. + * @retval HAL status (HAL_OK/HAL_TIMEOUT) + */ +HAL_StatusTypeDef HAL_ICACHE_Disable(void) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Make sure BSYENDF is reset before to disable the instruction cache */ + /* as it automatically starts a cache invalidation procedure */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for instruction cache being disabled */ + while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_TIMEOUT; + break; + } + } + } + + return status; +} + +/** + * @brief Check whether the Instruction Cache is enabled or not. + * @retval Status (0: disabled, 1: enabled) + */ +uint32_t HAL_ICACHE_IsEnabled(void) +{ + return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL); +} + +/** + * @brief Invalidate the Instruction Cache. + * @note This function waits for the end of cache invalidation procedure + * and clears the associated BSYENDF flag. + * @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT) + */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate(void) +{ + HAL_StatusTypeDef status; + + /* Check if no ongoing operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U) + { + /* Launch cache invalidation */ + SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); + } + + status = HAL_ICACHE_WaitForInvalidateComplete(); + + return status; +} + +/** + * @brief Invalidate the Instruction Cache with interrupt. + * @note This function launches cache invalidation and returns. + * User application shall resort to interrupt generation to check + * the end of the cache invalidation with the BSYENDF flag and the + * HAL_ICACHE_InvalidateCompleteCallback() callback. + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check no ongoing operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Make sure BSYENDF is reset before to start cache invalidation */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + /* Enable end of cache invalidation interrupt */ + SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); + + /* Launch cache invalidation */ + SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); + } + + return status; +} + +/** + * @brief Wait for the end of the Instruction Cache invalidate procedure. + * @note This function checks and clears the BSYENDF flag when set. + * @retval HAL status (HAL_OK/HAL_TIMEOUT) + */ +HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Check if ongoing invalidation operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for end of cache invalidation */ + while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) + { + if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) + { + status = HAL_TIMEOUT; + break; + } + } + } + } + + /* Clear BSYENDF */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + return status; +} + + +/** + * @brief Start the Instruction Cache performance monitoring. + * @param MonitorType Monitoring type + * This parameter can be one of the following values: + * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring + * @arg ICACHE_MONITOR_HIT Hit monitoring + * @arg ICACHE_MONITOR_MISS Miss monitoring + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType) +{ + /* Check the parameters */ + assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); + + SET_BIT(ICACHE->CR, MonitorType); + + return HAL_OK; +} + +/** + * @brief Stop the Instruction Cache performance monitoring. + * @note Stopping the monitoring does not reset the values. + * @param MonitorType Monitoring type + * This parameter can be one of the following values: + * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring + * @arg ICACHE_MONITOR_HIT Hit monitoring + * @arg ICACHE_MONITOR_MISS Miss monitoring + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType) +{ + /* Check the parameters */ + assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); + + CLEAR_BIT(ICACHE->CR, MonitorType); + + return HAL_OK; +} + +/** + * @brief Reset the Instruction Cache performance monitoring values. + * @param MonitorType Monitoring type + * This parameter can be one of the following values: + * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring + * @arg ICACHE_MONITOR_HIT Hit monitoring + * @arg ICACHE_MONITOR_MISS Miss monitoring + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType) +{ + /* Check the parameters */ + assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); + + /* Force/Release reset */ + SET_BIT(ICACHE->CR, (MonitorType << 2U)); + CLEAR_BIT(ICACHE->CR, (MonitorType << 2U)); + + return HAL_OK; +} + +/** + * @brief Get the Instruction Cache performance Hit monitoring value. + * @note Upon reaching the 32-bit maximum value, monitor does not wrap. + * @retval Hit monitoring value + */ +uint32_t HAL_ICACHE_Monitor_GetHitValue(void) +{ + return (ICACHE->HMONR); +} + +/** + * @brief Get the Instruction Cache performance Miss monitoring value. + * @note Upon reaching the 32-bit maximum value, monitor does not wrap. + * @retval Miss monitoring value + */ +uint32_t HAL_ICACHE_Monitor_GetMissValue(void) +{ + return (ICACHE->MMONR); +} + +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions + * @brief IRQ and callback functions + * + @verbatim + ============================================================================== + ##### IRQ and callback functions ##### + ============================================================================== + [..] + This section provides functions allowing to handle ICACHE global interrupt + and the associated callback functions. + @endverbatim + * @{ + */ + +/** + * @brief Handle the Instruction Cache interrupt request. + * @note This function should be called under the ICACHE_IRQHandler(). + * @note This function respectively disables the interrupt and clears the + * flag of any pending flag before calling the associated user callback. + * @retval None + */ +void HAL_ICACHE_IRQHandler(void) +{ + /* Get current interrupt flags and interrupt sources value */ + uint32_t itflags = READ_REG(ICACHE->SR); + uint32_t itsources = READ_REG(ICACHE->IER); + + /* Check Instruction cache Error interrupt flag */ + if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U) + { + /* Disable error interrupt */ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); + + /* Clear ERR pending flag */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); + + /* Instruction cache error interrupt user callback */ + HAL_ICACHE_ErrorCallback(); + } + + /* Check Instruction cache BusyEnd interrupt flag */ + if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U) + { + /* Disable end of cache invalidation interrupt */ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); + + /* Clear BSYENDF pending flag */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + /* Instruction cache busyend interrupt user callback */ + HAL_ICACHE_InvalidateCompleteCallback(); + } +} + +/** + * @brief Cache invalidation complete callback. + */ +__weak void HAL_ICACHE_InvalidateCompleteCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_ICACHE_InvalidateCompleteCallback() should be implemented in the user file + */ +} + +/** + * @brief Error callback. + */ +__weak void HAL_ICACHE_ErrorCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_ICACHE_ErrorCallback() should be implemented in the user file + */ +} + +/** + * @} + */ + +#if defined(ICACHE_CRRx_REN) +/** @defgroup ICACHE_Exported_Functions_Group3 Memory remapped regions functions + * @brief Memory remapped regions functions + * + @verbatim + ============================================================================== + ##### Memory remapped regions functions ##### + ============================================================================== + [..] + This section provides functions allowing to manage the remapping of + external memories to internal Code for execution. + @endverbatim + * @{ + */ + +/** + * @brief Configure and enable a region for memory remapping. + * @note The Instruction Cache and the region must be disabled. + * @param Region Region number + This parameter can be a value of @arg @ref ICACHE_Region + * @param pRegionConfig Pointer to structure of ICACHE region configuration parameters + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *p_reg; + uint32_t value; + + /* Check the parameters */ + assert_param(IS_ICACHE_REGION_NUMBER(Region)); + assert_param(IS_ICACHE_REGION_SIZE(pRegionConfig->Size)); + assert_param(IS_ICACHE_REGION_TRAFFIC_ROUTE(pRegionConfig->TrafficRoute)); + assert_param(IS_ICACHE_REGION_OUTPUT_BURST_TYPE(pRegionConfig->OutputBurstType)); + + /* Check cache is not enabled */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Get region control register address */ + p_reg = &(ICACHE->CRR0) + (1U * Region); + + /* Check region is not already enabled */ + if ((*p_reg & ICACHE_CRRx_REN) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */ + /* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */ + /* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */ + /* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */ + /* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */ + /* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */ + /* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */ + value = ((pRegionConfig->BaseAddress & 0x1FFFFFFFU) >> 21U) & \ + (0xFFU & ~(pRegionConfig->Size - 1U)); + value |= ((pRegionConfig->RemapAddress >> 5U) & \ + ((uint32_t)(0x7FFU & ~(pRegionConfig->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos)); + value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \ + pRegionConfig->OutputBurstType; + *p_reg = (value | ICACHE_CRRx_REN); + } + } + + return status; +} + +/** + * @brief Disable the memory remapping for a predefined region. + * @param Region Region number + This parameter can be a value of @arg @ref ICACHE_Region + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *p_reg; + + /* Check the parameters */ + assert_param(IS_ICACHE_REGION_NUMBER(Region)); + + /* Check cache is not enabled */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Get region control register address */ + p_reg = &(ICACHE->CRR0) + (1U * Region); + + *p_reg &= ~ICACHE_CRRx_REN; + } + + return status; +} + + +/** + * @} + */ +#endif /* ICACHE_CRRx_REN */ + +/** + * @} + */ + +#endif /* ICACHE && HAL_ICACHE_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c new file mode 100644 index 00000000..aca2facf --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c @@ -0,0 +1,674 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/De-Initialization Functions. + * + Peripheral Control Functions. + * + PWR Attributes Functions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#if defined (HAL_PWR_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PWR_Private_Defines PWR Private Defines + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVD + trigger */ +#define PVD_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVD + trigger */ +#define PVD_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVD + threshold crossing */ +#define PVD_MODE_EVT (0x08U) /*!< Mask for event yielded by PVD threshold + crossing */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and de-Initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and De-Initialization Functions ##### + =============================================================================== + [..] +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the HAL PWR peripheral registers to their default reset + * values. + * @note This functionality is not available in this product. + * The prototype is kept just to maintain compatibility with other + * products. + * @retval None. + */ +void HAL_PWR_DeInit(void) +{ +} + +/** + * @brief Enable access to the backup domain (RCC Backup domain control + * register RCC_BDCR, RTC registers, TAMP registers, backup registers + * and backup SRAM). + * @note After a system reset, the backup domain is protected against + * possible unwanted write accesses. + * @retval None. + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP); +} + +/** + * @brief Disable access to the backup domain (RCC Backup domain control + * register RCC_BDCR, RTC registers, TAMP registers, backup registers + * and backup SRAM). + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->DBPCR, PWR_DBPCR_DBP); +} +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @brief Low power modes configuration functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] +@endverbatim + * @{ + */ + +/** + * @brief Configure the voltage threshold detected by the Programmed Voltage + * Detector (PVD). + * @param sConfigPVD : Pointer to a PWR_PVDTypeDef structure that contains the + * PVD configuration information (PVDLevel and EventMode). + * @retval None. + */ +HAL_StatusTypeDef HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[3:1] bits according to PVDLevel value */ + MODIFY_REG(PWR->VMCR, PWR_VMCR_PLS, sConfigPVD->PVDLevel); + + /* Disable PVD Event/Interrupt */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the PVD in interrupt mode */ + if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure the PVD in event mode */ + if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the PVD in rising edge */ + if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + /* Configure the PVD in falling edge */ + if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } + + return HAL_OK; +} + +/** + * @brief Enable the programmable voltage detector (PVD). + * @retval None. + */ +void HAL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->VMCR, PWR_VMCR_PVDEN); +} + +/** + * @brief Disable the programmable voltage detector (PVD). + * @retval None. + */ +void HAL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->VMCR, PWR_VMCR_PVDEN); +} + +/** + * @brief Enable the WakeUp PINx functionality. + * @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values, which + * sets the default (rising edge): + * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,PWR_WAKEUP_PIN4, + * PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6, PWR_WAKEUP_PIN7.PWR_WAKEUP_PIN8. + * or one of the following values where the user can explicitly states + * the enabled pin and the chosen polarity: + * @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, + * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, + * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW, + * PWR_WAKEUP_PIN7_HIGH, PWR_WAKEUP_PIN7_LOW, + * PWR_WAKEUP_PIN8_HIGH, PWR_WAKEUP_PIN8_LOW. + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @note The PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW, PWR_WAKEUP_PIN7_HIGH, PWR_WAKEUP_PIN7_LOW, + * PWR_WAKEUP_PIN8_HIGH and PWR_WAKEUP_PIN8_LOW are not available for STM32H503xx devices. + * @retval None. + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* + Enable and Specify the Wake-Up pin polarity and the pull configuration + for the event detection (rising or falling edge). + */ + MODIFY_REG(PWR->WUCR, PWR_EWUP_MASK, WakeUpPinPolarity); +} + +/** + * @brief Disable the WakeUp PINx functionality. + * @param WakeUpPinx : Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,PWR_WAKEUP_PIN4, + * PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6, PWR_WAKEUP_PIN7.PWR_WAKEUP_PIN8. + * or one of the following values where the user can explicitly states + * the enabled pin and the chosen polarity: + * @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, + * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, + * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW, + * PWR_WAKEUP_PIN7_HIGH, PWR_WAKEUP_PIN7_LOW, + * PWR_WAKEUP_PIN8_HIGH, PWR_WAKEUP_PIN8_LOW. + * @note The PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW, PWR_WAKEUP_PIN7_HIGH, PWR_WAKEUP_PIN7_LOW, + * PWR_WAKEUP_PIN8_HIGH and PWR_WAKEUP_PIN8_LOW are not available for STM32H503xx devices. + * @retval None. + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + /* Disable the wake up pin selected */ + CLEAR_BIT(PWR->WUCR, (PWR_WUCR_WUPEN & WakeUpPinx)); +} + +/** + * @brief Enter the CPU in SLEEP mode. + * @note In SLEEP mode, all I/O pins keep the same state as in Run mode. + * @note CPU clock is off and all peripherals including Cortex-M33 core such + * as NVIC and SysTick can run and wake up the CPU when an interrupt + * or an event occurs. + * @param Regulator : Specifies the regulator state in Sleep mode. + * This parameter can be one of the following values : + * @arg @ref PWR_MAINREGULATOR_ON + * @arg @ref PWR_LOWPOWERREGULATOR_ON + * @note This parameter is not available in this product. + * The parameter is kept just to maintain compatibility with other + * products. + * @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE + * instruction. + * This parameter can be one of the following values : + * @arg @ref PWR_SLEEPENTRY_WFI enter SLEEP mode with Wait + * For Interrupt request. + * @arg @ref PWR_SLEEPENTRY_WFE enter SLEEP mode with Wait + * For Event request. + * @note When WFI entry is used, ticks interrupt must be disabled to avoid + * unexpected CPU wake up. + * @retval None. + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + UNUSED(Regulator); + + /* Check the parameter */ + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select SLEEP mode entry */ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Wait For Interrupt Request */ + __WFI(); + } + else + { + /* Wait For Event Request */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enter the whole system to STOP mode. + * @note In STOP mode, the regulator remains in main regulator mode, + * allowing a very fast wakeup time but with much higher consumption + * comparing to other STOP modes. + * @note STOP offers the largest number of active peripherals and wakeup + * sources, a smaller wakeup time but a higher consumption. + * STOP mode achieves the lowest power consumption while retaining + * the content of SRAM and registers. All clocks in the VCORE domain + * are stopped. The PLL, the HSI, the CSI and the HSE crystal oscillators + * are disabled. The LSE or LSI is still running. + * @note The system clock when exiting from Stop mode can be either HSI + * or CSI, depending on software configuration. + * @param Regulator : Specifies the regulator state in Sleep mode. + * This parameter can be one of the following values : + * @arg @ref PWR_MAINREGULATOR_ON + * @arg @ref PWR_LOWPOWERREGULATOR_ON + * @note This parameter is not available in this product. + * The parameter is kept just to maintain compatibility with other + * products. + * @param STOPEntry : Specifies if STOP mode is entered with WFI or WFE + * instruction. + * This parameter can be one of the following values : + * @arg @ref PWR_STOPENTRY_WFI enter STOP mode with Wait + * For Interrupt request. + * @arg @ref PWR_STOPENTRY_WFE enter STOP mode with Wait + * For Event request. + * @retval None. + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + UNUSED(Regulator); + + /* Check the parameter */ + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select STOP mode */ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_LPMS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select STOP mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Wait For Interrupt Request */ + __WFI(); + } + else + { + /* Wait For Event Request */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enter the whole system to STANDBY mode. + * @note The STANDBY mode is used to achieve the lowest power consumption + * with BOR. The internal regulator is switched off so that the VCORE + * domain is powered off. The PLL, the HSI, the CSI and the HSE crystal + * oscillators are also switched off. + * @note After entering STANDBY mode, SRAMs and register contents are lost + * except for registers and backup SRAM in the Backup domain and + * STANDBY circuitry. + * @retval None. + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select STANDBY mode */ + SET_BIT(PWR->PMCR, PWR_PMCR_LPMS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Wait For all memory accesses to complete before continuing */ + __DSB(); + + /* Ensure that the processor pipeline is flushed */ + __ISB(); + + /* Wait For Interrupt Request */ + __WFI(); +} + +/** + * @brief Indicate SLEEP-ON-EXIT feature when returning from handler mode to + * thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run + * only on interruptions handling. + * @retval None. + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex-M33 System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Disable SLEEP-ON-EXIT feature when returning from handler mode to + * thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters SLEEP mode when an interruption handling is over. + * @retval None. + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex-M33 System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enable CORTEX SEV-ON-PEND feature. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, any + * pending event / interrupt even if it's disabled or has insufficient + * priority to cause exception entry wakes up the Cortex-M33. + * @retval None. + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex-M33 System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Disable CORTEX SEVONPEND feature. + * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only + * enabled pending causes exception entry wakes up the Cortex-M33. + * @retval None. + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex-M33 System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_AVD_IRQHandler(). + * @note The use of this API is only when we activate the PVD. + * @note When the PVD and AVD are activated at the same time you must use this API: + * HAL_PWREx_PVD_AVD_IRQHandler. + * @retval None. + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + uint32_t rising_flag; + uint32_t falling_flag; + + /* Get pending flags */ + rising_flag = READ_REG(EXTI->RPR1); + falling_flag = READ_REG(EXTI->FPR1); + + /* Check PWR EXTI flags for PVD */ + if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0U) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PVD EXTI pending bit */ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); + } +} + +/** + * @brief PWR PVD interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback can be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group3 Attributes Management Functions + * @brief Attributes management functions + * +@verbatim + =============================================================================== + ##### PWR Attributes Functions ##### + =============================================================================== + [..] +@endverbatim + * @{ + */ + +/** + * @brief Configure the PWR item attributes. + * @note Available attributes are security and privilege protection. + * @note Security attribute can only be set only by secure access. + * @note Privilege attribute for secure items can be managed only by a secure + * privileged access. + * @note Privilege attribute for nsecure items can be managed by a secure + * privileged access or by a nsecure privileged access. + * @note As the privileged attributes concern either all secure or all non-secure + * PWR resources accesses and not each PWR individual items access attribute, + * the application must ensure that the privilege access attribute configurations + * are coherent amongst the security level set on PWR individual items so not to + * overwrite a previous more restricted access rule (consider either all secure + * and/or all non-secure PWR resources accesses by privileged-only transactions + * or privileged and unprivileged transactions). + * @param Item : Specifies the item(s) to set attributes on. + * This parameter can be a combination of @ref PWR_Items. + * @param Attributes : Specifies the available attribute(s). + * This parameter can be one of @ref PWR_Attributes. + * @retval None. + */ +void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes) +{ + /* Check the parameters */ + assert_param(IS_PWR_ATTRIBUTES(Attributes)); + +#if defined (PWR_SECCFGR_WUP1SEC) + assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Secure item management (TZEN = 1) */ + if ((Attributes & PWR_ITEM_ATTR_SEC_PRIV_MASK) == PWR_ITEM_ATTR_SEC_PRIV_MASK) + { + /* Privilege item management */ + if ((Attributes & PWR_SEC_PRIV) == PWR_SEC_PRIV) + { + SET_BIT(PWR->SECCFGR, Item); + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); + } + else + { + SET_BIT(PWR->SECCFGR, Item); + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); + } + } + /* NSecure item management */ + else + { + /* Privilege item management */ + if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV) + { + CLEAR_BIT(PWR->SECCFGR, Item); + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); + } + else + { + CLEAR_BIT(PWR->SECCFGR, Item); + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); + } + } +#else + /* NSecure item management (TZEN = 0) */ + if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK) + { + /* Privilege item management */ + if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV) + { + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); + } + else + { + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); + } + } +#endif /* __ARM_FEATURE_CMSE */ + +#else /* PWR_SECCFGR_WUP1SEC */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); + + /* NSecure item management (TZEN = 0) */ + if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK) + { + /* Privilege item management */ + if ((Attributes & PWR_PRIV) == PWR_PRIV) + { + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV); + } + else + { + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV); + } + } +#endif /* PWR_SECCFGR_WUP1SEC */ +} + +/** + * @brief Get attribute(s) of a PWR item. + * @param Item : Specifies the item(s) to set attributes on. + * This parameter can be one of @ref PWR_Items. + * @param pAttributes : Pointer to return attribute(s). + * Returned value could be on of @ref PWR_Attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) +{ + uint32_t attributes; + + /* Check attribute pointer */ + if (pAttributes == NULL) + { + return HAL_ERROR; + } +#if defined (PWR_SECCFGR_WUP1SEC) + /* Check the parameter */ + assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item)); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Check item security */ + if ((PWR->SECCFGR & Item) == Item) + { + /* Get Secure privileges attribute */ + attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_SPRIV) == 0U) ? PWR_SEC_NPRIV : PWR_SEC_PRIV; + } + else + { + /* Get Non-Secure privileges attribute */ + attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; + } +#else + /* Get Non-Secure privileges attribute */ + attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; +#endif /* __ARM_FEATURE_CMSE */ + +#else /* PWR_SECCFGR_WUP1SEC*/ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); + + /* Get Non-Secure privileges attribute */ + attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_PRIV) == 0U) ? PWR_NPRIV : PWR_PRIV; +#endif /* PWR_SECCFGR_WUP1SEC */ + + /* return value */ + *pAttributes = attributes; + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (HAL_PWR_MODULE_ENABLED) */ +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c new file mode 100644 index 00000000..0f43dfe2 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c @@ -0,0 +1,914 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller extension peripheral : + * + Power Supply Control Functions + * + Voltage Monitoring Functions + * + Wakeup Pins configuration Functions + * + Memories Retention Functions + * + IO and JTAG Retention Functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR Extended HAL module driver + * @{ + */ + +#if defined (HAL_PWR_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines + * @{ + */ +/* PORTI pins mask */ +#define PWR_PORTI_AVAILABLE_PINS (0xFFU) +/*!< Time out value of flags setting */ +#define PWR_FLAG_SETTING_DELAY (0x32U) + +/** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask + * @{ + */ +#define PVM_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVM trigger */ +#define PVM_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVM trigger */ +#define PVM_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVM threshold crossing */ +#define PVM_MODE_EVT (0x08U) /*!< Mask for event yielded by PVM threshold crossing */ +/** + * @} + */ + +/** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins offsets + * @{ + */ + +/* Wake-Up Pins PWR Pin Pull shift offsets */ +#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U) + +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @brief Power supply control functions + * +@verbatim + =============================================================================== + ##### Power supply control functions ##### + =============================================================================== + [..] +@endverbatim + * @{ + */ + +/** + * @brief Configure the system Power Supply. + * @param SupplySource : Specifies the Power Supply source to set after a + * system startup. + * This parameter can be one of the following values : + * @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_PWR_SUPPLY(SupplySource)); + + if ((PWR->SCCR & PWR_SCCR_BYPASS) != (PWR_SCCR_BYPASS)) + { + /* Set the power supply configuration */ + MODIFY_REG(PWR->SCCR, PWR_SUPPLY_CONFIG_MASK, SupplySource); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG(PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief Get the power supply configuration. + * @retval The supply configuration. + */ +uint32_t HAL_PWREx_GetSupplyConfig(void) +{ + return (PWR->SCCR & PWR_SUPPLY_CONFIG_MASK); +} + +/** + * @brief Configure the main internal regulator output voltage. + * @param VoltageScaling : Specifies the regulator output voltage to achieve + * a tradeoff between performance and power + * consumption. + * This parameter can be one of the following values : + * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output + * Scale 0 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output + * range 1 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output + * range 2 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output + * range 3 mode. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + /* Get the voltage scaling */ + if ((PWR->VOSSR & PWR_VOSSR_ACTVOS) == (VoltageScaling << 10U)) + { + /* Old and new voltage scaling configuration match : nothing to do */ + return HAL_OK; + } + + /* Set the voltage range */ + MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, VoltageScaling); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Get the main internal regulator output voltage. Reflecting the last + * VOS value applied to the PMU. + * @retval The current applied VOS selection. + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + /* Get the active voltage scaling */ + return (PWR->VOSSR & PWR_VOSSR_ACTVOS); +} + +/** + * @brief Configure the main internal regulator output voltage in STOP mode. + * @param VoltageScaling : Specifies the regulator output voltage when the + * system enters Stop mode to achieve a tradeoff between performance + * and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range + * 3 mode. + * @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range + * 4 mode. + * @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range + * 5 mode. + * @note The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage + * regulator in Low-power (LP) mode to further reduce power consumption. + * When preselecting SVOS3, the use of the voltage regulator low-power + * mode (LP) can be selected by LPDS register bit. + * @note The selected SVOS4 and SVOS5 levels add an additional startup delay + * when exiting from system Stop mode. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param(IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VoltageScaling)); + + /* Return the stop mode voltage range */ + MODIFY_REG(PWR->PMCR, PWR_PMCR_SVOS, VoltageScaling); + + return HAL_OK; +} + +/** + * @brief Get the main internal regulator output voltage in STOP mode. + * @retval The actual applied VOS selection. + */ +uint32_t HAL_PWREx_GetStopModeVoltageRange(void) +{ + /* Return the stop voltage scaling */ + return (PWR->PMCR & PWR_PMCR_SVOS); +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group2 Voltage Monitoring Functions + * @brief Voltage monitoring functions + * +@verbatim + =============================================================================== + ##### Voltage Monitoring Functions ##### + =============================================================================== + [..] +@endverbatim + * @{ + */ + +/** + * @brief Configure the event mode and the voltage threshold detected by the + * Analog Voltage Detector (AVD). + * @param sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains + * the configuration information for the AVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None. + */ +void HAL_PWREx_ConfigAVD(const PWREx_AVDTypeDef *sConfigAVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_AVD_LEVEL(sConfigAVD->AVDLevel)); + assert_param(IS_PWR_AVD_MODE(sConfigAVD->Mode)); + + /* Set the ALS[10:9] bits according to AVDLevel value */ + MODIFY_REG(PWR->VMCR, PWR_VMCR_ALS, sConfigAVD->AVDLevel); + + /* Clear any previous config */ + __HAL_PWR_AVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_AVD_EXTI_DISABLE_IT(); + __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the interrupt mode */ + if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) + { + __HAL_PWR_AVD_EXTI_ENABLE_IT(); + } + + /* Configure the event mode */ + if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) + { + __HAL_PWR_AVD_EXTI_ENABLE_EVENT(); + } + + /* Rising edge configuration */ + if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) + { + __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); + } + + /* Falling edge configuration */ + if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) + { + __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enable the Analog Voltage Detector (AVD). + * @retval None. + */ +void HAL_PWREx_EnableAVD(void) +{ + /* Enable the Analog Voltage Detector */ + SET_BIT(PWR->VMCR, PWR_VMCR_AVDEN); +} + +/** + * @brief Disable the Analog Voltage Detector(AVD). + * @retval None. + */ +void HAL_PWREx_DisableAVD(void) +{ + /* Disable the Analog Voltage Detector */ + CLEAR_BIT(PWR->VMCR, PWR_VMCR_AVDEN); +} + +#if defined (PWR_USBSCR_USB33DEN) +/** + * @brief Enable the USB voltage level detector. + * @retval None. + */ +void HAL_PWREx_EnableUSBVoltageDetector(void) +{ + /* Enable the USB voltage detector */ + SET_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN); +} + +/** + * @brief Disable the USB voltage level detector. + * @retval None. + */ +void HAL_PWREx_DisableUSBVoltageDetector(void) +{ + /* Disable the USB voltage detector */ + CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN); +} + +/** + * @brief Enable VDDUSB supply. + * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply + * is present for consumption saving. + * @retval None. + */ +void HAL_PWREx_EnableVddUSB(void) +{ + SET_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV); +} + +/** + * @brief Disable VDDUSB supply. + * @retval None. + */ +void HAL_PWREx_DisableVddUSB(void) +{ + CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV); +} +#endif /* PWR_USBSCR_USB33DEN */ + +#if defined (PWR_USBSCR_OTGHSEN) +/** + * @brief Enable the USB OTGHS PHY. + * @retval None. + */ +void HAL_PWREx_EnableUSBOTGHSPhy(void) +{ + /* Enable the USB OTGHS PHY */ + SET_BIT(PWR->USBSCR, PWR_USBSCR_OTGHSEN); +} + +/** + * @brief Disable the USB OTGHS PHY. + * @retval None. + */ +void HAL_PWREx_DisableUSBOTGHSPhy(void) +{ + /* Disable the OTGHS PHY */ + CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_OTGHSEN); +} +#endif /* PWR_USBSCR_OTGHSEN */ + +/** + * @brief Enable the VBAT and temperature monitoring. + * @retval None. + */ +void HAL_PWREx_EnableMonitoring(void) +{ + SET_BIT(PWR->BDCR, PWR_BDCR_MONEN); +} + +/** + * @brief Disable the VBAT and temperature monitoring. + * @retval None. + */ +void HAL_PWREx_DisableMonitoring(void) +{ + CLEAR_BIT(PWR->BDCR, PWR_BDCR_MONEN); +} + +#if defined (PWR_UCPDR_UCPD_STBY) +/** + * @brief Enable UCPD configuration memorization in Standby mode. + * @retval None. + */ +void HAL_PWREx_EnableUCPDStandbyMode(void) +{ + SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY); +} + +/** + * @brief Disable UCPD configuration memorization in Standby mode. + * @note This function must be called on exiting the Standby mode and before + * any UCPD configuration update. + * @retval None. + */ +void HAL_PWREx_DisableUCPDStandbyMode(void) +{ + CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY); +} +#endif /* PWR_UCPDR_UCPD_STBY */ + +#if defined (PWR_UCPDR_UCPD_DBDIS) +/** + * @brief Enable dead battery behavior. + * @note After exiting reset, the USB Type-C (dead battery) behavior is + * enabled, which may have a pull-down effect on CC1 and CC2 pins. + * It is recommended to disable it in all cases, either to stop this + * pull-down or to handover control to the UCPD (the UCPD must be + * initialized before doing the disable). + * @retval None. + */ +void HAL_PWREx_EnableUCPDDeadBattery(void) +{ + CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); +} + +/** + * @brief Disable dead battery behavior. + * @note After exiting reset, the USB Type-C (dead battery) behavior is + * enabled, which may have a pull-down effect on CC1 and CC2 pins. + * It is recommended to disable it in all cases, either to stop this + * pull-down or to handover control to the UCPD (the UCPD must be + * initialized before doing the disable). + * @retval None. + */ +void HAL_PWREx_DisableUCPDDeadBattery(void) +{ + SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); +} +#endif /* PWR_UCPDR_UCPD_DBDIS */ + +/** + * @brief Enable the Battery charging. + * @note When VDD is present, charge the external battery through an internal + * resistor. + * @param ResistorValue : Specifies the charging resistor. + * This parameter can be one of the following values : + * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor. + * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor. + * @retval None. + */ +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue) +{ + /* Check the parameter */ + assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue)); + + /* Specify the charging resistor */ + MODIFY_REG(PWR->BDCR, PWR_BDCR_VBRS, ResistorValue); + + /* Enable the Battery charging */ + SET_BIT(PWR->BDCR, PWR_BDCR_VBE); +} + +/** + * @brief Disable the Battery charging. + * @retval None. + */ +void HAL_PWREx_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->BDCR, PWR_BDCR_VBE); +} + +/** + * @brief Enable the booster to guarantee the analog switch AC performance when + * the VDD supply voltage is below 2V7. + * @note The VDD supply voltage can be monitored through the PVD and the PLS + * field bits. + * @retval None. + */ +void HAL_PWREx_EnableAnalogBooster(void) +{ + /* Enable the Analog voltage */ + SET_BIT(PWR->PMCR, PWR_PMCR_AVD_READY); + + /* Enable VDDA booster */ + SET_BIT(PWR->PMCR, PWR_PMCR_BOOSTE); +} + +/** + * @brief Disable the analog booster. + * @retval None. + */ +void HAL_PWREx_DisableAnalogBooster(void) +{ + /* Disable VDDA booster */ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_BOOSTE); + + /* Disable the Analog voltage */ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_AVD_READY); +} + +/** + * @brief This function handles the PWR PVD/AVD interrupt request. + * @note This API should be called under the PVD_AVD_IRQHandler(). + * @note The use of this API is when the PVD and AVD are activated at the same time. + * @retval None + */ +void HAL_PWREx_PVD_AVD_IRQHandler(void) +{ + /* Check PWR PVD AVD EXTI Rising flag */ + if (__HAL_PWR_PVD_AVD_EXTI_GET_RISING_FLAG() != 0U) + { + /* Clear PWR PVD AVD EXTI Rising pending bit */ + WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVD); + + /* PWR PVD AVD Rising interrupt user callback */ + HAL_PWREx_PVD_AVD_Rising_Callback(); + } + + /* Check PWR PVD AVD EXTI Falling flag */ + if (__HAL_PWR_PVD_AVD_EXTI_GET_FALLING_FLAG() != 0U) + { + /* Clear PWR PVD AVD EXTI Falling pending bit */ + WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVD); + + /* PWR PVD AVD Falling interrupt user callback */ + HAL_PWREx_PVD_AVD_Falling_Callback(); + } +} + +/** + * @brief PWR PVD AVD Rising interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_PVD_AVD_Rising_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_AVDCallback can be implemented in the user file + */ +} + +/** + * @brief PWR PVD AVD Falling interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_PVD_AVD_Falling_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_AVDCallback can be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group3 Wakeup Pins configuration Functions + * @brief Wakeup Pins configuration functions + * +@verbatim + =============================================================================== + ##### Wakeup Pins configuration Functions ##### + =============================================================================== + [..] +@endverbatim + * @{ + */ + +/** + * @brief Enable the Wake-up PINx functionality. + * @param sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that + * contains the configuration information for the wake-up + * Pin. + * @retval None. + */ +void HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef *sPinParams) +{ + uint32_t pinConfig; + uint32_t regMask; + const uint32_t pullMask = PWR_WUCR_WUPPUPD1; + + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(sPinParams->WakeUpPin)); + assert_param(IS_PWR_WAKEUP_PIN_POLARITY(sPinParams->PinPolarity)); + assert_param(IS_PWR_WAKEUP_PIN_PULL(sPinParams->PinPull)); + + pinConfig = sPinParams->WakeUpPin | \ + (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WUCR_WUPP1_Pos) & 0x1FU)) | \ + (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) \ + + PWR_WUCR_WUPPUPD1_Pos) & 0x1FU)); + + regMask = sPinParams->WakeUpPin | \ + (PWR_WUCR_WUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \ + (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU)); + + /* Enable and Specify the Wake-Up pin polarity and the pull configuration + for the event detection (rising or falling edge) */ + MODIFY_REG(PWR->WUCR, regMask, pinConfig); +} + +/** + * @brief Disable the Wake-up PINx functionality. + * @param WakeUpPinx : Specifies the Wake-Up pin to be disabled. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 + * @arg PWR_WAKEUP_PIN3 + * @arg PWR_WAKEUP_PIN4 + * @arg PWR_WAKEUP_PIN5 + * @arg PWR_WAKEUP_PIN6 + * @arg PWR_WAKEUP_PIN7 + * @arg PWR_WAKEUP_PIN8 + * @note The PWR_WAKEUP_PIN6, PWR_WAKEUP_PIN7 and PWR_WAKEUP_PIN8 are not available for + * STM32H503xx devices. + * @retval None + */ +void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + /* Disable the WakeUpPin */ + CLEAR_BIT(PWR->WUCR, (PWR_WUCR_WUPEN & WakeUpPinx)); +} + +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group4 Memories Retention Functions + * @brief Memories retention functions + * +@verbatim + =============================================================================== + ##### Memories Retention Functions ##### + =============================================================================== + [..] +@endverbatim + * @{ + */ + +/** + * @brief Enable the Flash Power Down in Stop mode. + * @note When Flash Power Down is enabled the Flash memory enters low-power + * mode. This feature allows to + * obtain the best trade-off between low-power consumption and restart + * time when exiting from Stop mode. + * @retval None. + */ +void HAL_PWREx_EnableFlashPowerDown(void) +{ + /* Enable the Flash Power Down */ + SET_BIT(PWR->PMCR, PWR_PMCR_FLPS); +} + +/** + * @brief Disable the Flash Power Down in Stop mode. + * @note When Flash Power Down is disabled the Flash memory is kept on + * normal mode. This feature allows + * to obtain the best trade-off between low-power consumption and + * restart time when exiting from Stop mode. + * @retval None. + */ +void HAL_PWREx_DisableFlashPowerDown(void) +{ + /* Disable the Flash Power Down */ + CLEAR_BIT(PWR->PMCR, PWR_PMCR_FLPS); +} + +/** + * @brief Enable memory block shut-off in Stop mode + * @note In Stop mode, the content of the memory blocks is + * maintained. Further power optimization can be obtained by switching + * off some memory blocks. This optimization implies loss of the memory + * content. The user can select which memory is discarded during STOP + * mode by means of xxSO bits. + * @param MemoryBlock : Specifies the memory block to shut-off during Stop mode. + * This parameter can be one of the following values for STM32H5F5xx/STM32H5F4xx/STM32H5E5xx/STM32H5E4xx : + * @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode + * @arg PWR_LTDC_MEMORY_BLOCK PWR_PMCR_LTDCSO : LTDC shut-off control in Stop mode + * @arg PWR_RAM5_MEMORY_BLOCK PWR_PMCR_SRAM5SO : RAM5 shut-off control in Stop mode + * @arg PWR_RAM4_MEMORY_BLOCK PWR_PMCR_SRAM4SO : RAM4 shut-off control in Stop mode + * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode + * @arg PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO : RAM2 Low 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO : RAM2 High 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_LOW_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48LSO : RAM2 Low 48k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_HIGH_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48HSO : RAM2 High 48k byte shut-off control + * in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * This parameter can be one of the following values for STM32H553xx/STM32H543xx : + * @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode + * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode + * @arg PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO : RAM2 Low 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO : RAM2 High 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * This parameter can be one of the following values for STM32H573xx/STM32H563xx/STM32H562xx : + * @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode + * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode + * @arg PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO : RAM2 16k byte shut-off control in Stop mode + * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * This parameter can be one of the following values for STM32H533xx/STM32H523xx : + * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode + * @arg PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO : RAM2 Low 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO : RAM2 High 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * This parameter can be one of the following values for STM32H503xx : + * @arg PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO : RAM2 shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * @retval None. + */ +void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock) +{ + /* Check the parameter */ + assert_param(IS_PWR_MEMORY_BLOCK(MemoryBlock)); + + /* Enable memory block shut-off */ + SET_BIT(PWR->PMCR, MemoryBlock); +} + +/** + * @brief Disable memory block shut-off in Stop mode + * @param MemoryBlock : Specifies the memory block to keep content during + * Stop mode. + * This parameter can be one of the following values for STM32H5F5xx/STM32H5F4xx/STM32H5E5xx/STM32H5E4xx : + * @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode + * @arg PWR_LTDC_MEMORY_BLOCK PWR_PMCR_LTDCSO : LTDC shut-off control in Stop mode + * @arg PWR_RAM5_MEMORY_BLOCK PWR_PMCR_SRAM5SO : RAM5 shut-off control in Stop mode + * @arg PWR_RAM4_MEMORY_BLOCK PWR_PMCR_SRAM4SO : RAM4 shut-off control in Stop mode + * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode + * @arg PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO : RAM2 Low 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO : RAM2 High 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_LOW_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48LSO : RAM2 Low 48k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_HIGH_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48HSO : RAM2 High 48k byte shut-off control + * in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * This parameter can be one of the following values for STM32H553xx/STM32H543xx : + * @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode + * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode + * @arg PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO : RAM2 Low 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO : RAM2 High 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * This parameter can be one of the following values for STM32H573xx/STM32H563xx/STM32H562xx : + * @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode + * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode + * @arg PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO : RAM2 16k byte shut-off control in Stop mode + * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * This parameter can be one of the following values for STM32H533xx/STM32H523xx : + * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode + * @arg PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO : RAM2 Low 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO : RAM2 High 16k byte shut-off control + * in Stop mode + * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * This parameter can be one of the following values for STM32H503xx : + * @arg PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO : RAM2 shut-off control in Stop mode + * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode + * @retval None. + */ +void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock) +{ + /* Check the parameter */ + assert_param(IS_PWR_MEMORY_BLOCK(MemoryBlock)); + + /* Disable memory block shut-off */ + CLEAR_BIT(PWR->PMCR, MemoryBlock); +} + +/** + * @brief Enable the Backup RAM retention in Standby and VBAT modes. + * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and + * Stop modes. However, its content is lost in Standby, Shutdown and + * VBAT modes. This bit can be writte + * @retval None. + */ +HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void) +{ + SET_BIT(PWR->BDCR, PWR_BDCR_BREN); + + return HAL_OK; +} + +/** + * @brief Disable the Backup RAM retention in Standby and VBAT modes. + * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and + * Stop modes. However, its content is lost in Standby, Shutdown and + * VBAT modes. This bit can be write + * @retval None. + */ +void HAL_PWREx_DisableBkupRAMRetention(void) +{ + CLEAR_BIT(PWR->BDCR, PWR_BDCR_BREN); +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group5 IO and JTAG Retention Functions + * @brief IO and JTAG Retention functions + * +@verbatim + =============================================================================== + ##### IO and JTAG Retention Functions ##### + =============================================================================== + [..] + In the Standby mode, the I/Os are by default in floating state. If the IORETEN bit in the + PWR_IORETR register is set, the I/Os output state is retained. IO Retention mode is + enabled for all IO except the IO support the standby functionality and JTAG IOs (PA13, + PA14, PA15 and PB4). When entering into Standby mode, the state of the output is + sampled, and pull-up or pull-down resistor are set to maintain the IO output during Standby + mode. + If the JTAGIORETEN bit in the PWR_IORETR register is set, the I/Os output state is + retained. IO Retention mode is enabled for PA13, PA14, PA15 and PB4 (default JTAG pullup/ + pull-down after wakeup are not enabled). +@endverbatim + * @{ + */ + +/** + * @brief Enable GPIO state retention in Standby mode. + * @note When entering into standby mode, the output is sampled, and applied to the output IO during + * the standby power mode + * @retval None. + */ +void HAL_PWREx_EnableStandbyIORetention(void) +{ + /* Enable GPIO state retention */ + SET_BIT(PWR->IORETR, PWR_IORETR_IORETEN); +} + +/** + * @brief Disable GPIO state retention in Standby mode. + * @retval None. + */ +void HAL_PWREx_DisableStandbyIORetention(void) +{ + /* Disable GPIO state retention */ + CLEAR_BIT(PWR->IORETR, PWR_IORETR_IORETEN); +} + +/** + * @brief Enable JTAG IOs state retention in Standby mode. + * @note when entering into standby mode, the output is sampled, and applied to the output IO during + * the standby power mode + * @retval None. + */ +void HAL_PWREx_EnableStandbyJTAGIORetention(void) +{ + /* Enable JTAG IOs state retention */ + SET_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN); +} + +/** + * @brief Disable JTAG IOs state retention in Standby mode. + * @retval None. + */ +void HAL_PWREx_DisableStandbyJTAGIORetention(void) +{ + /* Enable JTAG IOs state retention */ + CLEAR_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN); +} + +/** + * @} + */ +#endif /* defined (HAL_PWR_MODULE_ENABLED) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c new file mode 100644 index 00000000..8be8454a --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c @@ -0,0 +1,1901 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from High Speed Internal oscillator + (64 MHz) with Flash 3 wait states. Flash prefetch buffer, D-Cache + and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + + (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses: + all peripherals mapped on these busses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in analog mode, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (SAIx, RTC, ADC, USB, SDMMC, etc.) + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ + +/** @defgroup RCC_Timeout_Value Timeout Values + * @{ + */ +#define RCC_LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#define RCC_HSI48_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#define RCC_PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#define RCC_CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */ +#define RCC_PLL_FRAC_WAIT_VALUE 1U /* PLL Fractional part waiting time before new latch enable : 1 ms */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define MCO2_GPIO_PORT GPIOC +#define MCO2_PIN GPIO_PIN_9 + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal and external oscillators + (HSE, HSI, LSE, CSI, LSI, PLL1, HSE CSS and MCOs) and the System busses clocks (SYSCLK, AHB, APB1, APB2 + and APB3). + + [..] Internal/external clock and PLL configuration + (+) HSI (high-speed internal): 64 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral + clock, or PLL input. But even with frequency calibration, is less accurate than an + external crystal oscillator or ceramic resonator. + + (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also optionally as RTC clock source. + + (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source. + + (+) PLL1 (clocked by HSI, HSE or CSI) providing up to three independent output clocks: + (++) The first output is used to generate the high speed system clock (up to 250MHz). + (++) The second output is used to generate the clock for the USB (48 MHz), the FDCAN1/2, + the SPI1/2/3, the OCTOSPI, the RNG (<=48 MHz), the SDMMC1/2 and to generate an accurate + clock to achieve high-quality audio performance on SAI1/2 interface. + + (+) PLL2 (clocked by HSI, HSE or CSI) providing up to three independent output clocks: + (++) The first output is used to generate the clock for the LPTIMs, the SPI1/2/3 and to generate + an accurate clock to achieve high-quality audio performance on SAI1/2 interface. + (++) The second output is used to generate the clock for USARTs, the UARTs, the LPUART1, + the FDCAN1/2, the SPI4/5/6 and the USB. + (++) The third output is used to generate the clock the SDMMC1/2, the ADC/DAC, the I2C1/2, + the I3C1/2 and the OCTOSPI. + + (+) PLL3 (clocked by HSI , HSE or CSI) providing up to three independent output clocks: + (++) The first output is used to generate the clock for SPI1/2/3 and to generate an accurate + clock to achieve high-quality audio performance on SAI1/2 interface. + (++) The second output is used to generate the clock for USARTs, the UARTs, the LPUART1, + the SPI4/5/6 and the USB. + (++) The third output is used to generate the clock for the I2Cs, the I3Cs and the LPTIMs. + + (+) HSE CSS (HSE Clock Security System): once enabled, if a HSE clock failure occurs + (HSE used directly or through PLL1 as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M33 NMI (Non-Maskable Interrupt) + exception vector. + + (#) MCO1 (micro controller clock output1), used to output HSI, LSE, HSE, PLL1(PLL1_Q) + or HSI48 clock (through a configurable pre-scaler) on PA8 pin. + + (#) MCO2 (micro controller clock output2), used to output HSE, PLL2(PLL2_P), SYSCLK, + LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin. + + [..] System, AHB and APB busses clocks configuration + (+) Several clock sources can be used to drive the System clock (SYSCLK): CSI, HSI, HSE and the main PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1), APB2 (PCLK2) and APB3 (PCLK3) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + + (+@) SAI: the SAI clock can be derived either from specific PLL (PLL1, PLL2 or PLL3), + the per_ck clock (HSE, HSI or CSI) or from an external clock mapped on the SAI_CKIN pin. + You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. + (+@) SPI/I2S: the SPI1/2/3 clock can be derived either from specific PLL (PLL1, PLL2 or PLL3), + the per_ck clock (HSE, HSI or CSI) or from an external clock mapped on the SPI_CKIN pin. + You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. + (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. + You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function + to configure this clock. + (+@) USB: USB requires a frequency equal to 48 MHz to work correctly. This clock is derived + of the main PLL or PLL2 through PLLQ divider. You have to use HAL_RCCEx_PeriphCLKConfig() + function to configure this clock. + (+@) UCPD: the UCPD clock is derived from HSI (divided by 4) clock. + (+@) SDMMC: SDMMC1/2 peripherals require a frequency equal or lower than 48 MHz. + This clock is derived from the PLL1 or PLL2 through PLL1Q or PLL2R divider. You have + to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. + (+@) IWDG clock which is always the LSI clock. You have to use HAL_RCCEx_PeriphCLKConfig() + function to configure this clock. + (+@) RNG: the RNG clock can be derived either from PLL1Q, HSI48, LSE or LSI clock. You have + to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. + (+@) DAC: the DAC clock can be derived either from LSE or LSI clock. You have + to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. + (+@) FDCAN: the FDCAN1/2 clock can be derived either from HSE, PLL1Q or PLL2Q clock. You have + to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. + (+@) CEC: the CEC clock can be derived either from LSE, LSI or CSI (divided by 122) clock.You have + to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. + (+@) ETH: the Ethernet clock is derived from PLL1Q clock. + + + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1, PCLK2 and PCLK3 is 250 MHz. + The clock source frequency should be adapted depending on the device voltage range + as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter. + + @endverbatim + + + Table 1. HCLK clock frequency for STM32H5xx devices + +-----------------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |-----------------------------------------------------------------------------| + | | voltage range 0 | voltage range 1 | voltage range 2 | voltage range 3 | + | | 1.26 - 1.35V | 1.15 - 1.26V | 1.05 - 1.15V | 0,95 - 1,05V | + |-----------------|-------------------|------------------|------------------|-------------------| + |0WS(1 CPU cycles)| 0 < HCLK <= 38 | 0 < HCLK <= 32 | 0 < HCLK <= 26 | 0 < HCLK <= 16 | + |-----------------|-------------------|------------------|------------------|-------------------| + |1WS(2 CPU cycles)| 38 < HCLK <= 76 | 32 < HCLK <= 64 | 26 < HCLK <= 50 | 16 < HCLK <= 32 | + |-----------------|-------------------|------------------|------------------|-------------------| + |2WS(3 CPU cycles)| 76 < HCLK <= 114 | 64 < HCLK <= 96 | 50 < HCLK <= 80 | 32 < HCLK <= 50 | + |-----------------|-------------------|------------------|------------------|-------------------| + |3WS(4 CPU cycles)| 114 < HCLK <= 152 | 96 < HCLK <= 128 | 80 < HCLK <= 106 | 50 < HCLK <= 65 | + |-----------------|-------------------|------------------|------------------|-------------------| + |4WS(5 CPU cycles)| 152 < HCLK <= 190| 128 < HCLK <= 160| 106 < HCLK <= 130| 65 < HCLK <= 80 | + |-----------------|-------------------|------------------|------------------|-------------------| + |5WS(6 CPU cycles)| 190 < HCLK <= 250| 160 < HCLK <= 180| NA | NA | + +-----------------+-------------------+------------------+------------------+-------------------+ + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, CSI, PLL, PLL2 and PLL3 OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - HSECSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL Status. + */ + +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Increasing the CPU frequency */ + if (FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + { + return HAL_ERROR; + } + + } + + /* Get start tick*/ + tickstart = HAL_GetTick(); + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSIDIV Default value */ + CLEAR_BIT(RCC->CR, RCC_CR_HSIDIV); + + /* Set HSITRIM default value */ + WRITE_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6); + + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get start tick*/ + tickstart = HAL_GetTick(); + + /* Reset CFGR register (HSI is selected as system clock source) */ + CLEAR_REG(RCC->CFGR1); + CLEAR_REG(RCC->CFGR2); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset HSECSSON, HSEON, HSIKERON, CSION, CSIKERON and HSI48ON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSECSSON | RCC_CR_HSIKERON | RCC_CR_HSI48ON | \ + RCC_CR_HSEON); + + /* Reset HSEEXT bit*/ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLL1ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); + + /* Wait till PLL1 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLL2N bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); + + /* Wait till PLL2 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + +#if defined(RCC_CR_PLL3ON) + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLL3 bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); + + /* Wait till PLL3 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_CR_PLL3ON */ + + /* Reset PLL1CFGR register */ + CLEAR_REG(RCC->PLL1CFGR); + + /* Reset PLL1DIVR register */ + WRITE_REG(RCC->PLL1DIVR, 0x01010280U); + + /* Reset PLL1FRACR register */ + CLEAR_REG(RCC->PLL1FRACR); + + /* Reset PLL2CFGR register */ + CLEAR_REG(RCC->PLL2CFGR); + + /* Reset PLL2DIVR register */ + WRITE_REG(RCC->PLL2DIVR, 0x01010280U); + + /* Reset PLL2FRACR register */ + CLEAR_REG(RCC->PLL2FRACR); + +#if defined(RCC_CR_PLL3ON) + /* Reset PLL3CFGR register */ + CLEAR_REG(RCC->PLL3CFGR); + + /* Reset PLL3DIVR register */ + WRITE_REG(RCC->PLL3DIVR, 0x01010280U); + + /* Reset PLL3FRACR register */ + CLEAR_REG(RCC->PLL3FRACR); +#endif /* RCC_CR_PLL3ON */ + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIER); + + /* Clear all interrupts flags */ + WRITE_REG(RCC->CICR, 0xFFFFFFFFU); + + /* Reset all RSR flags */ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + { + return HAL_ERROR; + } + } + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Initialize the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param pOscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pOscInitStruct) +{ + uint32_t tickstart; + uint32_t temp_sysclksrc; + uint32_t temp_pllckselr; + uint32_t temp1_pllckcfg; + uint32_t temp2_pllckcfg; + + /* Check Null pointer */ + if (pOscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(pOscInitStruct->OscillatorType)); + temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + temp_pllckselr = __HAL_RCC_GET_PLL1_OSCSOURCE(); + + /*----------------------------- CSI Configuration --------------------------*/ + if (((pOscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) + { + /* Check the parameters */ + assert_param(IS_RCC_CSI(pOscInitStruct->CSIState)); + assert_param(IS_RCC_CSICALIBRATION_VALUE(pOscInitStruct->CSICalibrationValue)); + + /* When the CSI is used as system clock it will not be disabled */ + if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_CSI) || + ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckselr == RCC_PLL1_SOURCE_CSI))) + { + if (pOscInitStruct->CSIState == RCC_CSI_OFF) + { + return HAL_ERROR; + } + + /* Otherwise, just the calibration and CSI is allowed */ + else + { + /* Adjusts the Internal Low-power oscillator (CSI) calibration value.*/ + __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(pOscInitStruct->CSICalibrationValue); + } + } + else + { + /* Check the CSI State */ + if ((pOscInitStruct->CSIState) != RCC_CSI_OFF) + { + /* Enable the Internal High Speed oscillator (CSI). */ + __HAL_RCC_CSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till CSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_CSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ + __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(pOscInitStruct->CSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (CSI). */ + __HAL_RCC_CSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till CSI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_CSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------- HSE Configuration ------------------------*/ + if (((pOscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(pOscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) || + ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckselr == RCC_PLL1_SOURCE_HSE))) + { + if (pOscInitStruct->HSEState == RCC_HSE_OFF) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(pOscInitStruct->HSEState); + + /* Check the HSE State */ + if (pOscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((pOscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(pOscInitStruct->HSIState)); + assert_param(IS_RCC_HSIDIV(pOscInitStruct->HSIDiv)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(pOscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) || + ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckselr == RCC_PLL1_SOURCE_HSI))) + { + /* When HSI is used as system clock it will not be disabled */ + if (pOscInitStruct->HSIState == RCC_HSI_OFF) + { + return HAL_ERROR; + } + /* Otherwise, HSI calibration and division may be allowed */ + else + { + + /* HSI division is allowed if HSI is used as system clock */ + if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) + { + if (__HAL_RCC_GET_HSI_DIVIDER() != (pOscInitStruct->HSIDiv)) + { + /* Adjust the HSI division factor */ + __HAL_RCC_HSI_DIVIDER_CONFIG(pOscInitStruct->HSIDiv); + + /* Update the SystemCoreClock global variable with new HSI value */ + (void) HAL_RCC_GetHCLKFreq(); + + /* Configure the source of time base considering new system clocks settings*/ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + } + } + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pOscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if (pOscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Adjust the HSI division factor */ + __HAL_RCC_HSI_DIVIDER_CONFIG(pOscInitStruct->HSIDiv); + + /* Enable the HSI oscillator */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjust the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pOscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((pOscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + + /* Check the parameters */ + assert_param(IS_RCC_LSI(pOscInitStruct->LSIState)); + + /* Update LSI configuration in Backup Domain control register */ + + /* Check the LSI State */ + if (pOscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((pOscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + + /* Check the parameters */ + assert_param(IS_RCC_LSE(pOscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain */ + if (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(pOscInitStruct->LSEState); + + /* Check the LSE State */ + if (pOscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + } + /*------------------------------ HSI48 Configuration -----------------------*/ + if (((pOscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(pOscInitStruct->HSI48State)); + + /* Check the HSI48 State */ + if (pOscInitStruct->HSI48State != RCC_HSI48_OFF) + { + /* Enable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*-------------------------------- PLL1 Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(pOscInitStruct->PLL.PLLState)); + + if ((pOscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL1 is used as system clock or not */ + if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if ((pOscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLL1_SOURCE(pOscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL1_DIVM_VALUE(pOscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLL1_MULN_VALUE(pOscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLL1_DIVP_VALUE(pOscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLL1_DIVQ_VALUE(pOscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLL1_DIVR_VALUE(pOscInitStruct->PLL.PLLR)); + + /* Disable the PLL1. */ + __HAL_RCC_PLL1_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL1 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the PLL1 clock source, multiplication and division factors. */ + __HAL_RCC_PLL1_CONFIG(pOscInitStruct->PLL.PLLSource, + pOscInitStruct->PLL.PLLM, + pOscInitStruct->PLL.PLLN, + pOscInitStruct->PLL.PLLP, + pOscInitStruct->PLL.PLLQ, + pOscInitStruct->PLL.PLLR); + + assert_param(IS_RCC_PLL1_FRACN_VALUE(pOscInitStruct->PLL.PLLFRACN)); + + /* Disable PLL1FRACN . */ + __HAL_RCC_PLL1_FRACN_DISABLE(); + + /* Configure PLL PLL1FRACN */ + __HAL_RCC_PLL1_FRACN_CONFIG(pOscInitStruct->PLL.PLLFRACN); + + /* Enable PLL1FRACN . */ + __HAL_RCC_PLL1_FRACN_ENABLE(); + + assert_param(IS_RCC_PLL1_VCIRGE_VALUE(pOscInitStruct->PLL.PLLRGE)); + + /* Select PLL1 input reference frequency range: VCI */ + __HAL_RCC_PLL1_VCIRANGE(pOscInitStruct->PLL.PLLRGE) ; + + assert_param(IS_RCC_PLL1_VCORGE_VALUE(pOscInitStruct->PLL.PLLVCOSEL)); + + /* Select PLL1 output frequency range : VCO */ + __HAL_RCC_PLL1_VCORANGE(pOscInitStruct->PLL.PLLVCOSEL) ; + + /* Enable PLL1 System Clock output. */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVP); + + /* Enable the PLL1. */ + __HAL_RCC_PLL1_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL1 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the PLL1. */ + __HAL_RCC_PLL1_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL1 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Unselect PLL1 clock source and disable all PLL1 outputs to save power */ + RCC->PLL1CFGR &= ~(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1PEN | RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1REN); + + } + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp1_pllckcfg = RCC->PLL1CFGR; + temp2_pllckcfg = RCC->PLL1DIVR; + if (((pOscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1SRC) != pOscInitStruct->PLL.PLLSource) || + ((READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1M) >> \ + RCC_PLL1CFGR_PLL1M_Pos) != (pOscInitStruct->PLL.PLLM)) || + (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1N) != (pOscInitStruct->PLL.PLLN - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1P) >> \ + RCC_PLL1DIVR_PLL1P_Pos) != (pOscInitStruct->PLL.PLLP - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1Q) >> \ + RCC_PLL1DIVR_PLL1Q_Pos) != (pOscInitStruct->PLL.PLLQ - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1R) >> \ + RCC_PLL1DIVR_PLL1R_Pos) != (pOscInitStruct->PLL.PLLR - 1U))) + { + return HAL_ERROR; + } + + /* FRACN1 on-the-fly value update */ + if ((READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> \ + RCC_PLL1FRACR_PLL1FRACN_Pos) != (pOscInitStruct->PLL.PLLFRACN)) + { + assert_param(IS_RCC_PLL1_FRACN_VALUE(pOscInitStruct->PLL.PLLFRACN)); + + /* Disable PLL1FRACN . */ + __HAL_RCC_PLL1_FRACN_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value + will be taken into account. */ + while ((HAL_GetTick() - tickstart) < RCC_PLL_FRAC_WAIT_VALUE) + { + } + + /* Configure PLL PLL1FRACN */ + __HAL_RCC_PLL1_FRACN_CONFIG(pOscInitStruct->PLL.PLLFRACN); + + /* Enable PLL1FRACN to latch the new value. */ + __HAL_RCC_PLL1_FRACN_ENABLE(); + } + + } + } + return HAL_OK; +} + +/** + * @brief Initialize the CPU, AHB and APB busses clocks according to the specified + * parameters in the pClkInitStruct. + * @param pClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle + * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle + * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles + * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles + * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles + * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used by default as system clock source after + * startup from Reset, wake-up from STANDBY mode. After restart from Reset, + * the HSI frequency is set to its default value 64 MHz. + * + * @note The HSI or CSI can be selected as system clock source after wake-up + * from STOP modes or in case of failure of the HSE when used directly or indirectly + * as system clock (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source is ready. + * + * @note You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *pClkInitStruct, uint32_t FLatency) +{ + HAL_StatusTypeDef halstatus; + uint32_t tickstart; + + /* Check Null pointer */ + if (pClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(pClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /* Increasing the BUS frequency divider */ + /*-------------------------- PCLK3 Configuration ---------------------------*/ + if (((pClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3) + { + if ((pClkInitStruct->APB3CLKDivider) > ((RCC->CFGR2 & RCC_CFGR2_PPRE3) >> 8)) + { + assert_param(IS_RCC_PCLK(pClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE3, ((pClkInitStruct->APB3CLKDivider) << 8)); + } + } + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((pClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + if ((pClkInitStruct->APB2CLKDivider) > ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4)) + { + assert_param(IS_RCC_PCLK(pClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pClkInitStruct->APB2CLKDivider) << 4)); + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((pClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + if ((pClkInitStruct->APB1CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE1)) + { + assert_param(IS_RCC_PCLK(pClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pClkInitStruct->APB1CLKDivider); + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((pClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + if ((pClkInitStruct->AHBCLKDivider) > (RCC->CFGR2 & RCC_CFGR2_HPRE)) + { + assert_param(IS_RCC_HCLK(pClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pClkInitStruct->AHBCLKDivider); + } + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((pClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(pClkInitStruct->SYSCLKSource)); + + /* PLL is selected as System Clock Source */ + if (pClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U) + { + return HAL_ERROR; + } + } + else + { + /* HSE is selected as System Clock Source */ + if (pClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + return HAL_ERROR; + } + } + /* CSI is selected as System Clock Source */ + else if (pClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) + { + /* Check the CSI ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + return HAL_ERROR; + } + } + } + + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, pClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + if (pClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + if (pClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if (pClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_CSI) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + + /* Decreasing the BUS frequency divider */ + /*-------------------------- HCLK Configuration --------------------------*/ + if (((pClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + if ((pClkInitStruct->AHBCLKDivider) < (RCC->CFGR2 & RCC_CFGR2_HPRE)) + { + assert_param(IS_RCC_HCLK(pClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pClkInitStruct->AHBCLKDivider); + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((pClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + if ((pClkInitStruct->APB1CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE1)) + { + assert_param(IS_RCC_PCLK(pClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pClkInitStruct->APB1CLKDivider); + } + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((pClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + if ((pClkInitStruct->APB2CLKDivider) < ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4)) + { + assert_param(IS_RCC_PCLK(pClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pClkInitStruct->APB2CLKDivider) << 4)); + } + } + + /*-------------------------- PCLK3 Configuration ---------------------------*/ + if (((pClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3) + { + if ((pClkInitStruct->APB3CLKDivider) < ((RCC->CFGR2 & RCC_CFGR2_PPRE3) >> 8)) + { + assert_param(IS_RCC_PCLK(pClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE3, ((pClkInitStruct->APB3CLKDivider) << 8)); + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; + + /* Configure the source of time base considering new system clocks settings*/ + halstatus = HAL_InitTick(uwTickPrio); + + return halstatus; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to: + + (+) Output clock to MCO pin. + (+) Retrieve current clock frequencies. + (+) Enable the Clock Security System. + +@endverbatim + * @{ + */ + +/** + * @brief Select the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). + * @note PA8/PC9 should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * For STM32H5xx family this parameter can have only one value: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @arg @ref RCC_MCO2 Clock source to output on MCO2 pin(PC9). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLL1PCLK: PLL1P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_CSI: CSI clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_LSI: LSI clock selected as MCO2 source + * @param RCC_MCODiv specifies the MCO prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCOx clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + /* RCC_MCO1 */ + if (RCC_MCOx == RCC_MCO1) + { + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO1_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */ + MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO1SEL | RCC_CFGR1_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + } + else + { + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + + /* MCO2 Clock Enable */ + MCO2_CLK_ENABLE(); + + /* Configure the MCO2 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO2_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */ + MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO2SEL | RCC_CFGR1_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7U))); + } +} + +/** + * @brief Return the SYSCLK frequency. + * + * @note The system frequency computed by this function may not be the real + * frequency in the chip. It is calculated based on the predefined + * constants of the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on HSI_VALUE(*), CSI_VALUE(**) + * or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32h5xx_hal_conf.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) CSI_VALUE is a constant defined in stm32h5xx_hal_conf.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in stm32h5xx_hal_conf.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllsource; + uint32_t pllp; + uint32_t pllm; + uint32_t pllfracen; + uint32_t sysclockfreq; + uint32_t hsivalue; + float_t fracn1; + float_t pllvco; + + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_CSI) + { + /* CSI used as system clock source */ + sysclockfreq = CSI_VALUE; + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + { + /* HSI used as system clock source */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVF) != 0U) + { + sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + sysclockfreq = (uint32_t) HSI_VALUE; + } + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + { + /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + } + + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); + pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); + pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & \ + RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLL1_SOURCE_HSI: /* HSI used as PLL1 clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVF) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1); + } + else + { + pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1); + } + + break; + + case RCC_PLL1_SOURCE_HSE: /* HSE used as PLL1 clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1); + + break; + + case RCC_PLL1_SOURCE_CSI: /* CSI used as PLL1 clock source */ + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U) ; + sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); + } + else + { + sysclockfreq = 0; + } + } + + else + { + /* HSI is the default system clock source */ + sysclockfreq = (uint32_t) HSI_VALUE; + } + + return sysclockfreq; +} + +/** + * @brief Return the HCLK frequency. + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) \ + >> RCC_CFGR2_HPRE_Pos] & 0x1FU); + + return SystemCoreClock; +} + +/** + * @brief Return the PCLK1 frequency. + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> ((APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]) & 0x1FU)); +} + +/** + * @brief Return the PCLK2 frequency. + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> ((APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE2) >> RCC_CFGR2_PPRE2_Pos]) & 0x1FU)); +} + +/** + * @brief Return the PCLK3 frequency. + * @note Each time PCLK3 changes, this function must be called to update the + * right PCLK3 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK3 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK3Freq(void) +{ + /* Get HCLK source and Compute PCLK3 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> ((APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE3) >> RCC_CFGR2_PPRE3_Pos]) & 0x1FU)); +} +/** + * @brief Configure the pOscInitStruct according to the internal + * RCC configuration registers. + * @param pOscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pOscInitStruct) +{ + uint32_t regval; + uint32_t reg1val; + uint32_t reg2val; + + /* Check the parameters */ + assert_param(pOscInitStruct != (void *)NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ + pOscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; + + /* Get Control register */ + regval = RCC->CR; + + /* Get the HSE configuration -----------------------------------------------*/ + pOscInitStruct->HSEState = (regval & (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_HSEEXT)); + + /* Get the CSI configuration -----------------------------------------------*/ + pOscInitStruct->CSIState = regval & RCC_CR_CSION; + + /* Get the HSI configuration -----------------------------------------------*/ + pOscInitStruct->HSIState = regval & RCC_CR_HSION; + pOscInitStruct->HSIDiv = regval & RCC_CR_HSIDIV; + pOscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, \ + RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); + + /* Get BDCR register */ + regval = RCC->BDCR; + + /* Get the LSE configuration -----------------------------------------------*/ + pOscInitStruct->LSEState = (regval & (RCC_BDCR_LSEON | RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)); + + /* Get the LSI configuration -----------------------------------------------*/ + pOscInitStruct->LSIState = regval & RCC_BDCR_LSION; + + /* Get Control register */ + regval = RCC->CR; + + /* Get the HSI48 configuration ---------------------------------------------*/ + pOscInitStruct->HSI48State = regval & RCC_CR_HSI48ON; + + /* Get the PLL configuration -----------------------------------------------*/ + if ((regval & RCC_CR_PLL1ON) == RCC_CR_PLL1ON) + { + pOscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + pOscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + + /* Get PLL configuration register */ + reg1val = RCC->PLL1CFGR; + reg2val = RCC->PLL1DIVR; + + pOscInitStruct->PLL.PLLSource = (uint32_t)(reg1val & RCC_PLL1CFGR_PLL1SRC); + pOscInitStruct->PLL.PLLM = (uint32_t)((reg1val & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); + pOscInitStruct->PLL.PLLN = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1U); + pOscInitStruct->PLL.PLLQ = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U); + pOscInitStruct->PLL.PLLR = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); + pOscInitStruct->PLL.PLLP = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U); + pOscInitStruct->PLL.PLLRGE = (uint32_t)((reg1val & RCC_PLL1CFGR_PLL1RGE)); + pOscInitStruct->PLL.PLLVCOSEL = (uint32_t)((reg1val & RCC_PLL1CFGR_PLL1VCOSEL) >> RCC_PLL1CFGR_PLL1VCOSEL_Pos); + pOscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) \ + >> RCC_PLL1FRACR_PLL1FRACN_Pos)); +} + +/** + * @brief Configure the pClkInitStruct according to the internal + * RCC configuration registers. + * @param pClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pClkInitStruct, uint32_t *pFLatency) +{ + uint32_t regval; + + /* Check the parameters */ + assert_param(pClkInitStruct != (void *)NULL); + assert_param(pFLatency != (void *)NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + pClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | \ + RCC_CLOCKTYPE_PCLK3; + + /* Get the SYSCLK configuration --------------------------------------------*/ + pClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR1 & RCC_CFGR1_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + regval = RCC->CFGR2; + pClkInitStruct->AHBCLKDivider = (uint32_t)(regval & RCC_CFGR2_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + pClkInitStruct->APB1CLKDivider = (uint32_t)(regval & RCC_CFGR2_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + pClkInitStruct->APB2CLKDivider = (uint32_t)((regval & RCC_CFGR2_PPRE2) >> 4); + + /* Get the APB3 configuration ----------------------------------------------*/ + pClkInitStruct->APB3CLKDivider = (uint32_t)((regval & RCC_CFGR2_PPRE3) >> 8); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief Get and clear reset flags + * @note Once reset flags are retrieved, this API is clearing them in order + * to isolate next reset reason. + * @retval can be a combination of @ref RCC_Reset_Flag + */ +uint32_t HAL_RCC_GetResetSource(void) +{ + uint32_t reset; + + /* Get all reset flags */ + reset = RCC->RSR & RCC_RESET_FLAG_ALL; + + /* Clear Reset flags */ + RCC->RSR |= RCC_RSR_RMVF; + + return reset; +} + +/** + * @brief Enable the HSE Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M NMI (Non-Maskable Interrupt) exception vector. + * @note The Clock Security System can only be cleared by reset. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSECSSON); +} + +/** + * @brief Handle the RCC Clock Security System interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF interrupt flag */ + if (__HAL_RCC_GET_IT(RCC_IT_HSECSS)) + { + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_HSECSS); + + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + } +} + +/** + * @brief RCC HSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group3 Attributes management functions + * @brief Attributes management functions. + * +@verbatim + =============================================================================== + ##### RCC attributes functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to: + + (+) Configure the RCC item(s) attributes. + (+) Get the attribute of an RCC item. + +@endverbatim + * @{ + */ +/** + * @brief Configure the RCC item(s) attribute(s). + * @note Available attributes are to secure items and set RCC as privileged (*). + * Default state is non-secure and unprivileged access allowed. + * @note Secure and non-secure attributes can only be set from the secure + * state when the system implements the security (TZEN=1). + * @note As the privileged attributes concern either all secure or all non-secure + * RCC resources accesses and not each RCC individual items access attribute, + * the application must ensure that the privilege access attribute configurations + * are coherent amongst the security level set on RCC individual items + * so not to overwrite a previous more restricted access rule (consider either + * all secure and/or all non-secure RCC resources accesses by privileged-only + * transactions or privileged and unprivileged transactions). + * @param Item Item(s) to set attributes on. + * This parameter can be a one or a combination of @ref RCC_items (**). + * @param Attributes specifies the RCC secure/privilege attributes. + * This parameter can be a value of @ref RCC_attributes + * @retval None + * + * (*) : For stm32h503xx devices, attributes specifies the privilege attribute only (no items). + * (**) : For stm32h503xx devices, this parameter is unused, it can take 0 or any other numerical value. + */ +void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes) +{ + + /* Check the parameters */ + assert_param(IS_RCC_ATTRIBUTES(Attributes)); + +#if defined(RCC_SECCFGR_HSISEC) + assert_param(IS_RCC_ITEM_ATTRIBUTES(Item)); + + switch (Attributes) + { +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Secure Privilege attribute */ + case RCC_SEC_PRIV: + SET_BIT(RCC->SECCFGR, Item); + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); + break; + /* Secure Non-Privilege attribute */ + case RCC_SEC_NPRIV: + SET_BIT(RCC->SECCFGR, Item); + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); + break; + /* Non-secure Privilege attribute */ + case RCC_NSEC_PRIV: + CLEAR_BIT(RCC->SECCFGR, Item); + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + break; + /* Non-secure Non-Privilege attribute */ + case RCC_NSEC_NPRIV: + CLEAR_BIT(RCC->SECCFGR, Item); + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + break; +#else /* __ARM_FEATURE_CMSE */ + /* Non-secure Privilege attribute */ + case RCC_NSEC_PRIV: + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + break; + /* Non-secure Non-Privilege attribute */ + case RCC_NSEC_NPRIV: + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + break; +#endif /* __ARM_FEATURE_CMSE */ + default: + /* Nothing to do */ + break; + } + +#else /* RCC_SECCFGR_HSISEC */ + + UNUSED(Item); + + switch (Attributes) + { + /* Privilege attribute */ + case RCC_PRIV: + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_PRIV); + break; + /* Non-secure Non-Privilege attribute */ + case RCC_NPRIV: + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_PRIV); + break; + default: + /* Nothing to do */ + break; + } + +#endif /* RCC_SECCFGR_HSISEC */ +} + +/** + * @brief Get the attribute of an RCC item. + * @note Secure and non-secure attributes are only available from secure state + * when the system implements the security (TZEN=1) + * @param Item Single item to get secure/non-secure and privilege/non-privilege attribute from. + * This parameter can be a one value of @ref RCC_items except RCC_ALL. (*) + * @param pAttributes pointer to return the attributes. + * @retval HAL Status. + * + * (*) : This parameter is unused for stm32h503xx devices, it can take 0 or any other numerical value. + */ +HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) +{ + uint32_t attributes; + + /* Check null pointer */ + if (pAttributes == NULL) + { + return HAL_ERROR; + } + +#if defined(RCC_SECCFGR_HSISEC) + /* Check the parameters */ + assert_param(IS_RCC_SINGLE_ITEM_ATTRIBUTES(Item)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + + /* Check item security */ + if ((RCC->SECCFGR & Item) == Item) + { + /* Get Secure privileges attribute */ + attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_SPRIV) == 0U) ? RCC_SEC_NPRIV : RCC_SEC_PRIV; + } + else + { + /* Get Non-Secure privileges attribute */ + attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV; + } +#else /* __ARM_FEATURE_CMSE */ + attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV; +#endif /* __ARM_FEATURE_CMSE */ + +#else /* RCC_SECCFGR_HSISEC */ + UNUSED(Item); + /* Get privileges attribute */ + attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_PRIV) == 0U) ? RCC_NPRIV : RCC_PRIV; +#endif /* RCC_SECCFGR_HSISEC */ + + /* return value */ + *pAttributes = attributes; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c new file mode 100644 index 00000000..a963b2a9 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c @@ -0,0 +1,7331 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extended peripheral: + * + Extended Peripheral Control functions + * + Extended Clock management functions + * + Extended Clock Recovery System Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC Extended HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +#define PLL1_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#define PLL2_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#if defined(RCC_CR_PLL3ON) +#define PLL3_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#endif /* RCC_CR_PLL3ON */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCCEx_Private_Functions RCCEx Private Functions + * @{ + */ +static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource); +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *Pll2); +#if defined(RCC_CR_PLL3ON) +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *Pll3); +#endif /* RCC_CR_PLL3ON */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) are set to their reset values. + +@endverbatim + * @{ + */ +/** + * @brief Initialize the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains a field PeriphClockSelection which can be a combination of the following values: + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_UART7 UART7 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_UART8 UART8 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_UART9 UART9 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_USART10 USART10 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_USART11 USART11 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_UART12 UART12 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_I3C1 I3C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I3C2 I3C2 peripheral clock (***) + * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock + * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_ADCDAC ADCDAC peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_SDMMC2 SDMMC2 peripheral clock (**) + * @arg @ref RCC_PERIPHCLK_CKPER CKPER peripheral clock + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI4 SPI4 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_SPI5 SPI5 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_SPI6 SPI6 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_OSPI OCTOSPI peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (*****) + * @arg @ref RCC_PERIPHCLK_LPTIM3 LPTIM3 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPTIM4 LPTIM4 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPTIM5 LPTIM5 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPTIM6 LPTIM6 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_DAC_LP DAC peripheral low-power clock + * @arg @ref RCC_PERIPHCLK_TIM TIM peripheral clock + * @arg @ref RCC_PERIPHCLK_PLAY1 PLAY1 peripheral clock (****) + * @arg @ref RCC_PERIPHCLK_OTGFS USB_OTG_FS peripheral clock (****) + * @arg @ref RCC_PERIPHCLK_OTGHS USB_OTG_HS peripheral clock (****) + * @arg @ref RCC_PERIPHCLK_OSPI2 OCTOSPI2 peripheral clock (****) + * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (****) + * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock (****) + * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock (****) + * @arg @ref RCC_PERIPHCLK_ETH ETH peripheral clock + * @arg @ref RCC_PERIPHCLK_ETHPTP ETHPTP peripheral clock (****) + * @arg @ref RCC_PERIPHCLK_ETHREF ETHREF peripheral clock (****) + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source: in this case the access to Backup domain is enabled. + * + * @retval HAL status + * + * (*) : For stm32h56xxx and stm32h57xxx family lines only. + * (**) : For stm32h563xx and stm32h57xxx family lines only. + * (***) : For stm32h503xx family line only. + * (****) : For stm32h5exxx and stm32h5fxxx family lines only. + * (*****) : Not available for stm32h5exxx and stm32h5fxxx family lines. + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit) +{ + uint32_t tmpregister; + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(pPeriphClkInit->PeriphClockSelection)); + + /*------------------------------------ CKPER configuration --------------------------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) + { + /* Check the parameters */ + assert_param(IS_RCC_CLKPSOURCE(pPeriphClkInit->CkperClockSelection)); + + /* Configure the CKPER clock source */ + __HAL_RCC_CLKP_CONFIG(pPeriphClkInit->CkperClockSelection); + } + + /*-------------------------- USART1 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(pPeriphClkInit->Usart1ClockSelection)); + + switch (pPeriphClkInit->Usart1ClockSelection) + { + case RCC_USART1CLKSOURCE_PCLK2: /* PCLK2 is used as clock source for USART1*/ + + /* USART1 clock source config set later after clock selection check */ + break; + + case RCC_USART1CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART1*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* USART1 clock source config set later after clock selection check */ + break; +#if defined(RCC_USART1CLKSOURCE_PLL3Q) + case RCC_USART1CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART1*/ + /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* USART1 clock source config set later after clock selection check */ + break; +#endif /* RCC_USART1CLKSOURCE_PLL3Q */ + + case RCC_USART1CLKSOURCE_HSI: /* HSI clock is used as source of USART1 clock*/ + /* USART1 clock source config set later after clock selection check */ + break; + + case RCC_USART1CLKSOURCE_CSI: /* CSI clock is used as source of USART1 clock*/ + /* USART1 clock source config set later after clock selection check */ + break; + + case RCC_USART1CLKSOURCE_LSE: /* LSE clock is used as source of USART1 clock*/ + /* USART1 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART1 clock*/ + __HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- USART2 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(pPeriphClkInit->Usart2ClockSelection)); + + switch (pPeriphClkInit->Usart2ClockSelection) + { + case RCC_USART2CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART2*/ + + /* USART2 clock source config set later after clock selection check */ + break; + + case RCC_USART2CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART2*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* USART2 clock source config set later after clock selection check */ + break; + +#if defined(RCC_USART2CLKSOURCE_PLL3Q) + case RCC_USART2CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART2*/ + /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* USART2 clock source config set later after clock selection check */ + break; +#endif /* RCC_USART2CLKSOURCE_PLL3 */ + + case RCC_USART2CLKSOURCE_HSI: /* HSI clock is used as source of USART2 clock*/ + /* USART2 clock source config set later after clock selection check */ + break; + + case RCC_USART2CLKSOURCE_CSI: /* CSI clock is used as source of USART2 clock*/ + /* USART2 clock source config set later after clock selection check */ + break; + + case RCC_USART2CLKSOURCE_LSE: /* LSE clock is used as source of USART2 clock*/ + /* USART2 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART2 clock*/ + __HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- USART3 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(pPeriphClkInit->Usart3ClockSelection)); + + switch (pPeriphClkInit->Usart3ClockSelection) + { + case RCC_USART3CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART3*/ + + /* USART3 clock source config set later after clock selection check */ + break; + + case RCC_USART3CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART3*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* USART3 clock source config set later after clock selection check */ + break; + +#if defined(RCC_USART3CLKSOURCE_PLL3Q) + case RCC_USART3CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART3*/ + /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* USART3 clock source config set later after clock selection check */ + break; +#endif /* RCC_USART3CLKSOURCE_PLL3Q */ + + case RCC_USART3CLKSOURCE_HSI: /* HSI clock is used as source of USART3 clock*/ + /* USART3 clock source config set later after clock selection check */ + break; + + case RCC_USART3CLKSOURCE_CSI: /* CSI clock is used as source of USART3 clock*/ + /* USART3 clock source config set later after clock selection check */ + break; + + case RCC_USART3CLKSOURCE_LSE: /* LSE clock is used as source of USART3 clock*/ + /* USART3 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART3 clock*/ + __HAL_RCC_USART3_CONFIG(pPeriphClkInit->Usart3ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(UART4) + /*-------------------------- UART4 clock source configuration --------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(pPeriphClkInit->Uart4ClockSelection)); + + switch (pPeriphClkInit->Uart4ClockSelection) + { + case RCC_UART4CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART4*/ + + /* UART4 clock source config set later after clock selection check */ + break; + + case RCC_UART4CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART4*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* UART4 clock source config set later after clock selection check */ + break; +#if defined(RCC_UART4CLKSOURCE_PLL3Q) + case RCC_UART4CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART4*/ + /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* UART4 clock source config set later after clock selection check */ + break; +#endif /* RCC_UART4CLKSOURCE_PLL3Q */ + case RCC_UART4CLKSOURCE_HSI: /* HSI clock is used as source of UART4 clock*/ + /* UART4 clock source config set later after clock selection check */ + break; + + case RCC_UART4CLKSOURCE_CSI: /* CSI clock is used as source of UART4 clock*/ + /* UART4 clock source config set later after clock selection check */ + break; + + case RCC_UART4CLKSOURCE_LSE: /* LSE clock is used as source of UART4 clock*/ + /* UART4 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of UART4 clock*/ + __HAL_RCC_UART4_CONFIG(pPeriphClkInit->Uart4ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* UART4 */ + +#if defined(UART5) + /*-------------------------- UART5 clock source configuration --------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(pPeriphClkInit->Uart5ClockSelection)); + + switch (pPeriphClkInit->Uart5ClockSelection) + { + case RCC_UART5CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART5*/ + + /* UART5 clock source config set later after clock selection check */ + break; + + case RCC_UART5CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART5*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* UART5 clock source config set later after clock selection check */ + break; +#if defined(RCC_UART5CLKSOURCE_PLL3Q) + case RCC_UART5CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART5*/ + /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* UART5 clock source config set later after clock selection check */ + break; +#endif /* RCC_UART5CLKSOURCE_PLL3Q */ + case RCC_UART5CLKSOURCE_HSI: /* HSI clock is used as source of UART5 clock*/ + /* UART5 clock source config set later after clock selection check */ + break; + + case RCC_UART5CLKSOURCE_CSI: /* CSI clock is used as source of UART5 clock*/ + /* UART5 clock source config set later after clock selection check */ + break; + + case RCC_UART5CLKSOURCE_LSE: /* LSE clock is used as source of UART5 clock*/ + /* UART5 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of UART5 clock*/ + __HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* UART5 */ + +#if defined(USART6) + /*-------------------------- USART6 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(pPeriphClkInit->Usart6ClockSelection)); + + switch (pPeriphClkInit->Usart6ClockSelection) + { + case RCC_USART6CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART6*/ + + /* USART6 clock source config set later after clock selection check */ + break; + + case RCC_USART6CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART6*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* USART6 clock source config set later after clock selection check */ + break; +#if defined(RCC_USART6CLKSOURCE_PLL3Q) + case RCC_USART6CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART6*/ + /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* USART6 clock source config set later after clock selection check */ + break; +#endif /* RCC_USART6CLKSOURCE_PLL3Q */ + case RCC_USART6CLKSOURCE_HSI: /* HSI clock is used as source of USART6 clock*/ + /* USART6 clock source config set later after clock selection check */ + break; + + case RCC_USART6CLKSOURCE_CSI: /* CSI clock is used as source of USART6 clock*/ + /* USART6 clock source config set later after clock selection check */ + break; + + case RCC_USART6CLKSOURCE_LSE: /* LSE clock is used as source of USART6 clock*/ + /* USART6 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART6 clock*/ + __HAL_RCC_USART6_CONFIG(pPeriphClkInit->Usart6ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* USART6 */ + +#if defined(UART7) + /*-------------------------- UART7 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(pPeriphClkInit->Uart7ClockSelection)); + + switch (pPeriphClkInit->Uart7ClockSelection) + { + case RCC_UART7CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART7*/ + + /* UART7 clock source config set later after clock selection check */ + break; + + case RCC_UART7CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART7*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* UART7 clock source config set later after clock selection check */ + break; +#if defined(RCC_UART7CLKSOURCE_PLL3Q) + case RCC_UART7CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART7*/ + /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* UART7 clock source config set later after clock selection check */ + break; +#endif /* RCC_UART7CLKSOURCE_PLL3Q */ + case RCC_UART7CLKSOURCE_HSI: /* HSI clock is used as source of UART7 clock*/ + /* UART7 clock source config set later after clock selection check */ + break; + + case RCC_UART7CLKSOURCE_CSI: /* CSI clock is used as source of UART7 clock*/ + /* UART7 clock source config set later after clock selection check */ + break; + + case RCC_UART7CLKSOURCE_LSE: /* LSE clock is used as source of UART7 clock*/ + /* UART7 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of UART7 clock*/ + __HAL_RCC_UART7_CONFIG(pPeriphClkInit->Uart7ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* UART7 */ + +#if defined(UART8) + /*-------------------------- UART8 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(pPeriphClkInit->Uart8ClockSelection)); + + switch (pPeriphClkInit->Uart8ClockSelection) + { + case RCC_UART8CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART8*/ + + /* UART8 clock source config set later after clock selection check */ + break; + + case RCC_UART8CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART8*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* UART8 clock source config set later after clock selection check */ + break; +#if defined(RCC_UART8CLKSOURCE_PLL3Q) + case RCC_UART8CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART8*/ + /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* UART8 clock source config set later after clock selection check */ + break; +#endif /* RCC_UART8CLKSOURCE_PLL3Q */ + case RCC_UART8CLKSOURCE_HSI: /* HSI clock is used as source of UART8 clock*/ + /* UART8 clock source config set later after clock selection check */ + break; + + case RCC_UART8CLKSOURCE_CSI: /* CSI clock is used as source of UART8 clock*/ + /* UART8 clock source config set later after clock selection check */ + break; + + case RCC_UART8CLKSOURCE_LSE: /* LSE clock is used as source of UART8 clock*/ + /* UART8 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of UART8 clock*/ + __HAL_RCC_UART8_CONFIG(pPeriphClkInit->Uart8ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* UART9 */ + +#if defined(UART9) + /*-------------------------- UART9 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART9) == RCC_PERIPHCLK_UART9) + { + /* Check the parameters */ + assert_param(IS_RCC_UART9CLKSOURCE(pPeriphClkInit->Uart9ClockSelection)); + + switch (pPeriphClkInit->Uart9ClockSelection) + { + case RCC_UART9CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART9*/ + + /* UART9 clock source config set later after clock selection check */ + break; + + case RCC_UART9CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART9*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* UART9 clock source config set later after clock selection check */ + break; + case RCC_UART9CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART9*/ + /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* UART9 clock source config set later after clock selection check */ + break; + case RCC_UART9CLKSOURCE_HSI: /* HSI clock is used as source of UART9 clock*/ + /* UART9 clock source config set later after clock selection check */ + break; + + case RCC_UART9CLKSOURCE_CSI: /* CSI clock is used as source of UART9 clock*/ + /* UART9 clock source config set later after clock selection check */ + break; + + case RCC_UART9CLKSOURCE_LSE: /* LSE clock is used as source of UART9 clock*/ + /* UART9 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of UART9 clock*/ + __HAL_RCC_UART9_CONFIG(pPeriphClkInit->Uart9ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* UART9 */ + +#if defined(USART10) + /*-------------------------- USART10 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART10) == RCC_PERIPHCLK_USART10) + { + /* Check the parameters */ + assert_param(IS_RCC_USART10CLKSOURCE(pPeriphClkInit->Usart10ClockSelection)); + + switch (pPeriphClkInit->Usart10ClockSelection) + { + case RCC_USART10CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART10*/ + + /* USART10 clock source config set later after clock selection check */ + break; + + case RCC_USART10CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART10*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* USART10 clock source config set later after clock selection check */ + break; + case RCC_USART10CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART10*/ + /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* USART10 clock source config set later after clock selection check */ + break; + case RCC_USART10CLKSOURCE_HSI: /* HSI clock is used as source of USART10 clock*/ + /* USART10 clock source config set later after clock selection check */ + break; + + case RCC_USART10CLKSOURCE_CSI: /* CSI clock is used as source of USART10 clock*/ + /* USART10 clock source config set later after clock selection check */ + break; + + case RCC_USART10CLKSOURCE_LSE: /* LSE clock is used as source of USART10 clock*/ + /* USART10 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART10 clock*/ + __HAL_RCC_USART10_CONFIG(pPeriphClkInit->Usart10ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* USART10 */ + +#if defined(USART11) + /*-------------------------- USART11 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART11) == RCC_PERIPHCLK_USART11) + { + /* Check the parameters */ + assert_param(IS_RCC_USART11CLKSOURCE(pPeriphClkInit->Usart11ClockSelection)); + + switch (pPeriphClkInit->Usart11ClockSelection) + { + case RCC_USART11CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART11*/ + + /* USART11 clock source config set later after clock selection check */ + break; + + case RCC_USART11CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART11*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* USART11 clock source config set later after clock selection check */ + break; + case RCC_USART11CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART11*/ + /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* USART11 clock source config set later after clock selection check */ + break; + case RCC_USART11CLKSOURCE_HSI: /* HSI clock is used as source of USART11 clock*/ + /* USART11 clock source config set later after clock selection check */ + break; + + case RCC_USART11CLKSOURCE_CSI: /* CSI clock is used as source of USART11 clock*/ + /* USART11 clock source config set later after clock selection check */ + break; + + case RCC_USART11CLKSOURCE_LSE: /* LSE clock is used as source of USART11 clock*/ + /* USART11 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART11 clock*/ + __HAL_RCC_USART11_CONFIG(pPeriphClkInit->Usart11ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*USART11*/ + +#if defined(UART12) + /*-------------------------- UART12 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART12) == RCC_PERIPHCLK_UART12) + { + /* Check the parameters */ + assert_param(IS_RCC_UART12CLKSOURCE(pPeriphClkInit->Uart12ClockSelection)); + + switch (pPeriphClkInit->Uart12ClockSelection) + { + case RCC_UART12CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART12*/ + + /* UART12 clock source config set later after clock selection check */ + break; + + case RCC_UART12CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART12*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* UART12 clock source config set later after clock selection check */ + break; + case RCC_UART12CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART12*/ + /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* UART12 clock source config set later after clock selection check */ + break; + case RCC_UART12CLKSOURCE_HSI: /* HSI clock is used as source of UART12 clock*/ + /* UART12 clock source config set later after clock selection check */ + break; + + case RCC_UART12CLKSOURCE_CSI: /* CSI clock is used as source of UART12 clock*/ + /* UART12 clock source config set later after clock selection check */ + break; + + case RCC_UART12CLKSOURCE_LSE: /* LSE clock is used as source of UART12 clock*/ + /* UART12 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of UART12 clock*/ + __HAL_RCC_UART12_CONFIG(pPeriphClkInit->Uart12ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* UART12 */ + + /*-------------------------- LPUART1 clock source configuration ------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(pPeriphClkInit->Lpuart1ClockSelection)); + + switch (pPeriphClkInit->Lpuart1ClockSelection) + { + case RCC_LPUART1CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPUART1*/ + + /* LPUART1 clock source config set later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for LPUART1*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* LPUART1 clock source config set later after clock selection check */ + break; + +#if defined(RCC_LPUART1CLKSOURCE_PLL3Q) + case RCC_LPUART1CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for LPUART1*/ + /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* LPUART1 clock source config set later after clock selection check */ + break; +#endif /* RCC_LPUART1CLKSOURCE_PLL3Q */ + + case RCC_LPUART1CLKSOURCE_HSI: /* HSI clock is used as source of LPUART1 clock*/ + /* LPUART1 clock source config set later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_CSI: /* CSI clock is used as source of LPUART1 clock*/ + /* LPUART1 clock source config set later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_LSE: /* LSE clock is used as source of LPUART1 clock*/ + /* LPUART1 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPUART1 clock*/ + __HAL_RCC_LPUART1_CONFIG(pPeriphClkInit->Lpuart1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- I2C1 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(pPeriphClkInit->I2c1ClockSelection)); + + switch (pPeriphClkInit->I2c1ClockSelection) + { + case RCC_I2C1CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I2C1*/ + + /* I2C1 clock source config set later after clock selection check */ + break; + +#if defined(RCC_I2C1CLKSOURCE_PLL3R) + case RCC_I2C1CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C1*/ + /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); +#else + case RCC_I2C1CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I2C1*/ + /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); +#endif /* RCC_I2C1CLKSOURCE_PLL3R */ + /* I2C1 clock source config set later after clock selection check */ + break; + + + case RCC_I2C1CLKSOURCE_HSI: /* HSI clock is used as source of I2C1 clock*/ + /* I2C1 clock source config set later after clock selection check */ + break; + + case RCC_I2C1CLKSOURCE_CSI: /* CSI clock is used as source of I2C1 clock*/ + /* I2C1 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of I2C1 clock*/ + __HAL_RCC_I2C1_CONFIG(pPeriphClkInit->I2c1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- I2C2 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(pPeriphClkInit->I2c2ClockSelection)); + + switch (pPeriphClkInit->I2c2ClockSelection) + { + case RCC_I2C2CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I2C2*/ + + /* I2C2 clock source config set later after clock selection check */ + break; + +#if defined(RCC_I2C2CLKSOURCE_PLL3R) + case RCC_I2C2CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C2*/ + /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); +#else + case RCC_I2C2CLKSOURCE_PLL2R: /* PLL32 is used as clock source for I2C2*/ + /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); +#endif /* RCC_I2C2CLKSOURCE_PLL3R */ + /* I2C2 clock source config set later after clock selection check */ + break; + + case RCC_I2C2CLKSOURCE_HSI: /* HSI clock is used as source of I2C2 clock*/ + /* I2C2 clock source config set later after clock selection check */ + break; + + case RCC_I2C2CLKSOURCE_CSI: /* CSI clock is used as source of I2C2 clock*/ + /* I2C2 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of I2C2 clock*/ + __HAL_RCC_I2C2_CONFIG(pPeriphClkInit->I2c2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(I2C3) + /*-------------------------- I2C3 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(pPeriphClkInit->I2c3ClockSelection)); + + switch (pPeriphClkInit->I2c3ClockSelection) + { + case RCC_I2C3CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for I2C3*/ + + /* I2C3 clock source config set later after clock selection check */ + break; +#if defined(RCC_I2C3CLKSOURCE_PLL3R) + case RCC_I2C3CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C3*/ + /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* I2C3 clock source config set later after clock selection check */ + break; +#else + case RCC_I2C3CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I2C3*/ + /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* I2C3 clock source config set later after clock selection check */ + break; +#endif /* RCC_I2C3CLKSOURCE_PLL3R */ + case RCC_I2C3CLKSOURCE_HSI: /* HSI clock is used as source of I2C3 clock*/ + /* I2C3 clock source config set later after clock selection check */ + break; + + case RCC_I2C3CLKSOURCE_CSI: /* CSI clock is used as source of I2C3 clock*/ + /* I2C3 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of I2C3 clock*/ + __HAL_RCC_I2C3_CONFIG(pPeriphClkInit->I2c3ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* I2C3 */ + +#if defined(I2C4) + /*-------------------------- I2C4 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(pPeriphClkInit->I2c4ClockSelection)); + + switch (pPeriphClkInit->I2c4ClockSelection) + { + case RCC_I2C4CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for I2C4*/ + + /* I2C4 clock source config set later after clock selection check */ + break; + case RCC_I2C4CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C4*/ + /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* I2C4 clock source config set later after clock selection check */ + break; + case RCC_I2C4CLKSOURCE_HSI: /* HSI clock is used as source of I2C4 clock*/ + /* I2C4 clock source config set later after clock selection check */ + break; + + case RCC_I2C4CLKSOURCE_CSI: /* CSI clock is used as source of I2C4 clock*/ + /* I2C4 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of I2C4 clock*/ + __HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* I2C4 */ + + /*-------------------------- I3C1 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I3C1) == RCC_PERIPHCLK_I3C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I3C1CLKSOURCE(pPeriphClkInit->I3c1ClockSelection)); + + switch (pPeriphClkInit->I3c1ClockSelection) + { + case RCC_I3C1CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I3C1*/ + + /* I3C1 clock source config set later after clock selection check */ + break; + +#if defined(RCC_I3C1CLKSOURCE_PLL3R) + case RCC_I3C1CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I3C1*/ + /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); +#else + case RCC_I3C1CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I3C1*/ + /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); +#endif /* RCC_I3C1CLKSOURCE_PLL3R */ + /* I3C1 clock source config set later after clock selection check */ + break; + + case RCC_I3C1CLKSOURCE_HSI: /* HSI clock is used as source of I3C1 clock*/ + /* I3C1 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of I3C1 clock*/ + __HAL_RCC_I3C1_CONFIG(pPeriphClkInit->I3c1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined (I3C2) + /*-------------------------- I3C2 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I3C2) == RCC_PERIPHCLK_I3C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I3C2CLKSOURCE(pPeriphClkInit->I3c2ClockSelection)); + + switch (pPeriphClkInit->I3c2ClockSelection) + { + case RCC_I3C2CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for I3C2*/ + + /* I3C2 clock source config set later after clock selection check */ + break; + +#if defined(RCC_I3C2CLKSOURCE_PLL3R) + case RCC_I3C2CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I3C2*/ + /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); +#else + case RCC_I3C2CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I3C2*/ + /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); +#endif /* RCC_I3C2CLKSOURCE_PLL3R */ + /* I3C2 clock source config set later after clock selection check */ + break; + + case RCC_I3C2CLKSOURCE_HSI: /* HSI clock is used as source of I3C2 clock*/ + /* I3C2 clock source config set later after clock selection check */ + break; + +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) + case RCC_I3C2CLKSOURCE_CSI: /* CSI clock is used as source of I3C2 clock*/ + /* I3C2 clock source config set later after clock selection check */ + break; +#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */ + + default: + ret = HAL_ERROR; + break; + } + if (ret == HAL_OK) + { + /* Set the source of I3C2 clock*/ + __HAL_RCC_I3C2_CONFIG(pPeriphClkInit->I3c2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* I3C2 */ + + /*------------------------------------ TIM configuration --------------------------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(pPeriphClkInit->TimPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(pPeriphClkInit->TimPresSelection); + } + + /*-------------------------- LPTIM1 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLK(pPeriphClkInit->Lptim1ClockSelection)); + + switch (pPeriphClkInit->Lptim1ClockSelection) + { + case RCC_LPTIM1CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM1*/ + + /* LPTIM1 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM1*/ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* LPTIM1 clock source config set later after clock selection check */ + break; + +#if defined(RCC_LPTIM1CLKSOURCE_PLL3R) + case RCC_LPTIM1CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM1*/ + /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* LPTIM1 clock source config set later after clock selection check */ + break; +#endif /* RCC_LPTIM1CLKSOURCE_PLL3R */ + + case RCC_LPTIM1CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM1 clock*/ + /* LPTIM1 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM1 clock*/ + /* LPTIM1 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM1 clock*/ + /* LPTIM1 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM1 clock*/ + __HAL_RCC_LPTIM1_CONFIG(pPeriphClkInit->Lptim1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- LPTIM2 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM2CLK(pPeriphClkInit->Lptim2ClockSelection)); + + switch (pPeriphClkInit->Lptim2ClockSelection) + { + case RCC_LPTIM2CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for LPTIM2*/ + + /* LPTIM2 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM2*/ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* LPTIM2 clock source config set later after clock selection check */ + break; + +#if defined(RCC_LPTIM2CLKSOURCE_PLL3R) + case RCC_LPTIM2CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM2*/ + /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* LPTIM2 clock source config set later after clock selection check */ + break; +#endif /* RCC_LPTIM2CLKSOURCE_PLL3R */ + + case RCC_LPTIM2CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM2 clock*/ + /* LPTIM2 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM2 clock*/ + /* LPTIM2 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM2 clock*/ + /* LPTIM2 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM2 clock*/ + __HAL_RCC_LPTIM2_CONFIG(pPeriphClkInit->Lptim2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(LPTIM3) + /*-------------------------- LPTIM3 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM3CLK(pPeriphClkInit->Lptim3ClockSelection)); + + switch (pPeriphClkInit->Lptim3ClockSelection) + { + case RCC_LPTIM3CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM3*/ + + /* LPTIM3 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM3CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM3*/ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* LPTIM3 clock source config set later after clock selection check */ + break; + case RCC_LPTIM3CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM3*/ + /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* LPTIM3 clock source config set later after clock selection check */ + break; + case RCC_LPTIM3CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM3 clock*/ + /* LPTIM3 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM3CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM3 clock*/ + /* LPTIM3 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM3CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM3 clock*/ + /* LPTIM3 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM3 clock*/ + __HAL_RCC_LPTIM3_CONFIG(pPeriphClkInit->Lptim3ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* LPTIM3 */ + +#if defined(LPTIM4) + /*-------------------------- LPTIM4 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM4) == RCC_PERIPHCLK_LPTIM4) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM4CLK(pPeriphClkInit->Lptim4ClockSelection)); + + switch (pPeriphClkInit->Lptim4ClockSelection) + { + case RCC_LPTIM4CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM4*/ + + /* LPTIM4 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM4CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM4*/ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* LPTIM4 clock source config set later after clock selection check */ + break; + case RCC_LPTIM4CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM4*/ + /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* LPTIM4 clock source config set later after clock selection check */ + break; + case RCC_LPTIM4CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM4 clock*/ + /* LPTIM4 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM4CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM4 clock*/ + /* LPTIM4 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM4CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM4 clock*/ + /* LPTIM4 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM4 clock*/ + __HAL_RCC_LPTIM4_CONFIG(pPeriphClkInit->Lptim4ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* LPTIM4 */ + +#if defined(LPTIM5) + /*-------------------------- LPTIM5 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM5) == RCC_PERIPHCLK_LPTIM5) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM5CLK(pPeriphClkInit->Lptim5ClockSelection)); + + switch (pPeriphClkInit->Lptim5ClockSelection) + { + case RCC_LPTIM5CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM5*/ + + /* LPTIM5 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM5CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM5*/ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* LPTIM5 clock source config set later after clock selection check */ + break; + case RCC_LPTIM5CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM5*/ + /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* LPTIM5 clock source config set later after clock selection check */ + break; + case RCC_LPTIM5CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM5 clock*/ + /* LPTIM5 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM5CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM5 clock*/ + /* LPTIM5 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM5CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM5 clock*/ + /* LPTIM5 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM5 clock*/ + __HAL_RCC_LPTIM5_CONFIG(pPeriphClkInit->Lptim5ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* LPTIM5 */ + +#if defined(LPTIM6) + /*-------------------------- LPTIM6 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM6) == RCC_PERIPHCLK_LPTIM6) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM6CLK(pPeriphClkInit->Lptim6ClockSelection)); + + switch (pPeriphClkInit->Lptim6ClockSelection) + { + case RCC_LPTIM6CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM6*/ + + /* LPTIM6 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM6CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM6*/ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* LPTIM6 clock source config set later after clock selection check */ + break; + case RCC_LPTIM6CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM6*/ + /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* LPTIM6 clock source config set later after clock selection check */ + break; + case RCC_LPTIM6CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM6 clock*/ + /* LPTIM6 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM6CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM6 clock*/ + /* LPTIM6 clock source config set later after clock selection check */ + break; + + case RCC_LPTIM6CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM6 clock*/ + /* LPTIM6 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM6 clock*/ + __HAL_RCC_LPTIM6_CONFIG(pPeriphClkInit->Lptim6ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* LPTIM6 */ + +#if defined(SAI1) + /*-------------------------- SAI1 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLK(pPeriphClkInit->Sai1ClockSelection)); + + switch (pPeriphClkInit->Sai1ClockSelection) + { + case RCC_SAI1CLKSOURCE_PLL1Q: /* PLL is used as clock source for SAI1*/ + /* Enable SAI Clock output generated from System PLL . */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* SAI1 clock source config set later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SAI1*/ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* SAI1 clock source config set later after clock selection check */ + break; + case RCC_SAI1CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SAI1*/ + /* PLL3 P input clock, parameters M, N & P configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* SAI1 clock source config set later after clock selection check */ + break; + case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/ + break; + + case RCC_SAI1CLKSOURCE_CLKP: /* CLKP is used as source of SAI1 clock*/ + /* SAI1 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI1 clock*/ + __HAL_RCC_SAI1_CONFIG(pPeriphClkInit->Sai1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* SAI1*/ + +#if defined(SAI2) + /*-------------------------- SAI2 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLK(pPeriphClkInit->Sai2ClockSelection)); + + switch (pPeriphClkInit->Sai2ClockSelection) + { + case RCC_SAI2CLKSOURCE_PLL1Q: /* PLL is used as clock source for SAI2*/ + /* Enable SAI Clock output generated from System PLL . */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* SAI2 clock source config set later after clock selection check */ + break; + + case RCC_SAI2CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SAI2*/ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* SAI2 clock source config set later after clock selection check */ + break; + case RCC_SAI2CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SAI2*/ + /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* SAI2 clock source config set later after clock selection check */ + break; + case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/ + case RCC_SAI2CLKSOURCE_CLKP: /* CLKP is used as source of SAI2 clock*/ + /* SAI2 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2 clock*/ + __HAL_RCC_SAI2_CONFIG(pPeriphClkInit->Sai2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* SAI2*/ + + /*-------------------------- ADCDAC clock source configuration ----------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC) + { + /* Check the parameters */ + assert_param(IS_RCC_ADCDACCLKSOURCE(pPeriphClkInit->AdcDacClockSelection)); + + switch (pPeriphClkInit->AdcDacClockSelection) + { + + case RCC_ADCDACCLKSOURCE_HCLK: /* Bus clock is used as source of ADCDAC clock*/ + case RCC_ADCDACCLKSOURCE_SYSCLK: /* System clock is used as source of ADCDAC clock*/ + /* ADCDAC clock source config set later after clock selection check */ + break; + + case RCC_ADCDACCLKSOURCE_PLL2R: + /* PLL2 input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + break; + + case RCC_ADCDACCLKSOURCE_HSE:/* HSE clock is used as source of ADCDAC clock*/ + case RCC_ADCDACCLKSOURCE_HSI:/* HSI clock is used as source of ADCDAC clock*/ + case RCC_ADCDACCLKSOURCE_CSI:/* CSI clock is used as source of ADCDAC clock*/ + /* ADCDAC clock source configuration done later after clock selection check */ + break; + + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the ADCDAC interface clock source */ + __HAL_RCC_ADCDAC_CONFIG(pPeriphClkInit->AdcDacClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*-------------------------- DAC low-power clock source configuration ----------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC_LP) == RCC_PERIPHCLK_DAC_LP) + { + /* Check the parameters */ + assert_param(IS_RCC_DACLPCLKSOURCE(pPeriphClkInit->DacLowPowerClockSelection)); + + switch (pPeriphClkInit->DacLowPowerClockSelection) + { + + case RCC_DACLPCLKSOURCE_LSE: + /* LSE oscillator is used as source of DAC low-power clock */ + /* DAC clock source configuration done later after clock selection check */ + break; + + case RCC_DACLPCLKSOURCE_LSI: + /* LSI is used as clock source for DAC low-power clock */ + /* DAC clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the DAC low-power interface clock source */ + __HAL_RCC_DAC_LP_CONFIG(pPeriphClkInit->DacLowPowerClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*-------------------------- RTC clock source configuration ----------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection)); + + /* Enable write access to Backup domain */ + SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + + if (ret == HAL_OK) + { + /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ + tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); + + if ((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) + && (tmpregister != ((pPeriphClkInit->RTCClockSelection) & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpregister; + } + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + } + + if (ret == HAL_OK) + { + /* Apply new RTC clock source selection */ + __HAL_RCC_RTC_CONFIG(pPeriphClkInit->RTCClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*------------------------------ RNG Configuration -------------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) + { + + /* Check the parameters */ + assert_param(IS_RCC_RNGCLKSOURCE(pPeriphClkInit->RngClockSelection)); + + switch (pPeriphClkInit->RngClockSelection) + { + + case RCC_RNGCLKSOURCE_HSI48: /* HSI48 is used as clock source for RNG*/ + + /* RNG clock source configuration done later after clock selection check */ + break; + + case RCC_RNGCLKSOURCE_PLL1Q: /* PLL1 is used as clock source for RNG*/ + /* Enable PLL1Q Clock output generated from System PLL . */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* RNG clock source configuration done later after clock selection check */ + break; + case RCC_RNGCLKSOURCE_LSE: + /* LSE oscillator is used as source of RNG clock */ + /* RNG clock source configuration done later after clock selection check */ + break; + + case RCC_RNGCLKSOURCE_LSI: /* HSI48 is used as clock source for RNG*/ + + /* RNG clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of RNG clock*/ + __HAL_RCC_RNG_CONFIG(pPeriphClkInit->RngClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + +#if defined(SDMMC1) + /*-------------------------- SDMMC1 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + { + + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(pPeriphClkInit->Sdmmc1ClockSelection)); + + switch (pPeriphClkInit->Sdmmc1ClockSelection) + { + case RCC_SDMMC1CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SDMMC1 kernel clock*/ + /* Enable PLL1Q Clock output generated from System PLL . */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* SDMMC1 kernel clock source config set later after clock selection check */ + break; + + case RCC_SDMMC1CLKSOURCE_PLL2R: /* PLL2 is used as clock source for SDMMC1 kernel clock*/ + /* PLL2R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* SDMMC1 kernel clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the SDMMC1 clock source */ + __HAL_RCC_SDMMC1_CONFIG(pPeriphClkInit->Sdmmc1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } +#endif /* SDMMC1 */ + +#if defined(SDMMC2) + /*-------------------------- SDMMC2 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + { + + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(pPeriphClkInit->Sdmmc2ClockSelection)); + + switch (pPeriphClkInit->Sdmmc2ClockSelection) + { + case RCC_SDMMC2CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SDMMC2 kernel clock*/ + /* Enable PLL1Q Clock output generated from System PLL . */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* SDMMC2 kernel clock source config set later after clock selection check */ + break; + + case RCC_SDMMC2CLKSOURCE_PLL2R: /* PLL2 is used as clock source for SDMMC2 kernel clock*/ + /* PLL2R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* SDMMC2 kernel clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the SDMMC2 clock source */ + __HAL_RCC_SDMMC2_CONFIG(pPeriphClkInit->Sdmmc2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } +#endif /* SDMMC2 */ + + /*-------------------------- SPI1 clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) + { + + /* Check the parameters */ + assert_param(IS_RCC_SPI1CLKSOURCE(pPeriphClkInit->Spi1ClockSelection)); + + switch (pPeriphClkInit->Spi1ClockSelection) + { + case RCC_SPI1CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SPI1 */ + /* Enable SPI Clock output generated from System PLL . */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SPI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI1CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SPI1*/ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + + /* SPI1 clock source configuration done later after clock selection check */ + break; + +#if defined(RCC_SPI1CLKSOURCE_PLL3P) + case RCC_SPI1CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SPI1 */ + /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + + /* SPI1 clock source configuration done later after clock selection check */ + break; +#endif /* RCC_SPI1CLKSOURCE_PLL3P */ + + case RCC_SPI1CLKSOURCE_PIN: + /* External clock is used as source of SPI1 clock*/ + /* SPI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI1CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SPI1 clock */ + /* SPI1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the SPI1 clock source */ + __HAL_RCC_SPI1_CONFIG(pPeriphClkInit->Spi1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*-------------------------- SPI2 clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2) + { + + /* Check the parameters */ + assert_param(IS_RCC_SPI2CLKSOURCE(pPeriphClkInit->Spi2ClockSelection)); + + switch (pPeriphClkInit->Spi2ClockSelection) + { + case RCC_SPI2CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SPI2 */ + /* Enable SPI Clock output generated from System PLL . */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SPI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI2CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SPI2*/ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + + /* SPI2 clock source configuration done later after clock selection check */ + break; + +#if defined(RCC_SPI2CLKSOURCE_PLL3P) + case RCC_SPI2CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SPI2 */ + /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + + /* SPI2 clock source configuration done later after clock selection check */ + break; +#endif /* RCC_SPI2CLKSOURCE_PLL3P */ + + case RCC_SPI2CLKSOURCE_PIN: + /* External clock is used as source of SPI2 clock*/ + /* SPI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI2CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SPI2 clock */ + /* SPI2 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the SPI2 clock source */ + __HAL_RCC_SPI2_CONFIG(pPeriphClkInit->Spi2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*-------------------------- SPI3 clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3) + { + + /* Check the parameters */ + assert_param(IS_RCC_SPI3CLKSOURCE(pPeriphClkInit->Spi3ClockSelection)); + + switch (pPeriphClkInit->Spi3ClockSelection) + { + case RCC_SPI3CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SPI3 */ + /* Enable SPI Clock output generated from System PLL . */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SPI3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI3CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SPI3*/ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + + /* SPI3 clock source configuration done later after clock selection check */ + break; + +#if defined(RCC_SPI3CLKSOURCE_PLL3P) + case RCC_SPI3CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SPI3 */ + /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + + /* SPI3 clock source configuration done later after clock selection check */ + break; +#endif /* RCC_SPI3CLKSOURCE_PLL3P */ + + case RCC_SPI3CLKSOURCE_PIN: + /* External clock is used as source of SPI3 clock*/ + /* SPI3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI3CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SPI3 clock */ + /* SPI3 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the SPI3 clock source */ + __HAL_RCC_SPI3_CONFIG(pPeriphClkInit->Spi3ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + +#if defined(SPI4) + /*-------------------------- SPI4 clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI4) == RCC_PERIPHCLK_SPI4) + { + + /* Check the parameters */ + assert_param(IS_RCC_SPI4CLKSOURCE(pPeriphClkInit->Spi4ClockSelection)); + + switch (pPeriphClkInit->Spi4ClockSelection) + { + case RCC_SPI4CLKSOURCE_PCLK2: /* PCLK2 (APB2 Clock) is used as clock source for SPI4 */ + /* SPI4 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI4CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for SPI4*/ + /* PLL2 Q input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + + /* SPI4 clock source configuration done later after clock selection check */ + break; +#if defined(RCC_SPI4CLKSOURCE_PLL3Q) + case RCC_SPI4CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for SPI4 */ + /* PLL3 Q input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + + /* SPI4 clock source configuration done later after clock selection check */ + break; +#endif /* RCC_SPI4CLKSOURCE_PLL3Q */ + case RCC_SPI4CLKSOURCE_HSI: + /* HSI oscillator is used as source of SPI4 clock*/ + /* SPI4 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI4CLKSOURCE_CSI: + /* CSI oscillator is used as source of SPI4 clock */ + /* SPI4 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI4CLKSOURCE_HSE: + /* HSE oscillator is used as source of SPI4 clock */ + /* SPI4 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the SPI4 clock source */ + __HAL_RCC_SPI4_CONFIG(pPeriphClkInit->Spi4ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } +#endif /* SPI4 */ + +#if defined(SPI5) + /*-------------------------- SPI5 clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI5) == RCC_PERIPHCLK_SPI5) + { + + /* Check the parameters */ + assert_param(IS_RCC_SPI5CLKSOURCE(pPeriphClkInit->Spi5ClockSelection)); + + switch (pPeriphClkInit->Spi5ClockSelection) + { + case RCC_SPI5CLKSOURCE_PCLK3: /* PCLK3 (APB3 Clock) is used as clock source for SPI5 */ + /* SPI5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI5CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for SPI5*/ + /* PLL2 Q input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + + /* SPI5 clock source configuration done later after clock selection check */ + break; + case RCC_SPI5CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for SPI5 */ + /* PLL3 Q input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + + /* SPI5 clock source configuration done later after clock selection check */ + break; + case RCC_SPI5CLKSOURCE_HSI: + /* HSI oscillator is used as source of SPI5 clock*/ + /* SPI5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI5CLKSOURCE_CSI: + /* CSI oscillator is used as source of SPI5 clock */ + /* SPI5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI5CLKSOURCE_HSE: + /* HSE oscillator is used as source of SPI5 clock */ + /* SPI5 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the SPI5 clock source */ + __HAL_RCC_SPI5_CONFIG(pPeriphClkInit->Spi5ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } +#endif /* SPI5 */ + +#if defined(SPI6) + /*-------------------------- SPI6 clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) + { + + /* Check the parameters */ + assert_param(IS_RCC_SPI6CLKSOURCE(pPeriphClkInit->Spi6ClockSelection)); + + switch (pPeriphClkInit->Spi6ClockSelection) + { + case RCC_SPI6CLKSOURCE_PCLK2: /* PCLK2 (APB2 Clock) is used as clock source for SPI6 */ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for SPI6*/ + /* PLL2 Q input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + + /* SPI6 clock source configuration done later after clock selection check */ + break; + case RCC_SPI6CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for SPI6 */ + /* PLL3 Q input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + + /* SPI6 clock source configuration done later after clock selection check */ + break; + case RCC_SPI6CLKSOURCE_HSI: + /* HSI oscillator is used as source of SPI6 clock*/ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_CSI: + /* CSI oscillator is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_HSE: + /* HSE oscillator is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the SPI6 clock source */ + __HAL_RCC_SPI6_CONFIG(pPeriphClkInit->Spi6ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } +#endif /* SPI6 */ + +#if defined(OCTOSPI1) + /*-------------------------- OctoSPIx clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) + { + /* Check the parameters */ + assert_param(IS_RCC_OSPICLKSOURCE(pPeriphClkInit->OspiClockSelection)); + + switch (pPeriphClkInit->OspiClockSelection) + { + case RCC_OSPICLKSOURCE_HCLK: /* HCLK is used as clock source for OCTOSPI */ + + /* OCTOSPI clock source config set later after clock selection check */ + break; + + case RCC_OSPICLKSOURCE_PLL1Q: /* PLL1 Q is used as clock source for OCTOSPI*/ + + /* Enable PLL1 Q CLK output */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ); + break; + + case RCC_OSPICLKSOURCE_PLL2R: /* PLL2 is used as clock source for OCTOSPI*/ + /* PLL2 R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* OCTOSPI clock source config set later after clock selection check */ + break; + + case RCC_OSPICLKSOURCE_CLKP: /* CLKP is used as source of OCTOSPI clock*/ + /* OCTOSPI clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the OctoSPI clock source */ + __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* OCTOSPI1*/ + + /*-------------------------- FDCAN kernel clock source configuration -------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) + { + assert_param(IS_RCC_FDCANCLK(pPeriphClkInit->FdcanClockSelection)); + + switch (pPeriphClkInit->FdcanClockSelection) + { + case RCC_FDCANCLKSOURCE_HSE: /* HSE is used as source of FDCAN kernel clock*/ + /* FDCAN kernel clock source config set later after clock selection check */ + break; + + case RCC_FDCANCLKSOURCE_PLL1Q: /* PLL1 is used as clock source for FDCAN kernel clock*/ + /* Enable PLL1Q Clock output generated from System PLL . */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* FDCAN kernel clock source config set later after clock selection check */ + break; + + case RCC_FDCANCLKSOURCE_PLL2Q: /* PLL2 is used as clock source for FDCAN kernel clock*/ + /* PLL2Q input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* FDCAN kernel clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of FDCAN kernel clock*/ + __HAL_RCC_FDCAN_CONFIG(pPeriphClkInit->FdcanClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(USB_DRD_FS) + /*------------------------------ USB Configuration -------------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + + /* Check the parameters */ + assert_param(IS_RCC_USBCLKSOURCE(pPeriphClkInit->UsbClockSelection)); + + switch (pPeriphClkInit->UsbClockSelection) + { + case RCC_USBCLKSOURCE_PLL1Q: /* PLL is used as clock source for USB*/ + /* Enable USB Clock output generated form System USB . */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* USB clock source configuration done later after clock selection check */ + break; + +#if defined(RCC_USBCLKSOURCE_PLL3Q) + case RCC_USBCLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USB*/ + /* PLL3Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); +#else + case RCC_USBCLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USB*/ + /* PLL2Q input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); +#endif /* RCC_USBCLKSOURCE_PLL3Q */ + /* USB clock source configuration done later after clock selection check */ + break; + + case RCC_USBCLKSOURCE_HSI48: + /* HSI48 oscillator is used as source of USB clock */ + /* USB clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USB clock*/ + __HAL_RCC_USB_CONFIG(pPeriphClkInit->UsbClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } +#endif /* USB_DRD_FS */ + +#if defined(CEC) + /*-------------------------- CEC clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(pPeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(pPeriphClkInit->CecClockSelection); + + } +#endif /* CEC */ + +#if defined (PLAY1) + /*-------------------------- PLAY1 clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLAY1) == RCC_PERIPHCLK_PLAY1) + { + /* Check the parameters */ + assert_param(IS_RCC_PLAY1CLKSOURCE(pPeriphClkInit->PLAY1ClockSelection)); + assert_param(IS_RCC_PLAY1_DIV(pPeriphClkInit->PLAY1ClockDivider)); + + switch (pPeriphClkInit->PLAY1ClockSelection) + { + case RCC_PLAY1CLKSOURCE_PCLK3: /* PCLK3 (APB3 Clock) is used as clock source for PLAY1 */ + /* PLAY1 clock source configuration done later after clock selection check */ + break; + + case RCC_PLAY1CLKSOURCE_PLL2P: /* PLL2 P is used as clock source for PLAY1 kernel clock*/ + /* PLL2P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* PLAY1 kernel clock source config set later after clock selection check */ + break; +#if defined(RCC_PLAY1CLKSOURCE_PLL3R) + case RCC_PLAY1CLKSOURCE_PLL3R: /* PLL3 R is used as clock source for PLAY1 kernel clock*/ + /* PLL3R input clock, parameters M, N & R configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* PLAY1 kernel clock source config set later after clock selection check */ + break; +#endif /* RCC_PLAY1CLKSOURCE_PLL3R */ + case RCC_PLAY1CLKSOURCE_LSE: /* LSE is used as clock source for PLAY1 */ + /* PLAY1 clock source configuration done later after clock selection check */ + break; + + case RCC_PLAY1CLKSOURCE_LSI: /* LSI is used as clock source for PLAY1 */ + /* PLAY1 clock source configuration done later after clock selection check */ + break; + + case RCC_PLAY1CLKSOURCE_CLKP: /* CLKP is used as clock source for PLAY1 */ + /* PLAY1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of PLAY1 clock*/ + __HAL_RCC_PLAY1_CONFIG(pPeriphClkInit->PLAY1ClockSelection); + + /* Set the divider for PLAY1 clock (N: 0..15, divider = 2^N) */ + __HAL_RCC_PLAY1_DIV_CONFIG(pPeriphClkInit->PLAY1ClockDivider); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*PLAY1*/ + +#if defined (USB_OTG_FS) + /*-------------------------- USB_OTG_FS clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OTGFS) == RCC_PERIPHCLK_OTGFS) + { + + /* Check the parameters */ + assert_param(IS_RCC_OTGFSCLKSOURCE(pPeriphClkInit->OtgfsClockSelection)); + + switch (pPeriphClkInit->OtgfsClockSelection) + { + case RCC_OTGFSCLKSOURCE_HSI48: /* HSI48 is used as clock source for USB_OTG_FS */ + /* USB_OTG_FS clock source configuration done later after clock selection check */ + break; + + case RCC_OTGFSCLKSOURCE_PLL1Q: /* PLL1 Q is used as clock source for USB_OTG_FS kernel clock*/ + /* PLL1Q input clock, parameters M, N & Q configuration and clock output (PLL1ClockOut) */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* USB_OTG_FS kernel clock source config set later after clock selection check */ + break; + + case RCC_OTGFSCLKSOURCE_PLL3Q: /* PLL3 Q is used as clock source for USB_OTG_FS kernel clock*/ + /* PLL3Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* USB_OTG_FS kernel clock source config set later after clock selection check */ + break; +#if defined(PWR_USBSCR_OTGHSEN) + case RCC_OTGFSCLKSOURCE_CLK48: /* OTG_HS PHY CLK48 output is used as clock source for USB_OTG_FS */ + /* USB_OTG_FS clock source configuration done later after clock selection check */ + break; +#endif /* PWR_USBSCR_OTGHSEN */ + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USB_OTG_FS clock*/ + __HAL_RCC_OTGFS_CONFIG(pPeriphClkInit->OtgfsClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* USB_OTG_FS */ + +#if defined (USB_OTG_HS) + /*-------------------------- USB_OTG_HS clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OTGHS) == RCC_PERIPHCLK_OTGHS) + { + + /* Check the parameters */ + assert_param(IS_RCC_OTGHSCLKSOURCE(pPeriphClkInit->OtghsClockSelection)); + + switch (pPeriphClkInit->OtghsClockSelection) + { + case RCC_OTGHSCLKSOURCE_HSE: /* HSE is used as clock source for USB_OTG_HS */ + /* USB_OTG_HS clock source configuration done later after clock selection check */ + break; + + case RCC_OTGHSCLKSOURCE_PLL3Q: /* PLL3 Q is used as clock source for USB_OTG_HS kernel clock*/ + /* PLL3Q input clock, parameters M, N & Q configuration and clock output (PLL1ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* USB_OTG_HS kernel clock source config set later after clock selection check */ + break; + + case RCC_OTGHSCLKSOURCE_HSE_DIV2: /* HSE div 2 is used as clock source for USB_OTG_HS */ + /* USB_OTG_HS kernel clock source config set later after clock selection check */ + break; + + case RCC_OTGHSCLKSOURCE_PLL1Q_DIV2: /* PLL1 Q div 2 is used as clock source for USB_OTG_HS */ + /* Enable PLL1 Clock output generated from System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* USB_OTG_HS clock source configuration done later after clock selection check */ + break; + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USB clock*/ + __HAL_RCC_OTGHS_CONFIG(pPeriphClkInit->OtghsClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* USB_OTG_HS */ + +#if defined(OCTOSPI2) + /*-------------------------- OctoSPI2 clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI2) == RCC_PERIPHCLK_OSPI2) + { + /* Check the parameters */ + assert_param(IS_RCC_OSPI2CLKSOURCE(pPeriphClkInit->Ospi2ClockSelection)); + + switch (pPeriphClkInit->Ospi2ClockSelection) + { + case RCC_OSPI2CLKSOURCE_HCLK: /* HCLK is used as clock source for OCTOSPI2 */ + + /* OCTOSPI2 clock source config set later after clock selection check */ + break; + + case RCC_OSPI2CLKSOURCE_PLL1Q: /* PLL1 Q is used as clock source for OCTOSPI2*/ + + /* Enable PLL1 Q CLK output */ + __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ); + break; + + case RCC_OSPI2CLKSOURCE_PLL2R: /* PLL2 R is used as clock source for OCTOSPI2*/ + /* PLL2 R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* OCTOSPI clock source config set later after clock selection check */ + break; + + case RCC_OSPI2CLKSOURCE_CLKP: /* CLKP is used as source of OCTOSPI2 clock*/ + /* OCTOSPI2 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the OctoSPI2 clock source */ + __HAL_RCC_OSPI2_CONFIG(pPeriphClkInit->Ospi2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* OCTOSPI2*/ + +#if defined (LTDC) + /*-------------------------- LTDC clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + /* Check the parameters */ + assert_param(IS_RCC_LTDCCLKSOURCE(pPeriphClkInit->LtdcClockSelection)); + + switch (pPeriphClkInit->LtdcClockSelection) + { + case RCC_LTDCCLKSOURCE_PLL3R: /* PLL3 R is used as clock source for LTDC*/ + /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* LTDC clock source config set later after clock selection check */ + break; + case RCC_LTDCCLKSOURCE_PLL2R: /* PLL2 R is used as clock source for LTDC*/ + /* PLL2 R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* LTDC clock source config set later after clock selection check */ + break; + default: + ret = HAL_ERROR; + break; + } + if (ret == HAL_OK) + { + /* Configure the LTDC interface clock source */ + __HAL_RCC_LTDC_CONFIG(pPeriphClkInit->LtdcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* LTDC */ + +#if defined (MDF1) + /*-------------------------- MDF1 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_MDF1) == RCC_PERIPHCLK_MDF1) + { + /* Check the parameters */ + assert_param(IS_RCC_MDF1CLKSOURCE(pPeriphClkInit->Mdf1ClockSelection)); + + switch (pPeriphClkInit->Mdf1ClockSelection) + { + case RCC_MDF1CLKSOURCE_PLL1Q: /* PLL1 Q is used as clock source for MDF1 */ + /* Enable PLL1 Clock output generated from System PLL */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + break; + case RCC_MDF1CLKSOURCE_PLL2P: /* PLL2 P is used as clock source for MDF1 */ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* MDF1 clock source configuration done later after clock selection check */ + break; + case RCC_MDF1CLKSOURCE_PLL3P: /* PLL3 P is used as clock source for MDF1 */ + /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* MDF1 clock source configuration done later after clock selection check */ + break; + case RCC_MDF1CLKSOURCE_PIN: /* External clock is used as clock source of MDF1 */ + /* MDF1 clock source configuration done later after clock selection check */ + break; + case RCC_MDF1CLKSOURCE_CLKP: /* CLKP is used as clock source for MDF1 */ + /* MDF1 clock source configuration done later after clock selection check */ + break; + default: + ret = HAL_ERROR; + break; + } + if (ret == HAL_OK) + { + /* Configure the MDF1 interface clock source */ + __HAL_RCC_MDF1_CONFIG(pPeriphClkInit->Mdf1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* MDF1 */ + +#if defined (RCC_CCIPR4_ETHCLKSEL) + /*-------------------------- ETH clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ETH) == RCC_PERIPHCLK_ETH) + { + /* Check the parameters */ + assert_param(IS_RCC_ETHCLKSOURCE(pPeriphClkInit->EthClockSelection)); + + switch (pPeriphClkInit->EthClockSelection) + { + case RCC_ETHCLKSOURCE_HSE: /* HSE is used as clock source for ETH */ + /* ETH clock source configuration done later after clock selection check */ + break; + case RCC_ETHCLKSOURCE_PLL1Q: /* PLL1 Q is used as clock source for ETH */ + /* Enable PLL1 Clock output generated from System PLL */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* ETH clock source configuration done later after clock selection check */ + break; + default: + ret = HAL_ERROR; + break; + } + if (ret == HAL_OK) + { + /* Configure the ETH interface clock source */ + __HAL_RCC_ETH_CONFIG(pPeriphClkInit->EthClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* RCC_CCIPR4_ETHCLKSEL */ + +#if defined (ADF1) + /*-------------------------- ADF1 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1) + { + /* Check the parameters */ + assert_param(IS_RCC_ADF1CLKSOURCE(pPeriphClkInit->Adf1ClockSelection)); + + switch (pPeriphClkInit->Adf1ClockSelection) + { + case RCC_ADF1CLKSOURCE_PLL1Q: /* PLL1 Q is used as clock source for ADF1 */ + /* Enable PLL1 Clock output generated from System PLL */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* ADF1 clock source configuration done later after clock selection check */ + break; + case RCC_ADF1CLKSOURCE_PLL2P: /* PLL2 P is used as clock source for ADF1 */ + /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* ADF1 clock source configuration done later after clock selection check */ + break; + case RCC_ADF1CLKSOURCE_PLL3P: /* PLL3 P is used as clock source for ADF1 */ + /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + break; + case RCC_ADF1CLKSOURCE_PIN: /* External clock is used as source of ADF1 clock*/ + /* ADF1 clock source configuration done later after clock selection check */ + break; + case RCC_ADF1CLKSOURCE_CLKP: /* CLKP is used as clock source for ADF1 */ + /* ADF1 clock source configuration done later after clock selection check */ + break; + default: + ret = HAL_ERROR; + break; + } + if (ret == HAL_OK) + { + /* Configure the ADF1 interface clock source */ + __HAL_RCC_ADF1_CONFIG(pPeriphClkInit->Adf1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* ADF1 */ + +#if defined (RCC_CCIPR5_ETHPTPCLKSEL) + /*-------------------------- ETHPTP clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ETHPTP) == RCC_PERIPHCLK_ETHPTP) + { + /* Check the parameters */ + assert_param(IS_RCC_ETHPTPCLKSOURCE(pPeriphClkInit->EthptpClockSelection)); + assert_param(IS_RCC_ETHPTP_DIV(pPeriphClkInit->EthptpClockDivider)); + + switch (pPeriphClkInit->EthptpClockSelection) + { + case RCC_ETHPTPCLKSOURCE_HCLK: /* HCLK is used as clock source for ETHPTP */ + /* ETHPTP clock source configuration done later after clock selection check */ + break; + case RCC_ETHPTPCLKSOURCE_PLL1R: /* PLL1 R is used as clock source for ETHPTP */ + /* Enable PLL1 Clock output generated from System PLL */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); + /* ETHPTP clock source configuration done later after clock selection check */ + break; + case RCC_ETHPTPCLKSOURCE_PLL1Q: /* PLL1 Q is used as clock source for ETHPTP */ + /* Enable PLL1 Clock output generated from System PLL */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* ETHPTP clock source configuration done later after clock selection check */ + break; +#if defined(RCC_ETHPTPCLKSOURCE_PLL3P) + case RCC_ETHPTPCLKSOURCE_PLL3P: /* PLL3 P is used as clock source for ETHPTP */ + /* Enable PLL3 Clock output generated from System PLL */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* ETHPTP clock source configuration done later after clock selection check */ + break; +#endif /* RCC_ETHPTPCLKSOURCE_PLL3P */ + default: + ret = HAL_ERROR; + break; + } + if (ret == HAL_OK) + { + /* Configure the ETHPTP interface clock source */ + __HAL_RCC_ETHPTP_CONFIG(pPeriphClkInit->EthptpClockSelection); + + /* Set the divider for ETHPTP clock (N: 0..15, divider = N) */ + __HAL_RCC_ETHPTP_DIV_CONFIG(pPeriphClkInit->EthptpClockDivider); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + +#if defined (RCC_CCIPR5_ETHREFCLKSEL) + /*-------------------------- ETHREF clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ETHREF) == RCC_PERIPHCLK_ETHREF) + { + /* Check the parameters */ + assert_param(IS_RCC_ETHREFCLKSOURCE(pPeriphClkInit->EthrefClockSelection)); + + switch (pPeriphClkInit->EthrefClockSelection) + { + case RCC_ETHREFCLKSOURCE_PLL1Q: /* PLL1 Q is used as clock source for ETHREF */ + /* Enable PLL1 Clock output generated from System PLL */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + break; + case RCC_ETHREFCLKSOURCE_PLL1R: /* PLL1 R is used as clock source for ETHREF */ + /* Enable PLL1 Clock output generated from System PLL */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); + break; + default: + ret = HAL_ERROR; + break; + } + if (ret == HAL_OK) + { + /* Configure the ETHREF interface clock source */ + __HAL_RCC_ETHREF_CONFIG(pPeriphClkInit->EthrefClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /* RCC_CCIPR5_ETHREFCLKSEL */ + + return status; +} + +/** + * @brief Get the pPeriphClkInit according to the internal RCC configuration registers. + * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals + * clocks (ADC12, DAC, SDMMC1, SDMMC2, OCTOSPI1, TIM, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6, + * SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8, + * UART9, USART10, USART11, UART12, LPUART1, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2, CEC, FDCAN, SAI1, + * SAI2, USB, PLAY1), PLL2 and PLL3. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_ADCDAC | \ + RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ + RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_CKPER; + +#if defined(USB_DRD_FS) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; +#endif /* USB_DRD_FS */ +#if defined(UART4) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART4; +#endif /* UART4 */ +#if defined(UART5) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART5; +#endif /* UART5 */ +#if defined(USART6) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART6; +#endif /* UART6 */ +#if defined(UART7) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART7; +#endif /* UART7 */ +#if defined(UART8) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART8; +#endif /* UART8 */ +#if defined(UART9) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART9; +#endif /* UART9 */ +#if defined(USART10) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART10; +#endif /* UART10 */ +#if defined(USART11) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART11; +#endif /* UART11 */ +#if defined(UART12) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART12; +#endif /* UART12 */ +#if defined(I2C3) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3; +#endif /* I2C3 */ +#if defined(I2C4) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C4; +#endif /* I2C4 */ +#if defined(I3C2) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I3C2; +#endif /* I3C2 */ +#if defined(LPTIM3) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM3; +#endif /* LPTIM3 */ +#if defined(LPTIM4) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM4; +#endif /* LPTIM4 */ +#if defined(LPTIM5) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM5; +#endif /* LPTIM5 */ +#if defined(LPTIM6) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM6; +#endif /* LPTIM6 */ +#if defined(SPI4) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SPI4; +#endif /* SPI4 */ +#if defined(SPI5) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SPI5; +#endif /* SPI5 */ +#if defined(SPI6) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SPI6; +#endif /* SPI6 */ +#if defined(SAI1) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI1; +#endif /* SAI1 */ +#if defined(SAI2) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2; +#endif /* SAI2 */ + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_FDCAN; +#if defined(SDMMC1) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDMMC1; +#endif /* SDMMC1*/ +#if defined(SDMMC2) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDMMC2; +#endif /* SDMMC2*/ +#if defined(OCTOSPI1) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI; +#endif /* OCTOSPI1 */ +#if defined(CEC) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; +#endif /* CEC */ +#if defined(PLAY1) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_PLAY1; +#endif /* PLAY1 */ +#if defined(USB_OTG_FS) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OTGFS; +#endif /* USB_OTG_FS */ +#if defined(USB_OTG_HS) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OTGHS; +#endif /* USB_OTG_HS */ +#if defined(OCTOSPI2) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI2; +#endif /* OCTOSPI2 */ +#if defined(LTDC) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC; +#endif /* LTDC */ +#if defined(ADF1) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADF1; +#endif /* ADF1 */ +#if defined(MDF1) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_MDF1; +#endif /* MDF1 */ +#if defined(RCC_CCIPR4_ETHCLKSEL) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ETH; +#endif /* RCC_CCIPR4_ETHCLKSEL */ +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ETHPTP; +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ +#if defined(RCC_CCIPR5_ETHREFCLKSEL) + pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ETHREF; +#endif /* RCC_CCIPR5_ETHREFCLKSEL */ + + /* Get the PLL2 Clock configuration -----------------------------------------------*/ + pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFGR_PLL2SRC_Pos); + pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos); + pPeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1U; + pPeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1U; + pPeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1U; + pPeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + 1U; + pPeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_PLL2RGE_Pos); + pPeriphClkInit->PLL2.PLL2FRACN = (uint32_t)((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \ + RCC_PLL2FRACR_PLL2FRACN_Pos); + +#if defined(RCC_CR_PLL3ON) + /* Get the PLL3 Clock configuration -----------------------------------------------*/ + pPeriphClkInit->PLL3.PLL3Source = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC) >> RCC_PLL3CFGR_PLL3SRC_Pos); + pPeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos); + pPeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1U; + pPeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1U; + pPeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1U; + pPeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1U; + pPeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3RGE) >> RCC_PLL3CFGR_PLL3RGE_Pos); + pPeriphClkInit->PLL3.PLL3FRACN = (uint32_t)((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \ + RCC_PLL3FRACR_PLL3FRACN_Pos); +#endif /* RCC_CR_PLL3ON */ + + /* Get the USART1 clock source ---------------------------------------------*/ + pPeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + + /* Get the USART2 clock source ---------------------------------------------*/ + pPeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + + /* Get the USART3 clock source ---------------------------------------------*/ + pPeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + +#if defined(UART4) + /* Get the UART4 clock source ----------------------------------------------*/ + pPeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); +#endif /* UART4 */ + +#if defined(UART5) + /* Get the UART5 clock source ----------------------------------------------*/ + pPeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); +#endif /* UART5 */ + +#if defined(USART6) + /* Get the USART6 clock source ---------------------------------------------*/ + pPeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); +#endif /* USART6 */ + +#if defined(UART7) + /* Get the UART7 clock source ---------------------------------------------*/ + pPeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); +#endif /* UART7 */ + +#if defined(UART8) + /* Get the UART8 clock source ---------------------------------------------*/ + pPeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); +#endif /* UART8 */ + +#if defined(UART9) + /* Get the UART9 clock source ---------------------------------------------*/ + pPeriphClkInit->Uart9ClockSelection = __HAL_RCC_GET_UART9_SOURCE(); +#endif /* UART9 */ + +#if defined(USART10) + /* Get the USART10 clock source ---------------------------------------------*/ + pPeriphClkInit->Usart10ClockSelection = __HAL_RCC_GET_USART10_SOURCE(); +#endif /* USART10 */ + +#if defined(USART11) + /* Get the USART11 clock source ---------------------------------------------*/ + pPeriphClkInit->Usart11ClockSelection = __HAL_RCC_GET_USART11_SOURCE(); +#endif /* USART11 */ + +#if defined(UART12) + /* Get the UART12 clock source ---------------------------------------------*/ + pPeriphClkInit->Uart12ClockSelection = __HAL_RCC_GET_UART12_SOURCE(); +#endif /* UART12 */ + + /* Get the LPUART1 clock source --------------------------------------------*/ + pPeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); + + /* Get the I2C1 clock source -----------------------------------------------*/ + pPeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Get the I2C2 clock source -----------------------------------------------*/ + pPeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + +#if defined(I2C3) + /* Get the I2C3 clock source -----------------------------------------------*/ + pPeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); +#endif /* I2C3 */ + +#if defined(I2C4) + /* Get the I2C4 clock source -----------------------------------------------*/ + pPeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); +#endif /* I2C4 */ + + /* Get the I3C1 clock source -----------------------------------------------*/ + pPeriphClkInit->I3c1ClockSelection = __HAL_RCC_GET_I3C1_SOURCE(); + +#if defined(I3C2) + /* Get the I3C2 clock source -----------------------------------------------*/ + pPeriphClkInit->I3c2ClockSelection = __HAL_RCC_GET_I3C2_SOURCE(); +#endif /* I3C2 */ + + /* Get the LPTIM1 clock source ---------------------------------------------*/ + pPeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + + /* Get the LPTIM2 clock source ---------------------------------------------*/ + pPeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); + +#if defined(LPTIM3) + /* Get the LPTIM3 clock source ---------------------------------------------*/ + pPeriphClkInit->Lptim3ClockSelection = __HAL_RCC_GET_LPTIM3_SOURCE(); +#endif /* LPTIM3 */ + +#if defined(LPTIM4) + /* Get the LPTIM4 clock source ---------------------------------------------*/ + pPeriphClkInit->Lptim4ClockSelection = __HAL_RCC_GET_LPTIM4_SOURCE(); +#endif /* LPTIM4 */ + +#if defined(LPTIM5) + /* Get the LPTIM5 clock source ---------------------------------------------*/ + pPeriphClkInit->Lptim5ClockSelection = __HAL_RCC_GET_LPTIM5_SOURCE(); +#endif /* LPTIM5 */ + +#if defined(LPTIM6) + /* Get the LPTIM6 clock source ---------------------------------------------*/ + pPeriphClkInit->Lptim6ClockSelection = __HAL_RCC_GET_LPTIM6_SOURCE(); +#endif /* LPTIM6 */ + + /* Get the FDCAN clock source ---------------------------------------------*/ + pPeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); + +#if defined(SAI1) + /* Get the SAI1 clock source -----------------------------------------------*/ + pPeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); +#endif /* SAI1 */ + +#if defined(SAI2) + /* Get the SAI2 clock source -----------------------------------------------*/ + pPeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); +#endif /* SAI2 */ + +#if defined(SDMMC1) + /* Get the SDMMC1 clock source ----------------------------------------------*/ + pPeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); +#endif /* SDMMC1 */ + +#if defined(SDMMC2) + /* Get the SDMMC2 clock source ----------------------------------------------*/ + pPeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); +#endif /* SDMMC2 */ + + /* Get the ADCDAC clock source ---------------------------------------------*/ + pPeriphClkInit->AdcDacClockSelection = __HAL_RCC_GET_ADCDAC_SOURCE(); + + /* Get the DAC low-power clock source ---------------------------------------------*/ + pPeriphClkInit->DacLowPowerClockSelection = __HAL_RCC_GET_DAC_LP_SOURCE(); + +#if defined(OCTOSPI1) + /* Get the OSPI clock source -----------------------------------------------*/ + pPeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); +#endif /* OCTOSPI1 */ + + /* Get the SPI1 clock source -----------------------------------------------*/ + pPeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE(); + + /* Get the SPI2 clock source -----------------------------------------------*/ + pPeriphClkInit->Spi2ClockSelection = __HAL_RCC_GET_SPI2_SOURCE(); + + /* Get the SPI3 clock source -----------------------------------------------*/ + pPeriphClkInit->Spi3ClockSelection = __HAL_RCC_GET_SPI3_SOURCE(); + +#if defined(SPI4) + /* Get the SPI4 clock source -----------------------------------------------*/ + pPeriphClkInit->Spi4ClockSelection = __HAL_RCC_GET_SPI4_SOURCE(); +#endif /* SPI4 */ + +#if defined(SPI5) + /* Get the SPI5 clock source -----------------------------------------------*/ + pPeriphClkInit->Spi5ClockSelection = __HAL_RCC_GET_SPI5_SOURCE(); +#endif /* SPI5 */ + +#if defined(SPI6) + /* Get the SPI6 clock source -----------------------------------------------*/ + pPeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE(); +#endif /* SPI6 */ + + /* Get the RTC clock source ------------------------------------------------*/ + pPeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + + /* Get the RNG clock source ------------------------------------------------*/ + pPeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); + + /* Get the CKPER clock source ------------------------------------------------*/ + pPeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE(); + +#if defined(CEC) + /* Get the CEC clock source ------------------------------------------------*/ + pPeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); +#endif /* CEC */ + +#if defined(USB_DRD_FS) + /* Get the USB clock source ------------------------------------------------*/ + pPeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* USB_DRD_FS */ + + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->CFGR1 & RCC_CFGR1_TIMPRE) == 0U) + { + pPeriphClkInit->TimPresSelection = RCC_TIMPRES_DEACTIVATED; + } + else + { + pPeriphClkInit->TimPresSelection = RCC_TIMPRES_ACTIVATED; + } + +#if defined(PLAY1) + /* Get the PLAY1 clock source ------------------------------------------------*/ + pPeriphClkInit->PLAY1ClockSelection = __HAL_RCC_GET_PLAY1_SOURCE(); + /* Get the PLAY1 clock divider ------------------------------------------------*/ + pPeriphClkInit->PLAY1ClockDivider = __HAL_RCC_GET_PLAY1_DIV(); +#endif /* PLAY1 */ + +#if defined(USB_OTG_FS) + /* Get the USB_OTG_FS clock source ------------------------------------------------*/ + pPeriphClkInit->OtgfsClockSelection = __HAL_RCC_GET_OTGFS_SOURCE(); +#endif /* USB_OTG_FS */ + +#if defined(USB_OTG_HS) + /* Get the USB_OTG_HS clock source ------------------------------------------------*/ + pPeriphClkInit->OtghsClockSelection = __HAL_RCC_GET_OTGHS_SOURCE(); +#endif /* USB_OTG_HS */ + +#if defined(OCTOSPI2) + /* Get the OSPI2 clock source -----------------------------------------------*/ + pPeriphClkInit->Ospi2ClockSelection = __HAL_RCC_GET_OSPI2_SOURCE(); +#endif /* OCTOSPI2 */ + +#if defined(LTDC) + /* Get the LTDC clock source ------------------------------------------------*/ + pPeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); +#endif /* LTDC */ + +#if defined(ADF1) + /* Get the ADF1 clock source ------------------------------------------------*/ + pPeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE(); +#endif /* ADF1 */ + +#if defined(MDF1) + /* Get the MDF1 clock source ------------------------------------------------*/ + pPeriphClkInit->Mdf1ClockSelection = __HAL_RCC_GET_MDF1_SOURCE(); +#endif /* MDF1 */ + +#if defined(RCC_CCIPR4_ETHCLKSEL) + /* Get the ETH clock source ------------------------------------------------*/ + pPeriphClkInit->EthClockSelection = __HAL_RCC_GET_ETH_SOURCE(); +#endif /* RCC_CCIPR4_ETHCLKSEL */ + +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) + /* Get the ETHPTP clock source ------------------------------------------------*/ + pPeriphClkInit->EthptpClockSelection = __HAL_RCC_GET_ETHPTP_SOURCE(); + /* Get the ETHPTP clock source ------------------------------------------------*/ + pPeriphClkInit->EthptpClockDivider = __HAL_RCC_GET_ETHPTP_DIV(); +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + +#if defined(RCC_CCIPR5_ETHREFCLKSEL) + /* Get the ETHREF clock source ------------------------------------------------*/ + pPeriphClkInit->EthrefClockSelection = __HAL_RCC_GET_ETHREF_SOURCE(); +#endif /* RCC_CCIPR5_ETHREFCLKSEL */ +} + +/** + * @brief Returns the PLL1 clock frequencies : PLL1_P_Frequency, PLL1_R_Frequency and PLL1_Q_Frequency + * @note The PLL1 clock frequencies computed by this function may not be the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by + the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL1CLK changes, this function must be called to update the + * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param pPLL1_Clocks pointer to PLL1_ClocksTypeDef structure. + * @retval None + */ +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *pPLL1_Clocks) +{ + uint32_t pll1source; + uint32_t pll1m; + uint32_t pll1n; + uint32_t pll1fracen; + uint32_t hsivalue; + float_t fracn1; + float_t pll1vco; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL1M) * PLL1N + PLL1xCLK = PLL1_VCO / PLL1x + */ + + pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N); + pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); + pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); + pll1fracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ + RCC_PLL1FRACR_PLL1FRACN_Pos)); + + if (pll1m != 0U) + { + switch (pll1source) + { + + case RCC_PLL1_SOURCE_HSI: /* HSI used as PLL1 clock source */ + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \ + (float_t)1); + break; + + case RCC_PLL1_SOURCE_CSI: /* CSI used as PLL1 clock source */ + pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \ + (float_t)1); + break; + + case RCC_PLL1_SOURCE_HSE: /* HSE used as PLL1 clock source */ + pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \ + (float_t)1); + break; + + default: + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \ + (float_t)1); + break; + } + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + if (__HAL_RCC_GET_PLL1_CLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U) + { + pPLL1_Clocks->PLL1_P_Frequency = \ + (uint32_t)(float_t)(pll1vco / \ + ((float_t)(uint32_t)((RCC->PLL1DIVR & \ + RCC_PLL1DIVR_PLL1P) >> \ + RCC_PLL1DIVR_PLL1P_Pos) + \ + (float_t)1)); + } + else + { + pPLL1_Clocks->PLL1_P_Frequency = 0U; + } + } + else + { + pPLL1_Clocks->PLL1_P_Frequency = 0U; + } + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + if (__HAL_RCC_GET_PLL1_CLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U) + { + pPLL1_Clocks->PLL1_Q_Frequency = \ + (uint32_t)(float_t)(pll1vco / \ + ((float_t)(uint32_t)((RCC->PLL1DIVR & \ + RCC_PLL1DIVR_PLL1Q) >> \ + RCC_PLL1DIVR_PLL1Q_Pos) + \ + (float_t)1)); + } + else + { + pPLL1_Clocks->PLL1_Q_Frequency = 0U; + } + } + else + { + pPLL1_Clocks->PLL1_Q_Frequency = 0U; + } + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + if (__HAL_RCC_GET_PLL1_CLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U) + { + pPLL1_Clocks->PLL1_R_Frequency = \ + (uint32_t)(float_t)(pll1vco / \ + ((float_t)(uint32_t)((RCC->PLL1DIVR & \ + RCC_PLL1DIVR_PLL1R) >> \ + RCC_PLL1DIVR_PLL1R_Pos) + \ + (float_t)1)) ; + } + else + { + pPLL1_Clocks->PLL1_R_Frequency = 0U; + } + } + else + { + pPLL1_Clocks->PLL1_R_Frequency = 0U; + } + + } + else + { + pPLL1_Clocks->PLL1_P_Frequency = 0U; + pPLL1_Clocks->PLL1_Q_Frequency = 0U; + pPLL1_Clocks->PLL1_R_Frequency = 0U; + } + +} + +/** + * @brief Returns the PLL2 clock frequencies: PLL2_P_Frequency, PLL2_R_Frequency and PLL2_Q_Frequency + * @note The PLL2 clock frequencies computed by this function may not be the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by + the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL2CLK changes, this function must be called to update the + * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param pPLL2_Clocks pointer to PLL2_ClocksTypeDef structure. + * @retval None + */ +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *pPLL2_Clocks) +{ + uint32_t pll2source; + uint32_t pll2m; + uint32_t pll2n; + uint32_t pll2fracen; + uint32_t hsivalue; + float_t fracn2; + float_t pll2vco; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N + PLL2xCLK = PLL2_VCO / PLL2x + */ + pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N); + pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC); + pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos); + pll2fracen = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos); + fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \ + RCC_PLL2FRACR_PLL2FRACN_Pos)); + + if (pll2m != 0U) + { + switch (pll2source) + { + case RCC_PLL2_SOURCE_HSI: /* HSI used as PLL clock source */ + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \ + (float_t)1); + break; + + case RCC_PLL2_SOURCE_CSI: /* CSI used as PLL clock source */ + pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \ + (float_t)1); + break; + + case RCC_PLL2_SOURCE_HSE: /* HSE used as PLL clock source */ + pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \ + (float_t)1); + break; + + default: + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \ + (float_t)1); + break; + } + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + if (__HAL_RCC_GET_PLL2_CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U) + { + pPLL2_Clocks->PLL2_P_Frequency = \ + (uint32_t)(float_t)(pll2vco / \ + ((float_t)(uint32_t)((RCC->PLL2DIVR & \ + RCC_PLL2DIVR_PLL2P) >> \ + RCC_PLL2DIVR_PLL2P_Pos) + \ + (float_t)1)); + } + else + { + pPLL2_Clocks->PLL2_P_Frequency = 0U; + } + } + else + { + pPLL2_Clocks->PLL2_P_Frequency = 0U; + } + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + if (__HAL_RCC_GET_PLL2_CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U) + { + pPLL2_Clocks->PLL2_Q_Frequency = \ + (uint32_t)(float_t)(pll2vco / \ + ((float_t)(uint32_t)((RCC->PLL2DIVR & \ + RCC_PLL2DIVR_PLL2Q) >> \ + RCC_PLL2DIVR_PLL2Q_Pos) + \ + (float_t)1)); + } + else + { + pPLL2_Clocks->PLL2_Q_Frequency = 0U; + } + } + else + { + pPLL2_Clocks->PLL2_Q_Frequency = 0U; + } + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + if (__HAL_RCC_GET_PLL2_CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U) + { + pPLL2_Clocks->PLL2_R_Frequency = \ + (uint32_t)(float_t)(pll2vco / \ + ((float_t)(uint32_t)((RCC->PLL2DIVR & \ + RCC_PLL2DIVR_PLL2R) >> \ + RCC_PLL2DIVR_PLL2R_Pos) + \ + (float_t)1)); + } + else + { + pPLL2_Clocks->PLL2_R_Frequency = 0U; + } + } + else + { + pPLL2_Clocks->PLL2_R_Frequency = 0U; + } + } + else + { + pPLL2_Clocks->PLL2_P_Frequency = 0U; + pPLL2_Clocks->PLL2_Q_Frequency = 0U; + pPLL2_Clocks->PLL2_R_Frequency = 0U; + } +} + +#if defined(RCC_CR_PLL3ON) +/** + * @brief Returns the PLL3 clock frequencies: PLL3_P_Frequency, PLL3_R_Frequency and PLL3_Q_Frequency + * @note The PLL3 clock frequencies computed by this function may not be the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by + the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL3CLK changes, this function must be called to update the + * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param pPLL3_Clocks pointer to PLL3_ClocksTypeDef structure. + * @retval None + */ +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *pPLL3_Clocks) +{ + uint32_t pll3source; + uint32_t pll3m; + uint32_t pll3n; + uint32_t pll3fracen; + uint32_t hsivalue; + float_t fracn3; + float_t pll3vco; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N + PLL3xCLK = PLL3_VCO / PLL3x + */ + pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N); + pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC); + pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos); + pll3fracen = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN) >> RCC_PLL3CFGR_PLL3FRACEN_Pos); + fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \ + RCC_PLL3FRACR_PLL3FRACN_Pos)); + + if (pll3m != 0U) + { + switch (pll3source) + { + case RCC_PLL3_SOURCE_HSI: /* HSI used as PLL clock source */ + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \ + (float_t)1); + break; + + case RCC_PLL3_SOURCE_CSI: /* CSI used as PLL clock source */ + pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \ + (float_t)1); + break; + + case RCC_PLL3_SOURCE_HSE: /* HSE used as PLL clock source */ + pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \ + (float_t)1); + break; + + default: + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \ + (float_t)1); + break; + } + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + if (__HAL_RCC_GET_PLL3_CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U) + { + pPLL3_Clocks->PLL3_P_Frequency = \ + (uint32_t)(float_t)(pll3vco / \ + ((float_t)(uint32_t)((RCC->PLL3DIVR & \ + RCC_PLL3DIVR_PLL3P) >> \ + RCC_PLL3DIVR_PLL3P_Pos) + \ + (float_t)1)); + } + else + { + pPLL3_Clocks->PLL3_P_Frequency = 0U; + } + } + else + { + pPLL3_Clocks->PLL3_P_Frequency = 0U; + } + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + if (__HAL_RCC_GET_PLL3_CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U) + { + pPLL3_Clocks->PLL3_Q_Frequency = \ + (uint32_t)(float_t)(pll3vco / \ + ((float_t)(uint32_t)((RCC->PLL3DIVR & \ + RCC_PLL3DIVR_PLL3Q) >> \ + RCC_PLL3DIVR_PLL3Q_Pos) + \ + (float_t)1)); + } + else + { + pPLL3_Clocks->PLL3_Q_Frequency = 0U; + } + } + else + { + pPLL3_Clocks->PLL3_Q_Frequency = 0U; + } + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + if (__HAL_RCC_GET_PLL3_CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U) + { + pPLL3_Clocks->PLL3_R_Frequency = \ + (uint32_t)(float_t)(pll3vco / \ + ((float_t)(uint32_t)((RCC->PLL3DIVR & \ + RCC_PLL3DIVR_PLL3R) >> \ + RCC_PLL3DIVR_PLL3R_Pos) + \ + (float_t)1)); + } + else + { + pPLL3_Clocks->PLL3_R_Frequency = 0U; + } + } + else + { + pPLL3_Clocks->PLL3_R_Frequency = 0U; + } + } + else + { + pPLL3_Clocks->PLL3_P_Frequency = 0U; + pPLL3_Clocks->PLL3_Q_Frequency = 0U; + pPLL3_Clocks->PLL3_R_Frequency = 0U; + } +} +#endif /* RCC_CR_PLL3ON */ + +/** + * @brief Return the peripheral clock frequency for peripherals + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_UART7 UART7 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_UART8 UART8 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_UART9 UART9 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_USART10 USART10 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_USART11 USART11 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_UART12 UART12 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_I3C1 I3C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I3C2 I3C2 peripheral clock (***) + * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock + * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_ADCDAC ADCDAC peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_SDMMC2 SDMMC2 peripheral clock (**) + * @arg @ref RCC_PERIPHCLK_CKPER CKPER peripheral clock + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI4 SPI4 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_SPI5 SPI5 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_SPI6 SPI6 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_OSPI OCTOSPI peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (*****) + * @arg @ref RCC_PERIPHCLK_LPTIM3 LPTIM3 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPTIM4 LPTIM4 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPTIM5 LPTIM5 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPTIM6 LPTIM6 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_DAC_LP DAC low-power peripheral clock + * @arg @ref RCC_PERIPHCLK_PLAY1 PLAY1 peripheral clock (****) + * @arg @ref RCC_PERIPHCLK_OTGFS USB_OTG_FS peripheral clock (****) + * @arg @ref RCC_PERIPHCLK_OTGHS USB_OTG_HS peripheral clock (****) + * + * @retval Frequency in Hz + * + * (*) : For stm32h56xxx and stm32h57xxx family lines only. + * (**) : For stm32h563xx and stm32h57xxx family lines only. + * (***) : For stm32h503xx family line only. + * (****) : For stm32h5exxx and stm32h5fxxx family lines only. + * (*****) : Not available for stm32h5exxx and stm32h5fxxx family lines. + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) +{ + PLL1_ClocksTypeDef pll1_clocks; + PLL2_ClocksTypeDef pll2_clocks; +#if defined(RCC_CR_PLL3ON) + PLL3_ClocksTypeDef pll3_clocks; +#endif /* RCC_CR_PLL3ON */ + + uint32_t frequency = 0u; + uint32_t ckpclocksource = 0u; + uint32_t srcclk = 0u; +#if defined(PLAY1) + uint32_t play1_divider = 0u; +#endif /* PLAY1 */ +#if defined(RCC_CCIPR4_ETHPTPDIV) + uint32_t ethptp_divider = 0u; +#endif /* RCC_CCIPR4_ETHPTPDIV */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + if (PeriphClk == RCC_PERIPHCLK_RTC) + { + /* Get the current RTC source */ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if LSE is ready and if RTC clock selection is LSE */ + if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready and if RTC clock selection is LSI */ + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI)) + { + frequency = LSI_VALUE; + } + /* Check if HSE is ready and if RTC clock selection is HSE_DIVx*/ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIVx)) + { + if (__HAL_RCC_GET_RTC_HSE_PRESCALER() >= RCC_RTC_HSE_DIV2) + { + frequency = (HSE_VALUE / ((uint32_t)(__HAL_RCC_GET_RTC_HSE_PRESCALER() >> RCC_CFGR1_RTCPRE_Pos))); + } + else + { + frequency = 0U; + } + + } + /* Clock not enabled for RTC*/ + else + { + frequency = 0U; + } + } + else + { + /* Other external peripheral clock source than RTC */ + switch (PeriphClk) + { +#if defined (SAI1) + case RCC_PERIPHCLK_SAI1: + + srcclk = __HAL_RCC_GET_SAI1_SOURCE(); + + switch (srcclk) + { + case RCC_SAI1CLKSOURCE_PLL1Q: /* PLL1Q is the clock source for SAI1 */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_SAI1CLKSOURCE_PLL2P: /* PLL2P is the clock source for SAI1 */ + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } + case RCC_SAI1CLKSOURCE_PLL3P: /* PLLI3P is the clock source for SAI1 */ + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; + } + case RCC_SAI1CLKSOURCE_PIN: + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + case RCC_SAI1CLKSOURCE_CLKP: /* CLKP is the clock source for SAI1 */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default : + { + frequency = 0U; + break; + } + } + break; +#endif /*SAI1*/ + +#if defined(SAI2) + case RCC_PERIPHCLK_SAI2: + + srcclk = __HAL_RCC_GET_SAI2_SOURCE(); + + switch (srcclk) + { + case RCC_SAI2CLKSOURCE_PLL1Q: /* PLL1Q is the clock source for SAI2 */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_SAI2CLKSOURCE_PLL2P: /* PLL2P is the clock source for SAI2 */ + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } + case RCC_SAI2CLKSOURCE_PLL3P: /* PLLI3P is the clock source for SAI2 */ + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; + } + case RCC_SAI2CLKSOURCE_PIN: + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + case RCC_SAI2CLKSOURCE_CLKP: /* CLKP is the clock source for SAI2 */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default : + { + frequency = 0U; + break; + } + } + break; +#endif /* SAI2 */ + +#if defined(SDMMC1) + case RCC_PERIPHCLK_SDMMC1: + srcclk = __HAL_RCC_GET_SDMMC1_SOURCE(); + if (srcclk == RCC_SDMMC1CLKSOURCE_PLL1Q) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else if (srcclk == RCC_SDMMC1CLKSOURCE_PLL2R) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } + else + { + frequency = 0U; + } + break; +#endif /* SDMMC1 */ + +#if defined(SDMMC2) + case RCC_PERIPHCLK_SDMMC2: + srcclk = __HAL_RCC_GET_SDMMC2_SOURCE(); + if (srcclk == RCC_SDMMC2CLKSOURCE_PLL1Q) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else if (srcclk == RCC_SDMMC2CLKSOURCE_PLL2R) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } + else + { + frequency = 0U; + } + break; +#endif /* SDMMC2 */ + + case RCC_PERIPHCLK_USART1: + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); + + if (srcclk == RCC_USART1CLKSOURCE_PCLK2) + { + frequency = HAL_RCC_GetPCLK2Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART1CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } +#if defined(RCC_USART1CLKSOURCE_PLL3Q) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART1CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } +#endif /* RCC_USART1CLKSOURCE_PLL3Q */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART1 */ + else + { + frequency = 0U; + } + break; + + case RCC_PERIPHCLK_USART2: + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); + + if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART2CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } +#if defined(RCC_USART2CLKSOURCE_PLL3Q) + else if (srcclk == RCC_USART2CLKSOURCE_PLL3Q) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } +#endif /* RCC_USART2CLKSOURCE_PLL3Q */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART2 */ + else + { + frequency = 0U; + } + break; + + case RCC_PERIPHCLK_USART3: + /* Get the current USART3 source */ + srcclk = __HAL_RCC_GET_USART3_SOURCE(); + + if (srcclk == RCC_USART3CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART3CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } +#if defined(RCC_USART3CLKSOURCE_PLL3Q) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART3CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } +#endif /* RCC_USART3CLKSOURCE_PLL3Q */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART3 */ + else + { + frequency = 0U; + } + break; + +#if defined(UART4) + case RCC_PERIPHCLK_UART4: + /* Get the current UART4 source */ + srcclk = __HAL_RCC_GET_UART4_SOURCE(); + + if (srcclk == RCC_UART4CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART4CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } +#if defined(RCC_UART4CLKSOURCE_PLL3Q) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART4CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } +#endif /* RCC_UART4CLKSOURCE_PLL3Q */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART4 */ + else + { + frequency = 0U; + } + break; +#endif /* UART4 */ + +#if defined(UART5) + case RCC_PERIPHCLK_UART5: + /* Get the current UART5 source */ + srcclk = __HAL_RCC_GET_UART5_SOURCE(); + + if (srcclk == RCC_UART5CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART5CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } +#if defined(RCC_UART5CLKSOURCE_PLL3Q) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART5CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } +#endif /* RCC_UART5CLKSOURCE_PLL3Q */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART5 */ + else + { + frequency = 0U; + } + break; +#endif /* UART5 */ + +#if defined(USART6) + case RCC_PERIPHCLK_USART6: + /* Get the current USART6 source */ + srcclk = __HAL_RCC_GET_USART6_SOURCE(); + + if (srcclk == RCC_USART6CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART6CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } +#if defined(RCC_USART6CLKSOURCE_PLL3Q) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART6CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } +#endif /* RCC_USART6CLKSOURCE_PLL3Q */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART6CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART6 */ + else + { + frequency = 0U; + } + break; +#endif /* USART6 */ + +#if defined(UART7) + case RCC_PERIPHCLK_UART7: + /* Get the current UART7 source */ + srcclk = __HAL_RCC_GET_UART7_SOURCE(); + + if (srcclk == RCC_UART7CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART7CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } +#if defined(RCC_UART7CLKSOURCE_PLL3Q) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART7CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } +#endif /* RCC_UART7CLKSOURCE_PLL3Q */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART7CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART7CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART7CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART7 */ + else + { + frequency = 0U; + } + break; +#endif /* UART7 */ + +#if defined(UART8) + case RCC_PERIPHCLK_UART8: + /* Get the current UART8 source */ + srcclk = __HAL_RCC_GET_UART8_SOURCE(); + + if (srcclk == RCC_UART8CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART8CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } +#if defined(RCC_UART8CLKSOURCE_PLL3Q) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART8CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } +#endif /* RCC_UART8CLKSOURCE_PLL3Q */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART8CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART8CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART8CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART8 */ + else + { + frequency = 0U; + } + break; +#endif /* UART8 */ + +#if defined(UART9) + case RCC_PERIPHCLK_UART9: + /* Get the current UART9 source */ + srcclk = __HAL_RCC_GET_UART9_SOURCE(); + + if (srcclk == RCC_UART9CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART9CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART9CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART9CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART9CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART9CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART9 */ + else + { + frequency = 0U; + } + break; +#endif /* UART9 */ + +#if defined(USART10) + case RCC_PERIPHCLK_USART10: + /* Get the current USART10 source */ + srcclk = __HAL_RCC_GET_USART10_SOURCE(); + + if (srcclk == RCC_USART10CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART10CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART10CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART10CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART10CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART10CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART10 */ + else + { + frequency = 0U; + } + break; +#endif /* USART10 */ + +#if defined(USART11) + case RCC_PERIPHCLK_USART11: + /* Get the current USART11 source */ + srcclk = __HAL_RCC_GET_USART11_SOURCE(); + + if (srcclk == RCC_USART11CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART11CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART11CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART11CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART11CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART11CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART11 */ + else + { + frequency = 0U; + } + break; +#endif /* USART11 */ + +#if defined(UART12) + case RCC_PERIPHCLK_UART12: + /* Get the current UART12 source */ + srcclk = __HAL_RCC_GET_UART12_SOURCE(); + + if (srcclk == RCC_UART12CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART12CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART12CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART12CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART12CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART12CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART12 */ + else + { + frequency = 0U; + } + break; +#endif /* UART12 */ + + case RCC_PERIPHCLK_LPUART1: + /* Get the current LPUART1 source */ + srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); + + if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3) + { + frequency = HAL_RCC_GetPCLK3Freq(); + } + else if (srcclk == RCC_LPUART1CLKSOURCE_PLL2Q) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } +#if defined(RCC_LPUART1CLKSOURCE_PLL3Q) + else if (srcclk == RCC_LPUART1CLKSOURCE_PLL3Q) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } +#endif /* RCC_LPUART1CLKSOURCE_PLL3Q */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPUART1 */ + else + { + frequency = 0U; + } + break; + + case RCC_PERIPHCLK_ADCDAC: + /* Get the current ADCDAC source */ + srcclk = __HAL_RCC_GET_ADCDAC_SOURCE(); + + if (srcclk == RCC_ADCDACCLKSOURCE_HCLK) + { + frequency = HAL_RCC_GetHCLKFreq(); + } + else if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2R) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + /* Clock not enabled for ADCDAC */ + else + { + frequency = 0U; + } + break; + + + case RCC_PERIPHCLK_DAC_LP: + /* Get the current DAC low-power source */ + srcclk = __HAL_RCC_GET_DAC_LP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DACLPCLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DACLPCLKSOURCE_LSI)) + { + frequency = LSI_VALUE; + } + + /* Clock not enabled for DAC */ + else + { + frequency = 0U; + } + break; + + case RCC_PERIPHCLK_I2C1: + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + + if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } +#if defined(RCC_I2C1CLKSOURCE_PLL3R) + else if (srcclk == RCC_I2C1CLKSOURCE_PLL3R) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + } +#else + else if (srcclk == RCC_I2C1CLKSOURCE_PLL2R) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } +#endif /* RCC_I2C1CLKSOURCE_PLL3R */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + /* Clock not enabled for I2C1 */ + else + { + frequency = 0U; + } + break; + + case RCC_PERIPHCLK_I2C2: + /* Get the current I2C2 source */ + srcclk = __HAL_RCC_GET_I2C2_SOURCE(); + + if (srcclk == RCC_I2C2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } +#if defined(RCC_I2C2CLKSOURCE_PLL3R) + else if (srcclk == RCC_I2C2CLKSOURCE_PLL3R) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + } +#else + else if (srcclk == RCC_I2C2CLKSOURCE_PLL2R) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } +#endif /* RCC_I2C2CLKSOURCE_PLL3R */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + /* Clock not enabled for I2C2 */ + else + { + frequency = 0U; + } + break; + +#if defined(I2C3) + case RCC_PERIPHCLK_I2C3: + /* Get the current I2C3 source */ + srcclk = __HAL_RCC_GET_I2C3_SOURCE(); + + if (srcclk == RCC_I2C3CLKSOURCE_PCLK3) + { + frequency = HAL_RCC_GetPCLK3Freq(); + } +#if defined(RCC_I2C3CLKSOURCE_PLL3R) + else if (srcclk == RCC_I2C3CLKSOURCE_PLL3R) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + } +#else + else if (srcclk == RCC_I2C3CLKSOURCE_PLL2R) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } +#endif /* RCC_I2C3CLKSOURCE_PLL3R */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + /* Clock not enabled for I2C3 */ + else + { + frequency = 0U; + } + break; +#endif /* I2C3 */ + +#if defined(I2C4) + case RCC_PERIPHCLK_I2C4: + /* Get the current I2C4 source */ + srcclk = __HAL_RCC_GET_I2C4_SOURCE(); + + if (srcclk == RCC_I2C4CLKSOURCE_PCLK3) + { + frequency = HAL_RCC_GetPCLK3Freq(); + } + else if (srcclk == RCC_I2C4CLKSOURCE_PLL3R) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + /* Clock not enabled for I2C4 */ + else + { + frequency = 0U; + } + break; +#endif /* I2C4 */ + + case RCC_PERIPHCLK_I3C1: + /* Get the current I3C1 source */ + srcclk = __HAL_RCC_GET_I3C1_SOURCE(); + + if (srcclk == RCC_I3C1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } +#if defined(RCC_I3C1CLKSOURCE_PLL3R) + else if (srcclk == RCC_I3C1CLKSOURCE_PLL3R) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + } +#else + else if (srcclk == RCC_I3C1CLKSOURCE_PLL2R) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } +#endif /* RCC_I3C1CLKSOURCE_PLL3R */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I3C1CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + /* Clock not enabled for I3C1 */ + else + { + frequency = 0U; + } + break; + +#if defined(I3C2) + case RCC_PERIPHCLK_I3C2: + /* Get the current I3C2 source */ + srcclk = __HAL_RCC_GET_I3C2_SOURCE(); + if (srcclk == RCC_I3C2CLKSOURCE_PCLK3) + { + frequency = HAL_RCC_GetPCLK3Freq(); + } +#if defined(RCC_I3C1CLKSOURCE_PLL3R) + else if (srcclk == RCC_I3C2CLKSOURCE_PLL3R) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + } +#else + else if (srcclk == RCC_I3C2CLKSOURCE_PLL2R) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } +#endif /* RCC_I3C1CLKSOURCE_PLL3R */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I3C2CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } +#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I3C2CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } +#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */ + /* Clock not enabled for I3C2 */ + else + { + frequency = 0U; + } + break; +#endif /* I3C2*/ + + case RCC_PERIPHCLK_LPTIM1: + /* Get the current LPTIM1 source */ + srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); + + switch (srcclk) + { + case RCC_LPTIM1CLKSOURCE_PCLK3: + { + frequency = HAL_RCC_GetPCLK3Freq(); + break; + } + case RCC_LPTIM1CLKSOURCE_PLL2P: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } +#if defined(RCC_LPTIM1CLKSOURCE_PLL3R) + case RCC_LPTIM1CLKSOURCE_PLL3R: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + break; + } +#endif /* RCC_LPTIM1CLKSOURCE_PLL3R */ + case RCC_LPTIM1CLKSOURCE_LSE: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_LPTIM1CLKSOURCE_LSI: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) + { + frequency = LSI_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_LPTIM1CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM1 */ + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default : + { + frequency = 0U; + break; + } + } + break; + + case RCC_PERIPHCLK_LPTIM2: + /* Get the current LPTIM2 source */ + srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); + + switch (srcclk) + { + case RCC_LPTIM2CLKSOURCE_PCLK1: + { + frequency = HAL_RCC_GetPCLK1Freq(); + break; + } + case RCC_LPTIM2CLKSOURCE_PLL2P: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } +#if defined(RCC_LPTIM2CLKSOURCE_PLL3R) + case RCC_LPTIM2CLKSOURCE_PLL3R: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + break; + } +#endif /* RCC_LPTIM2CLKSOURCE_PLL3R */ + case RCC_LPTIM2CLKSOURCE_LSE: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_LPTIM2CLKSOURCE_LSI: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) + { + frequency = LSI_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_LPTIM2CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM2 */ + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default : + { + frequency = 0U; + break; + } + } + break; + +#if defined(LPTIM3) + case RCC_PERIPHCLK_LPTIM3: + /* Get the current LPTIM3 source */ + srcclk = __HAL_RCC_GET_LPTIM3_SOURCE(); + + switch (srcclk) + { + case RCC_LPTIM3CLKSOURCE_PCLK3: + { + frequency = HAL_RCC_GetPCLK3Freq(); + break; + } + case RCC_LPTIM3CLKSOURCE_PLL2P: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } + case RCC_LPTIM3CLKSOURCE_PLL3R: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + break; + } + case RCC_LPTIM3CLKSOURCE_LSE: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_LPTIM3CLKSOURCE_LSI: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) + { + frequency = LSI_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_LPTIM3CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM3 */ + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default : + { + frequency = 0U; + break; + } + } + break; +#endif /* LPTIM3 */ + +#if defined(LPTIM4) + case RCC_PERIPHCLK_LPTIM4: + /* Get the current LPTIM4 source */ + srcclk = __HAL_RCC_GET_LPTIM4_SOURCE(); + + switch (srcclk) + { + case RCC_LPTIM4CLKSOURCE_PCLK3: + { + frequency = HAL_RCC_GetPCLK3Freq(); + break; + } + case RCC_LPTIM4CLKSOURCE_PLL2P: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } + case RCC_LPTIM4CLKSOURCE_PLL3R: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + break; + } + case RCC_LPTIM4CLKSOURCE_LSE: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_LPTIM4CLKSOURCE_LSI: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) + { + frequency = LSI_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_LPTIM4CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM4 */ + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default : + { + frequency = 0U; + break; + } + } + break; +#endif /* LPTIM4 */ + +#if defined(LPTIM5) + case RCC_PERIPHCLK_LPTIM5: + /* Get the current LPTIM5 source */ + srcclk = __HAL_RCC_GET_LPTIM5_SOURCE(); + + switch (srcclk) + { + case RCC_LPTIM5CLKSOURCE_PCLK3: + { + frequency = HAL_RCC_GetPCLK3Freq(); + break; + } + case RCC_LPTIM5CLKSOURCE_PLL2P: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } + case RCC_LPTIM5CLKSOURCE_PLL3R: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + break; + } + case RCC_LPTIM5CLKSOURCE_LSE: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_LPTIM5CLKSOURCE_LSI: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) + { + frequency = LSI_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_LPTIM5CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM5 */ + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default : + { + frequency = 0U; + break; + } + } + break; +#endif /* LPTIM5 */ + +#if defined(LPTIM6) + case RCC_PERIPHCLK_LPTIM6: + /* Get the current LPTIM6 source */ + srcclk = __HAL_RCC_GET_LPTIM6_SOURCE(); + + switch (srcclk) + { + case RCC_LPTIM6CLKSOURCE_PCLK3: + { + frequency = HAL_RCC_GetPCLK3Freq(); + break; + } + case RCC_LPTIM6CLKSOURCE_PLL2P: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } + case RCC_LPTIM6CLKSOURCE_PLL3R: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + break; + } + case RCC_LPTIM6CLKSOURCE_LSE: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_LPTIM6CLKSOURCE_LSI: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) + { + frequency = LSI_VALUE; + } + else + { + frequency = 0U; + } + break; + } + case RCC_LPTIM6CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM6 */ + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default : + { + frequency = 0U; + break; + } + } + break; +#endif /* LPTIM6 */ + + case RCC_PERIPHCLK_FDCAN: + /* Get the current FDCAN kernel source */ + srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCANCLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else if (srcclk == RCC_FDCANCLKSOURCE_PLL1Q) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else if (srcclk == RCC_FDCANCLKSOURCE_PLL2Q) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + /* Clock not enabled for FDCAN */ + else + { + frequency = 0U; + } + break; + + case RCC_PERIPHCLK_SPI1: + /* Get the current SPI1 kernel source */ + srcclk = __HAL_RCC_GET_SPI1_SOURCE(); + switch (srcclk) + { + case RCC_SPI1CLKSOURCE_PLL1Q: + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_SPI1CLKSOURCE_PLL2P: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } +#if defined(RCC_SPI1CLKSOURCE_PLL3P) + case RCC_SPI1CLKSOURCE_PLL3P: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; + } +#endif /* RCC_SPI1CLKSOURCE_PLL3P */ + case RCC_SPI1CLKSOURCE_PIN: + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + case RCC_SPI1CLKSOURCE_CLKP: + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default: + { + frequency = 0U; + break; + } + } + break; + + case RCC_PERIPHCLK_SPI2: + /* Get the current SPI2 kernel source */ + srcclk = __HAL_RCC_GET_SPI2_SOURCE(); + switch (srcclk) + { + case RCC_SPI2CLKSOURCE_PLL1Q: + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_SPI2CLKSOURCE_PLL2P: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } +#if defined(RCC_SPI2CLKSOURCE_PLL3P) + case RCC_SPI2CLKSOURCE_PLL3P: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; + } +#endif /* RCC_SPI2CLKSOURCE_PLL3P */ + case RCC_SPI2CLKSOURCE_PIN: + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + case RCC_SPI2CLKSOURCE_CLKP: + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default: + { + frequency = 0U; + break; + } + } + break; + + case RCC_PERIPHCLK_SPI3: + /* Get the current SPI3 kernel source */ + srcclk = __HAL_RCC_GET_SPI3_SOURCE(); + switch (srcclk) + { + case RCC_SPI3CLKSOURCE_PLL1Q: + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_SPI3CLKSOURCE_PLL2P: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } +#if defined(RCC_SPI3CLKSOURCE_PLL3P) + case RCC_SPI3CLKSOURCE_PLL3P: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; + } +#endif /* RCC_SPI3CLKSOURCE_PLL3P */ + case RCC_SPI3CLKSOURCE_PIN: + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + case RCC_SPI3CLKSOURCE_CLKP: + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default: + { + frequency = 0U; + break; + } + } + break; + +#if defined(SPI4) + case RCC_PERIPHCLK_SPI4: + /* Get the current SPI4 kernel source */ + srcclk = __HAL_RCC_GET_SPI4_SOURCE(); + + if (srcclk == RCC_SPI4CLKSOURCE_PCLK2) + { + frequency = HAL_RCC_GetPCLK2Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_SPI4CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } +#if defined(RCC_SPI4CLKSOURCE_PLL3Q) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_SPI4CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } +#endif /* RCC_SPI4CLKSOURCE_PLL3Q */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SPI4CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_SPI4CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_SPI4CLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + /* Clock not enabled for SPI4 */ + else + { + frequency = 0U; + } + + break; +#endif /* SPI4 */ + +#if defined(SPI5) + case RCC_PERIPHCLK_SPI5: + /* Get the current SPI5 kernel source */ + srcclk = __HAL_RCC_GET_SPI5_SOURCE(); + + if (srcclk == RCC_SPI5CLKSOURCE_PCLK3) + { + frequency = HAL_RCC_GetPCLK3Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_SPI5CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_SPI5CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SPI5CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_SPI5CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_SPI5CLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + /* Clock not enabled for SPI5 */ + else + { + frequency = 0U; + } + + break; +#endif /* SPI5 */ + +#if defined(SPI6) + case RCC_PERIPHCLK_SPI6: + /* Get the current SPI6 kernel source */ + srcclk = __HAL_RCC_GET_SPI6_SOURCE(); + + if (srcclk == RCC_SPI6CLKSOURCE_PCLK2) + { + frequency = HAL_RCC_GetPCLK2Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_SPI6CLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_SPI6CLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SPI6CLKSOURCE_HSI)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_SPI6CLKSOURCE_CSI)) + { + frequency = CSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_SPI6CLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + /* Clock not enabled for SPI6 */ + else + { + frequency = 0U; + } + + break; +#endif /* SPI6 */ + +#if defined(OCTOSPI1) + case RCC_PERIPHCLK_OSPI: + /* Get the current OSPI kernel source */ + srcclk = __HAL_RCC_GET_OSPI_SOURCE(); + + switch (srcclk) + { + case RCC_OSPICLKSOURCE_HCLK: + { + frequency = HAL_RCC_GetHCLKFreq(); + break; + } + case RCC_OSPICLKSOURCE_PLL1Q: + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_OSPICLKSOURCE_PLL2R: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + break; + } + case RCC_OSPICLKSOURCE_CLKP: + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default: + { + frequency = 0U; + break; + } + } + break; +#endif /* OCTOSPI1*/ + +#if defined(CEC) + case RCC_PERIPHCLK_CEC: + /* Get the current CEC source */ + srcclk = __HAL_RCC_GET_CEC_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_CECCLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_CECCLKSOURCE_LSI)) + { + frequency = LSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_CECCLKSOURCE_CSI_DIV122)) + { + frequency = CSI_VALUE / 122U; + } + + /* Clock not enabled for CEC */ + else + { + frequency = 0U; + } + break; +#endif /* CEC */ + + case RCC_PERIPHCLK_RNG: + /* Get the current RNG source */ + srcclk = __HAL_RCC_GET_RNG_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48)) + { + frequency = HSI48_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) && (srcclk == RCC_RNGCLKSOURCE_PLL1Q)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RNGCLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RNGCLKSOURCE_LSI)) + { + frequency = LSI_VALUE; + } + + /* Clock not enabled for RNG */ + else + { + frequency = 0U; + } + break; + +#if defined(USB_DRD_FS) + case RCC_PERIPHCLK_USB: + /* Get the current USB kernel source */ + srcclk = __HAL_RCC_GET_USB_SOURCE(); + + if (srcclk == RCC_USBCLKSOURCE_PLL1Q) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } +#if defined(RCC_USBCLKSOURCE_PLL3Q) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USBCLKSOURCE_PLL3Q)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } +#else + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USBCLKSOURCE_PLL2Q)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } +#endif /* RCC_USBCLKSOURCE_PLL3 */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48)) + { + frequency = HSI48_VALUE; + } + /* Clock not enabled for USB */ + else + { + frequency = 0U; + } + + break; + + + default: + frequency = 0U; + break; +#endif /* USB_DRD_FS */ + +#if defined(PLAY1) + case RCC_PERIPHCLK_PLAY1: + /* Get the current PLAY1 kernel source */ + srcclk = __HAL_RCC_GET_PLAY1_SOURCE(); + + /* Get the current PLAY1 clock divider */ + play1_divider = __HAL_RCC_GET_PLAY1_DIV(); + switch (srcclk) + { + case RCC_PLAY1CLKSOURCE_PCLK3: + { + frequency = HAL_RCC_GetPCLK3Freq() >> (play1_divider >> RCC_CCIPR3_PLAY1DIV_Pos); + break; + } + case RCC_PLAY1CLKSOURCE_PLL2P: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency >> (play1_divider >> RCC_CCIPR3_PLAY1DIV_Pos); + break; + } +#if defined(RCC_PLAY1CLKSOURCE_PLL3R) + case RCC_PLAY1CLKSOURCE_PLL3R: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency >> (play1_divider >> RCC_CCIPR3_PLAY1DIV_Pos); + break; + } +#endif /* RCC_PLAY1CLKSOURCE_PLL3R */ + case RCC_PLAY1CLKSOURCE_LSE: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE >> (play1_divider >> RCC_CCIPR3_PLAY1DIV_Pos); + } + break; + } + case RCC_PLAY1CLKSOURCE_LSI: + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) + { + frequency = LSI_VALUE >> (play1_divider >> RCC_CCIPR3_PLAY1DIV_Pos); + } + break; + } + case RCC_PLAY1CLKSOURCE_CLKP: + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)) >> + (play1_divider >> RCC_CCIPR3_PLAY1DIV_Pos); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE >> (play1_divider >> RCC_CCIPR3_PLAY1DIV_Pos); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE >> (play1_divider >> RCC_CCIPR3_PLAY1DIV_Pos); + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + break; + } + + default: + { + frequency = 0U; + break; + } + } + break; +#endif /* PLAY1*/ +#if defined(USB_OTG_FS) + case RCC_PERIPHCLK_OTGFS: + /* Get the current USB_OTG_FS kernel source */ + srcclk = __HAL_RCC_GET_OTGFS_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_OTGFSCLKSOURCE_HSI48)) + { + frequency = HSI48_VALUE; + } + else if (srcclk == RCC_OTGFSCLKSOURCE_PLL1Q) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else if (srcclk == RCC_OTGFSCLKSOURCE_PLL3Q) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } +#if defined(PWR_USBSCR_OTGHSEN) + else if (srcclk == RCC_OTGFSCLKSOURCE_CLK48) + { + frequency = OTGHS_CLK48_VALUE; + } +#endif /* PWR_USBSCR_OTGHSEN */ + /* Clock not enabled for USB_OTG_FS */ + else + { + frequency = 0U; + } + break; +#endif /* USB_OTG_FS*/ +#if defined(USB_OTG_HS) + case RCC_PERIPHCLK_OTGHS: + /* Get the current USB_OTG_HS kernel source */ + srcclk = __HAL_RCC_GET_OTGHS_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (srcclk == RCC_OTGHSCLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else if (srcclk == RCC_OTGHSCLKSOURCE_PLL3Q) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (srcclk == RCC_OTGHSCLKSOURCE_HSE_DIV2)) + { + frequency = HSE_VALUE / 2 ; + } + else if (srcclk == RCC_OTGHSCLKSOURCE_PLL1Q_DIV2) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = (pll1_clocks.PLL1_P_Frequency) / 2U; + } + /* Clock not enabled for USB_OTG_HS */ + else + { + frequency = 0U; + } + break; +#endif /* USB_OTG_HS*/ + +#if defined(OCTOSPI2) + case RCC_PERIPHCLK_OSPI2: + /* Get the current OSPI2 kernel source */ + srcclk = __HAL_RCC_GET_OSPI2_SOURCE(); + + switch (srcclk) + { + case RCC_OSPI2CLKSOURCE_HCLK: + { + frequency = HAL_RCC_GetHCLKFreq(); + break; + } + case RCC_OSPI2CLKSOURCE_PLL1Q: + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_OSPI2CLKSOURCE_PLL2R: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + break; + } + case RCC_OSPI2CLKSOURCE_CLKP: + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default: + { + frequency = 0U; + break; + } + } + break; +#endif /* OCTOSPI2*/ + +#if defined (LTDC) + case RCC_PERIPHCLK_LTDC: + + /* Get the current LTDC kernel source */ + srcclk = __HAL_RCC_GET_LTDC_SOURCE(); + + switch (srcclk) + { + case RCC_LTDCCLKSOURCE_PLL3R: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + break; + } + case RCC_LTDCCLKSOURCE_PLL2R: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + break; + } + default: + { + frequency = 0U; + break; + } + } + break; +#endif /* LTDC */ + +#if defined (MDF1) + case RCC_PERIPHCLK_MDF1: + + /* Get the current MDF1 kernel source */ + srcclk = __HAL_RCC_GET_MDF1_SOURCE(); + + switch (srcclk) + { + case RCC_MDF1CLKSOURCE_PLL1Q: + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_MDF1CLKSOURCE_PLL2P: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } + case RCC_MDF1CLKSOURCE_PLL3P: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; + } + case RCC_MDF1CLKSOURCE_PIN: + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + case RCC_MDF1CLKSOURCE_CLKP: + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + + break; + } + default: + { + frequency = 0U; + break; + } + } + break; +#endif /* MDF1 */ + +#if defined(RCC_CCIPR4_ETHCLKSEL) + case RCC_PERIPHCLK_ETH: + + /* Get the current ETH kernel source */ + srcclk = __HAL_RCC_GET_ETH_SOURCE(); + switch (srcclk) + { + case RCC_ETHCLKSOURCE_PLL1Q: + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_ETHCLKSOURCE_HSE: + { + frequency = HSE_VALUE; + break; + } + default: + { + frequency = 0U; + break; + } + } + break; +#endif /* RCC_CCIPR4_ETHCLKSEL */ + +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) + case RCC_PERIPHCLK_ETHPTP: + /* Get the current ETHPTP kernel source */ + srcclk = __HAL_RCC_GET_ETHPTP_SOURCE(); + + /* Get the current ETHPTP clock divider */ + ethptp_divider = __HAL_RCC_GET_ETHPTP_DIV(); + + switch (srcclk) + { + case RCC_ETHPTPCLKSOURCE_HCLK: + { + frequency = HAL_RCC_GetHCLKFreq() / ethptp_divider; + break; + } + case RCC_ETHPTPCLKSOURCE_PLL1R: + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_R_Frequency / ethptp_divider; + break; + } + case RCC_ETHPTPCLKSOURCE_PLL1Q: + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency / ethptp_divider; + break; + } +#if defined(RCC_ETHPTPCLKSOURCE_PLL3P) + case RCC_ETHPTPCLKSOURCE_PLL3P: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency / ethptp_divider; + break; + } +#endif /* RCC_ETHPTPCLKSOURCE_PLL3P */ + default: + { + frequency = 0U; + break; + } + } + break; +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + +#if defined(RCC_CCIPR5_ETHREFCLKSEL) + case RCC_PERIPHCLK_ETHREF: + + /* Get the current ETHREF kernel source */ + srcclk = __HAL_RCC_GET_ETHREF_SOURCE(); + switch (srcclk) + { + case RCC_ETHREFCLKSOURCE_PLL1Q: + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_ETHREFCLKSOURCE_PLL1R: + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_R_Frequency; + break; + } + default: + { + frequency = 0U; + break; + } + } + break; +#endif /* RCC_CCIPR5_ETHREFCLKSEL */ + +#if defined (ADF1) + case RCC_PERIPHCLK_ADF1: + + /* Get the current ADF1 kernel source */ + srcclk = __HAL_RCC_GET_ADF1_SOURCE(); + switch (srcclk) + { + case RCC_ADF1CLKSOURCE_PLL1Q: + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_ADF1CLKSOURCE_PLL2P: + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } + case RCC_ADF1CLKSOURCE_PLL3P: + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; + } + case RCC_ADF1CLKSOURCE_PIN: + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + case RCC_ADF1CLKSOURCE_CLKP: + { + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0U; + } + break; + } + default: + { + frequency = 0U; + break; + } + } + break; +#endif /* ADF1 */ + } + } + return (frequency); +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of PLL2, PLL3, LSE CSS, + Low speed clock output and clock after wake-up from STOP mode. +@endverbatim + * @{ + */ + +/** + * @brief Initialize and Enable the PLL2 according to the specified + * parameters in the RCC_PLL2InitTypeDef. + * @param pPLL2Init pointer to an RCC_PLL2InitTypeDef structure that + * contains the configuration information for the PLL2 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *pPLL2Init) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* check for PLL2 Parameters used to output PLL2CLK */ + assert_param(IS_RCC_PLL2_SOURCE(pPLL2Init->PLL2Source)); + assert_param(IS_RCC_PLL2_DIVM_VALUE(pPLL2Init->PLL2M)); + assert_param(IS_RCC_PLL2_MULN_VALUE(pPLL2Init->PLL2N)); + assert_param(IS_RCC_PLL2_DIVP_VALUE(pPLL2Init->PLL2P)); + assert_param(IS_RCC_PLL2_DIVQ_VALUE(pPLL2Init->PLL2Q)); + assert_param(IS_RCC_PLL2_DIVR_VALUE(pPLL2Init->PLL2R)); + assert_param(IS_RCC_PLL2_CLOCKOUT_VALUE(pPLL2Init->PLL2ClockOut)); + assert_param(IS_RCC_PLL2_VCIRGE_VALUE(pPLL2Init->PLL2RGE)); + assert_param(IS_RCC_PLL2_VCORGE_VALUE(pPLL2Init->PLL2VCOSEL)); + assert_param(IS_RCC_PLL2_FRACN_VALUE(pPLL2Init->PLL2FRACN)); + + /* Disable the PLL2 */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready to be updated */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + + if (status == HAL_OK) + { + /* Make sure PLL2Source is ready */ + status = RCCEx_PLLSource_Enable(pPLL2Init->PLL2Source); + + if (status == HAL_OK) + { + /* Configure the PLL2 clock source, multiplication factor N, */ + /* and division factors M, P, Q and R */ + __HAL_RCC_PLL2_CONFIG(pPLL2Init->PLL2Source, pPLL2Init->PLL2M, pPLL2Init->PLL2N, + pPLL2Init->PLL2P, pPLL2Init->PLL2Q, pPLL2Init->PLL2R); + + /* Disable PLL2FRACN . */ + __HAL_RCC_PLL2_FRACN_DISABLE(); + + /* Configure PLL2 FRACN */ + __HAL_RCC_PLL2_FRACN_CONFIG(pPLL2Init->PLL2FRACN); + + /* Enable PLL2FRACN */ + __HAL_RCC_PLL2_FRACN_ENABLE(); + + /* Select PLL2 input reference frequency range: VCI */ + __HAL_RCC_PLL2_VCIRANGE(pPLL2Init->PLL2RGE); + + /* Select PLL2 output frequency range : VCO */ + __HAL_RCC_PLL2_VCORANGE(pPLL2Init->PLL2VCOSEL); + + /* Configure the PLL2 Clock output(s) */ + __HAL_RCC_PLL2_CLKOUT_ENABLE(pPLL2Init->PLL2ClockOut); + + /* Enable the PLL2 again by setting PLL2ON to 1*/ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + } + } + + return status; +} + +/** + * @brief Disable PLL2. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* Disable the PLL2 */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + + /* To save power, disable the PLL2 Source, FRACN and Clock outputs */ + CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_PLL2CFGR_PLL2SRC | + RCC_PLL2CFGR_PLL2FRACEN); + + return status; +} + +#if defined(RCC_CR_PLL3ON) +/** + * @brief Initialize and Enable the PLL3 according to the specified + * parameters in the RCC_PLL3InitTypeDef. + * @param pPLL3Init pointer to an RCC_PLL3InitTypeDef structure that + * contains the configuration information for the PLL3 + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *pPLL3Init) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* check for PLL3 Parameters used to output PLL3CLK */ + assert_param(IS_RCC_PLL3_SOURCE(pPLL3Init->PLL3Source)); + assert_param(IS_RCC_PLL3_DIVM_VALUE(pPLL3Init->PLL3M)); + assert_param(IS_RCC_PLL3_MULN_VALUE(pPLL3Init->PLL3N)); + assert_param(IS_RCC_PLL3_DIVP_VALUE(pPLL3Init->PLL3P)); + assert_param(IS_RCC_PLL3_DIVQ_VALUE(pPLL3Init->PLL3Q)); + assert_param(IS_RCC_PLL3_DIVR_VALUE(pPLL3Init->PLL3R)); + assert_param(IS_RCC_PLL3_CLOCKOUT_VALUE(pPLL3Init->PLL3ClockOut)); + assert_param(IS_RCC_PLL3_VCIRGE_VALUE(pPLL3Init->PLL3RGE)); + assert_param(IS_RCC_PLL3_VCORGE_VALUE(pPLL3Init->PLL3VCOSEL)); + assert_param(IS_RCC_PLL3_FRACN_VALUE(pPLL3Init->PLL3FRACN)); + + /* Disable the PLL3 */ + __HAL_RCC_PLL3_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL3 is ready to be updated */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + + if (status == HAL_OK) + { + /* Make sure PLL3Source is ready */ + status = RCCEx_PLLSource_Enable(pPLL3Init->PLL3Source); + + if (status == HAL_OK) + { + /* Configure the PLL3 clock source, multiplication factor N, */ + /* and division factors M and P */ + __HAL_RCC_PLL3_CONFIG(pPLL3Init->PLL3Source, pPLL3Init->PLL3M, pPLL3Init->PLL3N, pPLL3Init->PLL3P, + pPLL3Init->PLL3Q, pPLL3Init->PLL3R); + + /* Disable PLL3FRACN . */ + __HAL_RCC_PLL3_FRACN_DISABLE(); + + /* Configure PLL3 FRACN */ + __HAL_RCC_PLL3_FRACN_CONFIG(pPLL3Init->PLL3FRACN); + + /* Enable PLL3FRACN . */ + __HAL_RCC_PLL3_FRACN_ENABLE(); + + /* Select PLL3 input reference frequency range: VCI */ + __HAL_RCC_PLL3_VCIRANGE(pPLL3Init->PLL3RGE); + + /* Select PLL3 output frequency range : VCO */ + __HAL_RCC_PLL3_VCORANGE(pPLL3Init->PLL3VCOSEL); + + /* Configure the PLL3 Clock output(s) */ + __HAL_RCC_PLL3_CLKOUT_ENABLE(pPLL3Init->PLL3ClockOut); + + /* Enable the PLL3 again by setting PLL3ON to 1*/ + __HAL_RCC_PLL3_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL3 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + } + } + + return status; +} + + +/** + * @brief Disable PLL3. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* Disable the PLL3 */ + __HAL_RCC_PLL3_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL3 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + + /* To save power, disable the PLL3 Source and Clock outputs */ + CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_PLL3CFGR_PLL3SRC | + RCC_PLL3CFGR_PLL3FRACEN); + + return status; +} +#endif /* RCC_CR_PLL3ON */ + +/** + * @brief Configure the oscillator clock source for wakeup from Stop and HSE CSS backup clock. + * @param WakeUpClk Wakeup clock + * This parameter can be one of the following values: + * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection + * @arg @ref RCC_STOP_WAKEUPCLOCK_CSI CSI oscillator selection + * @note This function shall not be called after the Clock Security System on HSE has been + * enabled. + * @retval None + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +/** + * @brief Configure the oscillator Kernel clock source for wakeup from Stop + * @param WakeUpClk: Kernel Wakeup clock + * This parameter can be one of the following values: + * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection + * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection + * @retval None + */ +void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +/** + * @brief Enable the LSE Clock Security System. + * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled + * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC + * clock with HAL_RCCEx_PeriphCLKConfig(). + * @retval None + */ +void HAL_RCCEx_EnableLSECSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Disable the LSE Clock Security System. + * @note LSE Clock Security System can only be disabled after a LSE failure detection. + * @retval None + */ +void HAL_RCCEx_DisableLSECSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Handle the RCC LSE Clock Security System interrupt request. + * @retval None + */ +void HAL_RCCEx_LSECSS_IRQHandler(void) +{ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) != 0U) + { + /* RCC LSE Clock Security System interrupt user callback */ + HAL_RCCEx_LSECSS_Callback(); + } +} + +/** + * @brief RCCEx LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_LSECSS_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + */ +} + +/** + * @brief Select the Low Speed Microcontroller Clock source to output on LSCO pin (PB2). + * @param LSCOSource specifies the Low Speed clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source + * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source + * @retval None + */ +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) +{ + FlagStatus backupchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); + + /* Update LSCOSEL clock source in Backup Domain control register */ + if (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP)) + { + HAL_PWR_EnableBkUpAccess(); + backupchanged = SET; + } + + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); + + if (backupchanged == SET) + { + HAL_PWR_DisableBkUpAccess(); + } +} + +/** + * @brief Disable the Low Speed Microcontroller Clock Output. + * @retval None + */ +void HAL_RCCEx_DisableLSCO(void) +{ + FlagStatus backupchanged = RESET; + + /* Update LSCOEN bit in Backup Domain control register */ + if (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP)) + { + /* Enable access to the backup domain */ + HAL_PWR_EnableBkUpAccess(); + backupchanged = SET; + } + + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); + + /* Restore previous configuration */ + if (backupchanged == SET) + { + /* Disable access to the backup domain */ + HAL_PWR_DisableBkUpAccess(); + } +} + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and synchronization frequencies values + (##) Call function HAL_RCCEx_CRSConfig which + (+++) Resets CRS registers to their default values. + (+++) Configures CRS registers with synchronization configuration + (+++) Enables automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (CRS_IRQn/CRS_IRQHandler) + (++) Call function HAL_RCCEx_CRSConfig() + (++) Enable CRS_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) HAL_RCCEx_CRS_SyncOkCallback() + (+++) HAL_RCCEx_CRS_SyncWarnCallback() + (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit) +{ + uint32_t value; + + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); + + /* Set the SYNCDIV[2:0] bits according to Prescaler value */ + /* Set the SYNCSRC[1:0] bits according to Source value */ + /* Set the SYNCSPOL bit according to Polarity value */ + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + value |= pInit->ReloadValue; + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); + WRITE_REG(CRS->CFGR, value); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +} + +/** + * @brief Generate the software synchronization event + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Return synchronization info + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != (void *)NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); + + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Wait for CRS Synchronization status. + * @param Timeout Duration of the timeout + * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization + * frequency. + * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. + * @retval Combination of Synchronization status + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_TIMEOUT + * @arg @ref RCC_CRS_SYNCOK + * @arg @ref RCC_CRS_SYNCWARN + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + */ +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + uint32_t crsstatus = RCC_CRS_NONE; + uint32_t tickstart; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait for CRS flag or timeout detection */ + do + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARN; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOVF; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } while (RCC_CRS_NONE == crsstatus); + + return crsstatus; +} + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) + { + if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) + { + crserror |= RCC_CRS_SYNCERR; + } + if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) + { + crserror |= RCC_CRS_SYNCMISS; + } + if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/** @addtogroup RCCEx_Private_Functions + * @{ + */ + +/** + * @brief Enable PLLx source clock and check ready flag + * @param PllSource contains the selected PLLx source clock (HSE, HSI or CSI) + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + switch (PllSource) + { + case RCC_PLL1_SOURCE_CSI: + /* Check whether CSI in not ready and enable it */ + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U) + { + /* Enable the Internal Low power oscillator (CSI). */ + __HAL_RCC_CSI_ENABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till CSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_CSI_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + } + break; + + case RCC_PLL1_SOURCE_HSI: + /* Check whether HSI in not ready and enable it */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + } + break; + + case RCC_PLL1_SOURCE_HSE: + /* Check whether HSE in not ready and enable it */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + /* Enable the External High Speed oscillator (HSE). */ + SET_BIT(RCC->CR, RCC_CR_HSEON); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + break; + } + } + } + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Configure the PLL2 VCI/VCO ranges, multiplication and division factors and its output clock(s) + * @param pll2 pointer to an RCC_PLL2InitTypeDef structure that + * contains the configuration parameters M, N, FRACN, VCI/VCO ranges as well as PLL2 output clocks dividers + * @note PLL2 is temporary disabled to apply new parameters + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2) +{ + + uint32_t tickstart; + assert_param(IS_RCC_PLL2_SOURCE(pll2->PLL2Source)); + assert_param(IS_RCC_PLL2_DIVM_VALUE(pll2->PLL2M)); + assert_param(IS_RCC_PLL2_MULN_VALUE(pll2->PLL2N)); + assert_param(IS_RCC_PLL2_DIVP_VALUE(pll2->PLL2P)); + assert_param(IS_RCC_PLL2_DIVQ_VALUE(pll2->PLL2Q)); + assert_param(IS_RCC_PLL2_DIVR_VALUE(pll2->PLL2R)); + assert_param(IS_RCC_PLL2_CLOCKOUT_VALUE(pll2->PLL2ClockOut)); + assert_param(IS_RCC_PLL2_VCIRGE_VALUE(pll2->PLL2RGE)); + assert_param(IS_RCC_PLL2_VCORGE_VALUE(pll2->PLL2VCOSEL)); + assert_param(IS_RCC_PLL2_FRACN_VALUE(pll2->PLL2FRACN)); + + /* Disable PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure PLL2 multiplication and division factors. */ + __HAL_RCC_PLL2_CONFIG(pll2->PLL2Source, + pll2->PLL2M, + pll2->PLL2N, + pll2->PLL2P, + pll2->PLL2Q, + pll2->PLL2R); + + /* Select PLL2 input reference frequency range: VCI */ + __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE); + + /* Select PLL2 output frequency range : VCO */ + __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL); + + /* Configure the PLL2 Clock output(s) */ + __HAL_RCC_PLL2_CLKOUT_ENABLE(pll2->PLL2ClockOut); + + /* Disable PLL2FRACN . */ + __HAL_RCC_PLL2_FRACN_DISABLE(); + + /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ + __HAL_RCC_PLL2_FRACN_CONFIG(pll2->PLL2FRACN); + + /* Enable PLL2FRACN . */ + __HAL_RCC_PLL2_FRACN_ENABLE(); + + /* Enable PLL2. */ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; + +} + +#if defined(RCC_CR_PLL3ON) +/** + * @brief Configure the PLL3 VCI/VCO ranges, multiplication and division factors and its output clock(s) + * @param pll3 pointer to an RCC_PLL3InitTypeDef structure that + * contains the configuration parameters M, N, FRACN, VCI/VCO ranges as well as PLL3 output clocks dividers + * @note PLL3 is temporary disabled to apply new parameters + * @retval HAL status. + */ +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3) +{ + + uint32_t tickstart; + assert_param(IS_RCC_PLL3_SOURCE(pll3->PLL3Source)); + assert_param(IS_RCC_PLL3_DIVM_VALUE(pll3->PLL3M)); + assert_param(IS_RCC_PLL3_MULN_VALUE(pll3->PLL3N)); + assert_param(IS_RCC_PLL3_DIVP_VALUE(pll3->PLL3P)); + assert_param(IS_RCC_PLL3_DIVQ_VALUE(pll3->PLL3Q)); + assert_param(IS_RCC_PLL3_DIVR_VALUE(pll3->PLL3R)); + assert_param(IS_RCC_PLL3_CLOCKOUT_VALUE(pll3->PLL3ClockOut)); + assert_param(IS_RCC_PLL3_VCIRGE_VALUE(pll3->PLL3RGE)); + assert_param(IS_RCC_PLL3_VCORGE_VALUE(pll3->PLL3VCOSEL)); + assert_param(IS_RCC_PLL3_FRACN_VALUE(pll3->PLL3FRACN)); + + /* Disable PLL3. */ + __HAL_RCC_PLL3_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL3 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure PLL3 multiplication and division factors. */ + __HAL_RCC_PLL3_CONFIG(pll3->PLL3Source, + pll3->PLL3M, + pll3->PLL3N, + pll3->PLL3P, + pll3->PLL3Q, + pll3->PLL3R); + + /* Select PLL3 input reference frequency range: VCI */ + __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; + + /* Select PLL3 output frequency range : VCO */ + __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL); + + /* Configure the PLL3 Clock output(s) */ + __HAL_RCC_PLL3_CLKOUT_ENABLE(pll3->PLL3ClockOut); + + /* Disable PLL3FRACN . */ + __HAL_RCC_PLL3_FRACN_DISABLE(); + + /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ + __HAL_RCC_PLL3_FRACN_CONFIG(pll3->PLL3FRACN); + + /* Enable PLL3FRACN . */ + __HAL_RCC_PLL3_FRACN_ENABLE(); + + /* Enable PLL3. */ + __HAL_RCC_PLL3_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL3 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} +#endif /* RCC_CR_PLL3ON */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c new file mode 100644 index 00000000..06735604 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c @@ -0,0 +1,4854 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) UART interrupts handling: + -@@- The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. + (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware + flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + in the huart handle AdvancedInit structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + by calling the HAL_LIN_Init() API. + + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] + (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), + also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customized HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ + USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ + +#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ +#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +#if defined(HAL_DMA_MODULE_ENABLED) +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup UART_Private_variables + * @{ + */ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +/** + * @} + */ + +/* Exported Constants --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + and UART multiprocessor mode configuration procedures (details for the procedures + are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the UART mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Initialize the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + /* LIN mode limited to 8-bit data length */ + if (huart->Init.WordLength != UART_WORDLENGTH_8B) + { + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In LIN mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + * @note If the user resorts to idle line detection wake up, the Address parameter + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection, the API + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the wake up method parameter */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In multiprocessor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + { + /* If address mark wake up method is chosen, set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); + } + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief DeInitialize the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + + huart->gState = HAL_UART_STATE_BUSY; + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Initialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used to override the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = pCallback; + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = pCallback; + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = pCallback; + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: + (++) HAL_UARTEx_RxEventCallback() + + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (const uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) + { + huart->TxXferCount--; + } + else + { + /* Process was aborted during the transmission */ + return HAL_ERROR; + } + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + huart->RxXferCount--; + } + else + { + /* Process was aborted during the reception */ + return HAL_ERROR; + } + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + huart->TxISR = NULL; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Configure Tx interrupt processing */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT_FIFOEN; + } + else + { + huart->TxISR = UART_TxISR_8BIT_FIFOEN; + } + + /* Enable the TX FIFO threshold interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + } + else + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + /* Enable the Transmit Data Register Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_IT(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + +#endif /* USART_DMAREQUESTS_SW_WA */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((huart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((huart->hdmatx->LinkedListQueue != NULL) && (huart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)huart->pTxBuffPtr; + + /* Set DMA destination address */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&huart->Instance->TDR; + + /* Enable the UART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(huart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the UART transmit DMA channel */ + status = HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, nbByte); + } + + if (status != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + +#endif /* USART_DMAREQUESTS_SW_WA */ + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_DMA(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + /* Suspend the UART DMA Tx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + /* Suspend the UART DMA Rx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmarx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Resume the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Resume the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmarx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t abortcplt = 1U; + + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable DMA Tx at UART level */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (huart->hdmarx->Mode != DMA_LINKEDLIST_CIRCULAR) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } + return; + } + else + { +#endif /* HAL_DMA_MODULE_ENABLED */ + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; +#if defined(HAL_DMA_MODULE_ENABLED) + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + + /* UART Rx state is not reset as a reception process might be ongoing. + If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } + return; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + UART_EndTransmit_IT(huart); + return; + } + + /* UART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + huart->TxFifoEmptyCallback(huart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_UARTEx_TxFifoEmptyCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + huart->RxFifoFullCallback(huart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_UARTEx_RxFifoFullCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode + (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) UART_SetConfig() API configures the UART peripheral + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_LIN_SendBreak() API transmits the break characters +@endverbatim + * @{ + */ + +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); + } +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable USART mute mode by setting the MME bit in the CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Enter UART mute mode (means UART actually enters mute mode). + * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart UART handle. + * @retval None + */ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +} + +/** + * @brief Enable the UART transmitter and disable the UART receiver. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the UART receiver and disable the UART transmitter. + * @param huart UART handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + + +/** + * @brief Transmit break characters. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief UART Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the UART handle state. + (+) Return the UART handle error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the UART handle state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) +{ + uint32_t temp1; + uint32_t temp2; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART handle error code. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint16_t brrtemp; + uint32_t clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t lpuart_ker_ck_pres; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + if (UART_INSTANCE_LOWPOWER(huart)) + { + assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); + } + else + { + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + } + + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + + if (!(UART_INSTANCE_LOWPOWER(huart))) + { + tmpreg |= huart->Init.OneBitSampling; + } + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ + MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + + /* Check LPUART instance */ + if (UART_INSTANCE_LOWPOWER(huart)) + { + /* Retrieve frequency clock */ + pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource); + + /* If proper clock source reported */ + if (pclk != 0U) + { + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + { + ret = HAL_ERROR; + } + else + { + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ + } + /* Check UART Over Sampling to set Baud Rate Register */ + else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource); + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + } + } + else + { + pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource); + + if (pclk != 0U) + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = (uint16_t)usartdiv; + } + else + { + ret = HAL_ERROR; + } + } + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + huart->NbTxDataToProcess = 1; + huart->NbRxDataToProcess = 1; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + return ret; +} + +/** + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + } +} + +/** + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status The actual Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + + return HAL_TIMEOUT; + } + + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + } + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((huart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((huart->hdmarx->LinkedListQueue != NULL) && (huart->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&huart->Instance->RDR; + + /* Set DMA destination address */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)huart->pRxBuffPtr; + + /* Enable the UART receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(huart->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the UART receive DMA channel */ + status = HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, nbByte); + } + + if (status != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + + /* Enable the UART Parity Error Interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, TXFT interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; +} + + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + huart->TxXferCount = 0U; + +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + huart->RxXferCount = 0; + + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +{ + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_8BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_16BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c new file mode 100644 index 00000000..bf5efdb7 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c @@ -0,0 +1,1056 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_uart_ex.c + * @author MCD Application Team + * @brief Extended UART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### UART peripheral extended features ##### + ============================================================================== + [..] + (#) Declare a UART_HandleTypeDef handle structure. + + (#) For the UART RS485 Driver Enable mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When UART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup UARTEx UARTEx + * @brief UART Extended HAL module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UARTEX_Private_Constants UARTEx Private Constants + * @{ + */ +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UARTEx_Private_Functions UARTEx Private Functions + * @{ + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ + +/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Extended Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + procedures (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) +{ + uint32_t temp; + + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of Wakeup and FIFO mode related callback functions. + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() + (#) TX/RX Fifos Callbacks: + (++) HAL_UARTEx_RxFifoFullCallback() + (++) HAL_UARTEx_TxFifoEmptyCallback() +@endverbatim + * @{ + */ + +/** + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + +/** + * @brief UART RX Fifo full callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief UART TX Fifo empty callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. + (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + trigger: address match, Start Bit detection or RXNE bit status. + (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + (+) HAL_UARTEx_DisableStopMode() API disables the above functionality + (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (+++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (++) Detection that a specific character has been received. + + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (++) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (++) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (++) HAL_UARTEx_ReceiveToIdle_DMA() + +@endverbatim + * @{ + */ + +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Set Wakeup from Stop mode interrupt flag selection. + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* check the wake-up from stop mode UART instance */ + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + status = HAL_TIMEOUT; + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Enable UART Stop Mode. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UESM bit */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UESM bit */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_ENABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Disable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_DISABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param huart UART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_TXFIFO_THRESHOLD_1_8 + * @arg @ref UART_TXFIFO_THRESHOLD_1_4 + * @arg @ref UART_TXFIFO_THRESHOLD_1_2 + * @arg @ref UART_TXFIFO_THRESHOLD_3_4 + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param huart UART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_RXFIFO_THRESHOLD_1_8 + * @arg @ref UART_RXFIFO_THRESHOLD_1_4 + * @arg @ref UART_RXFIFO_THRESHOLD_1_2 + * @arg @ref UART_RXFIFO_THRESHOLD_3_4 + * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update RX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + (void)UART_Start_Receive_IT(huart, pData, Size); + + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return (huart->RxEventType); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Private_Functions + * @{ + */ + +/** + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); +} + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the UART configuration registers. + * @param huart UART handle. + * @retval None + */ +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (huart->FifoMode == UART_FIFOMODE_DISABLE) + { + huart->NbTxDataToProcess = 1U; + huart->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c new file mode 100644 index 00000000..f6b06cf8 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c @@ -0,0 +1,4032 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_usart.c + * @author MCD Application Team + * @brief USART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter + * Peripheral (USART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The USART HAL driver can be used as follows: + + (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart). + (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) USART pins configuration: + (+++) Enable the clock for the USART GPIOs. + (+++) Configure these USART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(), + HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) USART interrupts handling: + -@@- The specific USART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process. + (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA() + HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode + (Receiver/Transmitter) in the husart handle Init structure. + + (#) Initialize the USART registers by calling the HAL_USART_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_USART_MspInit(&husart) API. + + [..] + (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's + HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and + HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_USART_RegisterCallback() to register a user callback. + Function HAL_USART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_USART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + + [..] + By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_USART_Init() + and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit() + or HAL_USART_Init() function. + + [..] + When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup USART USART + * @brief HAL USART Synchronous SPI module driver + * @{ + */ + +#ifdef HAL_USART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup USART_Private_Constants USART Private Constants + * @{ + */ +#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */ +#define USART_TEACK_REACK_TIMEOUT 1000U /*!< USART TX or RX enable acknowledge time-out value */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \ + USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by USART_SetConfig API */ + +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \ + USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \ + USART_CR2_DIS_NSS)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */ + +#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */ +#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup USART_Private_Functions + * @{ + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +static void USART_EndTransfer(USART_HandleTypeDef *husart); +#if defined(HAL_DMA_MODULE_ENABLED) +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAError(DMA_HandleTypeDef *hdma); +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart); +static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart); +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart); +static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in synchronous SPI master/slave mode. + (+) For the synchronous SPI mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) USART polarity + (++) USART phase + (++) USART LastBit + (++) Receiver/transmitter modes + + [..] + The HAL_USART_Init() function follows the USART synchronous SPI configuration + procedure (details for the procedure are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible USART formats are listed in the + following table. + + Table 1. USART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | USART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the USART mode according to the specified + * parameters in the USART_InitTypeDef and initialize the associated handle. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if (husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + if (husart->State == HAL_USART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + husart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + USART_InitCallbacksToDefault(husart); + + if (husart->MspInitCallback == NULL) + { + husart->MspInitCallback = HAL_USART_MspInit; + } + + /* Init the low level hardware */ + husart->MspInitCallback(husart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_USART_MspInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + + husart->State = HAL_USART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_USART_DISABLE(husart); + + /* Set the Usart Communication parameters */ + if (USART_SetConfig(husart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In Synchronous SPI mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register. + */ + husart->Instance->CR2 &= ~USART_CR2_LINEN; + husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + + /* Enable the Peripheral */ + __HAL_USART_ENABLE(husart); + + /* TEACK and/or REACK to check before moving husart->State to Ready */ + return (USART_CheckIdleState(husart)); +} + +/** + * @brief DeInitialize the USART peripheral. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if (husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + husart->State = HAL_USART_STATE_BUSY; + + husart->Instance->CR1 = 0x0U; + husart->Instance->CR2 = 0x0U; + husart->Instance->CR3 = 0x0U; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + if (husart->MspDeInitCallback == NULL) + { + husart->MspDeInitCallback = HAL_USART_MspDeInit; + } + /* DeInit the low level hardware */ + husart->MspDeInitCallback(husart); +#else + /* DeInit the low level hardware */ + HAL_USART_MspDeInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Initialize the USART MSP. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the USART MSP. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User USART Callback + * To be used to override the weak predefined callback + * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID + * @param husart usart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status ++ */ +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (husart->State == HAL_USART_STATE_READY) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = pCallback; + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = pCallback; + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = pCallback; + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = pCallback; + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = pCallback; + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = pCallback; + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = pCallback; + break; + + case HAL_USART_RX_FIFO_FULL_CB_ID : + husart->RxFifoFullCallback = pCallback; + break; + + case HAL_USART_TX_FIFO_EMPTY_CB_ID : + husart->TxFifoEmptyCallback = pCallback; + break; + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (husart->State == HAL_USART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an USART Callback + * USART callaback is redirected to the weak predefined callback + * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID + * @param husart usart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_USART_STATE_READY == husart->State) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_USART_RX_FIFO_FULL_CB_ID : + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_USART_TX_FIFO_EMPTY_CB_ID : + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_USART_STATE_RESET == husart->State) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group2 IO operation functions + * @brief USART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI + data transfers. + + [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input). + + [..] + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (++) HAL_USART_Transmit() in simplex mode + (++) HAL_USART_Receive() in full duplex receive only + (++) HAL_USART_TransmitReceive() in full duplex mode + + (#) Non-Blocking mode API's with Interrupt are : + (++) HAL_USART_Transmit_IT() in simplex mode + (++) HAL_USART_Receive_IT() in full duplex receive only + (++) HAL_USART_TransmitReceive_IT() in full duplex mode + (++) HAL_USART_IRQHandler() + + (#) No-Blocking mode API's with DMA are : + (++) HAL_USART_Transmit_DMA() in simplex mode + (++) HAL_USART_Receive_DMA() in full duplex receive only + (++) HAL_USART_TransmitReceive_DMA() in full duplex mode + (++) HAL_USART_DMAPause() + (++) HAL_USART_DMAResume() + (++) HAL_USART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (++) HAL_USART_TxCpltCallback() + (++) HAL_USART_RxCpltCallback() + (++) HAL_USART_TxHalfCpltCallback() + (++) HAL_USART_RxHalfCpltCallback() + (++) HAL_USART_ErrorCallback() + (++) HAL_USART_TxRxCpltCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_USART_Abort() + (++) HAL_USART_Abort_IT() + + (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided: + (++) HAL_USART_AbortCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify + error type, and HAL_USART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on USART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, + and HAL_USART_ErrorCallback() user callback is executed. + +@endverbatim + * @{ + */ + +/** + * @brief Simplex send an amount of data in blocking mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout) +{ + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + ptxdata8bits = NULL; + ptxdata16bits = (const uint16_t *) pTxData; + } + else + { + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + } + + /* Check the remaining data to be sent */ + while (husart->TxXferCount > 0U) + { + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear Transmission Complete Flag */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + + /* At end of Tx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->RxXferSize = Size; + husart->RxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + uhMask = husart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + prxdata16bits = NULL; + } + + /* as long as data have to be received */ + while (husart->RxXferCount > 0U) + { + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) + { + /* Wait until TXE flag is set to send dummy byte in order to generate the + * clock for the slave to send data. + * Whatever the frame length (7, 8 or 9-bit long), the same dummy value + * can be written for all the cases. */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); + } + + /* Wait for RXNE Flag */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (prxdata8bits == NULL) + { + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; + } + else + { + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + prxdata8bits++; + } + + husart->RxXferCount--; + + } + + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* At end of Rx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send and Receive an amount of data in blocking mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; + uint16_t uhMask; + uint16_t rxdatacount; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->RxXferSize = Size; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + husart->RxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + uhMask = husart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + ptxdata8bits = NULL; + ptxdata16bits = (const uint16_t *) pTxData; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + prxdata16bits = NULL; + } + + if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE)) + { + /* Wait until TXE flag is set to send data */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + /* Check the remain data to be sent */ + /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + rxdatacount = husart->RxXferCount; + while ((husart->TxXferCount > 0U) || (rxdatacount > 0U)) + { + if (husart->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + if (husart->RxXferCount > 0U) + { + /* Wait for RXNE Flag */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (prxdata8bits == NULL) + { + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; + } + else + { + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + prxdata8bits++; + } + + husart->RxXferCount--; + } + rxdatacount = husart->RxXferCount; + } + + /* At end of TxRx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) +{ + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + husart->TxISR = NULL; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* The USART Error Interrupts: (Frame error, noise error, overrun error) + are not managed by the USART Transmit Process to avoid the overrun interrupt + when the usart mode is configured for transmit and receive "USART_MODE_TX_RX" + to benefit for the frame error and noise interrupts the usart mode should be + configured only for transmit "USART_MODE_TX" */ + + /* Configure Tx interrupt processing */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT_FIFOEN; + } + else + { + husart->TxISR = USART_TxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the TX FIFO threshold interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT); + } + else + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Transmit Data Register Empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + uint16_t nb_dummy_data; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + husart->RxISR = NULL; + + USART_MASK_COMPUTATION(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->RxISR = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->RxISR = USART_RxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->RxISR = USART_RxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error and Data Register not empty Interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) + { + /* Send dummy data in order to generate the clock for the Slave to send the next data. + When FIFO mode is disabled only one data must be transferred. + When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold. + */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--) + { + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + else + { + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + /* Configure TxRx interrupt processing */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT_FIFOEN; + husart->RxISR = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->TxISR = USART_TxISR_8BIT_FIFOEN; + husart->RxISR = USART_RxISR_8BIT_FIFOEN; + } + + /* Process Locked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the TX and RX FIFO Threshold interrupts */ + SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE)); + } + else + { + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + husart->RxISR = USART_RxISR_8BIT; + } + + /* Process Locked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + + /* Enable the USART Transmit Data Register Empty Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + const uint32_t *tmp; + uint16_t nbByte = Size; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + if (husart->hdmatx != NULL) + { + /* Set the USART DMA transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the DMA error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + tmp = (const uint32_t *)&pTxData; + + /* Check linked list mode */ + if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; + + /* Set DMA destination address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->TDR; + + /* Enable the USART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the USART transmit DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + } + } + + if (status == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the USART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t *tmp = (uint32_t *)&pRxData; + uint16_t nbByte = Size; + + /* Check that a Rx process is not already ongoing */ + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pRxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + if (husart->hdmarx != NULL) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((husart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmarx->LinkedListQueue != NULL) && (husart->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->RDR; + + /* Set DMA destination address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(uint32_t *)tmp; + + /* Enable the USART receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the USART receive DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, nbByte); + } + } + + if ((status == HAL_OK) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Enable the USART transmit DMA channel: the transmit channel is used in order + to generate in the non-blocking mode the clock to the slave device, + this mode isn't a simplex receive mode but a full-duplex receive mode */ + + /* Set the USART DMA Tx Complete and Error callback to Null */ + if (husart->hdmatx != NULL) + { + husart->hdmatx->XferErrorCallback = NULL; + husart->hdmatx->XferHalfCpltCallback = NULL; + husart->hdmatx->XferCpltCallback = NULL; + + /* Check linked list mode */ + if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(uint32_t *)tmp; + + /* Set DMA destination address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->TDR; + + /* Enable the USART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + } + } + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + if ((husart->hdmarx != NULL) && ((husart->hdmarx->Mode & DMA_LINKEDLIST) != DMA_LINKEDLIST)) + { + status = HAL_DMA_Abort(husart->hdmarx); + } + + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. + * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received/sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + HAL_StatusTypeDef status; + const uint32_t *tmp; + uint16_t nbByte = Size; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL)) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Tx transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the USART DMA Tx transfer error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + tmp = (uint32_t *)&pRxData; + if ((husart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmarx->LinkedListQueue != NULL) && (husart->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->RDR; + + /* Set DMA destination address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; + + /* Enable the USART receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the USART receive DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, nbByte); + } + + /* Enable the USART transmit DMA channel */ + if (status == HAL_OK) + { + tmp = (const uint32_t *)&pTxData; + + /* Check linked list mode */ + if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; + + /* Set DMA destination address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->TDR; + + /* Enable the USART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + } + } + } + else + { + status = HAL_ERROR; + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + if ((husart->hdmarx != NULL) && ((husart->hdmarx->Mode & DMA_LINKEDLIST) != DMA_LINKEDLIST)) + { + status = HAL_DMA_Abort(husart->hdmarx); + } + + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Process Locked */ + __HAL_LOCK(husart); + + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) && + (state == HAL_USART_STATE_BUSY_TX)) + { + /* Suspend the USART DMA Tx channel : use blocking DMA Suspend API (no callback) */ + if (husart->hdmatx != NULL) + { + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmarx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + + if (state == HAL_USART_STATE_BUSY_TX_RX) + { + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Process Locked */ + __HAL_LOCK(husart); + + if (state == HAL_USART_STATE_BUSY_TX) + { + /* Resume the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Resume the USART DMA Rx channel */ + if (husart->hdmarx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmarx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } + + if (state == HAL_USART_STATE_BUSY_TX_RX) + { + /* Resume the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() / + HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + /* Disable the USART Tx/Rx DMA requests */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + /* Abort the USART DMA rx channel */ + if (husart->hdmarx != NULL) + { + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + USART_EndTransfer(husart); + husart->State = HAL_USART_STATE_READY; + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable USART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) +{ + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the USART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (husart->hdmatx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (husart->hdmarx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Reset Handle ErrorCode to No Error */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable USART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) +{ + uint32_t abortcplt = 1U; + + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (husart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if USART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback; + } + else + { + husart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (husart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if USART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback; + } + else + { + husart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Abort the USART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable DMA Tx at USART level */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (husart->hdmatx != NULL) + { + /* USART Tx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK) + { + husart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (husart->hdmarx != NULL) + { + /* USART Rx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + husart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle USART interrupt request. + * @param husart USART handle. + * @retval None + */ +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) +{ + uint32_t isrflags = READ_REG(husart->Instance->ISR); + uint32_t cr1its = READ_REG(husart->Instance->CR1); + uint32_t cr3its = READ_REG(husart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | + USART_ISR_UDR)); + if (errorflags == 0U) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))) + { + /* USART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); + + husart->ErrorCode |= HAL_USART_ERROR_PE; + } + + /* USART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); + + husart->ErrorCode |= HAL_USART_ERROR_FE; + } + + /* USART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); + + husart->ErrorCode |= HAL_USART_ERROR_NE; + } + + /* USART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); + + husart->ErrorCode |= HAL_USART_ERROR_ORE; + } + + /* USART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF); + + husart->ErrorCode |= HAL_USART_ERROR_RTO; + } + + /* USART SPI slave underrun error interrupt occurred -------------------------*/ + if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + /* Ignore SPI slave underrun errors when reception is going on */ + if (husart->State == HAL_USART_STATE_BUSY_RX) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + return; + } + else + { + __HAL_USART_CLEAR_UDRFLAG(husart); + husart->ErrorCode |= HAL_USART_ERROR_UDR; + } + } + + /* Call USART Error Call back function if need be --------------------------*/ + if (husart->ErrorCode != HAL_USART_ERROR_NONE) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE; + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) || + (errorcode != 0U)) + { + /* Blocking error : transfer is aborted + Set the USART state ready to be able to start again the process, + Disable Interrupts, and disable DMA requests, if ongoing */ + USART_EndTransfer(husart); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + /* Set the USART Tx DMA Abort callback to NULL : no callback + executed at end of DMA abort procedure */ + husart->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA TX */ + (void)HAL_DMA_Abort_IT(husart->hdmatx); + } + + /* Abort the USART DMA Rx channel */ + if (husart->hdmarx != NULL) + { + /* Set the USART Rx DMA Abort callback : + will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */ + husart->hdmarx->XferAbortCallback(husart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + + /* USART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (husart->TxISR != NULL) + { + husart->TxISR(husart); + } + return; + } + + /* USART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + USART_EndTransmit_IT(husart); + return; + } + + /* USART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + husart->TxFifoEmptyCallback(husart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_USARTEx_TxFifoEmptyCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + return; + } + + /* USART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + husart->RxFifoFullCallback(husart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_USARTEx_RxFifoFullCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_RxHalfCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Tx/Rx Transfers completed callback for the non-blocking process. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_TxRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief USART error callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief USART Abort Complete callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief USART Peripheral State and Error functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the USART handle state + (+) Return the USART handle error code + +@endverbatim + * @{ + */ + + +/** + * @brief Return the USART handle state. + * @param husart pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART. + * @retval USART handle state + */ +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart) +{ + return husart->State; +} + +/** + * @brief Return the USART error code. + * @param husart pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART. + * @retval USART handle Error Code + */ +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart) +{ + return husart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions USART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param husart USART handle. + * @retval none + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart) +{ + /* Init the USART Callback settings */ + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion). + * @param husart USART handle. + * @retval None + */ +static void USART_EndTransfer(USART_HandleTypeDef *husart) +{ + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + + /* At end of process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA USART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + husart->TxXferCount = 0U; + + if (husart->State == HAL_USART_STATE_BUSY_TX) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + } + /* DMA Circular mode */ + else + { + if (husart->State == HAL_USART_STATE_BUSY_TX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief DMA USART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Half Complete Callback */ + husart->TxHalfCpltCallback(husart); +#else + /* Call legacy weak Tx Half Complete Callback */ + HAL_USART_TxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode*/ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + husart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit + in USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + /* similarly, disable the DMA TX transfer that was started to provide the + clock to the slave device */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + if (husart->State == HAL_USART_STATE_BUSY_RX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + husart->State = HAL_USART_STATE_READY; + } + /* DMA circular mode */ + else + { + if (husart->State == HAL_USART_STATE_BUSY_RX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief DMA USART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Half Complete Callback */ + husart->RxHalfCpltCallback(husart); +#else + /* Call legacy weak Rx Half Complete Callback */ + HAL_USART_RxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + USART_EndTransfer(husart); + + husart->ErrorCode |= HAL_USART_ERROR_DMA; + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (husart->hdmarx != NULL) + { + if (husart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +} + + +/** + * @brief DMA USART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (husart->hdmatx != NULL) + { + if (husart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Handle USART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param husart USART handle. + * @param Flag Specifies the USART flag to check. + * @param Status the actual Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Configure the USART peripheral. + * @param husart USART handle. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) +{ + uint32_t tmpreg; + USART_ClockSourceTypeDef clocksource; + HAL_StatusTypeDef ret = HAL_OK; + uint16_t brrtemp; + uint32_t usartdiv = 0x00000000; + PLL2_ClocksTypeDef pll2_clocks; +#if defined(RCC_CR_PLL3ON) + PLL3_ClocksTypeDef pll3_clocks; +#endif /* RCC_CR_PLL3ON */ + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); + assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); + assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); + assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); + assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength)); + assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); + assert_param(IS_USART_PARITY(husart->Init.Parity)); + assert_param(IS_USART_MODE(husart->Init.Mode)); + assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE and RE bits and configure + * the USART Word Length, Parity and Mode: + * set the M bits according to husart->Init.WordLength value + * set PCE and PS bits according to husart->Init.Parity value + * set TE and RE bits according to husart->Init.Mode value + * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ + tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; + MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*---------------------------- USART CR2 Configuration ---------------------*/ + /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: + * set CPOL bit according to husart->Init.CLKPolarity value + * set CPHA bit according to husart->Init.CLKPhase value + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) + * set STOP[13:12] bits according to husart->Init.StopBits value */ + tmpreg = (uint32_t)(USART_CLOCK_ENABLE); + tmpreg |= (uint32_t)husart->Init.CLKLastBit; + tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); + tmpreg |= (uint32_t)husart->Init.StopBits; + MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */ + MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ + USART_GETCLOCKSOURCE(husart, clocksource); + + switch (clocksource) + { + case USART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_PLL2Q: + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, husart->Init.BaudRate, + husart->Init.ClockPrescaler)); + break; +#if defined(RCC_CR_PLL3ON) + case USART_CLOCKSOURCE_PLL3Q: + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, husart->Init.BaudRate, + husart->Init.ClockPrescaler)); + break; +#endif /* RCC_CR_PLL3ON */ + case USART_CLOCKSOURCE_HSI: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_CSI: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(CSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_LSE: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */ + if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + husart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + husart->NbTxDataToProcess = 1U; + husart->NbRxDataToProcess = 1U; + + /* Clear ISR function pointers */ + husart->RxISR = NULL; + husart->TxISR = NULL; + + return ret; +} + +/** + * @brief Check the USART Idle State. + * @param husart USART handle. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) +{ + uint32_t tickstart; + + /* Initialize the USART ErrorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ + if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the USART state*/ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + if (husart->TxXferCount == 0U) + { + /* Disable the USART Transmit data register empty interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + else + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); + husart->pTxBuffPtr++; + husart->TxXferCount--; + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + const uint16_t *tmp; + + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + if (husart->TxXferCount == 0U) + { + /* Disable the USART Transmit data register empty interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + else + { + tmp = (const uint16_t *) husart->pTxBuffPtr; + husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + husart->pTxBuffPtr += 2U; + husart->TxXferCount--; + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (husart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + break; /* force exit loop */ + } + else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); + husart->pTxBuffPtr++; + husart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + const uint16_t *tmp; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (husart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + break; /* force exit loop */ + } + else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) + { + tmp = (const uint16_t *) husart->pTxBuffPtr; + husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + husart->pTxBuffPtr += 2U; + husart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wraps up transmission in non-blocking mode. + * @param husart Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) +{ + /* Disable the USART Transmit Complete Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TC); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + /* Clear TxISR function pointer */ + husart->TxISR = NULL; + + if (husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Tx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if (husart->RxXferCount == 0U) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t uhMask = husart->Mask; + uint32_t txftie; + + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + husart->pRxBuffPtr++; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t *tmp; + uint16_t uhMask = husart->Mask; + uint32_t txftie; + + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + tmp = (uint16_t *) husart->pRxBuffPtr; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2U; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t rxdatacount; + uint16_t uhMask = husart->Mask; + uint16_t nb_rx_data; + uint32_t txftie; + + /* Check that a Rx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { + if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) + { + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + husart->pRxBuffPtr++; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = husart->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess)) + { + /* Disable the USART RXFT interrupt*/ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + husart->RxISR = USART_RxISR_8BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t rxdatacount; + uint16_t *tmp; + uint16_t uhMask = husart->Mask; + uint16_t nb_rx_data; + uint32_t txftie; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { + if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) + { + tmp = (uint16_t *) husart->pRxBuffPtr; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2U; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = husart->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess)) + { + /* Disable the USART RXFT interrupt*/ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + husart->RxISR = USART_RxISR_16BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_USART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c new file mode 100644 index 00000000..8eae6477 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c @@ -0,0 +1,541 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_usart_ex.c + * @author MCD Application Team + * @brief Extended USART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### USART peripheral extended features ##### + ============================================================================== + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When USART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + (#) Slave mode enabling/disabling and NSS pin configuration. + + -@- When USART operates in Slave mode, Slave mode must be enabled prior + starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup USARTEx USARTEx + * @brief USART Extended HAL module driver + * @{ + */ + +#ifdef HAL_USART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Constants USARTEx Private Constants + * @{ + */ +/* USART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* USART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U +/** + * @} + */ + +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup USARTEx_Private_Functions USARTEx Private Functions + * @{ + */ +static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USARTEx_Exported_Functions USARTEx Exported Functions + * @{ + */ + +/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions + * @brief Extended USART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of FIFO mode related callback functions. + + (#) TX/RX Fifos Callbacks: + (+) HAL_USARTEx_RxFifoFullCallback() + (+) HAL_USARTEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +/** + * @brief USART RX Fifo full callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief USART TX Fifo empty callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode + (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode + (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS) + (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + +@endverbatim + * @{ + */ + +/** + * @brief Enable the SPI slave mode. + * @note When the USART operates in SPI slave mode, it handles data flow using + * the serial interface clock derived from the external SCLK signal + * provided by the external master SPI device. + * @note In SPI slave mode, the USART must be enabled before starting the master + * communications (or between frames while the clock is stable). Otherwise, + * if the USART slave is enabled while the master is in the middle of a + * frame, it will become desynchronized with the master. + * @note The data register of the slave needs to be ready before the first edge + * of the communication clock or before the end of the ongoing communication, + * otherwise the SPI slave will transmit zeros. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* In SPI slave mode mode, the following bits must be kept cleared: + - LINEN and CLKEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable SPI slave mode */ + SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->SlaveMode = USART_SLAVEMODE_ENABLE; + + husart->State = HAL_USART_STATE_READY; + + /* Enable USART */ + __HAL_USART_ENABLE(husart); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Disable the SPI slave mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Disable SPI slave mode */ + CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->SlaveMode = USART_SLAVEMODE_DISABLE; + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Configure the Slave Select input pin (NSS). + * @note Software NSS management: SPI slave will always be selected and NSS + * input pin will be ignored. + * @note Hardware NSS management: the SPI slave selection depends on NSS + * input pin. The slave is selected when NSS is low and deselected when + * NSS is high. + * @param husart USART handle. + * @param NSSConfig NSS configuration. + * This parameter can be one of the following values: + * @arg @ref USART_NSS_HARD + * @arg @ref USART_NSS_SOFT + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + assert_param(IS_USART_NSS(NSSConfig)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Program DIS_NSS bit in the USART_CR2 register */ + MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Enable the FIFO mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + husart->FifoMode = USART_FIFOMODE_ENABLE; + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Disable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + husart->FifoMode = USART_FIFOMODE_DISABLE; + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param husart USART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref USART_TXFIFO_THRESHOLD_1_8 + * @arg @ref USART_TXFIFO_THRESHOLD_1_4 + * @arg @ref USART_TXFIFO_THRESHOLD_1_2 + * @arg @ref USART_TXFIFO_THRESHOLD_3_4 + * @arg @ref USART_TXFIFO_THRESHOLD_7_8 + * @arg @ref USART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Update TX threshold configuration */ + MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param husart USART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref USART_RXFIFO_THRESHOLD_1_8 + * @arg @ref USART_RXFIFO_THRESHOLD_1_4 + * @arg @ref USART_RXFIFO_THRESHOLD_1_2 + * @arg @ref USART_RXFIFO_THRESHOLD_3_4 + * @arg @ref USART_RXFIFO_THRESHOLD_7_8 + * @arg @ref USART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Update RX threshold configuration */ + MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USARTEx_Private_Functions + * @{ + */ + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the USART configuration registers. + * @param husart USART handle. + * @retval None + */ +static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (husart->FifoMode == USART_FIFOMODE_DISABLE) + { + husart->NbTxDataToProcess = 1U; + husart->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU); + tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU); + husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} +/** + * @} + */ + +#endif /* HAL_USART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/embedded-software/firmware/gimbal_test_stand/STM32H533xx_FLASH.ld b/embedded-software/firmware/gimbal_test_stand/STM32H533xx_FLASH.ld new file mode 100644 index 00000000..84c1ec02 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/STM32H533xx_FLASH.ld @@ -0,0 +1,237 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H533xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 272K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + + } >RAM AT> FLASH + + /* Initialized TLS data section */ + .tdata : ALIGN(4) + { + *(.tdata .tdata.* .gnu.linkonce.td.*) + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + PROVIDE(__data_end = .); + PROVIDE(__tdata_end = .); + } >RAM AT> FLASH + + PROVIDE( __tdata_start = ADDR(.tdata) ); + PROVIDE( __tdata_size = __tdata_end - __tdata_start ); + + PROVIDE( __data_start = ADDR(.data) ); + PROVIDE( __data_size = __data_end - __data_start ); + + PROVIDE( __tdata_source = LOADADDR(.tdata) ); + PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); + PROVIDE( __tdata_source_size = __tdata_source_end - __tdata_source ); + + PROVIDE( __data_source = LOADADDR(.data) ); + PROVIDE( __data_source_end = __tdata_source_end ); + PROVIDE( __data_source_size = __data_source_end - __data_source ); + + + /* Uninitialized data section into "RAM" Ram type memory */ + /* Uninitialized TLS data section */ + .tbss (NOLOAD) : ALIGN(4) + { + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.tbss .tbss.*) + . = ALIGN(4); + PROVIDE( __tbss_end = . ); + } >RAM + + PROVIDE( __tbss_start = ADDR(.tbss) ); + PROVIDE( __tbss_size = __tbss_end - __tbss_start ); + PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); + + PROVIDE( __tls_base = __tdata_start ); + PROVIDE( __tls_end = __tbss_end ); + PROVIDE( __tls_size = __tls_end - __tls_base ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1) ); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); + + .bss (NOLOAD) : ALIGN(4) + { + /* This is used by the startup in order to initialize the .bss section */ + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + PROVIDE( __bss_end = .); + } >RAM + PROVIDE( __non_tls_bss_start = ADDR(.bss) ); + + PROVIDE( __bss_start = __tbss_start ); + PROVIDE( __bss_size = __bss_end - __bss_start ); + + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack (NOLOAD) : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a:* ( * ) + libm.a:* ( * ) + libgcc.a:* ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/embedded-software/firmware/gimbal_test_stand/STM32H533xx_RAM.ld b/embedded-software/firmware/gimbal_test_stand/STM32H533xx_RAM.ld new file mode 100644 index 00000000..16bbe8d8 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/STM32H533xx_RAM.ld @@ -0,0 +1,237 @@ +/* + ****************************************************************************** + ** + ** @file : LinkerScript.ld (debug in RAM dedicated) + ** + ** @author : Auto-generated by STM32CubeIDE + ** + ** @brief : Linker script for STM32H533xx Device from STM32H5 series + ** 512Kbytes FLASH + ** 272Kbytes RAM + ** + ** Set heap size, stack size and stack location according + ** to application requirements. + ** + ** Set memory bank area and size if external memory is used + ** + ** Target : STMicroelectronics STM32 + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ****************************************************************************** + ** @attention + ** + ** Copyright (c) 2023 STMicroelectronics. + ** All rights reserved. + ** + ** This software is licensed under terms that can be found in the LICENSE file + ** in the root directory of this software component. + ** If no LICENSE file comes with this software, it is provided AS-IS. + ** + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 272K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >RAM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >RAM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >RAM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >RAM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >RAM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >RAM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >RAM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + + } >RAM + + /* Initialized TLS data section */ + .tdata : ALIGN(4) + { + *(.tdata .tdata.* .gnu.linkonce.td.*) + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + PROVIDE(__data_end = .); + PROVIDE(__tdata_end = .); + } >RAM + + PROVIDE( __tdata_start = ADDR(.tdata) ); + PROVIDE( __tdata_size = __tdata_end - __tdata_start ); + + PROVIDE( __data_start = ADDR(.data) ); + PROVIDE( __data_size = __data_end - __data_start ); + + PROVIDE( __tdata_source = LOADADDR(.tdata) ); + PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); + PROVIDE( __tdata_source_size = __tdata_source_end - __tdata_source ); + + PROVIDE( __data_source = LOADADDR(.data) ); + PROVIDE( __data_source_end = __tdata_source_end ); + PROVIDE( __data_source_size = __data_source_end - __data_source ); + + + /* Uninitialized data section into "RAM" Ram type memory */ + /* Uninitialized TLS data section */ + .tbss (NOLOAD) : ALIGN(4) + { + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.tbss .tbss.*) + . = ALIGN(4); + PROVIDE( __tbss_end = . ); + } >RAM + + PROVIDE( __tbss_start = ADDR(.tbss) ); + PROVIDE( __tbss_size = __tbss_end - __tbss_start ); + PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); + + PROVIDE( __tls_base = __tdata_start ); + PROVIDE( __tls_end = __tbss_end ); + PROVIDE( __tls_size = __tls_end - __tls_base ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1) ); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); + + .bss (NOLOAD) : ALIGN(4) + { + /* This is used by the startup in order to initialize the .bss section */ + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + PROVIDE( __bss_end = .); + } >RAM + PROVIDE( __non_tls_bss_start = ADDR(.bss) ); + + PROVIDE( __bss_start = __tbss_start ); + PROVIDE( __bss_size = __bss_end - __bss_start ); + + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack (NOLOAD) : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a:* ( * ) + libm.a:* ( * ) + libgcc.a:* ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/embedded-software/firmware/gimbal_test_stand/cmake/gcc-arm-none-eabi.cmake b/embedded-software/firmware/gimbal_test_stand/cmake/gcc-arm-none-eabi.cmake new file mode 100644 index 00000000..3a1a3462 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/cmake/gcc-arm-none-eabi.cmake @@ -0,0 +1,47 @@ +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR arm) + +set(CMAKE_C_COMPILER_ID GNU) +set(CMAKE_CXX_COMPILER_ID GNU) + +# Some default GCC settings +# arm-none-eabi- must be part of path environment +set(TOOLCHAIN_PREFIX arm-none-eabi-) + +set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}gcc) +set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) +set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}g++) +set(CMAKE_LINKER ${TOOLCHAIN_PREFIX}g++) +set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}objcopy) +set(CMAKE_SIZE ${TOOLCHAIN_PREFIX}size) + +set(CMAKE_EXECUTABLE_SUFFIX_ASM ".elf") +set(CMAKE_EXECUTABLE_SUFFIX_C ".elf") +set(CMAKE_EXECUTABLE_SUFFIX_CXX ".elf") + +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) + +# MCU specific flags +set(TARGET_FLAGS "-mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard ") + +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${TARGET_FLAGS}") +set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp -MMD -MP") +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -fdata-sections -ffunction-sections -fstack-usage") + +# The cyclomatic-complexity parameter must be defined for the Cyclomatic complexity feature in STM32CubeIDE to work. +# However, most GCC toolchains do not support this option, which causes a compilation error; for this reason, the feature is disabled by default. +# set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fcyclomatic-complexity") + +set(CMAKE_C_FLAGS_DEBUG "-O0 -g3") +set(CMAKE_C_FLAGS_RELEASE "-Os -g0") +set(CMAKE_CXX_FLAGS_DEBUG "-O0 -g3") +set(CMAKE_CXX_FLAGS_RELEASE "-Os -g0") + +set(CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS} -fno-rtti -fno-exceptions -fno-threadsafe-statics") + +set(CMAKE_EXE_LINKER_FLAGS "${TARGET_FLAGS}") +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T \"${CMAKE_SOURCE_DIR}/STM32H533xx_FLASH.ld\"") +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} --specs=nano.specs") +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,-Map=${CMAKE_PROJECT_NAME}.map -Wl,--gc-sections") +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--print-memory-usage") +set(TOOLCHAIN_LINK_LIBRARIES "m") diff --git a/embedded-software/firmware/gimbal_test_stand/cmake/starm-clang.cmake b/embedded-software/firmware/gimbal_test_stand/cmake/starm-clang.cmake new file mode 100644 index 00000000..06fd9424 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/cmake/starm-clang.cmake @@ -0,0 +1,65 @@ +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR arm) + +set(CMAKE_C_COMPILER_ID Clang) +set(CMAKE_CXX_COMPILER_ID Clang) + +# Some default llvm settings +set(TOOLCHAIN_PREFIX starm-) + +set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}clang) +set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) +set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}clang++) +set(CMAKE_LINKER ${TOOLCHAIN_PREFIX}clang) +set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}objcopy) +set(CMAKE_SIZE ${TOOLCHAIN_PREFIX}size) + +set(CMAKE_EXECUTABLE_SUFFIX_ASM ".elf") +set(CMAKE_EXECUTABLE_SUFFIX_C ".elf") +set(CMAKE_EXECUTABLE_SUFFIX_CXX ".elf") + +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) + +# STARM_TOOLCHAIN_CONFIG allows you to choose the toolchain configuration. +# Possible values are: +# "STARM_HYBRID" : Hybrid configuration using starm-clang Assemler and Compiler and GNU Linker +# "STARM_NEWLIB" : starm-clang toolchain with NEWLIB C library +# "STARM_PICOLIBC" : starm-clang toolchain with PICOLIBC C library +set(STARM_TOOLCHAIN_CONFIG "STARM_PICOLIBC") + +if(STARM_TOOLCHAIN_CONFIG STREQUAL "STARM_HYBRID") + set(TOOLCHAIN_MULTILIBS "--multi-lib-config=\"$ENV{CLANG_GCC_CMSIS_COMPILER}/multilib.gnu_tools_for_stm32.yaml\" --gcc-toolchain=\"$ENV{GCC_TOOLCHAIN_ROOT}/..\"") +elseif (STARM_TOOLCHAIN_CONFIG STREQUAL "STARM_NEWLIB") + set(TOOLCHAIN_MULTILIBS "--config=newlib.cfg") +endif() + +# MCU specific flags +set(TARGET_FLAGS "-mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard ${TOOLCHAIN_MULTILIBS}") + +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${TARGET_FLAGS}") +set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp -MP") +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -fdata-sections -ffunction-sections -ftls-model=local-exec -fstack-usage") + +set(CMAKE_C_FLAGS_DEBUG "-Og -g3") +set(CMAKE_C_FLAGS_RELEASE "-Oz -g0") +set(CMAKE_CXX_FLAGS_DEBUG "-Og -g3") +set(CMAKE_CXX_FLAGS_RELEASE "-Oz -g0") + +set(CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS} -fno-rtti -fno-exceptions -fno-threadsafe-statics") + +set(CMAKE_EXE_LINKER_FLAGS "${TARGET_FLAGS}") + +if (STARM_TOOLCHAIN_CONFIG STREQUAL "STARM_HYBRID") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} --gcc-specs=nano.specs") + set(TOOLCHAIN_LINK_LIBRARIES "m") +elseif(STARM_TOOLCHAIN_CONFIG STREQUAL "STARM_NEWLIB") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -lcrt0-nosys") +elseif(STARM_TOOLCHAIN_CONFIG STREQUAL "STARM_PICOLIBC") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -lcrt0-hosted -z norelro") + +endif() + +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T \"${CMAKE_SOURCE_DIR}/STM32H533xx_FLASH.ld\"") +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,-Map=${CMAKE_PROJECT_NAME}.map -Wl,--gc-sections") +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -z noexecstack") +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--print-memory-usage ") diff --git a/embedded-software/firmware/gimbal_test_stand/cmake/stm32cubemx/CMakeLists.txt b/embedded-software/firmware/gimbal_test_stand/cmake/stm32cubemx/CMakeLists.txt new file mode 100644 index 00000000..ce0b6c6c --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/cmake/stm32cubemx/CMakeLists.txt @@ -0,0 +1,95 @@ +cmake_minimum_required(VERSION 3.22) +# Enable CMake support for ASM and C languages +enable_language(C ASM) +# STM32CubeMX generated symbols (macros) +set(MX_Defines_Syms + USE_NUCLEO_64 + USE_HAL_DRIVER + STM32H533xx + $<$:DEBUG> +) + +# STM32CubeMX generated include paths +set(MX_Include_Dirs + ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Inc + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/BSP/STM32H5xx_Nucleo + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/CMSIS/Device/ST/STM32H5xx/Include + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/CMSIS/Include +) + +# STM32CubeMX generated application sources +set(MX_Application_Src + ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/stm32h5xx_it.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/stm32h5xx_hal_msp.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/sysmem.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/syscalls.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../startup_stm32h533xx.s +) + +# STM32 HAL/LL Drivers +set(STM32_Drivers_Src + ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/system_stm32h5xx.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c +) + +# Drivers Midllewares + + + +# Link directories setup +set(MX_LINK_DIRS + +) +# Project static libraries +set(MX_LINK_LIBS + STM32_Drivers + ${TOOLCHAIN_LINK_LIBRARIES} + +) +# Interface library for includes and symbols +add_library(stm32cubemx INTERFACE) +target_include_directories(stm32cubemx INTERFACE ${MX_Include_Dirs}) +target_compile_definitions(stm32cubemx INTERFACE ${MX_Defines_Syms}) + +# Create STM32_Drivers static library +add_library(STM32_Drivers OBJECT) +target_sources(STM32_Drivers PRIVATE ${STM32_Drivers_Src}) +target_link_libraries(STM32_Drivers PUBLIC stm32cubemx) + + +# Add STM32CubeMX generated application sources to the project +target_sources(${CMAKE_PROJECT_NAME} PRIVATE ${MX_Application_Src}) + +# Link directories setup +target_link_directories(${CMAKE_PROJECT_NAME} PRIVATE ${MX_LINK_DIRS}) + +# Add libraries to the project +target_link_libraries(${CMAKE_PROJECT_NAME} ${MX_LINK_LIBS}) + +# Add the map file to the list of files to be removed with 'clean' target +set_target_properties(${CMAKE_PROJECT_NAME} PROPERTIES ADDITIONAL_CLEAN_FILES ${CMAKE_PROJECT_NAME}.map) + +# Validate that STM32CubeMX code is compatible with C standard +if((CMAKE_C_STANDARD EQUAL 90) OR (CMAKE_C_STANDARD EQUAL 99)) + message(ERROR "Generated code requires C11 or higher") +endif() diff --git a/embedded-software/firmware/gimbal_test_stand/gimbal_test_stand.ioc b/embedded-software/firmware/gimbal_test_stand/gimbal_test_stand.ioc new file mode 100644 index 00000000..8203742a --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/gimbal_test_stand.ioc @@ -0,0 +1,245 @@ +#MicroXplorer Configuration settings - do not modify +BOOTPATH.BootPathName=LEGACY +BOOTPATH.IPParameters=BootPathName +BOOTPATH.UserSelectedBootPath=LEGACY +BSP_IP_NAME=NUCLEO-H533RE +CAD.formats= +CAD.pinconfig= +CAD.provider= +CORTEX_M33_NS.IPParameters=default_mode_Activation,Number-Cortex_Memory_Protection_Unit_Region0_OTP_RO_AREAS_Settings +CORTEX_M33_NS.Number-Cortex_Memory_Protection_Unit_Region0_OTP_RO_AREAS_Settings=MPU_REGION_NUMBER0 +CORTEX_M33_NS.default_mode_Activation=1 +CORTEX_M33_NS.userName=CORTEX_M33 +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +MMTAppRegionsCount=0 +MMTConfigApplied=false +MMTSectionSuffix=_Section +Mcu.CPN=STM32H533RET6 +Mcu.ContextProject=TrustZoneDisabled +Mcu.Family=STM32H5 +Mcu.IP0=BOOTPATH +Mcu.IP1=CORTEX_M33_NS +Mcu.IP2=ICACHE +Mcu.IP3=MEMORYMAP +Mcu.IP4=NUCLEO-H533RE +Mcu.IP5=NVIC +Mcu.IP6=PWR +Mcu.IP7=RCC +Mcu.IP8=SYS +Mcu.IPNb=10 +Mcu.Name=STM32H533RETx +Mcu.Package=LQFP64 +Mcu.Pin0=PC13 +Mcu.Pin1=PA2 +Mcu.Pin10=PA14(JTCK/SWCLK) +Mcu.Pin11=PA15(JTDI) +Mcu.Pin12=PB3(JTDO/TRACESWO) +Mcu.Pin13=PB6 +Mcu.Pin14=PB7 +Mcu.Pin15=VP_CORTEX_M33_NS_VS_Hclk +Mcu.Pin16=VP_ICACHE_VS_ICACHE +Mcu.Pin17=VP_PWR_VS_SECSignals +Mcu.Pin18=VP_PWR_VS_LPOM +Mcu.Pin19=VP_SYS_VS_Systick +Mcu.Pin2=PA3 +Mcu.Pin20=VP_BOOTPATH_VS_BOOTPATH +Mcu.Pin21=VP_MEMORYMAP_VS_MEMORYMAP +Mcu.Pin22=VP_NUCLEO-H533RE_VS_BSP_COMMON +Mcu.Pin3=PA5 +Mcu.Pin4=PB2 +Mcu.Pin5=PC6 +Mcu.Pin6=PC7 +Mcu.Pin7=PC9 +Mcu.Pin8=PA8 +Mcu.Pin9=PA13(JTMS/SWDIO) +Mcu.PinsNb=23 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32H533RETx +MxCube.Version=6.17.0 +MxDb.Version=DB.6.0.170 +NUCLEO-H533RE.BUTTON=1 +NUCLEO-H533RE.IPParameters=LD4,VCP,BUTTON +NUCLEO-H533RE.LD4=true +NUCLEO-H533RE.VCP=true +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.EXTI13_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA13(JTMS/SWDIO).GPIOParameters=GPIO_Label +PA13(JTMS/SWDIO).GPIO_Label=SWDIO +PA13(JTMS/SWDIO).Locked=true +PA13(JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO +PA14(JTCK/SWCLK).GPIOParameters=GPIO_Label +PA14(JTCK/SWCLK).GPIO_Label=SWCLK +PA14(JTCK/SWCLK).Locked=true +PA14(JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK +PA15(JTDI).GPIOParameters=GPIO_Label +PA15(JTDI).GPIO_Label=JTDI +PA15(JTDI).Locked=true +PA15(JTDI).Signal=DEBUG_JTDI +PA2.Locked=true +PA2.Signal=USART2_TX +PA3.Locked=true +PA3.Signal=USART2_RX +PA5.Locked=true +PA8.Locked=true +PA8.Signal=I2C3_SCL +PB2.Locked=true +PB2.Signal=GPXTI2 +PB3(JTDO/TRACESWO).GPIOParameters=GPIO_Label +PB3(JTDO/TRACESWO).GPIO_Label=SWO +PB3(JTDO/TRACESWO).Locked=true +PB3(JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO +PB6.Locked=true +PB6.Signal=I2C1_SCL +PB7.Locked=true +PB7.Signal=I2C1_SDA +PC13.Locked=true +PC6.Locked=true +PC6.Signal=GPXTI6 +PC7.Locked=true +PC7.Signal=GPXTI7 +PC9.Locked=true +PC9.Signal=I2C3_SDA +PCC.Checker=false +PCC.Display=Plot\: All Steps +PCC.Line=STM32H5x3 +PCC.MCU=STM32H533RETx +PCC.PartNumber=STM32H533RETx +PCC.Series=STM32H5 +PCC.Temperature=25 +PCC.Vdd=3.0 +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerLinker=GCC +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32H533RETx +ProjectManager.FirmwarePackage=STM32Cube FW_H5 V1.6.0 +ProjectManager.FreePins=false +ProjectManager.FreePinsContext= +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=gimbal_test_stand.ioc +ProjectManager.ProjectName=gimbal_test_stand +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=CMake +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ICACHE_Init-ICACHE-false-HAL-true,false-0--NUCLEO-H533RE-true-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true +RCC.ADCFreq_Value=32000000 +RCC.AHBFreq_Value=32000000 +RCC.APB1Freq_Value=32000000 +RCC.APB1TimFreq_Value=32000000 +RCC.APB2Freq_Value=32000000 +RCC.APB2TimFreq_Value=32000000 +RCC.APB3Freq_Value=32000000 +RCC.CKPERFreq_Value=32000000 +RCC.CRSFreq_Value=48000000 +RCC.CSI_VALUE=4000000 +RCC.CortexFreq_Value=32000000 +RCC.DACFreq_Value=32768 +RCC.EPOD_VALUE=4000000 +RCC.FCLKCortexFreq_Value=32000000 +RCC.FDCANFreq_Value=25000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=32000000 +RCC.HSE_VALUE=25000000 +RCC.HSI48_VALUE=48000000 +RCC.HSI_VALUE=64000000 +RCC.I2C1Freq_Value=32000000 +RCC.I2C2Freq_Value=32000000 +RCC.I2C3Freq_Value=32000000 +RCC.I3C1Freq_Value=32000000 +RCC.I3C2Freq_Value=32000000 +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CKPERFreq_Value,CRSFreq_Value,CSI_VALUE,CortexFreq_Value,DACFreq_Value,EPOD_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I3C1Freq_Value,I3C2Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSIRC_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,OCTOSPIMFreq_Value,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PWRFreq_Value,RNGFreq_Value,SDMMC1Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SYSCLKFreq_VALUE,UART4Freq_Value,UART5Freq_Value,UCPD1outputFreq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value +RCC.LPTIM1Freq_Value=32000000 +RCC.LPTIM2Freq_Value=32000000 +RCC.LPUART1Freq_Value=32000000 +RCC.LSCOPinFreq_Value=32000 +RCC.LSE_VALUE=32768 +RCC.LSIRC_VALUE=32000 +RCC.MCO1PinFreq_Value=32000000 +RCC.MCO2PinFreq_Value=32000000 +RCC.OCTOSPIMFreq_Value=32000000 +RCC.PLL2PoutputFreq_Value=258000000 +RCC.PLL2QoutputFreq_Value=258000000 +RCC.PLL2RoutputFreq_Value=258000000 +RCC.PLL3PoutputFreq_Value=258000000 +RCC.PLL3QoutputFreq_Value=258000000 +RCC.PLL3RoutputFreq_Value=258000000 +RCC.PLLPoutputFreq_Value=258000000 +RCC.PLLQoutputFreq_Value=258000000 +RCC.PWRFreq_Value=32000000 +RCC.RNGFreq_Value=48000000 +RCC.SDMMC1Freq_Value=258000000 +RCC.SPI1Freq_Value=258000000 +RCC.SPI2Freq_Value=258000000 +RCC.SPI3Freq_Value=258000000 +RCC.SPI4Freq_Value=32000000 +RCC.SYSCLKFreq_VALUE=32000000 +RCC.UART4Freq_Value=32000000 +RCC.UART5Freq_Value=32000000 +RCC.UCPD1outputFreq_Value=8000000 +RCC.USART1Freq_Value=32000000 +RCC.USART2Freq_Value=32000000 +RCC.USART3Freq_Value=32000000 +RCC.USART6Freq_Value=32000000 +RCC.USBFreq_Value=48000000 +RCC.VCOInput2Freq_Value=4000000 +RCC.VCOInput3Freq_Value=4000000 +RCC.VCOInputFreq_Value=4000000 +RCC.VCOOutputFreq_Value=516000000 +RCC.VCOPLL2OutputFreq_Value=516000000 +RCC.VCOPLL3OutputFreq_Value=516000000 +SH.GPXTI2.0=GPIO_EXTI2 +SH.GPXTI2.ConfNb=1 +SH.GPXTI6.0=GPIO_EXTI6 +SH.GPXTI6.ConfNb=1 +SH.GPXTI7.0=GPIO_EXTI7 +SH.GPXTI7.ConfNb=1 +VP_BOOTPATH_VS_BOOTPATH.Mode=BP_Activate +VP_BOOTPATH_VS_BOOTPATH.Signal=BOOTPATH_VS_BOOTPATH +VP_CORTEX_M33_NS_VS_Hclk.Mode=Hclk_Mode +VP_CORTEX_M33_NS_VS_Hclk.Signal=CORTEX_M33_NS_VS_Hclk +VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache +VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE +VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg +VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP +VP_NUCLEO-H533RE_VS_BSP_COMMON.Mode=COMMON +VP_NUCLEO-H533RE_VS_BSP_COMMON.Signal=NUCLEO-H533RE_VS_BSP_COMMON +VP_PWR_VS_LPOM.Mode=PowerOptimisation +VP_PWR_VS_LPOM.Signal=PWR_VS_LPOM +VP_PWR_VS_SECSignals.Mode=Security/Privilege +VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=NUCLEO-H533RE +boardIOC=true diff --git a/embedded-software/firmware/gimbal_test_stand/platform/svd/STM32H533.svd b/embedded-software/firmware/gimbal_test_stand/platform/svd/STM32H533.svd new file mode 100644 index 00000000..57afd76e --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/platform/svd/STM32H533.svd @@ -0,0 +1,180402 @@ + + + + STM32H533 + 1.3 + STM32H533 + + CM33 + r0p0 + little + true + true + 4 + false + + 8 + 32 + 0x0 + 0xFFFFFFFF + + + ADC + ADC register block + ADC + 0x42028000 + + 0x0 + 0xCC + registers + + + ADC1 + ADC1 global interrupt + 37 + + + + ADC_ISR + ADC_ISR + ADC interrupt and status register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADRDY + ADC ready + + 0 + 1 + read-write + + + B_0x0 + ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + ADC is ready to start conversion + 0x1 + + + + + EOSMP + End of sampling flag + + 1 + 1 + read-write + + + B_0x0 + not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + End of sampling phase reached + 0x1 + + + + + EOC + End of conversion flag + + 2 + 1 + read-write + + + B_0x0 + Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Regular channel conversion complete + 0x1 + + + + + EOS + End of regular sequence flag + + 3 + 1 + read-write + + + B_0x0 + Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Regular Conversions sequence complete + 0x1 + + + + + OVR + ADC overrun + + 4 + 1 + read-write + + + B_0x0 + No overrun occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Overrun has occurred + 0x1 + + + + + JEOC + Injected channel end of conversion flag + + 5 + 1 + read-write + + + B_0x0 + Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Injected channel conversion complete + 0x1 + + + + + JEOS + Injected channel end of sequence flag + + 6 + 1 + read-write + + + B_0x0 + Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Injected conversions complete + 0x1 + + + + + AWD1 + Analog watchdog 1 flag + + 7 + 1 + read-write + + + B_0x0 + No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog 1 event occurred + 0x1 + + + + + AWD2 + Analog watchdog 2 flag + + 8 + 1 + read-write + + + B_0x0 + No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog 2 event occurred + 0x1 + + + + + AWD3 + Analog watchdog 3 flag + + 9 + 1 + read-write + + + B_0x0 + No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Analog watchdog 3 event occurred + 0x1 + + + + + JQOVF + Injected context queue overflow + + 10 + 1 + read-write + + + B_0x0 + No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software) + 0x0 + + + B_0x1 + Injected context queue overflow has occurred + 0x1 + + + + + + + ADC_IER + ADC_IER + ADC interrupt enable register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADRDYIE + ADC ready interrupt enable + + 0 + 1 + read-write + + + B_0x0 + ADRDY interrupt disabled + 0x0 + + + B_0x1 + ADRDY interrupt enabled. + 0x1 + + + + + EOSMPIE + End of sampling flag interrupt enable for regular conversions + + 1 + 1 + read-write + + + B_0x0 + EOSMP interrupt disabled. + 0x0 + + + B_0x1 + EOSMP interrupt enabled. + 0x1 + + + + + EOCIE + End of regular conversion interrupt enable + + 2 + 1 + read-write + + + B_0x0 + EOC interrupt disabled. + 0x0 + + + B_0x1 + EOC interrupt enabled. + 0x1 + + + + + EOSIE + End of regular sequence of conversions interrupt enable + + 3 + 1 + read-write + + + B_0x0 + EOS interrupt disabled + 0x0 + + + B_0x1 + EOS interrupt enabled. + 0x1 + + + + + OVRIE + Overrun interrupt enable + + 4 + 1 + read-write + + + B_0x0 + Overrun interrupt disabled + 0x0 + + + B_0x1 + Overrun interrupt enabled. + 0x1 + + + + + JEOCIE + End of injected conversion interrupt enable + + 5 + 1 + read-write + + + B_0x0 + JEOC interrupt disabled. + 0x0 + + + B_0x1 + JEOC interrupt enabled. + 0x1 + + + + + JEOSIE + End of injected sequence of conversions interrupt enable + + 6 + 1 + read-write + + + B_0x0 + JEOS interrupt disabled + 0x0 + + + B_0x1 + JEOS interrupt enabled. + 0x1 + + + + + AWD1IE + Analog watchdog 1 interrupt enable + + 7 + 1 + read-write + + + B_0x0 + Analog watchdog 1 interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog 1 interrupt enabled + 0x1 + + + + + AWD2IE + Analog watchdog 2 interrupt enable + + 8 + 1 + read-write + + + B_0x0 + Analog watchdog 2 interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog 2 interrupt enabled + 0x1 + + + + + AWD3IE + Analog watchdog 3 interrupt enable + + 9 + 1 + read-write + + + B_0x0 + Analog watchdog 3 interrupt disabled + 0x0 + + + B_0x1 + Analog watchdog 3 interrupt enabled + 0x1 + + + + + JQOVFIE + Injected context queue overflow interrupt enable + + 10 + 1 + read-write + + + B_0x0 + Injected Context Queue Overflow interrupt disabled + 0x0 + + + B_0x1 + Injected Context Queue Overflow interrupt enabled. + 0x1 + + + + + + + ADC_CR + ADC_CR + ADC control register + 0x08 + 0x20 + read-write + 0x20000000 + 0xFFFFFFFF + + + ADEN + ADC enable control + + 0 + 1 + read-write + + + B_0x0 + ADC is disabled (OFF state) + 0x0 + + + B_0x1 + Write 1 to enable the ADC. + 0x1 + + + + + ADDIS + ADC disable command + + 1 + 1 + read-write + + + B_0x0 + no ADDIS command ongoing + 0x0 + + + B_0x1 + Write 1 to disable the ADC. + 0x1 + + + + + ADSTART + ADC start of regular conversion + + 2 + 1 + read-write + + + B_0x0 + No ADC regular conversion is ongoing. + 0x0 + + + B_0x1 + Write 1 to start regular conversions. + 0x1 + + + + + JADSTART + ADC start of injected conversion + + 3 + 1 + read-write + + + B_0x0 + No ADC injected conversion is ongoing. + 0x0 + + + B_0x1 + Write 1 to start injected conversions. + 0x1 + + + + + ADSTP + ADC stop of regular conversion command + + 4 + 1 + read-write + + + B_0x0 + No ADC stop regular conversion command ongoing + 0x0 + + + B_0x1 + Write 1 to stop regular conversions ongoing. + 0x1 + + + + + JADSTP + ADC stop of injected conversion command + + 5 + 1 + read-write + + + B_0x0 + No ADC stop injected conversion command ongoing + 0x0 + + + B_0x1 + Write 1 to stop injected conversions ongoing. + 0x1 + + + + + ADVREGEN + ADC voltage regulator enable + + 28 + 1 + read-write + + + B_0x0 + ADC Voltage regulator disabled + 0x0 + + + B_0x1 + ADC Voltage regulator enabled. + 0x1 + + + + + DEEPPWD + Deep-power-down enable + + 29 + 1 + read-write + + + B_0x0 + ADC not in Deep-power down + 0x0 + + + B_0x1 + ADC in Deep-power-down (default reset state) + 0x1 + + + + + ADCALDIF + Differential mode for calibration + + 30 + 1 + read-write + + + B_0x0 + Writing ADCAL launches a calibration in single-ended inputs mode. + 0x0 + + + B_0x1 + Writing ADCAL launches a calibration in Differential inputs mode. + 0x1 + + + + + ADCAL + ADC calibration + + 31 + 1 + read-write + + + B_0x0 + Calibration complete + 0x0 + + + B_0x1 + Write 1 to calibrate the ADC. + 0x1 + + + + + + + ADC_CFGR + ADC_CFGR + ADC configuration register + 0x0C + 0x20 + read-write + 0x80000000 + 0xFFFFFFFF + + + DMAEN + Direct memory access enable + + 0 + 1 + read-write + + + B_0x0 + DMA disabled + 0x0 + + + B_0x1 + DMA enabled + 0x1 + + + + + DMACFG + Direct memory access configuration + + 1 + 1 + read-write + + + B_0x0 + DMA One Shot mode selected + 0x0 + + + B_0x1 + DMA Circular mode selected + 0x1 + + + + + RES + Data resolution + + 3 + 2 + read-write + + + B_0x0 + 12-bit + 0x0 + + + B_0x1 + 10-bit + 0x1 + + + B_0x2 + 8-bit + 0x2 + + + B_0x3 + 6-bit + 0x3 + + + + + EXTSEL + External trigger selection for regular group +These bits select the external event used to trigger the start of conversion of a regular group: +... +Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). + 5 + 5 + read-write + + + B_0x0 + adc_ext_trg0 + 0x0 + + + B_0x1 + adc_ext_trg1 + 0x1 + + + B_0x2 + adc_ext_trg2 + 0x2 + + + B_0x3 + adc_ext_trg3 + 0x3 + + + B_0x4 + adc_ext_trg4 + 0x4 + + + B_0x5 + adc_ext_trg5 + 0x5 + + + B_0x6 + adc_ext_trg6 + 0x6 + + + B_0x7 + adc_ext_trg7 + 0x7 + + + B_0x8 + adc_ext_trg8 + 0x8 + + + B_0x9 + adc_ext_trg9 + 0x9 + + + B_0xA + adc_ext_trg10 + 0xA + + + B_0xB + adc_ext_trg11 + 0xB + + + B_0xC + adc_ext_trg12 + 0xC + + + B_0xD + adc_ext_trg13 + 0xD + + + B_0xE + adc_ext_trg14 + 0xE + + + B_0xF + adc_ext_trg15 + 0xF + + + B_0x10 + adc_ext_trg16 + 0x10 + + + B_0x11 + adc_ext_trg17 + 0x11 + + + B_0x12 + adc_ext_trg18 + 0x12 + + + B_0x13 + adc_ext_trg19 + 0x13 + + + B_0x14 + adc_ext_trg20 + 0x14 + + + B_0x15 + adc_ext_trg21 + 0x15 + + + B_0x16 + adc_ext_trg22 + 0x16 + + + B_0x17 + adc_ext_trg23 + 0x17 + + + B_0x18 + adc_ext_trg24 + 0x18 + + + B_0x19 + adc_ext_trg25 + 0x19 + + + B_0x1A + adc_ext_trg26 + 0x1A + + + B_0x1B + adc_ext_trg27 + 0x1B + + + B_0x1C + adc_ext_trg28 + 0x1C + + + B_0x1D + adc_ext_trg29 + 0x1D + + + B_0x1E + adc_ext_trg30 + 0x1E + + + B_0x1F + adc_ext_trg31 + 0x1F + + + + + EXTEN + External trigger enable and polarity selection for regular channels + + 10 + 2 + read-write + + + B_0x0 + Hardware trigger detection disabled (conversions can be launched by software) + 0x0 + + + B_0x1 + Hardware trigger detection on the rising edge + 0x1 + + + B_0x2 + Hardware trigger detection on the falling edge + 0x2 + + + B_0x3 + Hardware trigger detection on both the rising and falling edges + 0x3 + + + + + OVRMOD + Overrun mode + + 12 + 1 + read-write + + + B_0x0 + ADC_DR register is preserved with the old data when an overrun is detected. + 0x0 + + + B_0x1 + ADC_DR register is overwritten with the last conversion result when an overrun is detected. + 0x1 + + + + + CONT + Single / continuous conversion mode for regular conversions + + 13 + 1 + read-write + + + B_0x0 + Single conversion mode + 0x0 + + + B_0x1 + Continuous conversion mode + 0x1 + + + + + AUTDLY + Delayed conversion mode + + 14 + 1 + read-write + + + B_0x0 + Auto-delayed conversion mode off + 0x0 + + + B_0x1 + Auto-delayed conversion mode on + 0x1 + + + + + ALIGN + Data alignment + + 15 + 1 + read-write + + + B_0x0 + Right alignment + 0x0 + + + B_0x1 + Left alignment + 0x1 + + + + + DISCEN + Discontinuous mode for regular channels + + 16 + 1 + read-write + + + B_0x0 + Discontinuous mode for regular channels disabled + 0x0 + + + B_0x1 + Discontinuous mode for regular channels enabled + 0x1 + + + + + DISCNUM + Discontinuous mode channel count + + 17 + 3 + read-write + + + B_0x0 + 1 channel + 0x0 + + + B_0x1 + 2 channels + 0x1 + + + B_0x7 + 8 channels + 0x7 + + + + + JDISCEN + Discontinuous mode on injected channels + + 20 + 1 + read-write + + + B_0x0 + Discontinuous mode on injected channels disabled + 0x0 + + + B_0x1 + Discontinuous mode on injected channels enabled + 0x1 + + + + + JQM + JSQR queue mode + + 21 + 1 + read-write + + + B_0x0 + JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR. + 0x0 + + + B_0x1 + JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence. + 0x1 + + + + + AWD1SGL + Enable the watchdog 1 on a single channel or on all channels + + 22 + 1 + read-write + + + B_0x0 + Analog watchdog 1 enabled on all channels + 0x0 + + + B_0x1 + Analog watchdog 1 enabled on a single channel + 0x1 + + + + + AWD1EN + Analog watchdog 1 enable on regular channels + + 23 + 1 + read-write + + + B_0x0 + Analog watchdog 1 disabled on regular channels + 0x0 + + + B_0x1 + Analog watchdog 1 enabled on regular channels + 0x1 + + + + + JAWD1EN + Analog watchdog 1 enable on injected channels + + 24 + 1 + read-write + + + B_0x0 + Analog watchdog 1 disabled on injected channels + 0x0 + + + B_0x1 + Analog watchdog 1 enabled on injected channels + 0x1 + + + + + JAUTO + Automatic injected group conversion + + 25 + 1 + read-write + + + B_0x0 + Automatic injected group conversion disabled + 0x0 + + + B_0x1 + Automatic injected group conversion enabled + 0x1 + + + + + AWD1CH + Analog watchdog 1 channel selection + + 26 + 5 + read-write + + + B_0x0 + ADC analog input channel 0 monitored by AWD1 (available on ADC1 only) + 0x0 + + + B_0x1 + ADC analog input channel 1 monitored by AWD1 + 0x1 + + + B_0x13 + ADC analog input channel 19 monitored by AWD1 + 0x13 + + + + + JQDIS + Injected queue disable + + 31 + 1 + read-write + + + B_0x0 + Injected queue enabled + 0x0 + + + B_0x1 + Injected queue disabled + 0x1 + + + + + + + ADC_CFGR2 + ADC_CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ROVSE + Regular oversampling Enable + + 0 + 1 + read-write + + + B_0x0 + Regular oversampling disabled + 0x0 + + + B_0x1 + Regular oversampling enabled + 0x1 + + + + + JOVSE + Injected oversampling Enable + + 1 + 1 + read-write + + + B_0x0 + Injected oversampling disabled + 0x0 + + + B_0x1 + Injected oversampling enabled + 0x1 + + + + + OVSR + Oversampling ratio + + 2 + 3 + read-write + + + B_0x0 + 2x + 0x0 + + + B_0x1 + 4x + 0x1 + + + B_0x2 + 8x + 0x2 + + + B_0x3 + 16x + 0x3 + + + B_0x4 + 32x + 0x4 + + + B_0x5 + 64x + 0x5 + + + B_0x6 + 128x + 0x6 + + + B_0x7 + 256x + 0x7 + + + + + OVSS + Oversampling shift + + 5 + 4 + read-write + + + B_0x0 + No shift + 0x0 + + + B_0x1 + Shift 1-bit + 0x1 + + + B_0x2 + Shift 2-bits + 0x2 + + + B_0x3 + Shift 3-bits + 0x3 + + + B_0x4 + Shift 4-bits + 0x4 + + + B_0x5 + Shift 5-bits + 0x5 + + + B_0x6 + Shift 6-bits + 0x6 + + + B_0x7 + Shift 7-bits + 0x7 + + + B_0x8 + Shift 8-bits + 0x8 + + + + + TROVS + Triggered Regular oversampling + + 9 + 1 + read-write + + + B_0x0 + All oversampled conversions for a channel are done consecutively following a trigger + 0x0 + + + B_0x1 + Each oversampled conversion for a channel needs a new trigger + 0x1 + + + + + ROVSM + Regular oversampling mode + + 10 + 1 + read-write + + + B_0x0 + Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) + 0x0 + + + B_0x1 + Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start) + 0x1 + + + + + SWTRIG + Software trigger bit for sampling time control trigger mode + + 25 + 1 + read-write + + + B_0x0 + Software trigger starts the conversion for sampling time control trigger mode + 0x0 + + + B_0x1 + Software trigger starts the sampling for sampling time control trigger mode + 0x1 + + + + + BULB + Bulb sampling mode + + 26 + 1 + read-write + + + B_0x0 + Bulb sampling mode disabled + 0x0 + + + B_0x1 + Bulb sampling mode enabled. + 0x1 + + + + + SMPTRIG + Sampling time control trigger mode + + 27 + 1 + read-write + + + B_0x0 + Sampling time control trigger mode disabled + 0x0 + + + B_0x1 + Sampling time control trigger mode enabled + 0x1 + + + + + + + ADC_SMPR1 + ADC_SMPR1 + ADC sample time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMP0 + Channel x sampling time selection (x=9 to 0) + + 0 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP1 + Channel x sampling time selection (x=9 to 0) + + 3 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP2 + Channel x sampling time selection (x=9 to 0) + + 6 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP3 + Channel x sampling time selection (x=9 to 0) + + 9 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP4 + Channel x sampling time selection (x=9 to 0) + + 12 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP5 + Channel x sampling time selection (x=9 to 0) + + 15 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP6 + Channel x sampling time selection (x=9 to 0) + + 18 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP7 + Channel x sampling time selection (x=9 to 0) + + 21 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP8 + Channel x sampling time selection (x=9 to 0) + + 24 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP9 + Channel x sampling time selection (x=9 to 0) + + 27 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMPPLUS + Addition of one clock cycle to the sampling time. + 31 + 1 + read-write + + + B_0x1 + 2. + 0x1 + + + B_0x0 + The sampling time remains set to 2. + 0x0 + + + + + + + ADC_SMPR2 + ADC_SMPR2 + ADC sample time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMP10 + Channel x sampling time selection (x=19 to 10) + + 0 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP11 + Channel x sampling time selection (x=19 to 10) + + 3 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP12 + Channel x sampling time selection (x=19 to 10) + + 6 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP13 + Channel x sampling time selection (x=19 to 10) + + 9 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP14 + Channel x sampling time selection (x=19 to 10) + + 12 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP15 + Channel x sampling time selection (x=19 to 10) + + 15 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP16 + Channel x sampling time selection (x=19 to 10) + + 18 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP17 + Channel x sampling time selection (x=19 to 10) + + 21 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP18 + Channel x sampling time selection (x=19 to 10) + + 24 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + SMP19 + Channel x sampling time selection (x=19 to 10) + + 27 + 3 + read-write + + + B_0x0 + 2. + 0x0 + + + B_0x1 + 6. + 0x1 + + + B_0x2 + 12. + 0x2 + + + B_0x3 + 24. + 0x3 + + + B_0x4 + 47. + 0x4 + + + B_0x5 + 92. + 0x5 + + + B_0x6 + 247. + 0x6 + + + B_0x7 + 640. + 0x7 + + + + + + + ADC_TR1 + ADC_TR1 + ADC watchdog threshold register 1 + 0x20 + 0x20 + read-write + 0x0FFF0000 + 0xFFFFFFFF + + + LT1 + Analog watchdog 1 lower threshold + + 0 + 12 + read-write + + + AWDFILT + Analog watchdog filtering parameter + + 12 + 3 + read-write + + + B_0x0 + No filtering + 0x0 + + + B_0x1 + two consecutive detection generates an AWDx flag or an interrupt + 0x1 + + + B_0x7 + Eight consecutive detection generates an AWDx flag or an interrupt + 0x7 + + + + + HT1 + Analog watchdog 1 higher threshold + + 16 + 12 + read-write + + + + + ADC_TR2 + ADC_TR2 + ADC watchdog threshold register 2 + 0x24 + 0x20 + read-write + 0x00FF0000 + 0xFFFFFFFF + + + LT2 + Analog watchdog 2 lower threshold + + 0 + 8 + read-write + + + HT2 + Analog watchdog 2 higher threshold + + 16 + 8 + read-write + + + + + ADC_TR3 + ADC_TR3 + ADC watchdog threshold register 3 + 0x28 + 0x20 + read-write + 0x00FF0000 + 0xFFFFFFFF + + + LT3 + Analog watchdog 3 lower threshold + + 0 + 8 + read-write + + + HT3 + Analog watchdog 3 higher threshold + + 16 + 8 + read-write + + + + + ADC_SQR1 + ADC_SQR1 + ADC regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + L + Regular channel sequence length + + 0 + 4 + read-write + + + B_0x0 + 1 conversion + 0x0 + + + B_0x1 + 2 conversions + 0x1 + + + B_0xF + 16 conversions + 0xF + + + + + SQ1 + 1st conversion in regular sequence + + 6 + 5 + read-write + + + SQ2 + 2nd conversion in regular sequence + + 12 + 5 + read-write + + + SQ3 + 3rd conversion in regular sequence + + 18 + 5 + read-write + + + SQ4 + 4th conversion in regular sequence + + 24 + 5 + read-write + + + + + ADC_SQR2 + ADC_SQR2 + ADC regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SQ5 + 5th conversion in regular sequence + + 0 + 5 + read-write + + + SQ6 + 6th conversion in regular sequence + + 6 + 5 + read-write + + + SQ7 + 7th conversion in regular sequence + + 12 + 5 + read-write + + + SQ8 + 8th conversion in regular sequence + + 18 + 5 + read-write + + + SQ9 + 9th conversion in regular sequence + + 24 + 5 + read-write + + + + + ADC_SQR3 + ADC_SQR3 + ADC regular sequence register 3 + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SQ10 + 10th conversion in regular sequence + + 0 + 5 + read-write + + + SQ11 + 11th conversion in regular sequence + + 6 + 5 + read-write + + + SQ12 + 12th conversion in regular sequence + + 12 + 5 + read-write + + + SQ13 + 13th conversion in regular sequence + + 18 + 5 + read-write + + + SQ14 + 14th conversion in regular sequence + + 24 + 5 + read-write + + + + + ADC_SQR4 + ADC_SQR4 + ADC regular sequence register 4 + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SQ15 + 15th conversion in regular sequence + + 0 + 5 + read-write + + + SQ16 + 16th conversion in regular sequence + + 6 + 5 + read-write + + + + + ADC_DR + ADC_DR + ADC regular data register + 0x40 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDATA + Regular data converted + + 0 + 16 + read-only + + + + + ADC_JSQR + ADC_JSQR + ADC injected sequence register + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + JL + Injected channel sequence length + + 0 + 2 + read-write + + + B_0x0 + 1 conversion + 0x0 + + + B_0x1 + 2 conversions + 0x1 + + + B_0x2 + 3 conversions + 0x2 + + + B_0x3 + 4 conversions + 0x3 + + + + + JEXTSEL + External Trigger Selection for injected group + + 2 + 5 + read-write + + + B_0x0 + adc_jext_trg0 + 0x0 + + + B_0x1 + adc_jext_trg1 + 0x1 + + + B_0x2 + adc_jext_trg2 + 0x2 + + + B_0x3 + adc_jext_trg3 + 0x3 + + + B_0x4 + adc_jext_trg4 + 0x4 + + + B_0x5 + adc_jext_trg5 + 0x5 + + + B_0x6 + adc_jext_trg6 + 0x6 + + + B_0x7 + adc_jext_trg7 + 0x7 + + + B_0x1F + adc_jext_trg31 + 0x1F + + + + + JEXTEN + External trigger enable and polarity selection for injected channels + + 7 + 2 + read-write + + + B_0x0 + If JQDIS=0 (queue enabled), hardware and software trigger detection disabled. + 0x0 + + + B_0x1 + Hardware trigger detection on the rising edge + 0x1 + + + B_0x2 + Hardware trigger detection on the falling edge + 0x2 + + + B_0x3 + Hardware trigger detection on both the rising and falling edges + 0x3 + + + + + JSQ1 + 1st conversion in the injected sequence + + 9 + 5 + read-write + + + JSQ2 + 2nd conversion in the injected sequence + + 15 + 5 + read-write + + + JSQ3 + 3rd conversion in the injected sequence + + 21 + 5 + read-write + + + JSQ4 + 4th conversion in the injected sequence + + 27 + 5 + read-write + + + + + ADC_OFR1 + ADC_OFR1 + ADC offset 1 register + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Data offset y for the channel programmed into bits OFFSET_CH[4:0] + + 0 + 12 + read-write + + + OFFSETPOS + Positive offset + + 24 + 1 + read-write + + + B_0x0 + Negative offset + 0x0 + + + B_0x1 + Positive offset + 0x1 + + + + + SATEN + Saturation enable + + 25 + 1 + read-write + + + B_0x0 + No saturation control, offset result can be signed + 0x0 + + + B_0x1 + Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF + 0x1 + + + + + OFFSET_CH + Channel selection for the data offset y + + 26 + 5 + read-write + + + OFFSET_EN + Offset y enable + + 31 + 1 + read-write + + + + + ADC_OFR2 + ADC_OFR2 + ADC offset 2 register + 0x64 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Data offset y for the channel programmed into bits OFFSET_CH[4:0] + + 0 + 12 + read-write + + + OFFSETPOS + Positive offset + + 24 + 1 + read-write + + + B_0x0 + Negative offset + 0x0 + + + B_0x1 + Positive offset + 0x1 + + + + + SATEN + Saturation enable + + 25 + 1 + read-write + + + B_0x0 + No saturation control, offset result can be signed + 0x0 + + + B_0x1 + Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF + 0x1 + + + + + OFFSET_CH + Channel selection for the data offset y + + 26 + 5 + read-write + + + OFFSET_EN + Offset y enable + + 31 + 1 + read-write + + + + + ADC_OFR3 + ADC_OFR3 + ADC offset 3 register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Data offset y for the channel programmed into bits OFFSET_CH[4:0] + + 0 + 12 + read-write + + + OFFSETPOS + Positive offset + + 24 + 1 + read-write + + + B_0x0 + Negative offset + 0x0 + + + B_0x1 + Positive offset + 0x1 + + + + + SATEN + Saturation enable + + 25 + 1 + read-write + + + B_0x0 + No saturation control, offset result can be signed + 0x0 + + + B_0x1 + Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF + 0x1 + + + + + OFFSET_CH + Channel selection for the data offset y + + 26 + 5 + read-write + + + OFFSET_EN + Offset y enable + + 31 + 1 + read-write + + + + + ADC_OFR4 + ADC_OFR4 + ADC offset 4 register + 0x6C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Data offset y for the channel programmed into bits OFFSET_CH[4:0] + + 0 + 12 + read-write + + + OFFSETPOS + Positive offset + + 24 + 1 + read-write + + + B_0x0 + Negative offset + 0x0 + + + B_0x1 + Positive offset + 0x1 + + + + + SATEN + Saturation enable + + 25 + 1 + read-write + + + B_0x0 + No saturation control, offset result can be signed + 0x0 + + + B_0x1 + Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF + 0x1 + + + + + OFFSET_CH + Channel selection for the data offset y + + 26 + 5 + read-write + + + OFFSET_EN + Offset y enable + + 31 + 1 + read-write + + + + + ADC_JDR1 + ADC_JDR1 + ADC injected channel 1 data register + 0x80 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + JDATA + Injected data + + 0 + 16 + read-only + + + + + ADC_JDR2 + ADC_JDR2 + ADC injected channel 2 data register + 0x84 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + JDATA + Injected data + + 0 + 16 + read-only + + + + + ADC_JDR3 + ADC_JDR3 + ADC injected channel 3 data register + 0x88 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + JDATA + Injected data + + 0 + 16 + read-only + + + + + ADC_JDR4 + ADC_JDR4 + ADC injected channel 4 data register + 0x8C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + JDATA + Injected data + + 0 + 16 + read-only + + + + + ADC_AWD2CR + ADC_AWD2CR + ADC analog watchdog 2 configuration register + 0xA0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AWD2CH + Analog watchdog 2 channel selection + + 0 + 20 + read-write + + + + + ADC_AWD3CR + ADC_AWD3CR + ADC analog watchdog 3 configuration register + 0xA4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AWD3CH + Analog watchdog 3 channel selection + + 0 + 20 + read-write + + + + + ADC_DIFSEL + ADC_DIFSEL + ADC Differential mode selection register + 0xB0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DIFSEL + Differential mode for channels 19 to 0. + 0 + 20 + read-write + + + + + ADC_CALFACT + ADC_CALFACT + ADC calibration factors + 0xB4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CALFACT_S + Calibration Factors In single-ended mode + + 0 + 7 + read-write + + + CALFACT_D + Calibration Factors in differential mode + + 16 + 7 + read-write + + + + + ADC_OR + ADC_OR + ADC option register + 0xC8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OP0 + Option bit 0 + + 0 + 1 + read-write + + + B_0x0 + Vless thansub>DDCORE less than/sub>channel disabled + 0x0 + + + B_0x1 + Vless thansub>DDCORE less than/sub>channel enabled + 0x1 + + + + + + + + + ADC_S + 0X52028000 + + + ADC2 + 0x42028100 + + ADC2 + ADC2 global interrupt + 69 + + + + ADC2_S + 0x52028100 + + + ADCC + ADC common registers block + ADC + 0x42028300 + + 0x0 + 0x100 + registers + + + + ADC_CSR + ADC_CSR + ADC common status register + 0x000 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ADRDY_MST + Master ADC ready + + 0 + 1 + read-only + + + EOSMP_MST + End of Sampling phase flag of the master ADC + + 1 + 1 + read-only + + + EOC_MST + End of regular conversion of the master ADC + + 2 + 1 + read-only + + + EOS_MST + End of regular sequence flag of the master ADC + + 3 + 1 + read-only + + + OVR_MST + Overrun flag of the master ADC + + 4 + 1 + read-only + + + JEOC_MST + End of injected conversion flag of the master ADC + + 5 + 1 + read-only + + + JEOS_MST + End of injected sequence flag of the master ADC + + 6 + 1 + read-only + + + AWD1_MST + Analog watchdog 1 flag of the master ADC + + 7 + 1 + read-only + + + AWD2_MST + Analog watchdog 2 flag of the master ADC + + 8 + 1 + read-only + + + AWD3_MST + Analog watchdog 3 flag of the master ADC + + 9 + 1 + read-only + + + JQOVF_MST + Injected Context Queue Overflow flag of the master ADC + + 10 + 1 + read-only + + + ADRDY_SLV + Slave ADC ready + + 16 + 1 + read-only + + + EOSMP_SLV + End of Sampling phase flag of the slave ADC + + 17 + 1 + read-only + + + EOC_SLV + End of regular conversion of the slave ADC + + 18 + 1 + read-only + + + EOS_SLV + End of regular sequence flag of the slave ADC. + 19 + 1 + read-only + + + OVR_SLV + Overrun flag of the slave ADC + + 20 + 1 + read-only + + + JEOC_SLV + End of injected conversion flag of the slave ADC + + 21 + 1 + read-only + + + JEOS_SLV + End of injected sequence flag of the slave ADC + + 22 + 1 + read-only + + + AWD1_SLV + Analog watchdog 1 flag of the slave ADC + + 23 + 1 + read-only + + + AWD2_SLV + Analog watchdog 2 flag of the slave ADC + + 24 + 1 + read-only + + + AWD3_SLV + Analog watchdog 3 flag of the slave ADC + + 25 + 1 + read-only + + + JQOVF_SLV + Injected Context Queue Overflow flag of the slave ADC + + 26 + 1 + read-only + + + + + ADC_CCR + ADC_CCR + ADC common control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DUAL + Dual ADC mode selection + + 0 + 5 + read-write + + + B_0x0 + Independent mode + 0x0 + + + B_0x1 + Combined regular simultaneous + injected simultaneous mode + 0x1 + + + B_0x2 + Combined regular simultaneous + alternate trigger mode + 0x2 + + + B_0x3 + Combined interleaved mode + injected simultaneous mode + 0x3 + + + B_0x5 + Injected simultaneous mode only + 0x5 + + + B_0x6 + Regular simultaneous mode only + 0x6 + + + B_0x7 + Interleaved mode only + 0x7 + + + B_0x9 + Alternate trigger mode only + 0x9 + + + + + DELAY + Delay between 2 sampling phases + + 8 + 4 + read-write + + + DMACFG + DMA configuration (for dual ADC mode) + + 13 + 1 + read-write + + + B_0x0 + DMA One Shot mode selected + 0x0 + + + B_0x1 + DMA Circular mode selected + 0x1 + + + + + MDMA + Direct memory access mode for dual ADC mode + + 14 + 2 + read-write + + + B_0x0 + MDMA mode disabled + 0x0 + + + B_0x2 + MDMA mode enabled for 12 and 10-bit resolution + 0x2 + + + B_0x3 + MDMA mode enabled for 8 and 6-bit resolution + 0x3 + + + + + CKMODE + ADC clock mode + + 16 + 2 + read-write + + + B_0x0 + adc_ker_ck (x = 1/2) (Asynchronous clock mode), generated at product level (refer to Section6: Reset and clock control (RCC)) + 0x0 + + + B_0x1 + adc_hclk/1 (Synchronous clock mode). + 0x1 + + + B_0x2 + adc_hclk/2 (Synchronous clock mode) + 0x2 + + + B_0x3 + adc_hclk/4 (Synchronous clock mode) + 0x3 + + + + + PRESC + ADC prescaler + + 18 + 4 + read-write + + + B_0x0 + input ADC clock not divided + 0x0 + + + B_0x1 + input ADC clock divided by 2 + 0x1 + + + B_0x2 + input ADC clock divided by 4 + 0x2 + + + B_0x3 + input ADC clock divided by 6 + 0x3 + + + B_0x4 + input ADC clock divided by 8 + 0x4 + + + B_0x5 + input ADC clock divided by 10 + 0x5 + + + B_0x6 + input ADC clock divided by 12 + 0x6 + + + B_0x7 + input ADC clock divided by 16 + 0x7 + + + B_0x8 + input ADC clock divided by 32 + 0x8 + + + B_0x9 + input ADC clock divided by 64 + 0x9 + + + B_0xA + input ADC clock divided by 128 + 0xA + + + B_0xB + input ADC clock divided by 256 + 0xB + + + + + VREFEN + Vless thansub>REFINTless than/sub> enable + + 22 + 1 + read-write + + + B_0x0 + Vless thansub>REFINTless than/sub> channel disabled + 0x0 + + + B_0x1 + Vless thansub>REFINTless than/sub> channel enabled + 0x1 + + + + + TSEN + Vless thansub>SENSEless than/sub> enable + + 23 + 1 + read-write + + + B_0x0 + Temperature sensor channel disabled + 0x0 + + + B_0x1 + Temperature sensor channel enabled + 0x1 + + + + + VBATEN + VBAT enable + + 24 + 1 + read-write + + + B_0x0 + Vless thansub>BATless than/sub> channel disabled + 0x0 + + + B_0x1 + Vless thansub>BATless than/sub> channel enabled + 0x1 + + + + + + + ADC_CDR + ADC_CDR + ADC common regular data register for dual mode + 0x00C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDATA_MST + Regular data of the master ADC. + 0 + 16 + read-only + + + RDATA_SLV + Regular data of the slave ADC + + 16 + 16 + read-only + + + + + ADC_HWCFGR0 + ADC_HWCFGR0 + ADC hardware configuration register + 0x0F0 + 0x20 + read-only + 0x00001212 + 0xFFFFFFFF + + + ADCNUM + Number of ADCs implemented + 0 + 4 + read-only + + + B_0x1 + One ADC instance implemented + 0x1 + + + B_0x2 + Two ADC instances implemented + 0x2 + + + B_0x3 + Three ADCs instances implemented + 0x3 + + + + + MULPIPE + Number of pipeline stages + 4 + 4 + read-only + + + B_0x1 + One-stage pipeline + 0x1 + + + + + OPBITS + Number of option bits + 8 + 4 + read-only + + + B_0x0 + No option register implemented + 0x0 + + + B_0x1 + 1 option bit implemented in the ADC option register (ADC_OR) at address offset 0xC8 + 0x1 + + + + + IDLEVALUE + Idle value for non-selected channels + 12 + 4 + read-only + + + B_0x0 + Dummy channel selection is 0x13 + 0x0 + + + B_0x1 + Dummy channel selection is 0x1F + 0x1 + + + + + + + ADC_VERR + ADC_VERR + ADC version register + 0x0F4 + 0x20 + read-only + 0x00000012 + 0xFFFFFFFF + + + MINREV + Minor revision + + 0 + 4 + read-only + + + B_0x1 + Minor revision = X. + 0x1 + + + + + MAJREV + Major revision + + 4 + 4 + read-only + + + B_0x1 + Major revision = 1. + 0x1 + + + + + + + ADC_IPDR + ADC_IPDR + ADC identification register + 0x0F8 + 0x20 + read-only + 0x00110006 + 0xFFFFFFFF + + + ID + Peripheral identifier + + 0 + 32 + read-only + + + + + ADC_SIDR + ADC_SIDR + ADC size identification register + 0x0FC + 0x20 + read-only + 0xA3C5DD01 + 0xFFFFFFFF + + + SID + Size Identification + + 0 + 32 + read-only + + + B_0x01 + 1Kbytes address offset + 0x01 + + + B_0x02 + 2Kbytes address offset + 0x02 + + + B_0x04 + 4Kbytes address offset + 0x04 + + + B_0x08 + 8 Kbytes address offset + 0x08 + + + + + + + + + SEC_ADCC + 0x52028300 + + + AES + AES register block + AES + 0x420C0000 + + 0x0 + 0x400 + registers + + + AES + AES global interrupt + 116 + + + + AES_CR + AES_CR + AES control register + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + Enable + + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DATATYPE + Data type + + 1 + 2 + read-write + + + B_0x0 + No swapping (32-bit data). + 0x0 + + + B_0x1 + Half-word swapping (16-bit data) + 0x1 + + + B_0x2 + Byte swapping (8-bit data) + 0x2 + + + B_0x3 + Bit-level swapping + 0x3 + + + + + MODE + Operating mode + + 3 + 2 + read-write + + + B_0x0 + Encryption + 0x0 + + + B_0x1 + Key derivation (or key preparation), for ECB/CBC decryption only + 0x1 + + + B_0x2 + Decryption + 0x2 + + + + + CHMOD + CHMOD[1:0]: Chaining mode + + 5 + 2 + read-write + + + B_0x0 + Electronic codebook (ECB) + 0x0 + + + B_0x1 + Cipher-block chaining (CBC) + 0x1 + + + B_0x2 + Counter mode (CTR) + 0x2 + + + B_0x3 + Galois counter mode (GCM) and Galois message authentication code (GMAC) + 0x3 + + + + + DMAINEN + DMA input enable + + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DMAOUTEN + DMA output enable + + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GCMPH + GCM or CCM phase selection + + 13 + 2 + read-write + + + B_0x0 + Initialization phase + 0x0 + + + B_0x1 + Header phase + 0x1 + + + B_0x2 + Payload phase + 0x2 + + + B_0x3 + Final phase + 0x3 + + + + + CHMOD_1 + CHMOD[2] + 16 + 1 + read-write + + + KEYSIZE + Key size selection + + 18 + 1 + read-write + + + B_0x0 + 128-bit + 0x0 + + + B_0x1 + 256-bit + 0x1 + + + + + NPBLB + Number of padding bytes in last block + + 20 + 4 + read-write + + + B_0x0 + All bytes are valid (no padding) + 0x0 + + + B_0x1 + Padding for the last LSB byte + 0x1 + + + B_0xF + Padding for the 15 LSB bytes of last block. + 0xF + + + + + KMOD + Key mode selection + + 24 + 2 + read-write + + + B_0x0 + Normal key mode. + 0x0 + + + B_0x2 + Shared key mode. + 0x2 + + + + + IPRST + AES peripheral software reset + + 31 + 1 + read-write + + + + + AES_SR + AES_SR + AES status register + 0x004 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDERRF + Read error flag + + 1 + 1 + read-only + + + B_0x0 + No error + 0x0 + + + B_0x1 + Unexpected read to AES_DOUTR register occurred during computation or data input phase. + 0x1 + + + + + WRERRF + Write error flag + + 2 + 1 + read-only + + + B_0x0 + No error + 0x0 + + + B_0x1 + Unexpected write to AES_DINR register occurred during computation or data output phase. + 0x1 + + + + + BUSY + Busy + + 3 + 1 + read-only + + + B_0x0 + Idle + 0x0 + + + B_0x1 + Busy + 0x1 + + + + + KEYVALID + Key valid flag + + 7 + 1 + read-only + + + B_0x0 + Key not valid + 0x0 + + + B_0x1 + Key valid + 0x1 + + + + + + + AES_DINR + AES_DINR + AES data input register + 0x008 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + DIN + Data input + + 0 + 32 + write-only + + + + + AES_DOUTR + AES_DOUTR + AES data output register + 0x00C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DOUT + Data output + + 0 + 32 + read-only + + + + + AES_KEYR0 + AES_KEYR0 + AES key register 0 + 0x010 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [31:0] + + 0 + 32 + write-only + + + + + AES_KEYR1 + AES_KEYR1 + AES key register 1 + 0x014 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [63:32] + + 0 + 32 + write-only + + + + + AES_KEYR2 + AES_KEYR2 + AES key register 2 + 0x018 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [95:64] + + 0 + 32 + write-only + + + + + AES_KEYR3 + AES_KEYR3 + AES key register 3 + 0x01C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [127:96] + + 0 + 32 + write-only + + + + + AES_IVR0 + AES_IVR0 + AES initialization vector register 0 + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [31:0] + + 0 + 32 + read-write + + + + + AES_IVR1 + AES_IVR1 + AES initialization vector register 1 + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [63:32] + + 0 + 32 + read-write + + + + + AES_IVR2 + AES_IVR2 + AES initialization vector register 2 + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [95:64] + + 0 + 32 + read-write + + + + + AES_IVR3 + AES_IVR3 + AES initialization vector register 3 + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [127:96] + + 0 + 32 + read-write + + + + + AES_KEYR4 + AES_KEYR4 + AES key register 4 + 0x030 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [159:128] + + 0 + 32 + write-only + + + + + AES_KEYR5 + AES_KEYR5 + AES key register 5 + 0x034 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [191:160] + + 0 + 32 + write-only + + + + + AES_KEYR6 + AES_KEYR6 + AES key register 6 + 0x038 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [223:192] + + 0 + 32 + write-only + + + + + AES_KEYR7 + AES_KEYR7 + AES key register 7 + 0x03C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [255:224] + + 0 + 32 + write-only + + + + + AES_SUSPR0 + AES_SUSPR0 + AES suspend registers + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + AES_SUSPR1 + AES_SUSPR1 + AES suspend registers + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + AES_SUSPR2 + AES_SUSPR2 + AES suspend registers + 0x48 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + AES_SUSPR3 + AES_SUSPR3 + AES suspend registers + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + AES_SUSPR4 + AES_SUSPR4 + AES suspend registers + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + AES_SUSPR5 + AES_SUSPR5 + AES suspend registers + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + AES_SUSPR6 + AES_SUSPR6 + AES suspend registers + 0x58 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + AES_SUSPR7 + AES_SUSPR7 + AES suspend registers + 0x5C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + AES_IER + AES_IER + AES interrupt enable register + 0x300 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCFIE + Computation complete flag interrupt enable + + 0 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + RWEIE + Read or write error interrupt enable + + 1 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + KEIE + Key error interrupt enable + + 2 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + + + AES_ISR + AES_ISR + AES interrupt status register + 0x304 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CCF + Computation complete flag + + 0 + 1 + read-only + + + B_0x0 + Not completed + 0x0 + + + B_0x1 + Completed + 0x1 + + + + + RWEIF + Read or write error interrupt flag + + 1 + 1 + read-only + + + B_0x0 + No read or write error detected + 0x0 + + + B_0x1 + Read or write error detected + 0x1 + + + + + KEIF + Key error interrupt flag + + 2 + 1 + read-only + + + B_0x0 + No key error detected + 0x0 + + + B_0x1 + Key information failed to load into key registers + 0x1 + + + + + + + AES_ICR + AES_ICR + AES interrupt clear register + 0x308 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CCF + Computation complete flag clear + + 0 + 1 + write-only + + + RWEIF + Read or write error interrupt flag clear + + 1 + 1 + write-only + + + KEIF + Key error interrupt flag clear + + 2 + 1 + write-only + + + + + + + AES_S + 0x520C0000 + + + CRC + CRC address block description + CRC + 0x40023000 + + 0x0 + 0x18 + registers + + + + CRC_DR + CRC_DR + CRC data register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DR + Data register bits + + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC independent data register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDR + General-purpose 32-bit data register bits + + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RESET + RESET bit + + 0 + 1 + read-write + + + POLYSIZE + Polynomial size + + 3 + 2 + read-write + + + B_0x0 + 32 bit polynomial + 0x0 + + + B_0x1 + 16 bit polynomial + 0x1 + + + B_0x2 + 8 bit polynomial + 0x2 + + + B_0x3 + 7 bit polynomial + 0x3 + + + + + REV_IN + Reverse input data + + 5 + 2 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit reversal done by byte + 0x1 + + + B_0x2 + Bit reversal done by half-word + 0x2 + + + B_0x3 + Bit reversal done by word + 0x3 + + + + + REV_OUT + Reverse output data + + 7 + 1 + read-write + + + B_0x0 + Bit order not affected + 0x0 + + + B_0x1 + Bit-reversed output format + 0x1 + + + + + + + CRC_INIT + CRC_INIT + CRC initial value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value + + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + 0xFFFFFFFF + + + POL + Programmable polynomial + + 0 + 32 + read-write + + + + + + + CRC_S + 0X50023000 + + + CRS + CRS address block description + CRS + 0x40006000 + + 0x0 + 0x10 + registers + + + CRS + Clock Recovery System global interrupt + 75 + + + + CRS_CR + CRS_CR + CRS control register + 0x00 + 0x20 + read-write + 0x00004000 + 0xFFFFFFFF + + + SYNCOKIE + SYNC event OK interrupt enable + 0 + 1 + read-write + + + B_0x0 + SYNC event OK (SYNCOKF) interrupt disabled + 0x0 + + + B_0x1 + SYNC event OK (SYNCOKF) interrupt enabled + 0x1 + + + + + SYNCWARNIE + SYNC warning interrupt enable + 1 + 1 + read-write + + + B_0x0 + SYNC warning (SYNCWARNF) interrupt disabled + 0x0 + + + B_0x1 + SYNC warning (SYNCWARNF) interrupt enabled + 0x1 + + + + + ERRIE + Synchronization or trimming error interrupt enable + 2 + 1 + read-write + + + B_0x0 + Synchronization or trimming error (ERRF) interrupt disabled + 0x0 + + + B_0x1 + Synchronization or trimming error (ERRF) interrupt enabled + 0x1 + + + + + ESYNCIE + Expected SYNC interrupt enable + 3 + 1 + read-write + + + B_0x0 + Expected SYNC (ESYNCF) interrupt disabled + 0x0 + + + B_0x1 + Expected SYNC (ESYNCF) interrupt enabled + 0x1 + + + + + CEN + Frequency error counter enable + + 5 + 1 + read-write + + + B_0x0 + Frequency error counter disabled + 0x0 + + + B_0x1 + Frequency error counter enabled + 0x1 + + + + + AUTOTRIMEN + Automatic trimming enable + + 6 + 1 + read-write + + + B_0x0 + Automatic trimming disabled, TRIM bits can be adjusted by the user. + 0x0 + + + B_0x1 + Automatic trimming enabled, TRIM bits are read-only and under hardware control. + 0x1 + + + + + SWSYNC + Generate software SYNC event + + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + A software SYNC event is generated. + 0x1 + + + + + TRIM + HSI48 oscillator smooth trimming + + 8 + 6 + read-write + + + + + CRS_CFGR + CRS_CFGR + CRS configuration register + 0x04 + 0x20 + read-write + 0x2022BB7F + 0xFFFFFFFF + + + RELOAD + Counter reload value + + 0 + 16 + read-write + + + FELIM + Frequency error limit + + 16 + 8 + read-write + + + SYNCDIV + SYNC divider + + 24 + 3 + read-write + + + B_0x0 + SYNC not divided (default) + 0x0 + + + B_0x1 + SYNC divided by 2 + 0x1 + + + B_0x2 + SYNC divided by 4 + 0x2 + + + B_0x3 + SYNC divided by 8 + 0x3 + + + B_0x4 + SYNC divided by 16 + 0x4 + + + B_0x5 + SYNC divided by 32 + 0x5 + + + B_0x6 + SYNC divided by 64 + 0x6 + + + B_0x7 + SYNC divided by 128 + 0x7 + + + + + SYNCSRC + SYNC signal source selection + + 28 + 2 + read-write + + + B_0x0 + crs_sync_in_1 selected as SYNC signal source + 0x0 + + + B_0x1 + crs_sync_in_2 selected as SYNC signal source + 0x1 + + + B_0x2 + crs_sync_in_3 selected as SYNC signal source + 0x2 + + + B_0x3 + crs_sync_in_4 selected as SYNC signal source + 0x3 + + + + + SYNCPOL + SYNC polarity selection + + 31 + 1 + read-write + + + B_0x0 + SYNC active on rising edge (default) + 0x0 + + + B_0x1 + SYNC active on falling edge + 0x1 + + + + + + + CRS_ISR + CRS_ISR + CRS interrupt and status register + 0x08 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SYNCOKF + SYNC event OK flag + + 0 + 1 + read-only + + + B_0x0 + No SYNC event OK signaled + 0x0 + + + B_0x1 + SYNC event OK signaled + 0x1 + + + + + SYNCWARNF + SYNC warning flag + + 1 + 1 + read-only + + + B_0x0 + No SYNC warning signaled + 0x0 + + + B_0x1 + SYNC warning signaled + 0x1 + + + + + ERRF + Error flag + + 2 + 1 + read-only + + + B_0x0 + No synchronization or trimming error signaled + 0x0 + + + B_0x1 + Synchronization or trimming error signaled + 0x1 + + + + + ESYNCF + Expected SYNC flag + + 3 + 1 + read-only + + + B_0x0 + No expected SYNC signaled + 0x0 + + + B_0x1 + Expected SYNC signaled + 0x1 + + + + + SYNCERR + SYNC error + + 8 + 1 + read-only + + + B_0x0 + No SYNC error signaled + 0x0 + + + B_0x1 + SYNC error signaled + 0x1 + + + + + SYNCMISS + SYNC missed + + 9 + 1 + read-only + + + B_0x0 + No SYNC missed error signaled + 0x0 + + + B_0x1 + SYNC missed error signaled + 0x1 + + + + + TRIMOVF + Trimming overflow or underflow + + 10 + 1 + read-only + + + B_0x0 + No trimming error signaled + 0x0 + + + B_0x1 + Trimming error signaled + 0x1 + + + + + FEDIR + Frequency error direction + + 15 + 1 + read-only + + + B_0x0 + Up-counting direction, the actual frequency is above the target + 0x0 + + + B_0x1 + Down-counting direction, the actual frequency is below the target + 0x1 + + + + + FECAP + Frequency error capture + + 16 + 16 + read-only + + + + + CRS_ICR + CRS_ICR + CRS interrupt flag clear register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYNCOKC + SYNC event OK clear flag + + 0 + 1 + read-write + + + SYNCWARNC + SYNC warning clear flag + + 1 + 1 + read-write + + + ERRC + Error clear flag + + 2 + 1 + read-write + + + ESYNCC + Expected SYNC clear flag + + 3 + 1 + read-write + + + + + + + CRS_S + 0X50006000 + + + DAC + DAC address block description + DAC + 0x42028400 + + 0x0 + 0x50 + registers + + + DAC1 + DAC1 global interrupt + 38 + + + + DAC_CR + DAC_CR + DAC control register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN1 + DAC channel1 enable + + 0 + 1 + read-write + + + B_0x0 + DAC channel1 disabled + 0x0 + + + B_0x1 + DAC channel1 enabled + 0x1 + + + + + TEN1 + DAC channel1 trigger enable + + 1 + 1 + read-write + + + B_0x0 + DAC channel1 trigger disabled and data written into the DAC_DHR1 register are transferred one dac_hclk clock cycle later to the DAC_DOR1 register + 0x0 + + + B_0x1 + DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred three dac_hclk clock cycles later to the DAC_DOR1 register + 0x1 + + + + + TSEL1 + DAC channel1 trigger selection + + 2 + 4 + read-write + + + B_0x0 + SWTRIG1 + 0x0 + + + B_0x1 + dac_ch1_trg1 + 0x1 + + + B_0x2 + dac_ch1_trg2 + 0x2 + + + B_0xF + dac_ch1_trg15 + 0xF + + + + + WAVE1 + DAC channel1 noise/triangle wave generation enable + + 6 + 2 + read-write + + + B_0x0 + wave generation disabled + 0x0 + + + B_0x1 + Noise wave generation enabled + 0x1 + + + + + MAMP1 + DAC channel1 mask/amplitude selector + + 8 + 4 + read-write + + + B_0x0 + Unmask bit0 of LFSR/ triangle amplitude equal to 1 + 0x0 + + + B_0x1 + Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 + 0x1 + + + B_0x2 + Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 + 0x2 + + + B_0x3 + Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 + 0x3 + + + B_0x4 + Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 + 0x4 + + + B_0x5 + Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 + 0x5 + + + B_0x6 + Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 + 0x6 + + + B_0x7 + Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 + 0x7 + + + B_0x8 + Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 + 0x8 + + + B_0x9 + Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 + 0x9 + + + B_0xA + Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 + 0xA + + + + + DMAEN1 + DAC channel1 DMA enable + + 12 + 1 + read-write + + + B_0x0 + DAC channel1 DMA mode disabled + 0x0 + + + B_0x1 + DAC channel1 DMA mode enabled + 0x1 + + + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt enable + + 13 + 1 + read-write + + + B_0x0 + DAC channel1 DMA Underrun Interrupt disabled + 0x0 + + + B_0x1 + DAC channel1 DMA Underrun Interrupt enabled + 0x1 + + + + + CEN1 + DAC channel1 calibration enable + + 14 + 1 + read-write + + + B_0x0 + DAC channel1 in Normal operating mode + 0x0 + + + B_0x1 + DAC channel1 in calibration mode + 0x1 + + + + + EN2 + DAC channel2 enable + + 16 + 1 + read-write + + + B_0x0 + DAC channel2 disabled + 0x0 + + + B_0x1 + DAC channel2 enabled + 0x1 + + + + + TEN2 + DAC channel2 trigger enable + + 17 + 1 + read-write + + + B_0x0 + DAC channel2 trigger disabled and data written into the DAC_DHR2 register are transferred one dac_hclk clock cycle later to the DAC_DOR2 register + 0x0 + + + B_0x1 + DAC channel2 trigger enabled and data from the DAC_DHR2 register are transferred three dac_hclk clock cycles later to the DAC_DOR2 register + 0x1 + + + + + TSEL2 + DAC channel2 trigger selection + + 18 + 4 + read-write + + + B_0x0 + SWTRIG2 + 0x0 + + + B_0x1 + dac_ch2_trg1 + 0x1 + + + B_0x2 + dac_ch2_trg2 + 0x2 + + + B_0xF + dac_ch2_trg15 + 0xF + + + + + WAVE2 + DAC channel2 noise/triangle wave generation enable + + 22 + 2 + read-write + + + B_0x0 + wave generation disabled + 0x0 + + + B_0x1 + Noise wave generation enabled + 0x1 + + + + + MAMP2 + DAC channel2 mask/amplitude selector + + 24 + 4 + read-write + + + B_0x0 + Unmask bit0 of LFSR/ triangle amplitude equal to 1 + 0x0 + + + B_0x1 + Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 + 0x1 + + + B_0x2 + Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 + 0x2 + + + B_0x3 + Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 + 0x3 + + + B_0x4 + Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 + 0x4 + + + B_0x5 + Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 + 0x5 + + + B_0x6 + Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 + 0x6 + + + B_0x7 + Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 + 0x7 + + + B_0x8 + Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 + 0x8 + + + B_0x9 + Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 + 0x9 + + + B_0xA + Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 + 0xA + + + + + DMAEN2 + DAC channel2 DMA enable + + 28 + 1 + read-write + + + B_0x0 + DAC channel2 DMA mode disabled + 0x0 + + + B_0x1 + DAC channel2 DMA mode enabled + 0x1 + + + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt enable + + 29 + 1 + read-write + + + B_0x0 + DAC channel2 DMA underrun interrupt disabled + 0x0 + + + B_0x1 + DAC channel2 DMA underrun interrupt enabled + 0x1 + + + + + CEN2 + DAC channel2 calibration enable + + 30 + 1 + read-write + + + B_0x0 + DAC channel2 in Normal operating mode + 0x0 + + + B_0x1 + DAC channel2 in calibration mode + 0x1 + + + + + + + DAC_SWTRGR + DAC_SWTRGR + DAC software trigger register + 0x04 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SWTRIG1 + DAC channel1 software trigger + + 0 + 1 + write-only + + + B_0x0 + No trigger + 0x0 + + + B_0x1 + Trigger + 0x1 + + + + + SWTRIG2 + DAC channel2 software trigger + + 1 + 1 + write-only + + + B_0x0 + No trigger + 0x0 + + + B_0x1 + Trigger + 0x1 + + + + + + + DAC_DHR12R1 + DAC_DHR12R1 + DAC channel1 12-bit right-aligned data holding register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit right-aligned data + + 0 + 12 + read-write + + + DACC1DHRB + DAC channel1 12-bit right-aligned data B + + 16 + 12 + read-write + + + + + DAC_DHR12L1 + DAC_DHR12L1 + DAC channel1 12-bit left aligned data holding register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit left-aligned data + + 4 + 12 + read-write + + + DACC1DHRB + DAC channel1 12-bit left-aligned data B + + 20 + 12 + read-write + + + + + DAC_DHR8R1 + DAC_DHR8R1 + DAC channel1 8-bit right aligned data holding register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 8-bit right-aligned data + + 0 + 8 + read-write + + + DACC1DHRB + DAC channel1 8-bit right-aligned data + + 8 + 8 + read-write + + + + + DAC_DHR12R2 + DAC_DHR12R2 + DAC channel2 12-bit right aligned data holding register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC2DHR + DAC channel2 12-bit right-aligned data + + 0 + 12 + read-write + + + DACC2DHRB + DAC channel2 12-bit right-aligned data + + 16 + 12 + read-write + + + + + DAC_DHR12L2 + DAC_DHR12L2 + DAC channel2 12-bit left aligned data holding register + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC2DHR + DAC channel2 12-bit left-aligned data + + 4 + 12 + read-write + + + DACC2DHRB + DAC channel2 12-bit left-aligned data B + + 20 + 12 + read-write + + + + + DAC_DHR8R2 + DAC_DHR8R2 + DAC channel2 8-bit right-aligned data holding register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC2DHR + DAC channel2 8-bit right-aligned data + + 0 + 8 + read-write + + + DACC2DHRB + DAC channel2 8-bit right-aligned data + + 8 + 8 + read-write + + + + + DAC_DHR12RD + DAC_DHR12RD + Dual DAC 12-bit right-aligned data holding register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit right-aligned data + + 0 + 12 + read-write + + + DACC2DHR + DAC channel2 12-bit right-aligned data + + 16 + 12 + read-write + + + + + DAC_DHR12LD + DAC_DHR12LD + Dual DAC 12-bit left aligned data holding register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 12-bit left-aligned data + + 4 + 12 + read-write + + + DACC2DHR + DAC channel2 12-bit left-aligned data + + 20 + 12 + read-write + + + + + DAC_DHR8RD + DAC_DHR8RD + Dual DAC 8-bit right aligned data holding register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DACC1DHR + DAC channel1 8-bit right-aligned data + + 0 + 8 + read-write + + + DACC2DHR + DAC channel2 8-bit right-aligned data + + 8 + 8 + read-write + + + + + DAC_DOR1 + DAC_DOR1 + DAC channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DACC1DOR + DAC channel1 data output + + 0 + 12 + read-only + + + DACC1DORB + DAC channel1 data output + + 16 + 12 + read-only + + + + + DAC_DOR2 + DAC_DOR2 + DAC channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DACC2DOR + DAC channel2 data output + + 0 + 12 + read-only + + + DACC2DORB + DAC channel2 data output + + 16 + 12 + read-only + + + + + DAC_SR + DAC_SR + DAC status register + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DAC1RDY + DAC channel1 ready status bit + + 11 + 1 + read-only + + + B_0x0 + DAC channel1 is not yet ready to accept the trigger nor output data + 0x0 + + + B_0x1 + DAC channel1 is ready to accept the trigger or output data + 0x1 + + + + + DORSTAT1 + DAC channel1 output register status bit + + 12 + 1 + read-only + + + B_0x0 + DOR[11:0] is used actual DAC output + 0x0 + + + B_0x1 + DORB[11:0] is used actual DAC output + 0x1 + + + + + DMAUDR1 + DAC channel1 DMA underrun flag + + 13 + 1 + read-write + + + B_0x0 + No DMA underrun error condition occurred for DAC channel1 + 0x0 + + + B_0x1 + DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) + 0x1 + + + + + CAL_FLAG1 + DAC channel1 calibration offset status + + 14 + 1 + read-only + + + B_0x0 + calibration trimming value is lower than the offset correction value + 0x0 + + + B_0x1 + calibration trimming value is equal or greater than the offset correction value + 0x1 + + + + + BWST1 + DAC channel1 busy writing sample time flag + + 15 + 1 + read-only + + + B_0x0 + There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written + 0x0 + + + B_0x1 + There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written + 0x1 + + + + + DAC2RDY + DAC channel2 ready status bit + + 27 + 1 + read-only + + + B_0x0 + DAC channel2 is not yet ready to accept the trigger nor output data + 0x0 + + + B_0x1 + DAC channel2 is ready to accept the trigger or output data + 0x1 + + + + + DORSTAT2 + DAC channel2 output register status bit + + 28 + 1 + read-only + + + B_0x0 + DOR[11:0] is used actual DAC output + 0x0 + + + B_0x1 + DORB[11:0] is used actual DAC output + 0x1 + + + + + DMAUDR2 + DAC channel2 DMA underrun flag + + 29 + 1 + read-write + + + B_0x0 + No DMA underrun error condition occurred for DAC channel2 + 0x0 + + + B_0x1 + DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate). + 0x1 + + + + + CAL_FLAG2 + DAC channel2 calibration offset status + + 30 + 1 + read-only + + + B_0x0 + calibration trimming value is lower than the offset correction value + 0x0 + + + B_0x1 + calibration trimming value is equal or greater than the offset correction value + 0x1 + + + + + BWST2 + DAC channel2 busy writing sample time flag + + 31 + 1 + read-only + + + B_0x0 + There is no write operation of DAC_SHSR2 ongoing: DAC_SHSR2 can be written + 0x0 + + + B_0x1 + There is a write operation of DAC_SHSR2 ongoing: DAC_SHSR2 cannot be written + 0x1 + + + + + + + DAC_CCR + DAC_CCR + DAC calibration control register + 0x38 + 0x20 + read-write + 0x00000000 + 0xFF00FF00 + + + OTRIM1 + DAC channel1 offset trimming value + 0 + 5 + read-write + + + OTRIM2 + DAC channel2 offset trimming value + + 16 + 5 + read-write + + + + + DAC_MCR + DAC_MCR + DAC mode control register + 0x3C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MODE1 + DAC channel1 mode + + 0 + 3 + read-write + + + B_0x0 + DAC channel1 is connected to external pin with Buffer enabled + 0x0 + + + B_0x2 + DAC channel1 is connected to external pin with Buffer disabled + 0x2 + + + B_0x4 + DAC channel1 is connected to external pin with Buffer enabled + 0x4 + + + B_0x6 + DAC channel1 is connected to external pin with Buffer disabled + 0x6 + + + + + DMADOUBLE1 + DAC channel1 DMA double data mode + + 8 + 1 + read-write + + + B_0x0 + DMA Normal mode selected + 0x0 + + + B_0x1 + DMA Double data mode selected + 0x1 + + + + + SINFORMAT1 + Enable signed format for DAC channel1 + + 9 + 1 + read-write + + + B_0x0 + Input data is in unsigned format + 0x0 + + + B_0x1 + Input data is in signed format (2's complement). + 0x1 + + + + + HFSEL + High frequency interface mode selection + 14 + 2 + read-write + + + B_0x0 + High frequency interface mode disabled + 0x0 + + + B_0x1 + High frequency interface mode enabled for AHB clock frequency > 80 MHz + 0x1 + + + B_0x2 + High frequency interface mode enabled for AHB clock frequency >160 MHz + 0x2 + + + + + MODE2 + DAC channel2 mode + + 16 + 3 + read-write + + + B_0x0 + DAC channel2 is connected to external pin with Buffer enabled + 0x0 + + + B_0x2 + DAC channel2 is connected to external pin with buffer disabled + 0x2 + + + B_0x4 + DAC channel2 is connected to external pin with Buffer enabled + 0x4 + + + B_0x6 + DAC channel2 is connected to external pin with Buffer disabled + 0x6 + + + + + DMADOUBLE2 + DAC channel2 DMA double data mode + + 24 + 1 + read-write + + + B_0x0 + DMA Normal mode selected + 0x0 + + + B_0x1 + DMA Double data mode selected + 0x1 + + + + + SINFORMAT2 + Enable signed format for DAC channel2 + + 25 + 1 + read-write + + + B_0x0 + Input data is in unsigned format + 0x0 + + + B_0x1 + Input data is in signed format (2's complement). + 0x1 + + + + + + + DAC_SHSR1 + DAC_SHSR1 + DAC channel1 sample and hold sample time register + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSAMPLE1 + DAC channel1 sample time (only valid in Sample and hold mode) + + 0 + 10 + read-write + + + + + DAC_SHSR2 + DAC_SHSR2 + DAC channel2 sample and hold sample time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSAMPLE2 + DAC channel2 sample time (only valid in Sample and hold mode) + + 0 + 10 + read-write + + + + + DAC_SHHR + DAC_SHHR + DAC sample and hold time register + 0x48 + 0x20 + read-write + 0x00010001 + 0xFFFFFFFF + + + THOLD1 + DAC channel1 hold time (only valid in Sample and hold mode) + + 0 + 10 + read-write + + + THOLD2 + DAC channel2 hold time (only valid in Sample and hold mode). + 16 + 10 + read-write + + + + + DAC_SHRR + DAC_SHRR + DAC sample and hold refresh time register + 0x4C + 0x20 + read-write + 0x00010001 + 0xFFFFFFFF + + + TREFRESH1 + DAC channel1 refresh time (only valid in Sample and hold mode) + + 0 + 8 + read-write + + + TREFRESH2 + DAC channel2 refresh time (only valid in Sample and hold mode) + + 16 + 8 + read-write + + + + + + + DAC_S + 0X52028400 + + + DBGMCU + DBGMCU register block + DBGMCU + 0x44024000 + + 0x0 + 0x1000 + registers + + + + DBGMCU_IDCODE + DBGMCU_IDCODE + DBGMCU identity code register + 0x00 + 0x20 + read-only + 0x00006000 + 0x0000F000 + + + DEV_ID + Device identification + 0 + 12 + read-only + + + B_0x484 + STM32H562/563/573 + 0x484 + + + B_0x478 + STM32H523/533 + 0x478 + + + + + REV_ID + Revision + + 16 + 16 + read-only + + + + + DBGMCU_CR + DBGMCU_CR + DBGMCU configuration register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_STOP + Allows debug in Stop mode + + 1 + 1 + read-write + + + B_0x0 + normal operation + 0x0 + + + B_0x1 + automatic clock stop disabled + 0x1 + + + + + DBG_STANDBY + Allows debug in Standby mode + + 2 + 1 + read-write + + + B_0x0 + normal operation + 0x0 + + + B_0x1 + automatic clock stop/power down disabled + 0x1 + + + + + TRACE_IOEN + trace pin enable + 4 + 1 + read-write + + + B_0x0 + disabled - trace pins not assigned + 0x0 + + + B_0x1 + enabled - trace pins assigned according to the value of TRACE_MODE field + 0x1 + + + + + TRACE_EN + trace port and clock enable. + 5 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + TRACE_MODE + trace pin assignment + 6 + 2 + read-write + + + B_0x0 + trace pins assigned for asynchronous mode (TRACESWO) + 0x0 + + + B_0x1 + trace pins assigned for synchronous mode with a port width of 1 (TRACECK, TRACED0) + 0x1 + + + B_0x2 + trace pins assigned for synchronous mode with a port width of 2 ((TRACECK, TRACED0-1) + 0x2 + + + B_0x3 + trace pins assigned for synchronous mode with a port width of 4 ((TRACECK, TRACED0-3) + 0x3 + + + + + DCRT + Debug credentials reset type + + 16 + 1 + read-write + + + B_0x0 + System reset + 0x0 + + + B_0x1 + Power reset + 0x1 + + + + + + + DBGMCU_APB1LFZR + DBGMCU_APB1LFZR + DBGMCU APB1L peripheral freeze register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_TIM2_STOP + TIM2 stop in debug + 0 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM3_STOP + TIM3 stop in debug + 1 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM4_STOP + TIM4 stop in debug + 2 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM5_STOP + TIM5 stop in debug + 3 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + Stop in debug. + 0x1 + + + + + DBG_TIM6_STOP + TIM6 stop in debug + 4 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM7_STOP + TIM7 stop in debug + 5 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM12_STOP + TIM12 stop in debug + 6 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM13_STOP + TIM13 stop in debug + 7 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM14_STOP + TIM14 stop in debug + 8 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_WWDG_STOP + WWDG stop in debug + 11 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_IWDG_STOP + IWDG stop in debug + 12 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_I2C1_STOP + I2C1 SMBUS timeout stop in debug + 21 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_I2C2_STOP + I2C2 SMBUS timeout stop in debug + 22 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_I3C1_STOP + I3C1 SCL stall counter stop in debug + 23 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + + + DBGMCU_APB1HFZR + DBGMCU_APB1HFZR + DBGMCU APB1H peripheral freeze register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_LPTIM2_STOP + LPTIM2 stop in debug + 5 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + + + DBGMCU_APB2FZR + DBGMCU_APB2FZR + DBGMCU APB2 peripheral freeze register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_TIM1_STOP + TIM1 stop in debug + 11 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM8_STOP + TIM8 stop in debug + 13 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM15_STOP + TIM15 stop in debug + 16 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM16_STOP + TIM16 stop in debug + 17 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_TIM17_STOP + TIM17 stop in debug + 18 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + + + DBGMCU_APB3FZR + DBGMCU_APB3FZR + DBGMCU APB3 peripheral freeze register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_I2C3_STOP + I2C3 SMBUS timeout stop in debug + 10 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_I2C4_STOP + I2C4 SMBUS timeout stop in debug + 11 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_LPTIM1_STOP + LPTIM1 stop in debug + 17 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_LPTIM3_STOP + LPTIM3 stop in debug + 18 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_LPTIM4_STOP + LPTIM4 stop in debug + 19 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_LPTIM5_STOP + LPTIM5 stop in debug + 20 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_LPTIM6_STOP + LPTIM6 stop in debug + 21 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_RTC_STOP + RTC stop in debug + 30 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + + + DBGMCU_AHB1FZR + DBGMCU_AHB1FZR + DBGMCU AHB1 peripheral freeze register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBG_GPDMA1_0_STOP + GPDMA1 channel 0 stop in debug + 0 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_1_STOP + GPDMA1 channel 1 stop in debug + 1 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_2_STOP + GPDMA1 channel 2 stop in debug + 2 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_3_STOP + GPDMA1 channel 3 stop in debug + 3 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_4_STOP + GPDMA1 channel 4 stop in debug + 4 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_5_STOP + GPDMA1 channel 5 stop in debug + 5 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_6_STOP + GPDMA1 channel 6 stop in debug + 6 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA1_7_STOP + GPDMA1 channel 7 stop in debug + 7 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_0_STOP + GPDMA2 channel 0 stop in debug + 16 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_1_STOP + GPDMA2 channel 1 stop in debug + 17 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_2_STOP + GPDMA2 channel 2 stop in debug + 18 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_3_STOP + GPDMA2 channel 3 stop in debug + 19 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_4_STOP + GPDMA2 channel 4 stop in debug + 20 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_5_STOP + GPDMA2 channel 5 stop in debug + 21 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_6_STOP + GPDMA2 channel 6 stop in debug + 22 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + DBG_GPDMA2_7_STOP + GPDMA2 channel 7 stop in debug + 23 + 1 + read-write + + + B_0x0 + normal operation. + 0x0 + + + B_0x1 + stop in debug. + 0x1 + + + + + + + DBGMCU_SR + DBGMCU_SR + DBGMCU status register + 0xFC + 0x20 + read-only + 0x00010003 + 0xFFFF00FF + + + AP_PRESENT + Bit n identifies whether access port AP n is present in device + + 0 + 16 + read-only + + + AP_ENABLED + Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) + + 16 + 16 + read-only + + + + + DBGMCU_DBG_AUTH_HOST + DBGMCU_DBG_AUTH_HOST + DBGMCU debug authentication mailbox host register + 0x100 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + MESSAGE + Debug host to device mailbox message. + 0 + 32 + read-write + + + + + DBGMCU_DBG_AUTH_DEVICE + DBGMCU_DBG_AUTH_DEVICE + DBGMCU debug authentication mailbox device register + 0x104 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + MESSAGE + Device to debug host mailbox message. + 0 + 32 + read-write + + + + + DBGMCU_DBG_AUTH_ACK + DBGMCU_DBG_AUTH_ACK + DBGMCU debug authentication mailbox acknowledge register + 0x108 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + HOST_ACK + Host to device acknowledge. + 0 + 1 + read-only + + + B_0x0 + DBGMCU_DBG_AUTH_HOST register is empty + 0x0 + + + + + DEV_ACK + Device to host acknowledge. + 1 + 1 + read-only + + + B_0x0 + DBGMCU_DBG_AUTH_DEVICE register is empty + 0x0 + + + + + + + DBGMCU_PIDR4 + DBGMCU_PIDR4 + DBGMCU CoreSight peripheral identity register 4 + 0xFD0 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + JEP106CON + JEP106 continuation code + 0 + 4 + read-only + + + B_0x0 + STMicroelectronics JEDEC code + 0x0 + + + + + SIZE + register file size + 4 + 4 + read-only + + + B_0x0 + The register file occupies a single 4-Kbyte region. + 0x0 + + + + + + + DBGMCU_PIDR0 + DBGMCU_PIDR0 + DBGMCU CoreSight peripheral identity register 0 + 0xFE0 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PARTNUM + part number bits [7:0] + 0 + 8 + read-only + + + B_0x00 + DBGMCU part number + 0x00 + + + + + + + DBGMCU_PIDR1 + DBGMCU_PIDR1 + DBGMCU CoreSight peripheral identity register 1 + 0xFE4 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PARTNUM + part number bits [11:8] + 0 + 4 + read-only + + + B_0x0 + DBGMCU part number + 0x0 + + + + + JEP106ID + JEP106 identity code bits [3:0] + 4 + 4 + read-only + + + B_0x0 + STMicroelectronics JEDEC code + 0x0 + + + + + + + DBGMCU_PIDR2 + DBGMCU_PIDR2 + DBGMCU CoreSight peripheral identity register 2 + 0xFE8 + 0x20 + read-only + 0x0000000A + 0xFFFFFFFF + + + JEP106ID + JEP106 identity code bits [6:4] + 0 + 3 + read-only + + + B_0x2 + STMicroelectronics JEDEC code + 0x2 + + + + + JEDEC + JEDEC assigned value + 3 + 1 + read-only + + + B_0x1 + designer identification specified by JEDEC + 0x1 + + + + + REVISION + component revision number + 4 + 4 + read-only + + + B_0x0 + r0p0 + 0x0 + + + + + + + DBGMCU_PIDR3 + DBGMCU_PIDR3 + DBGMCU CoreSight peripheral identity register 3 + 0xFEC + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CMOD + customer modified + 0 + 4 + read-only + + + B_0x0 + no customer modifications + 0x0 + + + + + REVAND + metal fix version + 4 + 4 + read-only + + + B_0x0 + no metal fix + 0x0 + + + + + + + DBGMCU_CIDR0 + DBGMCU_CIDR0 + DBGMCU CoreSight component identity register 0 + 0xFF0 + 0x20 + read-only + 0x0000000D + 0xFFFFFFFF + + + PREAMBLE + component identification bits [7:0] + 0 + 8 + read-only + + + B_0x0D + common identification value + 0x0D + + + + + + + DBGMCU_CIDR1 + DBGMCU_CIDR1 + DBGMCU CoreSight component identity register 1 + 0xFF4 + 0x20 + read-only + 0x000000F0 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [11:8] + 0 + 4 + read-only + + + B_0x0 + common identification value + 0x0 + + + + + CLASS + component identification bits [15:12] - component class + 4 + 4 + read-only + + + B_0xF + Non-CoreSight component + 0xF + + + + + + + DBGMCU_CIDR2 + DBGMCU_CIDR2 + DBGMCU CoreSight component identity register 2 + 0xFF8 + 0x20 + read-only + 0x00000005 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [23:16] + 0 + 8 + read-only + + + B_0x05 + common identification value + 0x05 + + + + + + + DBGMCU_CIDR3 + DBGMCU_CIDR3 + DBGMCU CoreSight component identity register 3 + 0xFFC + 0x20 + read-only + 0x000000B1 + 0xFFFFFFFF + + + PREAMBLE + component identification bits [31:24] + 0 + 8 + read-only + + + B_0xB1 + common identification value + 0xB1 + + + + + + + + + DBGMCU_S + 0x54024000 + + + DCACHE + DCACHE register block + DCACHE + 0x40031400 + + 0x0 + 0x400 + registers + + + DCACHE + Data cache global interrupt + 105 + + + + DCACHE_CR + DCACHE_CR + DCACHE control register + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + 0 + 1 + read-write + + + B_0x0 + cache disabled + 0x0 + + + B_0x1 + cache enabled + 0x1 + + + + + CACHEINV + full cache invalidation + + 1 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + invalidate entire cache (all cache lines valid bit = 0) + 0x1 + + + + + CACHECMD + cache command maintenance operation (cleans and/or invalidates an address range) + + 8 + 3 + read-write + + + B_0x0 + no operation + 0x0 + + + B_0x1 + clean range + 0x1 + + + B_0x2 + invalidate range + 0x2 + + + B_0x3 + clean and invalidate range + 0x3 + + + + + STARTCMD + starts maintenance command (maintenance operation defined in CACHECMD). + 11 + 1 + write-only + + + B_0x0 + command operation (cache maintenance) finished + 0x0 + + + B_0x1 + start maintenance command (cache maintenance) + 0x1 + + + + + RHITMEN + read-hit monitor enable + 16 + 1 + read-write + + + B_0x0 + cache read-hit monitor switched off. + 0x0 + + + B_0x1 + cache read-hit monitor enabled + 0x1 + + + + + RMISSMEN + read-miss monitor enable + 17 + 1 + read-write + + + B_0x0 + cache read-miss monitor switched off. + 0x0 + + + B_0x1 + cache read-miss monitor enabled + 0x1 + + + + + RHITMRST + read-hit monitor reset + 18 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + reset cache read-hit monitor + 0x1 + + + + + RMISSMRST + read-miss monitor reset + 19 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + reset cache read-miss monitor + 0x1 + + + + + WHITMEN + write-hit monitor enable + 20 + 1 + read-write + + + B_0x0 + cache write-hit monitor switched off. + 0x0 + + + B_0x1 + cache write-hit monitor enabled + 0x1 + + + + + WMISSMEN + write-miss monitor enable + 21 + 1 + read-write + + + B_0x0 + cache write-miss monitor switched off. + 0x0 + + + B_0x1 + cache write-miss monitor enabled + 0x1 + + + + + WHITMRST + write-hit monitor reset + 22 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + reset cache write-hit monitor + 0x1 + + + + + WMISSMRST + write-miss monitor reset + 23 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + reset cache write-miss monitor + 0x1 + + + + + HBURST + output burst type for cache master port read accesses + + 31 + 1 + read-write + + + B_0x0 + WRAP + 0x0 + + + B_0x1 + INCR + 0x1 + + + + + + + DCACHE_SR + DCACHE_SR + DCACHE status register + 0x004 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + BUSYF + full invalidate busy flag + 0 + 1 + read-only + + + B_0x0 + cache not busy on a CACHEINV operation + 0x0 + + + B_0x1 + cache executing a full invalidate CACHEINV operation + 0x1 + + + + + BSYENDF + full invalidate busy end flag + + 1 + 1 + read-only + + + B_0x0 + cache busy or in idle + 0x0 + + + B_0x1 + full invalidate CACHEINV operation finished + 0x1 + + + + + ERRF + cache error flag + + 2 + 1 + read-only + + + B_0x0 + no error + 0x0 + + + B_0x1 + an error occurred during the operation (eviction or clean operation write-back error). + 0x1 + + + + + BUSYCMDF + command busy flag + 3 + 1 + read-only + + + B_0x0 + cache not busy on a CACHECMD command + 0x0 + + + B_0x1 + cache busy on a CACHECMD command (clean and/or invalidate an address range) + 0x1 + + + + + CMDENDF + command end flag + + 4 + 1 + read-only + + + B_0x0 + cache busy or in idle + 0x0 + + + B_0x1 + CACHECMD command finished + 0x1 + + + + + + + DCACHE_IER + DCACHE_IER + DCACHE interrupt enable register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BSYENDIE + interrupt enable on busy end + + 1 + 1 + read-write + + + B_0x0 + Interrupt disabled on busy end + 0x0 + + + B_0x1 + Interrupt enabled on busy end + 0x1 + + + + + ERRIE + interrupt enable on cache error + + 2 + 1 + read-write + + + B_0x0 + interrupt disabled on error + 0x0 + + + B_0x1 + interrupt enabled on error + 0x1 + + + + + CMDENDIE + interrupt enable on command end + + 4 + 1 + read-write + + + B_0x0 + interrupt disabled on command end + 0x0 + + + B_0x1 + interrupt enabled on command end + 0x1 + + + + + + + DCACHE_FCR + DCACHE_FCR + DCACHE flag clear register + 0x00C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CBSYENDF + clear full invalidate busy end flag + + 1 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears BSYENDF flag in DCACHE_SR + 0x1 + + + + + CERRF + clear cache error flag + + 2 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears ERRF flag in DCACHE_SR + 0x1 + + + + + CCMDENDF + clear command end flag + + 4 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears CMDENDF flag in DCACHE_SR + 0x1 + + + + + + + DCACHE_RHMONR + DCACHE_RHMONR + DCACHE read-hit monitor register + 0x010 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RHITMON + cache read-hit monitor counter + 0 + 32 + read-only + + + + + DCACHE_RMMONR + DCACHE_RMMONR + DCACHE read-miss monitor register + 0x014 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RMISSMON + cache read-miss monitor counter + 0 + 16 + read-only + + + + + DCACHE_WHMONR + DCACHE_WHMONR + DCACHE write-hit monitor register + 0x020 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + WHITMON + cache write-hit monitor counter + 0 + 32 + read-only + + + + + DCACHE_WMMONR + DCACHE_WMMONR + DCACHE write-miss monitor register + 0x024 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + WMISSMON + cache write-miss monitor counter + 0 + 16 + read-only + + + + + DCACHE_CMDRSADDRR + DCACHE_CMDRSADDRR + DCACHE command range start address register + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CMDSTARTADDR + start address of range to which the cache maintenance command specified in DCACHE_CR. + 4 + 28 + read-write + + + + + DCACHE_CMDREADDRR + DCACHE_CMDREADDRR + DCACHE command range end address register + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CMDENDADDR + end address of range to which the cache maintenance command specified in DCACHE_CR. + 4 + 28 + read-write + + + + + + + DCACHE_S + 0X50031400 + + + DCMI + DCMI address block description + DCMI + 0x4202c000 + + 0x0 + 0x2C + registers + + + DCMI_PSSI + DCMI/PSSI global interrupt + 108 + + + + DCMI_CR + DCMI_CR + DCMI control register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CAPTURE + Capture enable + + 0 + 1 + read-write + + + B_0x0 + Capture disabled + 0x0 + + + B_0x1 + Capture enabled + 0x1 + + + + + CM + Capture mode + 1 + 1 + read-write + + + B_0x0 + Continuous grab mode - The received data are transferred into the destination memory through the DMA. + 0x0 + + + B_0x1 + Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. + 0x1 + + + + + CROP + Crop feature + 2 + 1 + read-write + + + B_0x0 + The full image is captured. + 0x0 + + + B_0x1 + Only the data inside the window specified by the crop register is captured. + 0x1 + + + + + JPEG + JPEG format + 3 + 1 + read-write + + + B_0x0 + Uncompressed video format + 0x0 + + + B_0x1 + This bit is used for JPEG data transfers. + 0x1 + + + + + ESS + Embedded synchronization select + + 4 + 1 + read-write + + + B_0x0 + Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals. + 0x0 + + + B_0x1 + Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow. + 0x1 + + + + + PCKPOL + Pixel clock polarity + + 5 + 1 + read-write + + + B_0x0 + Falling edge active + 0x0 + + + B_0x1 + Rising edge active + 0x1 + + + + + HSPOL + Horizontal synchronization polarity + + 6 + 1 + read-write + + + B_0x0 + DCMI_HSYNC active low + 0x0 + + + B_0x1 + DCMI_HSYNC active high + 0x1 + + + + + VSPOL + Vertical synchronization polarity + + 7 + 1 + read-write + + + B_0x0 + DCMI_VSYNC active low + 0x0 + + + B_0x1 + DCMI_VSYNC active high + 0x1 + + + + + FCRC + Frame capture rate control + + 8 + 2 + read-write + + + B_0x0 + All frames are captured. + 0x0 + + + B_0x1 + Every alternate frame captured (50% bandwidth reduction) + 0x1 + + + B_0x2 + One frame out of four captured (75% bandwidth reduction) + 0x2 + + + + + EDM + Extended data mode + 10 + 2 + read-write + + + B_0x0 + Interface captures 8-bit data on every pixel clock. + 0x0 + + + B_0x1 + Interface captures 10-bit data on every pixel clock. + 0x1 + + + B_0x2 + Interface captures 12-bit data on every pixel clock. + 0x2 + + + B_0x3 + Interface captures 14-bit data on every pixel clock. + 0x3 + + + + + ENABLE + DCMI enable + + 14 + 1 + read-write + + + B_0x0 + DCMI disabled + 0x0 + + + B_0x1 + DCMI enabled + 0x1 + + + + + BSM + Byte Select mode + + 16 + 2 + read-write + + + B_0x0 + Interface captures all received data. + 0x0 + + + B_0x1 + Interface captures every other byte from the received data. + 0x1 + + + B_0x2 + Interface captures one byte out of four. + 0x2 + + + B_0x3 + Interface captures two bytes out of four. + 0x3 + + + + + OEBS + Odd/Even Byte Select (Byte Select Start) + + 18 + 1 + read-write + + + B_0x0 + Interface captures first data (byte or double byte) from the frame/line start, second one being dropped. + 0x0 + + + B_0x1 + Interface captures second data (byte or double byte) from the frame/line start, first one being dropped. + 0x1 + + + + + LSM + Line Select mode + 19 + 1 + read-write + + + B_0x0 + Interface captures all received lines. + 0x0 + + + B_0x1 + Interface captures one line out of two. + 0x1 + + + + + OELS + Odd/Even Line Select (Line Select Start) + + 20 + 1 + read-write + + + B_0x0 + Interface captures first line after the frame start, second one being dropped. + 0x0 + + + B_0x1 + Interface captures second line from the frame start, first one being dropped. + 0x1 + + + + + + + DCMI_SR + DCMI_SR + DCMI status register + 0x04 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + HSYNC + Horizontal synchronization + + 0 + 1 + read-only + + + B_0x0 + active line + 0x0 + + + B_0x1 + synchronization between lines + 0x1 + + + + + VSYNC + Vertical synchronization + + 1 + 1 + read-only + + + B_0x0 + active frame + 0x0 + + + B_0x1 + synchronization between frames + 0x1 + + + + + FNE + FIFO not empty + + 2 + 1 + read-only + + + B_0x1 + FIFO contains valid data. + 0x1 + + + B_0x0 + FIFO empty + 0x0 + + + + + + + DCMI_RIS + DCMI_RIS + DCMI raw interrupt status register + 0x08 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + FRAME_RIS + Capture complete raw interrupt status + + 0 + 1 + read-only + + + B_0x0 + No new capture + 0x0 + + + B_0x1 + A frame has been captured. + 0x1 + + + + + OVR_RIS + Overrun raw interrupt status + + 1 + 1 + read-only + + + B_0x0 + No data buffer overrun occurred + 0x0 + + + B_0x1 + A data buffer overrun occurred and the data FIFO is corrupted. + 0x1 + + + + + ERR_RIS + Synchronization error raw interrupt status + + 2 + 1 + read-only + + + B_0x0 + No synchronization error detected + 0x0 + + + B_0x1 + Embedded synchronization characters are not received in the correct order. + 0x1 + + + + + VSYNC_RIS + DCMI_VSYNC raw interrupt status + + 3 + 1 + read-only + + + LINE_RIS + Line raw interrupt status + + 4 + 1 + read-only + + + + + DCMI_IER + DCMI_IER + DCMI interrupt enable register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FRAME_IE + Capture complete interrupt enable + 0 + 1 + read-write + + + B_0x0 + No interrupt generation + 0x0 + + + B_0x1 + An interrupt is generated at the end of each received frame/crop window (in crop mode). + 0x1 + + + + + OVR_IE + Overrun interrupt enable + 1 + 1 + read-write + + + B_0x0 + No interrupt generation + 0x0 + + + B_0x1 + An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received. + 0x1 + + + + + ERR_IE + Synchronization error interrupt enable + + 2 + 1 + read-write + + + B_0x0 + No interrupt generation + 0x0 + + + B_0x1 + An interrupt is generated if the embedded synchronization codes are not received in the correct order. + 0x1 + + + + + VSYNC_IE + DCMI_VSYNC interrupt enable + + 3 + 1 + read-write + + + B_0x0 + No interrupt generation + 0x0 + + + B_0x1 + An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state. + 0x1 + + + + + LINE_IE + Line interrupt enable + 4 + 1 + read-write + + + B_0x0 + No interrupt generation when the line is received + 0x0 + + + B_0x1 + An Interrupt is generated when a line has been completely received. + 0x1 + + + + + + + DCMI_MIS + DCMI_MIS + DCMI masked interrupt status register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + FRAME_MIS + Capture complete masked interrupt status + + 0 + 1 + read-only + + + B_0x0 + No interrupt is generated after a complete capture. + 0x0 + + + B_0x1 + An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER. + 0x1 + + + + + OVR_MIS + Overrun masked interrupt status + + 1 + 1 + read-only + + + B_0x0 + No interrupt is generated on overrun. + 0x0 + + + B_0x1 + An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER. + 0x1 + + + + + ERR_MIS + Synchronization error masked interrupt status + + 2 + 1 + read-only + + + B_0x0 + No interrupt is generated on a synchronization error. + 0x0 + + + B_0x1 + An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set. + 0x1 + + + + + VSYNC_MIS + VSYNC masked interrupt status + + 3 + 1 + read-only + + + B_0x0 + No interrupt is generated on DCMI_VSYNC transitions. + 0x0 + + + B_0x1 + An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER. + 0x1 + + + + + LINE_MIS + Line masked interrupt status + + 4 + 1 + read-only + + + B_0x0 + No interrupt generation when the line is received + 0x0 + + + B_0x1 + An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER. + 0x1 + + + + + + + DCMI_ICR + DCMI_ICR + DCMI interrupt clear register + 0x14 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + FRAME_ISC + Capture complete interrupt status clear + + 0 + 1 + write-only + + + OVR_ISC + Overrun interrupt status clear + + 1 + 1 + write-only + + + ERR_ISC + Synchronization error interrupt status clear + + 2 + 1 + write-only + + + VSYNC_ISC + Vertical Synchronization interrupt status clear + + 3 + 1 + write-only + + + LINE_ISC + line interrupt status clear + + 4 + 1 + write-only + + + + + DCMI_ESCR + DCMI_ESCR + DCMI embedded synchronization code register + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FSC + Frame start delimiter code + + 0 + 8 + read-write + + + LSC + Line start delimiter code + + 8 + 8 + read-write + + + LEC + Line end delimiter code + + 16 + 8 + read-write + + + FEC + Frame end delimiter code + + 24 + 8 + read-write + + + + + DCMI_ESUR + DCMI_ESUR + DCMI embedded synchronization unmask register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FSU + Frame start delimiter unmask + + 0 + 8 + read-write + + + B_0x0 + The corresponding bit in the FSC byte in DCMI_ESCR is masked while comparing the frame start delimiter with the received data. + 0x0 + + + B_0x1 + The corresponding bit in the FSC byte in DCMI_ESCR is compared while comparing the frame start delimiter with the received data. + 0x1 + + + + + LSU + Line start delimiter unmask + + 8 + 8 + read-write + + + B_0x0 + The corresponding bit in the LSC byte in DCMI_ESCR is masked while comparing the line start delimiter with the received data. + 0x0 + + + B_0x1 + The corresponding bit in the LSC byte in DCMI_ESCR is compared while comparing the line start delimiter with the received data. + 0x1 + + + + + LEU + Line end delimiter unmask + + 16 + 8 + read-write + + + B_0x0 + The corresponding bit in the LEC byte in DCMI_ESCR is masked while comparing the line end delimiter with the received data. + 0x0 + + + B_0x1 + The corresponding bit in the LEC byte in DCMI_ESCR is compared while comparing the line end delimiter with the received data. + 0x1 + + + + + FEU + Frame end delimiter unmask + + 24 + 8 + read-write + + + B_0x0 + The corresponding bit in the FEC byte in DCMI_ESCR is masked while comparing the frame end delimiter with the received data. + 0x0 + + + B_0x1 + The corresponding bit in the FEC byte in DCMI_ESCR is compared while comparing the frame end delimiter with the received data. + 0x1 + + + + + + + DCMI_CWSTRT + DCMI_CWSTRT + DCMI crop window start + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HOFFCNT + Horizontal offset count + + 0 + 14 + read-write + + + VST + Vertical start line count + + 16 + 13 + read-write + + + B_0x0000 + line 1 + 0x0000 + + + B_0x0001 + line 2 + 0x0001 + + + B_0x0002 + line 3 + 0x0002 + + + + + + + DCMI_CWSIZE + DCMI_CWSIZE + DCMI crop window size + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CAPCNT + Capture count + + 0 + 14 + read-write + + + B_0x0000 + 1 pixel + 0x0000 + + + B_0x0001 + 2 pixels + 0x0001 + + + B_0x0002 + 3 pixels + 0x0002 + + + + + VLINE + Vertical line count + + 16 + 14 + read-write + + + B_0x0000 + 1 line + 0x0000 + + + B_0x0001 + 2 lines + 0x0001 + + + B_0x0002 + 3 lines + 0x0002 + + + + + + + DCMI_DR + DCMI_DR + DCMI data register + 0x28 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + BYTE0 + Data byte 0 + 0 + 8 + read-only + + + BYTE1 + Data byte 1 + 8 + 8 + read-only + + + BYTE2 + Data byte 2 + 16 + 8 + read-only + + + BYTE3 + Data byte 3 + 24 + 8 + read-only + + + + + + + DCMI_S + 0X5202C000 + + + DLYBOS1 + DLYB address block description + DLYB + 0x4600F000 + + 0x0 + 0x8 + registers + + + + DLYB_CR + DLYB_CR + DLYB control register + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DEN + Delay block enable bit + 0 + 1 + read-write + + + B_0x0 + DLYB disabled. + 0x0 + + + B_0x1 + DLYB enabled. + 0x1 + + + + + SEN + Sampler length enable bit + 1 + 1 + read-write + + + B_0x0 + Sampler length and register access to UNIT[6:0] and SEL[3:0] disabled, output clock enabled. + 0x0 + + + B_0x1 + Sampler length and register access to UNIT[6:0] and SEL[3:0] enabled, output clock disabled. + 0x1 + + + + + + + DLYB_CFGR + DLYB_CFGR + DLYB configuration register + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEL + Phase for the output clock. + 0 + 4 + read-write + + + UNIT + Delay of a unit delay cell. + 8 + 7 + read-write + + + LNG + Delay line length value + + 16 + 12 + read-only + + + LNGF + Length valid flag + + 31 + 1 + read-only + + + B_0x0 + Length value in LNG is not valid. + 0x0 + + + B_0x1 + Length value in LNG is valid. + 0x1 + + + + + + + + + DLYBOS1_S + 0x5600F000 + + + DLYBSD1 + 0x46008400 + + + DLYBSD1_S + 0x56008400 + + + DTS + DTS address block description + DTS + 0x40008c00 + + 0x0 + 0x30 + registers + + + DTS_OR_DTS_WKUP + DTS interrupt OR DTS AIT through EXTI line + 113 + + + + DTS_CFGR1 + DTS_CFGR1 + Temperature sensor configuration register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TS1_EN + Temperature sensor 1 enable bit + + 0 + 1 + read-write + + + B_0x0 + Temperature sensor 1 disabled + 0x0 + + + B_0x1 + Temperature sensor 1 enabled + 0x1 + + + + + TS1_START + Start frequency measurement on temperature sensor 1 + + 4 + 1 + read-write + + + B_0x0 + No software trigger. + 0x0 + + + B_0x1 + Software trigger for a frequency measurement. + 0x1 + + + + + TS1_INTRIG_SEL + Input trigger selection bit for temperature sensor 1 + + 8 + 4 + read-write + + + TS1_SMP_TIME + Sampling time for temperature sensor 1 + + 16 + 4 + read-write + + + REFCLK_SEL + Reference clock selection bit + + 20 + 1 + read-write + + + B_0x0 + High speed reference clock (PCLK) + 0x0 + + + B_0x1 + Low speed reference clock (LSE) + 0x1 + + + + + Q_MEAS_OPT + Quick measurement option bit + + 21 + 1 + read-write + + + B_0x0 + Measurement with calibration + 0x0 + + + B_0x1 + Measurement without calibration + 0x1 + + + + + HSREF_CLK_DIV + High speed clock division ratio + + 24 + 7 + read-write + + + B_0x0 + No divider + 0x0 + + + B_0x1 + No divider + 0x1 + + + B_0x2 + 1/2 division ratio + 0x2 + + + B_0x7F + 1/127 division ratio + 0x7F + + + + + + + DTS_T0VALR1 + DTS_T0VALR1 + Temperature sensor T0 value register 1 + 0x08 + 0x20 + read-only + 0x00000000 + 0xFFF00000 + + + TS1_FMT0 + Engineering value of the frequency measured at T0 for + + 0 + 16 + read-only + + + TS1_T0 + Engineering value of the T0 temperature for temperature sensor 1. + 16 + 2 + read-only + + + B_0x0 + 30 C + 0x0 + + + B_0x1 + 130 C + 0x1 + + + + + + + DTS_RAMPVALR + DTS_RAMPVALR + Temperature sensor ramp value register + 0x10 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + TS1_RAMP_COEFF + Engineering value of the ramp coefficient for the temperature sensor 1. + 0 + 16 + read-only + + + + + DTS_ITR1 + DTS_ITR1 + Temperature sensor interrupt threshold register 1 + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TS1_LITTHD + Low interrupt threshold for temperature sensor 1 + + 0 + 16 + read-write + + + TS1_HITTHD + High interrupt threshold for temperature sensor 1 + + 16 + 16 + read-write + + + + + DTS_DR + DTS_DR + Temperature sensor data register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TS1_MFREQ + Value of the counter output value for temperature sensor 1 + 0 + 16 + read-write + + + + + DTS_SR + DTS_SR + Temperature sensor status register + 0x20 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TS1_ITEF + Interrupt flag for end of measurement on temperature sensor 1, synchronized on PCLK. + 0 + 1 + read-only + + + B_0x0 + No end of measurement detected on temperature sensor 1 + 0x0 + + + B_0x1 + End of measure detected on temperature sensor 1 + 0x1 + + + + + TS1_ITLF + Interrupt flag for low threshold on temperature sensor 1, synchronized on PCLK. + 1 + 1 + read-only + + + B_0x0 + Low threshold not reached on temperature sensor 1 + 0x0 + + + B_0x1 + Low threshold reached on temperature sensor 1 + 0x1 + + + + + TS1_ITHF + Interrupt flag for high threshold on temperature sensor 1, synchronized on PCLK + + 2 + 1 + read-only + + + B_0x0 + High threshold not reached on temperature sensor 1 + 0x0 + + + B_0x1 + High threshold reached on temperature sensor 1 + 0x1 + + + + + TS1_AITEF + Asynchronous interrupt flag for end of measure on temperature sensor 1 + + 4 + 1 + read-only + + + B_0x0 + End of measure not detected on temperature sensor 1 + 0x0 + + + B_0x1 + End of measure detected on temperature sensor 1 + 0x1 + + + + + TS1_AITLF + Asynchronous interrupt flag for low threshold on temperature sensor 1 + + 5 + 1 + read-only + + + B_0x0 + Low threshold not reached on temperature sensor 1 + 0x0 + + + B_0x1 + Low threshold reached on temperature sensor 1 + 0x1 + + + + + TS1_AITHF + Asynchronous interrupt flag for high threshold on temperature sensor 1 + + 6 + 1 + read-only + + + B_0x0 + High threshold not reached on temperature sensor 1 + 0x0 + + + B_0x1 + High threshold reached on temperature sensor 1 + 0x1 + + + + + TS1_RDY + Temperature sensor 1 ready flag + + 15 + 1 + read-only + + + B_0x0 + Temperature sensor 1 busy + 0x0 + + + B_0x1 + Temperature sensor 1 ready + 0x1 + + + + + + + DTS_ITENR + DTS_ITENR + Temperature sensor interrupt enable register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TS1_ITEEN + Interrupt enable flag for end of measurement on temperature sensor 1, synchronized on PCLK. + 0 + 1 + read-write + + + B_0x0 + Synchronous interrupt for end of measurement disabled on temperature sensor 1 + 0x0 + + + B_0x1 + Synchronous interrupt for end of measurement enabled on temperature sensor 1 + 0x1 + + + + + TS1_ITLEN + Interrupt enable flag for low threshold on temperature sensor 1, synchronized on PCLK. + 1 + 1 + read-write + + + B_0x0 + Synchronous interrupt for low threshold disabled on temperature sensor 1 + 0x0 + + + B_0x1 + Synchronous interrupt for low threshold enabled on temperature sensor 1 + 0x1 + + + + + TS1_ITHEN + Interrupt enable flag for high threshold on temperature sensor 1, synchronized on PCLK. + 2 + 1 + read-write + + + B_0x0 + Synchronous interrupt for high threshold disabled on temperature sensor 1 + 0x0 + + + B_0x1 + Synchronous interrupt for high threshold enabled on temperature sensor 1 + 0x1 + + + + + TS1_AITEEN + Asynchronous interrupt enable flag for end of measurement on temperature sensor 1 + + 4 + 1 + read-write + + + B_0x0 + Asynchronous interrupt for end of measurement disabled on temperature sensor 1 + 0x0 + + + B_0x1 + Asynchronous interrupt for end of measurement enabled on temperature sensor 1 + 0x1 + + + + + TS1_AITLEN + Asynchronous interrupt enable flag for low threshold on temperature sensor 1. + 5 + 1 + read-write + + + B_0x0 + Asynchronous interrupt on low threshold disabled for temperature sensor 1 + 0x0 + + + B_0x1 + Asynchronous interrupt on low threshold enabled for temperature sensor 1 + 0x1 + + + + + TS1_AITHEN + Asynchronous interrupt enable flag on high threshold for temperature sensor 1. + 6 + 1 + read-write + + + B_0x0 + Asynchronous interrupt on high threshold disabled for temperature sensor 1 + 0x0 + + + B_0x1 + Asynchronous interrupt on high threshold enabled for temperature sensor 1 + 0x1 + + + + + + + DTS_ICIFR + DTS_ICIFR + Temperature sensor clear interrupt flag register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TS1_CITEF + Interrupt clear flag for end of measurement on temperature sensor 1 + + 0 + 1 + read-write + + + TS1_CITLF + Interrupt clear flag for low threshold on temperature sensor 1 + + 1 + 1 + read-write + + + TS1_CITHF + Interrupt clear flag for high threshold on temperature sensor 1 + + 2 + 1 + read-write + + + TS1_CAITEF + Write once bit. + 4 + 1 + read-write + + + TS1_CAITLF + Asynchronous interrupt clear flag for low threshold on temperature sensor 1 + + 5 + 1 + read-write + + + TS1_CAITHF + Asynchronous interrupt clear flag for high threshold on temperature sensor 1 + + 6 + 1 + read-write + + + + + DTS_OR + DTS_OR + Temperature sensor option register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TS_OP0 + general purpose option bits + 0 + 1 + read-write + + + TS_OP1 + general purpose option bits + 1 + 1 + read-write + + + TS_OP2 + general purpose option bits + 2 + 1 + read-write + + + TS_OP3 + general purpose option bits + 3 + 1 + read-write + + + TS_OP4 + general purpose option bits + 4 + 1 + read-write + + + TS_OP5 + general purpose option bits + 5 + 1 + read-write + + + TS_OP6 + general purpose option bits + 6 + 1 + read-write + + + TS_OP7 + general purpose option bits + 7 + 1 + read-write + + + TS_OP8 + general purpose option bits + 8 + 1 + read-write + + + TS_OP9 + general purpose option bits + 9 + 1 + read-write + + + TS_OP10 + general purpose option bits + 10 + 1 + read-write + + + TS_OP11 + general purpose option bits + 11 + 1 + read-write + + + TS_OP12 + general purpose option bits + 12 + 1 + read-write + + + TS_OP13 + general purpose option bits + 13 + 1 + read-write + + + TS_OP14 + general purpose option bits + 14 + 1 + read-write + + + TS_OP15 + general purpose option bits + 15 + 1 + read-write + + + TS_OP16 + general purpose option bits + 16 + 1 + read-write + + + TS_OP17 + general purpose option bits + 17 + 1 + read-write + + + TS_OP18 + general purpose option bits + 18 + 1 + read-write + + + TS_OP19 + general purpose option bits + 19 + 1 + read-write + + + TS_OP20 + general purpose option bits + 20 + 1 + read-write + + + TS_OP21 + general purpose option bits + 21 + 1 + read-write + + + TS_OP22 + general purpose option bits + 22 + 1 + read-write + + + TS_OP23 + general purpose option bits + 23 + 1 + read-write + + + TS_OP24 + general purpose option bits + 24 + 1 + read-write + + + TS_OP25 + general purpose option bits + 25 + 1 + read-write + + + TS_OP26 + general purpose option bits + 26 + 1 + read-write + + + TS_OP27 + general purpose option bits + 27 + 1 + read-write + + + TS_OP28 + general purpose option bits + 28 + 1 + read-write + + + TS_OP29 + general purpose option bits + 29 + 1 + read-write + + + TS_OP30 + general purpose option bits + 30 + 1 + read-write + + + TS_OP31 + general purpose option bits + 31 + 1 + read-write + + + + + + + DTS_S + 0X50008C00 + + + EXTI + EXTI address block description + EXTI + 0x44022000 + + 0x0 + 0x98 + registers + + + EXTI15 + EXTI Line15 interrupt + 26 + + + EXTI14 + EXTI Line14 interrupt + 25 + + + EXTI13 + EXTI Line13 interrupt + 24 + + + EXTI12 + EXTI Line12 interrupt + 23 + + + EXTI11 + EXTI Line11 interrupt + 22 + + + EXTI10 + EXTI Line10 interrupt + 21 + + + EXTI9 + EXTI Line9 interrupt + 20 + + + EXTI8 + EXTI Line8 interrupt + 19 + + + EXTI7 + EXTI Line7 interrupt + 18 + + + EXTI6 + EXTI Line6 interrupt + 17 + + + EXTI5 + EXTI Line5 interrupt + 16 + + + EXTI4 + EXTI Line4 interrupt + 15 + + + EXTI3 + EXTI Line3 interrupt + 14 + + + EXTI2 + EXTI Line2 interrupt + 13 + + + EXTI1 + EXTI Line1 interrupt + 12 + + + EXTI0 + EXTI Line0 interrupt + 11 + + + FPU + Floating point interrupt + 103 + + + CEC + HDMI-CEC global interrupt + 119 + + + + EXTI_RTSR1 + EXTI_RTSR1 + EXTI rising trigger selection register + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RT0 + Rising trigger event configuration bit of configurable event input x + + 0 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT1 + Rising trigger event configuration bit of configurable event input x + + 1 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT2 + Rising trigger event configuration bit of configurable event input x + + 2 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT3 + Rising trigger event configuration bit of configurable event input x + + 3 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT4 + Rising trigger event configuration bit of configurable event input x + + 4 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT5 + Rising trigger event configuration bit of configurable event input x + + 5 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT6 + Rising trigger event configuration bit of configurable event input x + + 6 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT7 + Rising trigger event configuration bit of configurable event input x + + 7 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT8 + Rising trigger event configuration bit of configurable event input x + + 8 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT9 + Rising trigger event configuration bit of configurable event input x + + 9 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT10 + Rising trigger event configuration bit of configurable event input x + + 10 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT11 + Rising trigger event configuration bit of configurable event input x + + 11 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT12 + Rising trigger event configuration bit of configurable event input x + + 12 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT13 + Rising trigger event configuration bit of configurable event input x + + 13 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT14 + Rising trigger event configuration bit of configurable event input x + + 14 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT15 + Rising trigger event configuration bit of configurable event input x + + 15 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT16 + Rising trigger event configuration bit of configurable event input x + + 16 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + + + EXTI_FTSR1 + EXTI_FTSR1 + EXTI falling trigger selection register + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FT0 + Falling trigger event configuration bit of configurable event input x + + 0 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT1 + Falling trigger event configuration bit of configurable event input x + + 1 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT2 + Falling trigger event configuration bit of configurable event input x + + 2 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT3 + Falling trigger event configuration bit of configurable event input x + + 3 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT4 + Falling trigger event configuration bit of configurable event input x + + 4 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT5 + Falling trigger event configuration bit of configurable event input x + + 5 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT6 + Falling trigger event configuration bit of configurable event input x + + 6 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT7 + Falling trigger event configuration bit of configurable event input x + + 7 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT8 + Falling trigger event configuration bit of configurable event input x + + 8 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT9 + Falling trigger event configuration bit of configurable event input x + + 9 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT10 + Falling trigger event configuration bit of configurable event input x + + 10 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT11 + Falling trigger event configuration bit of configurable event input x + + 11 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT12 + Falling trigger event configuration bit of configurable event input x + + 12 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT13 + Falling trigger event configuration bit of configurable event input x + + 13 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT14 + Falling trigger event configuration bit of configurable event input x + + 14 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT15 + Falling trigger event configuration bit of configurable event input x + + 15 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT16 + Falling trigger event configuration bit of configurable event input x + + 16 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + + + EXTI_SWIER1 + EXTI_SWIER1 + EXTI software interrupt event register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SWI0 + Software interrupt on event x + + 0 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI1 + Software interrupt on event x + + 1 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI2 + Software interrupt on event x + + 2 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI3 + Software interrupt on event x + + 3 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI4 + Software interrupt on event x + + 4 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI5 + Software interrupt on event x + + 5 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI6 + Software interrupt on event x + + 6 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI7 + Software interrupt on event x + + 7 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI8 + Software interrupt on event x + + 8 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI9 + Software interrupt on event x + + 9 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI10 + Software interrupt on event x + + 10 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI11 + Software interrupt on event x + + 11 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI12 + Software interrupt on event x + + 12 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI13 + Software interrupt on event x + + 13 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI14 + Software interrupt on event x + + 14 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI15 + Software interrupt on event x + + 15 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI16 + Software interrupt on event x + + 16 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + + + EXTI_RPR1 + EXTI_RPR1 + EXTI rising edge pending register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RPIF0 + configurable event inputs x rising edge pending bit + + 0 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF1 + configurable event inputs x rising edge pending bit + + 1 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF2 + configurable event inputs x rising edge pending bit + + 2 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF3 + configurable event inputs x rising edge pending bit + + 3 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF4 + configurable event inputs x rising edge pending bit + + 4 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF5 + configurable event inputs x rising edge pending bit + + 5 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF6 + configurable event inputs x rising edge pending bit + + 6 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF7 + configurable event inputs x rising edge pending bit + + 7 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF8 + configurable event inputs x rising edge pending bit + + 8 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF9 + configurable event inputs x rising edge pending bit + + 9 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF10 + configurable event inputs x rising edge pending bit + + 10 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF11 + configurable event inputs x rising edge pending bit + + 11 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF12 + configurable event inputs x rising edge pending bit + + 12 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF13 + configurable event inputs x rising edge pending bit + + 13 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF14 + configurable event inputs x rising edge pending bit + + 14 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF15 + configurable event inputs x rising edge pending bit + + 15 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF16 + configurable event inputs x rising edge pending bit + + 16 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + + + EXTI_FPR1 + EXTI_FPR1 + EXTI falling edge pending register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FPIF0 + configurable event inputs x falling edge pending bit + + 0 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF1 + configurable event inputs x falling edge pending bit + + 1 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF2 + configurable event inputs x falling edge pending bit + + 2 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF3 + configurable event inputs x falling edge pending bit + + 3 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF4 + configurable event inputs x falling edge pending bit + + 4 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF5 + configurable event inputs x falling edge pending bit + + 5 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF6 + configurable event inputs x falling edge pending bit + + 6 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF7 + configurable event inputs x falling edge pending bit + + 7 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF8 + configurable event inputs x falling edge pending bit + + 8 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF9 + configurable event inputs x falling edge pending bit + + 9 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF10 + configurable event inputs x falling edge pending bit + + 10 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF11 + configurable event inputs x falling edge pending bit + + 11 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF12 + configurable event inputs x falling edge pending bit + + 12 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF13 + configurable event inputs x falling edge pending bit + + 13 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF14 + configurable event inputs x falling edge pending bit + + 14 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF15 + configurable event inputs x falling edge pending bit + + 15 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF16 + configurable event inputs x falling edge pending bit + + 16 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + + + EXTI_SECCFGR1 + EXTI_SECCFGR1 + EXTI security configuration register + 0x014 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEC0 + Security enable on event input x + + 0 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC1 + Security enable on event input x + + 1 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC2 + Security enable on event input x + + 2 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC3 + Security enable on event input x + + 3 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC4 + Security enable on event input x + + 4 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC5 + Security enable on event input x + + 5 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC6 + Security enable on event input x + + 6 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC7 + Security enable on event input x + + 7 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC8 + Security enable on event input x + + 8 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC9 + Security enable on event input x + + 9 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC10 + Security enable on event input x + + 10 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC11 + Security enable on event input x + + 11 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC12 + Security enable on event input x + + 12 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC13 + Security enable on event input x + + 13 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC14 + Security enable on event input x + + 14 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC15 + Security enable on event input x + + 15 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC16 + Security enable on event input x + + 16 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC17 + Security enable on event input x + + 17 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC18 + Security enable on event input x + + 18 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC19 + Security enable on event input x + + 19 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC20 + Security enable on event input x + + 20 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC21 + Security enable on event input x + + 21 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC22 + Security enable on event input x + + 22 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC23 + Security enable on event input x + + 23 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC24 + Security enable on event input x + + 24 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC25 + Security enable on event input x + + 25 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC26 + Security enable on event input x + + 26 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC27 + Security enable on event input x + + 27 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC28 + Security enable on event input x + + 28 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC29 + Security enable on event input x + + 29 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC30 + Security enable on event input x + + 30 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC31 + Security enable on event input x + + 31 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + + + EXTI_PRIVCFGR1 + EXTI_PRIVCFGR1 + EXTI privilege configuration register + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIV0 + Security enable on event input x + + 0 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV1 + Security enable on event input x + + 1 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV2 + Security enable on event input x + + 2 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV3 + Security enable on event input x + + 3 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV4 + Security enable on event input x + + 4 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV5 + Security enable on event input x + + 5 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV6 + Security enable on event input x + + 6 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV7 + Security enable on event input x + + 7 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV8 + Security enable on event input x + + 8 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV9 + Security enable on event input x + + 9 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV10 + Security enable on event input x + + 10 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV11 + Security enable on event input x + + 11 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV12 + Security enable on event input x + + 12 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV13 + Security enable on event input x + + 13 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV14 + Security enable on event input x + + 14 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV15 + Security enable on event input x + + 15 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV16 + Security enable on event input x + + 16 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV17 + Security enable on event input x + + 17 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV18 + Security enable on event input x + + 18 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV19 + Security enable on event input x + + 19 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV20 + Security enable on event input x + + 20 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV21 + Security enable on event input x + + 21 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV22 + Security enable on event input x + + 22 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV23 + Security enable on event input x + + 23 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV24 + Security enable on event input x + + 24 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV25 + Security enable on event input x + + 25 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV26 + Security enable on event input x + + 26 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV27 + Security enable on event input x + + 27 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV28 + Security enable on event input x + + 28 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV29 + Security enable on event input x + + 29 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV30 + Security enable on event input x + + 30 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV31 + Security enable on event input x + + 31 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + + + EXTI_RTSR2 + EXTI_RTSR2 + EXTI rising trigger selection register 2 + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RT46 + Rising trigger event configuration bit of configurable event input xless thansup>(1)less than/sup> + + 14 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT50 + Rising trigger event configuration bit of configurable event input xless thansup>(1)less than/sup> + + 18 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + RT53 + Rising trigger event configuration bit of configurable event input x + + 21 + 1 + read-write + + + B_0x0 + Rising trigger disabled (for event and interrupt) for input line + 0x0 + + + B_0x1 + Rising trigger enabled (for event and interrupt) for input line + 0x1 + + + + + + + EXTI_FTSR2 + EXTI_FTSR2 + EXTI falling trigger selection register 2 + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FT46 + Falling trigger event configuration bit of configurable event input x less thansup>(1)less than/sup> + + 14 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT50 + Falling trigger event configuration bit of configurable event input x less thansup>(1)less than/sup> + + 18 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + FT53 + Falling trigger event configuration bit of configurable event input x + + 21 + 1 + read-write + + + B_0x0 + Falling trigger disabled (for event and Interrupt) for input line + 0x0 + + + B_0x1 + Falling trigger enabled (for event and Interrupt) for input line. + 0x1 + + + + + + + EXTI_SWIER2 + EXTI_SWIER2 + EXTI software interrupt event register 2 + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SWI46 + Software interrupt on event x + + 14 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI50 + Software interrupt on event x + + 18 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + SWI53 + Software interrupt on event x + + 21 + 1 + read-write + + + B_0x0 + Writing 0 has no effect. + 0x0 + + + B_0x1 + Writing 1 triggers a rising edge event on event x. + 0x1 + + + + + + + EXTI_RPR2 + EXTI_RPR2 + EXTI rising edge pending register 2 + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RPIF46 + configurable event inputs x rising edge pending bit + + 14 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF50 + configurable event inputs x rising edge pending bit + + 18 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + RPIF53 + configurable event inputs x rising edge pending bit + + 21 + 1 + read-write + + + B_0x0 + No rising edge trigger request occurred + 0x0 + + + B_0x1 + Rising edge trigger request occurred + 0x1 + + + + + + + EXTI_FPR2 + EXTI_FPR2 + EXTI falling edge pending register 2 + 0x030 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FPIF46 + configurable event inputs x falling edge pending bit + + 14 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF50 + configurable event inputs x falling edge pending bit + + 18 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + FPIF53 + configurable event inputs x falling edge pending bit + + 21 + 1 + read-write + + + B_0x0 + No falling edge trigger request occurred + 0x0 + + + B_0x1 + Falling edge trigger request occurred + 0x1 + + + + + + + EXTI_SECCFGR2 + EXTI_SECCFGR2 + EXTI security configuration register 2 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEC32 + Security enable on event input x + + 0 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC33 + Security enable on event input x + + 1 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC34 + Security enable on event input x + + 2 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC35 + Security enable on event input x + + 3 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC36 + Security enable on event input x + + 4 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC37 + Security enable on event input x + + 5 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC38 + Security enable on event input x + + 6 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC39 + Security enable on event input x + + 7 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC40 + Security enable on event input x + + 8 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC41 + Security enable on event input x + + 9 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC42 + Security enable on event input x + + 10 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC43 + Security enable on event input x + + 11 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC44 + Security enable on event input x + + 12 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC45 + Security enable on event input x + + 13 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC46 + Security enable on event input x + + 14 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC47 + Security enable on event input x + + 15 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC48 + Security enable on event input x + + 16 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC49 + Security enable on event input x + + 17 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC50 + Security enable on event input x + + 18 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC51 + Security enable on event input x + + 19 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC52 + Security enable on event input x + + 20 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC53 + Security enable on event input x + + 21 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC54 + Security enable on event input x + + 22 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC55 + Security enable on event input x + + 23 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC56 + Security enable on event input x + + 24 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + SEC57 + Security enable on event input x + + 25 + 1 + read-write + + + B_0x0 + Event security disabled (non-secure) + 0x0 + + + B_0x1 + Event security enabled (secure) + 0x1 + + + + + + + EXTI_PRIVCFGR2 + EXTI_PRIVCFGR2 + EXTI privilege configuration register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIV32 + Security enable on event input x + + 0 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV33 + Security enable on event input x + + 1 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV34 + Security enable on event input x + + 2 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV35 + Security enable on event input x + + 3 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV36 + Security enable on event input x + + 4 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV37 + Security enable on event input x + + 5 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV38 + Security enable on event input x + + 6 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV39 + Security enable on event input x + + 7 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV40 + Security enable on event input x + + 8 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV41 + Security enable on event input x + + 9 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV42 + Security enable on event input x + + 10 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV43 + Security enable on event input x + + 11 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV44 + Security enable on event input x + + 12 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV45 + Security enable on event input x + + 13 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV46 + Security enable on event input x + + 14 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV47 + Security enable on event input x + + 15 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV48 + Security enable on event input x + + 16 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV49 + Security enable on event input x + + 17 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV50 + Security enable on event input x + + 18 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV51 + Security enable on event input x + + 19 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV52 + Security enable on event input x + + 20 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV53 + Security enable on event input x + + 21 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV54 + Security enable on event input x + + 22 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV55 + Security enable on event input x + + 23 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV56 + Security enable on event input x + + 24 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + PRIV57 + Security enable on event input x + + 25 + 1 + read-write + + + B_0x0 + Event privilege disabled (unprivileged) + 0x0 + + + B_0x1 + Event privilege enabled (privileged) + 0x1 + + + + + + + EXTI_EXTICR1 + EXTI_EXTICR1 + EXTI external interrupt selection register + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EXTI0 + EXTI0 GPIO port selection + + 0 + 8 + read-write + + + B_0x00 + PA0 pin + 0x00 + + + B_0x01 + PB0 pin + 0x01 + + + B_0x02 + PC0 pin + 0x02 + + + B_0x03 + PD0 pin + 0x03 + + + B_0x04 + PE0 pin + 0x04 + + + B_0x05 + PF0 pin + 0x05 + + + B_0x06 + PG0 pin + 0x06 + + + B_0x07 + PH0 pin + 0x07 + + + B_0x08 + PI0 pin + 0x08 + + + + + EXTI1 + EXTI1 GPIO port selection + + 8 + 8 + read-write + + + B_0x00 + PA1 pin + 0x00 + + + B_0x01 + PB1 pin + 0x01 + + + B_0x02 + PC1 pin + 0x02 + + + B_0x03 + PD1 pin + 0x03 + + + B_0x04 + PE1 pin + 0x04 + + + B_0x05 + PF1 pin + 0x05 + + + B_0x06 + PG1 pin + 0x06 + + + B_0x07 + PH1 pin + 0x07 + + + B_0x08 + PI1 pin + 0x08 + + + + + EXTI2 + EXTI2 GPIO port selection + + 16 + 8 + read-write + + + B_0x00 + PA2 pin + 0x00 + + + B_0x01 + PB2 pin + 0x01 + + + B_0x02 + PC2 pin + 0x02 + + + B_0x03 + PD2 pin + 0x03 + + + B_0x04 + PE2 pin + 0x04 + + + B_0x05 + PF2 pin + 0x05 + + + B_0x06 + PG2 pin + 0x06 + + + B_0x07 + PH2 pin + 0x07 + + + B_0x08 + PI2 pin + 0x08 + + + + + EXTI3 + EXTI3 GPIO port selection + + 24 + 8 + read-write + + + B_0x00 + PA3 pin + 0x00 + + + B_0x01 + PB3 pin + 0x01 + + + B_0x02 + PC3 pin + 0x02 + + + B_0x03 + PD3 pin + 0x03 + + + B_0x04 + PE3 pin + 0x04 + + + B_0x05 + PF3 pin + 0x05 + + + B_0x06 + PG3 pin + 0x06 + + + B_0x07 + PH3 pin + 0x07 + + + B_0x08 + PI3 pin + 0x08 + + + + + + + EXTI_EXTICR4 + EXTI_EXTICR4 + EXTI external interrupt selection register + EXTI_EXTICR1 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EXTI12 + EXTI12 GPIO port selection + + 0 + 8 + read-write + + + B_0x00 + PA12 pin + 0x00 + + + B_0x01 + PB12 pin + 0x01 + + + B_0x02 + PC12 pin + 0x02 + + + B_0x03 + PD12 pin + 0x03 + + + B_0x04 + PE12 pin + 0x04 + + + B_0x05 + PF12 pin + 0x05 + + + B_0x06 + PG12 pin + 0x06 + + + B_0x07 + PH12 pin + 0x07 + + + + + EXTI13 + EXTI13 GPIO port selection + + 8 + 8 + read-write + + + B_0x00 + PA13 pin + 0x00 + + + B_0x01 + PB13 pin + 0x01 + + + B_0x02 + PC13 pin + 0x02 + + + B_0x03 + PD13 pin + 0x03 + + + B_0x04 + PE13 pin + 0x04 + + + B_0x05 + PF13 pin + 0x05 + + + B_0x06 + PG13 pin + 0x06 + + + B_0x07 + PH13 pin + 0x07 + + + + + EXTI14 + EXTI14 GPIO port selection + + 16 + 8 + read-write + + + B_0x00 + PA14 pin + 0x00 + + + B_0x01 + PB14 pin + 0x01 + + + B_0x02 + PC14 pin + 0x02 + + + B_0x03 + PD14 pin + 0x03 + + + B_0x04 + PE14 pin + 0x04 + + + B_0x05 + PF14 pin + 0x05 + + + B_0x06 + PG14 pin + 0x06 + + + B_0x07 + PH14 pin + 0x07 + + + + + EXTI15 + EXTI15 GPIO port selection + + 24 + 8 + read-write + + + B_0x00 + PA15 pin + 0x00 + + + B_0x01 + PB15 pin + 0x01 + + + B_0x02 + PC15 pin + 0x02 + + + B_0x03 + PD15 pin + 0x03 + + + B_0x04 + PE15 pin + 0x04 + + + B_0x05 + PF15 pin + 0x05 + + + B_0x06 + PG15 pin + 0x06 + + + B_0x07 + PH15 pin + 0x07 + + + + + + + EXTI_EXTICR2 + EXTI_EXTICR2 + EXTI external interrupt selection register + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EXTI4 + EXTI4 GPIO port selection + + 0 + 8 + read-write + + + B_0x00 + PA4 pin + 0x00 + + + B_0x01 + PB4 pin + 0x01 + + + B_0x02 + PC4 pin + 0x02 + + + B_0x03 + PD4 pin + 0x03 + + + B_0x04 + PE4 pin + 0x04 + + + B_0x05 + PF4 pin + 0x05 + + + B_0x06 + PG4 pin + 0x06 + + + B_0x07 + PH4 pin + 0x07 + + + B_0x08 + PI4 pin + 0x08 + + + + + EXTI5 + EXTI5 GPIO port selection + + 8 + 8 + read-write + + + B_0x00 + PA5 pin + 0x00 + + + B_0x01 + PB5 pin + 0x01 + + + B_0x02 + PC5 pin + 0x02 + + + B_0x03 + PD5 pin + 0x03 + + + B_0x04 + PE5 pin + 0x04 + + + B_0x05 + PF5 pin + 0x05 + + + B_0x06 + PG5 pin + 0x06 + + + B_0x07 + PH5 pin + 0x07 + + + B_0x08 + PI5 pin + 0x08 + + + + + EXTI6 + EXTI6 GPIO port selection + + 16 + 8 + read-write + + + B_0x00 + PA6 pin + 0x00 + + + B_0x01 + PB6 pin + 0x01 + + + B_0x02 + PC6 pin + 0x02 + + + B_0x03 + PD6 pin + 0x03 + + + B_0x04 + PE6 pin + 0x04 + + + B_0x05 + PF6 pin + 0x05 + + + B_0x06 + PG6 pin + 0x06 + + + B_0x07 + PH6 pin + 0x07 + + + B_0x08 + PI6 pin + 0x08 + + + + + EXTI7 + EXTI7 GPIO port selection + + 24 + 8 + read-write + + + B_0x00 + PA7 pin + 0x00 + + + B_0x01 + PB7 pin + 0x01 + + + B_0x02 + PC7 pin + 0x02 + + + B_0x03 + PD7 pin + 0x03 + + + B_0x04 + PE7 pin + 0x04 + + + B_0x05 + PF7 pin + 0x05 + + + B_0x06 + PG7 pin + 0x06 + + + B_0x07 + PH7 pin + 0x07 + + + B_0x08 + PI7 pin + 0x08 + + + + + + + EXTI_EXTICR3 + EXTI_EXTICR3 + EXTI external interrupt selection register + 0x068 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EXTI8 + EXTI8 GPIO port selection + + 0 + 8 + read-write + + + B_0x00 + PA8 pin + 0x00 + + + B_0x01 + PB8 pin + 0x01 + + + B_0x02 + PC8 pin + 0x02 + + + B_0x03 + PD8 pin + 0x03 + + + B_0x04 + PE8 pin + 0x04 + + + B_0x05 + PF8 pin + 0x05 + + + B_0x06 + PG8 pin + 0x06 + + + B_0x07 + PH8 pin + 0x07 + + + B_0x08 + PI8 pin + 0x08 + + + + + EXTI9 + EXTI9 GPIO port selection + + 8 + 8 + read-write + + + B_0x00 + PA9 pin + 0x00 + + + B_0x01 + PB9 pin + 0x01 + + + B_0x02 + PC9 pin + 0x02 + + + B_0x03 + PD9 pin + 0x03 + + + B_0x04 + PE9 pin + 0x04 + + + B_0x05 + PF9 pin + 0x05 + + + B_0x06 + PG9 pin + 0x06 + + + B_0x07 + PH9 pin + 0x07 + + + B_0x08 + PI9 pin + 0x08 + + + + + EXTI10 + EXTI10 GPIO port selection + + 16 + 8 + read-write + + + B_0x00 + PA10 pin + 0x00 + + + B_0x01 + PB10 pin + 0x01 + + + B_0x02 + PC10 pin + 0x02 + + + B_0x03 + PD10 pin + 0x03 + + + B_0x04 + PE10 pin + 0x04 + + + B_0x05 + PF10 pin + 0x05 + + + B_0x06 + PG10 pin + 0x06 + + + B_0x07 + PH10 pin + 0x07 + + + B_0x08 + PI10 pin + 0x08 + + + + + EXTI11 + EXTI11 GPIO port selection + + 24 + 8 + read-write + + + B_0x00 + PA11 pin + 0x00 + + + B_0x01 + PB11 pin + 0x01 + + + B_0x02 + PC11 pin + 0x02 + + + B_0x03 + PD11 pin + 0x03 + + + B_0x04 + PE11 pin + 0x04 + + + B_0x05 + PF11 pin + 0x05 + + + B_0x06 + PG11 pin + 0x06 + + + B_0x07 + PH11 pin + 0x07 + + + B_0x08 + PI11 pin + 0x08 + + + + + + + EXTI_LOCKR + EXTI_LOCKR + EXTI lock register + 0x070 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LOCK + Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock + + 0 + 1 + read-write + + + B_0x0 + Security and privilege configuration open, can be modified. + 0x0 + + + B_0x1 + Security and privilege configuration locked, can no longer be modified. + 0x1 + + + + + + + EXTI_IMR1 + EXTI_IMR1 + EXTI CPU wake-up with interrupt mask register + 0x080 + 0x20 + read-write + 0xFFFE0000 + 0xFFFFFFFF + + + IM0 + CPU wake-up with interrupt mask on event input x + + 0 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM1 + CPU wake-up with interrupt mask on event input x + + 1 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM2 + CPU wake-up with interrupt mask on event input x + + 2 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM3 + CPU wake-up with interrupt mask on event input x + + 3 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM4 + CPU wake-up with interrupt mask on event input x + + 4 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM5 + CPU wake-up with interrupt mask on event input x + + 5 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM6 + CPU wake-up with interrupt mask on event input x + + 6 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM7 + CPU wake-up with interrupt mask on event input x + + 7 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM8 + CPU wake-up with interrupt mask on event input x + + 8 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM9 + CPU wake-up with interrupt mask on event input x + + 9 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM10 + CPU wake-up with interrupt mask on event input x + + 10 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM11 + CPU wake-up with interrupt mask on event input x + + 11 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM12 + CPU wake-up with interrupt mask on event input x + + 12 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM13 + CPU wake-up with interrupt mask on event input x + + 13 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM14 + CPU wake-up with interrupt mask on event input x + + 14 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM15 + CPU wake-up with interrupt mask on event input x + + 15 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM16 + CPU wake-up with interrupt mask on event input x + + 16 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM17 + CPU wake-up with interrupt mask on event input x + + 17 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM18 + CPU wake-up with interrupt mask on event input x + + 18 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM19 + CPU wake-up with interrupt mask on event input x + + 19 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM20 + CPU wake-up with interrupt mask on event input x + + 20 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM21 + CPU wake-up with interrupt mask on event input x + + 21 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM22 + CPU wake-up with interrupt mask on event input x + + 22 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM23 + CPU wake-up with interrupt mask on event input x + + 23 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM24 + CPU wake-up with interrupt mask on event input x + + 24 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM25 + CPU wake-up with interrupt mask on event input x + + 25 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM26 + CPU wake-up with interrupt mask on event input x + + 26 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM27 + CPU wake-up with interrupt mask on event input x + + 27 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM28 + CPU wake-up with interrupt mask on event input x + + 28 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM29 + CPU wake-up with interrupt mask on event input x + + 29 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM30 + CPU wake-up with interrupt mask on event input x + + 30 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM31 + CPU wake-up with interrupt mask on event input x + + 31 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + + + EXTI_EMR1 + EXTI_EMR1 + EXTI CPU wake-up with event mask register + 0x084 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EM0 + CPU wake-up with event generation mask on event input x + + 0 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM1 + CPU wake-up with event generation mask on event input x + + 1 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM2 + CPU wake-up with event generation mask on event input x + + 2 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM3 + CPU wake-up with event generation mask on event input x + + 3 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM4 + CPU wake-up with event generation mask on event input x + + 4 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM5 + CPU wake-up with event generation mask on event input x + + 5 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM6 + CPU wake-up with event generation mask on event input x + + 6 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM7 + CPU wake-up with event generation mask on event input x + + 7 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM8 + CPU wake-up with event generation mask on event input x + + 8 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM9 + CPU wake-up with event generation mask on event input x + + 9 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM10 + CPU wake-up with event generation mask on event input x + + 10 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM11 + CPU wake-up with event generation mask on event input x + + 11 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM12 + CPU wake-up with event generation mask on event input x + + 12 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM13 + CPU wake-up with event generation mask on event input x + + 13 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM14 + CPU wake-up with event generation mask on event input x + + 14 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM15 + CPU wake-up with event generation mask on event input x + + 15 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM16 + CPU wake-up with event generation mask on event input x + + 16 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM17 + CPU wake-up with event generation mask on event input x + + 17 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM18 + CPU wake-up with event generation mask on event input x + + 18 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM19 + CPU wake-up with event generation mask on event input x + + 19 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM20 + CPU wake-up with event generation mask on event input x + + 20 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM21 + CPU wake-up with event generation mask on event input x + + 21 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM22 + CPU wake-up with event generation mask on event input x + + 22 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM23 + CPU wake-up with event generation mask on event input x + + 23 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM24 + CPU wake-up with event generation mask on event input x + + 24 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM25 + CPU wake-up with event generation mask on event input x + + 25 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM26 + CPU wake-up with event generation mask on event input x + + 26 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM27 + CPU wake-up with event generation mask on event input x + + 27 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM28 + CPU wake-up with event generation mask on event input x + + 28 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM29 + CPU wake-up with event generation mask on event input x + + 29 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM30 + CPU wake-up with event generation mask on event input x + + 30 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM31 + CPU wake-up with event generation mask on event input x + + 31 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + + + EXTI_IMR2 + EXTI_IMR2 + EXTI CPU wake-up with interrupt mask register 2 + 0x090 + 0x20 + read-write + 0x07DBBFFF + 0xFFFFFFFF + + + IM32 + CPU wake-up with interrupt mask on event input x + + 0 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM33 + CPU wake-up with interrupt mask on event input x + + 1 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM34 + CPU wake-up with interrupt mask on event input x + + 2 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM35 + CPU wake-up with interrupt mask on event input x + + 3 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM36 + CPU wake-up with interrupt mask on event input x + + 4 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM37 + CPU wake-up with interrupt mask on event input x + + 5 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM38 + CPU wake-up with interrupt mask on event input x + + 6 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM39 + CPU wake-up with interrupt mask on event input x + + 7 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM40 + CPU wake-up with interrupt mask on event input x + + 8 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM41 + CPU wake-up with interrupt mask on event input x + + 9 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM42 + CPU wake-up with interrupt mask on event input x + + 10 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM43 + CPU wake-up with interrupt mask on event input x + + 11 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM44 + CPU wake-up with interrupt mask on event input x + + 12 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM45 + CPU wake-up with interrupt mask on event input x + + 13 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM46 + CPU wake-up with interrupt mask on event input x + + 14 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM47 + CPU wake-up with interrupt mask on event input x + + 15 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM48 + CPU wake-up with interrupt mask on event input x + + 16 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM49 + CPU wake-up with interrupt mask on event input x + + 17 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM50 + CPU wake-up with interrupt mask on event input x + + 18 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM51 + CPU wake-up with interrupt mask on event input x + + 19 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM52 + CPU wake-up with interrupt mask on event input x + + 20 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM53 + CPU wake-up with interrupt mask on event input x + + 21 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM54 + CPU wake-up with interrupt mask on event input x + + 22 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM55 + CPU wake-up with interrupt mask on event input x + + 23 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM56 + CPU wake-up with interrupt mask on event input x + + 24 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM57 + CPU wake-up with interrupt mask on event input x + + 25 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + IM58 + CPU wake-up with interrupt mask on event input x + + 26 + 1 + read-write + + + B_0x0 + Wake-up with interrupt request from input event x is masked. + 0x0 + + + B_0x1 + Wake-up with interrupt request from input event x is unmasked. + 0x1 + + + + + + + EXTI_EMR2 + EXTI_EMR2 + EXTI CPU wake-up with event mask register 2 + 0x094 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EM32 + CPU wake-up with event generation mask on event input x + + 0 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM33 + CPU wake-up with event generation mask on event input x + + 1 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM34 + CPU wake-up with event generation mask on event input x + + 2 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM35 + CPU wake-up with event generation mask on event input x + + 3 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM36 + CPU wake-up with event generation mask on event input x + + 4 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM37 + CPU wake-up with event generation mask on event input x + + 5 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM38 + CPU wake-up with event generation mask on event input x + + 6 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM39 + CPU wake-up with event generation mask on event input x + + 7 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM40 + CPU wake-up with event generation mask on event input x + + 8 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM41 + CPU wake-up with event generation mask on event input x + + 9 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM42 + CPU wake-up with event generation mask on event input x + + 10 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM43 + CPU wake-up with event generation mask on event input x + + 11 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM44 + CPU wake-up with event generation mask on event input x + + 12 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM45 + CPU wake-up with event generation mask on event input x + + 13 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM46 + CPU wake-up with event generation mask on event input x + + 14 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM47 + CPU wake-up with event generation mask on event input x + + 15 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM48 + CPU wake-up with event generation mask on event input x + + 16 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM49 + CPU wake-up with event generation mask on event input x + + 17 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM50 + CPU wake-up with event generation mask on event input x + + 18 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM51 + CPU wake-up with event generation mask on event input x + + 19 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM52 + CPU wake-up with event generation mask on event input x + + 20 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM53 + CPU wake-up with event generation mask on event input x + + 21 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM54 + CPU wake-up with event generation mask on event input x + + 22 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM55 + CPU wake-up with event generation mask on event input x + + 23 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM56 + CPU wake-up with event generation mask on event input x + + 24 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM57 + CPU wake-up with event generation mask on event input x + + 25 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + EM58 + CPU wake-up with event generation mask on event input x + + 26 + 1 + read-write + + + B_0x0 + Wake-up with event generation from Line x is masked. + 0x0 + + + B_0x1 + Wake-up with event generation from Line x is unmasked. + 0x1 + + + + + + + + + EXTI_S + 0X54022000 + + + FDCAN + FDCAN register blank and RAM + FDCAN + 0x4000a400 + + 0x0 + 0x400 + registers + + + FDCAN1_IT1 + FDCAN1 Interrupt 1 + 40 + + + FDCAN1_IT0 + FDCAN1 Interrupt 0 + 39 + + + + FDCAN_CREL + FDCAN_CREL + FDCAN core release register + 0x0000 + 0x20 + read-only + 0x32141218 + 0xFFFFFFFF + + + DAY + 18 + 0 + 8 + read-only + + + MON + 12 + 8 + 8 + read-only + + + YEAR + 4 + 16 + 4 + read-only + + + SUBSTEP + 1 + 20 + 4 + read-only + + + STEP + 2 + 24 + 4 + read-only + + + REL + 3 + 28 + 4 + read-only + + + + + FDCAN_ENDN + FDCAN_ENDN + FDCAN endian register + 0x0004 + 0x20 + read-only + 0x87654321 + 0xFFFFFFFF + + + ETV + Endianness test value + + 0 + 32 + read-only + + + + + FDCAN_DBTP + FDCAN_DBTP + FDCAN data bit timing and prescaler register + 0x000C + 0x20 + read-write + 0x00000A33 + 0xFFFFFFFF + + + DSJW + Synchronization jump width + + 0 + 4 + read-write + + + DTSEG2 + Data time segment after sample point + + 4 + 4 + read-write + + + DTSEG1 + Data time segment before sample point + + 8 + 5 + read-write + + + DBRP + Data bit rate prescaler + + 16 + 5 + read-write + + + TDC + Transceiver delay compensation + 23 + 1 + read-write + + + B_0x0 + Transceiver delay compensation disabled + 0x0 + + + B_0x1 + Transceiver delay compensation enabled + 0x1 + + + + + + + FDCAN_TEST + FDCAN_TEST + FDCAN test register + 0x0010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBCK + Loop back mode + 4 + 1 + read-write + + + B_0x0 + Reset value, Loop Back mode is disabled + 0x0 + + + B_0x1 + Loop Back mode is enabled (see Power down (Sleep mode)) + 0x1 + + + + + TX + Control of transmit pin + 5 + 2 + read-write + + + B_0x0 + Reset value, FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time + 0x0 + + + B_0x1 + Sample point can be monitored at pin FDCANx_TX + 0x1 + + + B_0x2 + Dominant (0) level at pin FDCANx_TX + 0x2 + + + B_0x3 + Recessive (1) at pin FDCANx_TX + 0x3 + + + + + RX + Receive pin + + 7 + 1 + read-only + + + B_0x0 + The CAN bus is dominant (FDCANx_RX = 0) + 0x0 + + + B_0x1 + The CAN bus is recessive (FDCANx_RX = 1) + 0x1 + + + + + + + FDCAN_RWD + FDCAN_RWD + FDCAN RAM watchdog register + 0x0014 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + WDC + Watchdog configuration + + 0 + 8 + read-write + + + WDV + Watchdog value + + 8 + 8 + read-only + + + + + FDCAN_CCCR + FDCAN_CCCR + FDCAN CC control register + 0x0018 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + INIT + Initialization + 0 + 1 + read-write + + + B_0x0 + Normal operation + 0x0 + + + B_0x1 + Initialization started + 0x1 + + + + + CCE + Configuration change enable + 1 + 1 + read-write + + + B_0x0 + The CPU has no write access to the protected configuration registers. + 0x0 + + + B_0x1 + The CPU has write access to the protected configuration registers (while CCCR. + 0x1 + + + + + ASM + ASM restricted operation mode + + 2 + 1 + read-write + + + B_0x0 + Normal CAN operation + 0x0 + + + B_0x1 + Restricted operation mode active + 0x1 + + + + + CSA + Clock stop acknowledge + 3 + 1 + read-only + + + B_0x0 + No clock stop acknowledged + 0x0 + + + B_0x1 + FDCAN can be set in power down by stopping APB clock and kernel clock. + 0x1 + + + + + CSR + Clock stop request + 4 + 1 + read-write + + + B_0x0 + No clock stop requested + 0x0 + + + B_0x1 + Clock stop requested. + 0x1 + + + + + MON + Bus monitoring mode + + 5 + 1 + read-write + + + B_0x0 + Bus monitoring mode disabled + 0x0 + + + B_0x1 + Bus monitoring mode enabled + 0x1 + + + + + DAR + Disable automatic retransmission + 6 + 1 + read-write + + + B_0x0 + Automatic retransmission of messages not transmitted successfully enabled + 0x0 + + + B_0x1 + Automatic retransmission disabled + 0x1 + + + + + TEST + Test mode enable + 7 + 1 + read-write + + + B_0x0 + Normal operation, register TEST holds reset values + 0x0 + + + B_0x1 + Test Mode, write access to register TEST enabled + 0x1 + + + + + FDOE + FD operation enable + 8 + 1 + read-write + + + B_0x0 + FD operation disabled + 0x0 + + + B_0x1 + FD operation enabled + 0x1 + + + + + BRSE + FDCAN bit rate switching + 9 + 1 + read-write + + + B_0x0 + Bit rate switching for transmissions disabled + 0x0 + + + B_0x1 + Bit rate switching for transmissions enabled + 0x1 + + + + + PXHD + Protocol exception handling disable + 12 + 1 + read-write + + + B_0x0 + Protocol exception handling enabled + 0x0 + + + B_0x1 + Protocol exception handling disabled + 0x1 + + + + + EFBI + Edge filtering during bus integration + 13 + 1 + read-write + + + B_0x0 + Edge filtering disabled + 0x0 + + + B_0x1 + Two consecutive dominant tq required to detect an edge for hard synchronization + 0x1 + + + + + TXP + If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame. + 14 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + NISO + Non ISO operation + + 15 + 1 + read-write + + + B_0x0 + CAN FD frame format according to ISO11898-1 + 0x0 + + + B_0x1 + CAN FD frame format according to Bosch CAN FD Specification V1. + 0x1 + + + + + + + FDCAN_NBTP + FDCAN_NBTP + FDCAN nominal bit timing and prescaler register + 0x001C + 0x20 + read-write + 0x06000A03 + 0xFFFFFFFF + + + NTSEG2 + Nominal time segment after sample point + + 0 + 7 + read-write + + + NTSEG1 + Nominal time segment before sample point + + 8 + 8 + read-write + + + NBRP + Bit rate prescaler + + 16 + 9 + read-write + + + NSJW + Nominal (re)synchronization jump width + + 25 + 7 + read-write + + + + + FDCAN_TSCC + FDCAN_TSCC + FDCAN timestamp counter configuration register + 0x0020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp select + + 0 + 2 + read-write + + + B_0x0 + Timestamp counter value always 0x0000 + 0x0 + + + B_0x1 + Timestamp counter value incremented according to TCP + 0x1 + + + B_0x2 + External timestamp counter from TIM3 value (tim3_cnt[0:15]) + 0x2 + + + B_0x3 + Same as 00. + 0x3 + + + + + TCP + Timestamp counter prescaler + + 16 + 4 + read-write + + + + + FDCAN_TSCV + FDCAN_TSCV + FDCAN timestamp counter value register + 0x0024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSC + Timestamp counter + + 0 + 16 + read-write + + + + + FDCAN_TOCC + FDCAN_TOCC + FDCAN timeout counter configuration register + 0x0028 + 0x20 + read-write + 0xFFFF0000 + 0xFFFFFFFF + + + ETOC + Timeout counter enable + + 0 + 1 + read-write + + + B_0x0 + Timeout counter disabled + 0x0 + + + B_0x1 + Timeout counter enabled + 0x1 + + + + + TOS + Timeout select + + 1 + 2 + read-write + + + B_0x0 + Continuous operation + 0x0 + + + B_0x1 + Timeout controlled by Tx event FIFO + 0x1 + + + B_0x2 + Timeout controlled by Rx FIFO 0 + 0x2 + + + B_0x3 + Timeout controlled by Rx FIFO 1 + 0x3 + + + + + TOP + Timeout period + + 16 + 16 + read-write + + + + + FDCAN_TOCV + FDCAN_TOCV + FDCAN timeout counter value register + 0x002C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + TOC + Timeout counter + + 0 + 16 + read-write + + + + + FDCAN_ECR + FDCAN_ECR + FDCAN error counter register + 0x0040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TEC + Transmit error counter + + 0 + 8 + read-only + + + REC + Receive error counter + + 8 + 7 + read-only + + + RP + Receive error passive + 15 + 1 + read-only + + + B_0x0 + The receive error counter is below the error passive level of 128. + 0x0 + + + B_0x1 + The receive error counter has reached the error passive level of 128. + 0x1 + + + + + CEL + CAN error logging + + 16 + 8 + read-write + + + + + FDCAN_PSR + FDCAN_PSR + FDCAN protocol status register + 0x0044 + 0x20 + read-write + 0x00000707 + 0xFFFFFFFF + + + LEC + Last error code + + 0 + 3 + read-write + + + B_0x0 + No Error: No error occurred since LEC has been reset by successful reception or transmission. + 0x0 + + + B_0x1 + Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. + 0x1 + + + B_0x2 + Form Error: A fixed format part of a received frame has the wrong format. + 0x2 + + + B_0x3 + AckError: The message transmitted by the FDCAN was not acknowledged by another node. + 0x3 + + + B_0x4 + Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant. + 0x4 + + + B_0x5 + Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. + 0x5 + + + B_0x6 + CRCError: The CRC check sum of a received message was incorrect. + 0x6 + + + B_0x7 + NoChange: Any read access to the Protocol status register re-initializes the LEC to 7'. + 0x7 + + + + + ACT + Activity + + 3 + 2 + read-only + + + B_0x0 + Synchronizing: node is synchronizing on CAN communication. + 0x0 + + + B_0x1 + Idle: node is neither receiver nor transmitter. + 0x1 + + + B_0x2 + Receiver: node is operating as receiver. + 0x2 + + + B_0x3 + Transmitter: node is operating as transmitter. + 0x3 + + + + + EP + Error passive + 5 + 1 + read-only + + + B_0x0 + The FDCAN is in the Error_Active state. + 0x0 + + + B_0x1 + The FDCAN is in the Error_Passive state. + 0x1 + + + + + EW + Warning Sstatus + 6 + 1 + read-only + + + B_0x0 + Both error counters are below the Error_Warning limit of 96. + 0x0 + + + B_0x1 + At least one of error counter has reached the Error_Warning limit of 96. + 0x1 + + + + + BO + Bus_Off status + 7 + 1 + read-only + + + B_0x0 + The FDCAN is not Bus_Off. + 0x0 + + + B_0x1 + The FDCAN is in Bus_Off state. + 0x1 + + + + + DLEC + Data last error code + + 8 + 3 + read-write + + + RESI + ESI flag of last received FDCAN message + + 11 + 1 + read-write + + + B_0x0 + Last received FDCAN message did not have its ESI flag set. + 0x0 + + + B_0x1 + Last received FDCAN message had its ESI flag set. + 0x1 + + + + + RBRS + BRS flag of last received FDCAN message + + 12 + 1 + read-write + + + B_0x0 + Last received FDCAN message did not have its BRS flag set. + 0x0 + + + B_0x1 + Last received FDCAN message had its BRS flag set. + 0x1 + + + + + REDL + Received FDCAN message + + 13 + 1 + read-write + + + B_0x0 + Since this bit was reset by the CPU, no FDCAN message has been received. + 0x0 + + + B_0x1 + Message in FDCAN format with EDL flag set has been received. + 0x1 + + + + + PXE + Protocol exception event + 14 + 1 + read-write + + + B_0x0 + No protocol exception event occurred since last read access + 0x0 + + + B_0x1 + Protocol exception event occurred + 0x1 + + + + + TDCV + Transmitter delay compensation value + + 16 + 7 + read-only + + + + + FDCAN_TDCR + FDCAN_TDCR + FDCAN transmitter delay compensation register + 0x0048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDCF + Transmitter delay compensation filter window length + + 0 + 7 + read-write + + + TDCO + Transmitter delay compensation offset + + 8 + 7 + read-write + + + + + FDCAN_IR + FDCAN_IR + FDCAN interrupt register + 0x0050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RF0N + Rx FIFO 0 new message + 0 + 1 + read-write + + + B_0x0 + No new message written to Rx FIFO 0 + 0x0 + + + B_0x1 + New message written to Rx FIFO 0 + 0x1 + + + + + RF0F + Rx FIFO 0 full + 1 + 1 + read-write + + + B_0x0 + Rx FIFO 0 not full + 0x0 + + + B_0x1 + Rx FIFO 0 full + 0x1 + + + + + RF0L + Rx FIFO 0 message lost + 2 + 1 + read-write + + + B_0x0 + No Rx FIFO 0 message lost + 0x0 + + + B_0x1 + Rx FIFO 0 message lost + 0x1 + + + + + RF1N + Rx FIFO 1 new message + 3 + 1 + read-write + + + B_0x0 + No new message written to Rx FIFO 1 + 0x0 + + + B_0x1 + New message written to Rx FIFO 1 + 0x1 + + + + + RF1F + Rx FIFO 1 full + 4 + 1 + read-write + + + B_0x0 + Rx FIFO 1 not full + 0x0 + + + B_0x1 + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 message lost + 5 + 1 + read-write + + + B_0x0 + No Rx FIFO 1 message lost + 0x0 + + + B_0x1 + Rx FIFO 1 message lost + 0x1 + + + + + HPM + High-priority message + 6 + 1 + read-write + + + B_0x0 + No high-priority message received + 0x0 + + + B_0x1 + High-priority message received + 0x1 + + + + + TC + Transmission completed + 7 + 1 + read-write + + + B_0x0 + No transmission completed + 0x0 + + + B_0x1 + Transmission completed + 0x1 + + + + + TCF + Transmission cancellation finished + 8 + 1 + read-write + + + B_0x0 + No transmission cancellation finished + 0x0 + + + B_0x1 + Transmission cancellation finished + 0x1 + + + + + TFE + Tx FIFO empty + 9 + 1 + read-write + + + B_0x0 + Tx FIFO non-empty + 0x0 + + + B_0x1 + Tx FIFO empty + 0x1 + + + + + TEFN + Tx event FIFO New Entry + 10 + 1 + read-write + + + B_0x0 + Tx event FIFO unchanged + 0x0 + + + B_0x1 + Tx handler wrote Tx event FIFO element. + 0x1 + + + + + TEFF + Tx event FIFO full + 11 + 1 + read-write + + + B_0x0 + Tx event FIFO Not full + 0x0 + + + B_0x1 + Tx event FIFO full + 0x1 + + + + + TEFL + Tx event FIFO element lost + 12 + 1 + read-write + + + B_0x0 + No Tx event FIFO element lost + 0x0 + + + B_0x1 + Tx event FIFO element lost + 0x1 + + + + + TSW + Timestamp wraparound + 13 + 1 + read-write + + + B_0x0 + No timestamp counter wrap-around + 0x0 + + + B_0x1 + Timestamp counter wrapped around + 0x1 + + + + + MRAF + Message RAM access failure + + 14 + 1 + read-write + + + B_0x0 + No Message RAM access failure occurred + 0x0 + + + B_0x1 + Message RAM access failure occurred + 0x1 + + + + + TOO + Timeout occurred + 15 + 1 + read-write + + + B_0x0 + No timeout + 0x0 + + + B_0x1 + Timeout reached + 0x1 + + + + + ELO + Error logging overflow + 16 + 1 + read-write + + + B_0x0 + CAN error logging counter did not overflow. + 0x0 + + + B_0x1 + Overflow of CAN error logging counter occurred. + 0x1 + + + + + EP + Error passive + 17 + 1 + read-write + + + B_0x0 + Error_Passive status unchanged + 0x0 + + + B_0x1 + Error_Passive status changed + 0x1 + + + + + EW + Warning status + 18 + 1 + read-write + + + B_0x0 + Error_Warning status unchanged + 0x0 + + + B_0x1 + Error_Warning status changed + 0x1 + + + + + BO + Bus_Off status + 19 + 1 + read-write + + + B_0x0 + Bus_Off status unchanged + 0x0 + + + B_0x1 + Bus_Off status changed + 0x1 + + + + + WDI + Watchdog interrupt + 20 + 1 + read-write + + + B_0x0 + No message RAM watchdog event occurred + 0x0 + + + B_0x1 + Message RAM watchdog event due to missing READY + 0x1 + + + + + PEA + Protocol error in arbitration phase (nominal bit time is used) + 21 + 1 + read-write + + + B_0x0 + No protocol error in arbitration phase + 0x0 + + + B_0x1 + Protocol error in arbitration phase detected (PSR. + 0x1 + + + + + PED + Protocol error in data phase (data bit time is used) + 22 + 1 + read-write + + + B_0x0 + No protocol error in data phase + 0x0 + + + B_0x1 + Protocol error in data phase detected (PSR. + 0x1 + + + + + ARA + Access to reserved address + 23 + 1 + read-write + + + B_0x0 + No access to reserved address occurred + 0x0 + + + B_0x1 + Access to reserved address occurred + 0x1 + + + + + + + FDCAN_IE + FDCAN_IE + FDCAN interrupt enable register + 0x0054 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RF0NE + Rx FIFO 0 new message interrupt enable + 0 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF0FE + Rx FIFO 0 full interrupt enable + 1 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF0LE + Rx FIFO 0 message lost interrupt enable + 2 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF1NE + Rx FIFO 1 new message interrupt enable + 3 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF1FE + Rx FIFO 1 full interrupt enable + 4 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + RF1LE + Rx FIFO 1 message lost interrupt enable + 5 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + HPME + High-priority message interrupt enable + 6 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TCE + Transmission completed interrupt enable + 7 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TCFE + Transmission cancellation finished interrupt enable + 8 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TFEE + Tx FIFO empty interrupt enable + 9 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TEFNE + Tx event FIFO new entry interrupt enable + 10 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TEFFE + Tx event FIFO full interrupt enable + 11 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TEFLE + Tx event FIFO element lost interrupt enable + 12 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TSWE + Timestamp wraparound interrupt enable + 13 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + MRAFE + Message RAM access failure interrupt enable + 14 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TOOE + Timeout occurred interrupt enable + 15 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + ELOE + Error logging overflow interrupt enable + 16 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EPE + Error passive interrupt enable + 17 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + EWE + Warning status interrupt enable + 18 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + BOE + Bus_Off status + 19 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + WDIE + Watchdog interrupt enable + 20 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + PEAE + Protocol error in arbitration phase enable + 21 + 1 + read-write + + + PEDE + Protocol error in data phase enable + 22 + 1 + read-write + + + ARAE + Access to reserved address enable + 23 + 1 + read-write + + + + + FDCAN_ILS + FDCAN_ILS + FDCAN interrupt line select register + 0x0058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RXFIFO0 + RX FIFO bit grouping the following interruption + + 0 + 1 + read-write + + + RXFIFO1 + RX FIFO bit grouping the following interruption + + 1 + 1 + read-write + + + SMSG + Status message bit grouping the following interruption + + 2 + 1 + read-write + + + TFERR + Tx FIFO ERROR grouping the following interruption + + 3 + 1 + read-write + + + MISC + Interrupt regrouping the following interruption + + 4 + 1 + read-write + + + BERR + Bit and line error grouping the following interruption + + 5 + 1 + read-write + + + PERR + Protocol error grouping the following interruption + + 6 + 1 + read-write + + + + + FDCAN_ILE + FDCAN_ILE + FDCAN interrupt line enable register + 0x005C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EINT0 + Enable interrupt line 0 + 0 + 1 + read-write + + + B_0x0 + Interrupt line fdcan_intr1_it disabled + 0x0 + + + B_0x1 + Interrupt line fdcan_intr1_it enabled + 0x1 + + + + + EINT1 + Enable interrupt line 1 + 1 + 1 + read-write + + + B_0x0 + Interrupt line fdcan_intr0_it disabled + 0x0 + + + B_0x1 + Interrupt line fdcan_intr0_it enabled + 0x1 + + + + + + + FDCAN_RXGFC + FDCAN_RXGFC + FDCAN global filter configuration register + 0x0080 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RRFE + Reject remote frames extended + + 0 + 1 + read-write + + + B_0x0 + Filter remote frames with 29-bit standard IDs + 0x0 + + + B_0x1 + Reject all remote frames with 29-bit standard IDs + 0x1 + + + + + RRFS + Reject remote frames standard + + 1 + 1 + read-write + + + B_0x0 + Filter remote frames with 11-bit standard IDs + 0x0 + + + B_0x1 + Reject all remote frames with 11-bit standard IDs + 0x1 + + + + + ANFE + Accept non-matching frames extended + + 2 + 2 + read-write + + + B_0x0 + Accept in Rx FIFO 0 + 0x0 + + + B_0x1 + Accept in Rx FIFO 1 + 0x1 + + + B_0x2 + Reject + 0x2 + + + B_0x3 + Reject + 0x3 + + + + + ANFS + Accept Non-matching frames standard + + 4 + 2 + read-write + + + B_0x0 + Accept in Rx FIFO 0 + 0x0 + + + B_0x1 + Accept in Rx FIFO 1 + 0x1 + + + B_0x2 + Reject + 0x2 + + + B_0x3 + Reject + 0x3 + + + + + F1OM + FIFO 1 operation mode (overwrite or blocking) + + 8 + 1 + read-write + + + F0OM + FIFO 0 operation mode (overwrite or blocking) + + 9 + 1 + read-write + + + LSS + List size standard + + 16 + 5 + read-write + + + B_0x0 + No standard message ID filter + 0x0 + + + + + LSE + List size extended + + 24 + 4 + read-write + + + B_0x0 + No extended message ID filter + 0x0 + + + + + + + FDCAN_XIDAM + FDCAN_XIDAM + FDCAN extended ID and mask register + 0x0084 + 0x20 + read-write + 0x1FFFFFFF + 0xFFFFFFFF + + + EIDM + Extended ID mask + + 0 + 29 + read-write + + + + + FDCAN_HPMS + FDCAN_HPMS + FDCAN high-priority message status register + 0x0088 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + BIDX + Buffer index + + 0 + 3 + read-only + + + MSI + Message storage indicator + 6 + 2 + read-only + + + B_0x0 + No FIFO selected + 0x0 + + + B_0x1 + FIFO overrun + 0x1 + + + B_0x2 + Message stored in FIFO 0 + 0x2 + + + B_0x3 + Message stored in FIFO 1 + 0x3 + + + + + FIDX + Filter index + + 8 + 5 + read-only + + + FLST + Filter list + + 15 + 1 + read-only + + + B_0x0 + Standard filter list + 0x0 + + + B_0x1 + Extended filter list + 0x1 + + + + + + + FDCAN_RXF0S + FDCAN_RXF0S + FDCAN Rx FIFO 0 status register + 0x0090 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + F0FL + Rx FIFO 0 fill level + + 0 + 4 + read-only + + + F0GI + Rx FIFO 0 get index + + 8 + 2 + read-only + + + F0PI + Rx FIFO 0 put index + + 16 + 2 + read-only + + + F0F + Rx FIFO 0 full + 24 + 1 + read-only + + + B_0x0 + Rx FIFO 0 not full + 0x0 + + + B_0x1 + Rx FIFO 0 full + 0x1 + + + + + RF0L + Rx FIFO 0 message lost + + 25 + 1 + read-only + + + B_0x0 + No Rx FIFO 0 message lost + 0x0 + + + B_0x1 + Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0 + 0x1 + + + + + + + FDCAN_RXF0A + FDCAN_RXF0A + CAN Rx FIFO 0 acknowledge register + 0x0094 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + F0AI + Rx FIFO 0 acknowledge index + + 0 + 3 + read-write + + + + + FDCAN_RXF1S + FDCAN_RXF1S + FDCAN Rx FIFO 1 status register + 0x0098 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + F1FL + Rx FIFO 1 fill level + + 0 + 4 + read-only + + + F1GI + Rx FIFO 1 get index + + 8 + 2 + read-only + + + F1PI + Rx FIFO 1 put index + + 16 + 2 + read-only + + + F1F + Rx FIFO 1 full + 24 + 1 + read-only + + + B_0x0 + Rx FIFO 1 not full + 0x0 + + + B_0x1 + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 message lost + + 25 + 1 + read-only + + + B_0x0 + No Rx FIFO 1 message lost + 0x0 + + + B_0x1 + Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0 + 0x1 + + + + + + + FDCAN_RXF1A + FDCAN_RXF1A + FDCAN Rx FIFO 1 acknowledge register + 0x009C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + F1AI + Rx FIFO 1 acknowledge index + + 0 + 3 + read-write + + + + + FDCAN_TXBC + FDCAN_TXBC + FDCAN Tx buffer configuration register + 0x00C0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TFQM + Tx FIFO/queue mode + + 24 + 1 + read-write + + + B_0x0 + Tx FIFO operation + 0x0 + + + B_0x1 + Tx queue operation. + 0x1 + + + + + + + FDCAN_TXFQS + FDCAN_TXFQS + FDCAN Tx FIFO/queue status register + 0x00C4 + 0x20 + read-only + 0x00000003 + 0xFFFFFFFF + + + TFFL + Tx FIFO free level + + 0 + 3 + read-only + + + TFGI + Tx FIFO get index + + 8 + 2 + read-only + + + TFQPI + Tx FIFO/queue put index + + 16 + 2 + read-only + + + TFQF + Tx FIFO/queue full + 21 + 1 + read-only + + + B_0x0 + Tx FIFO/queue not full + 0x0 + + + B_0x1 + Tx FIFO/queue full + 0x1 + + + + + + + FDCAN_TXBRP + FDCAN_TXBRP + FDCAN Tx buffer request pending register + 0x00C8 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TRP + Transmission request pending + + 0 + 3 + read-only + + + B_0x0 + No transmission request pending + 0x0 + + + B_0x1 + Transmission request pending + 0x1 + + + + + + + FDCAN_TXBAR + FDCAN_TXBAR + FDCAN Tx buffer add request register + 0x00CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AR + Add request + + 0 + 3 + read-write + + + B_0x0 + No transmission request added + 0x0 + + + B_0x1 + Transmission requested added. + 0x1 + + + + + + + FDCAN_TXBCR + FDCAN_TXBCR + FDCAN Tx buffer cancellation request register + 0x00D0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CR + Cancellation request + + 0 + 3 + read-write + + + B_0x0 + No cancellation pending + 0x0 + + + B_0x1 + Cancellation pending + 0x1 + + + + + + + FDCAN_TXBTO + FDCAN_TXBTO + FDCAN Tx buffer transmission occurred register + 0x00D4 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TO + Transmission occurred. + 0 + 3 + read-only + + + B_0x0 + No transmission occurred + 0x0 + + + B_0x1 + Transmission occurred + 0x1 + + + + + + + FDCAN_TXBCF + FDCAN_TXBCF + FDCAN Tx buffer cancellation finished register + 0x00D8 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CF + Cancellation finished + + 0 + 3 + read-only + + + B_0x0 + No transmit buffer cancellation + 0x0 + + + B_0x1 + Transmit buffer cancellation finished + 0x1 + + + + + + + FDCAN_TXBTIE + FDCAN_TXBTIE + FDCAN Tx buffer transmission interrupt enable register + 0x00DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIE + Transmission interrupt enable + + 0 + 3 + read-write + + + B_0x0 + Transmission interrupt disabled + 0x0 + + + B_0x1 + Transmission interrupt enable + 0x1 + + + + + + + FDCAN_TXBCIE + FDCAN_TXBCIE + FDCAN Tx buffer cancellation finished interrupt enable register + 0x00E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CFIE + Cancellation finished interrupt enable. + 0 + 3 + read-write + + + B_0x0 + Cancellation finished interrupt disabled + 0x0 + + + B_0x1 + Cancellation finished interrupt enabled + 0x1 + + + + + + + FDCAN_TXEFS + FDCAN_TXEFS + FDCAN Tx event FIFO status register + 0x00E4 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + EFFL + Event FIFO fill level + + 0 + 3 + read-only + + + EFGI + Event FIFO get index + + 8 + 2 + read-only + + + EFPI + Event FIFO put index + + 16 + 2 + read-only + + + EFF + Event FIFO full + 24 + 1 + read-only + + + B_0x0 + Tx event FIFO not full + 0x0 + + + B_0x1 + Tx event FIFO full + 0x1 + + + + + TEFL + Tx event FIFO element lost + + 25 + 1 + read-only + + + + + FDCAN_TXEFA + FDCAN_TXEFA + FDCAN Tx event FIFO acknowledge register + 0x00E8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EFAI + Event FIFO acknowledge index + + 0 + 2 + read-write + + + + + FDCAN_CKDIV + FDCAN_CKDIV + FDCAN CFG clock divider register + 0x0100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PDIV + input clock divider + + 0 + 4 + read-write + + + B_0x0 + Divide by 1 + 0x0 + + + B_0x1 + Divide by 2 + 0x1 + + + B_0x2 + Divide by 4 + 0x2 + + + B_0x3 + Divide by 6 + 0x3 + + + B_0x4 + Divide by 8 + 0x4 + + + B_0x5 + Divide by 10 + 0x5 + + + B_0x6 + Divide by 12 + 0x6 + + + B_0x7 + Divide by 14 + 0x7 + + + B_0x8 + Divide by 16 + 0x8 + + + B_0x9 + Divide by 18 + 0x9 + + + B_0xA + Divide by 20 + 0xA + + + B_0xB + Divide by 22 + 0xB + + + B_0xC + Divide by 24 + 0xC + + + B_0xD + Divide by 26 + 0xD + + + B_0xE + Divide by 28 + 0xE + + + B_0xF + Divide by 30 + 0xF + + + + + + + + + FDCAN_S + 0X5000A400 + + + FDCAN2 + 0x4000A800 + + FDCAN2_IT1 + FDCAN2 Interrupt 1 + 110 + + + FDCAN2_IT0 + FDCAN2 Interrupt 0 + 109 + + + + FDCAN2_S + 0x5000A800 + + + FLASH + Mustang_FLASH register block + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash non-secure global interrupt + 6 + + + + FLASH_ACR + FLASH_ACR + FLASH access control register + 0x000 + 0x20 + read-write + 0x00000013 + 0xFFFFFFFF + + + LATENCY + Read latency + + 0 + 4 + read-write + + + B_0x0 + no wait states used to read a word from nonvolatile memory + 0x0 + + + B_0x1 + one wait state used to read a word from nonvolatile memory + 0x1 + + + B_0x2 + two wait states used to read a word from nonvolatile memory + 0x2 + + + B_0x7 + seven wait states used to read a word from nonvolatile memory + 0x7 + + + B_0xF + 15 wait states used to read a word from nonvolatile memory + 0xF + + + + + WRHIGHFREQ + Flash signal delay + + 4 + 2 + read-write + + + PRFTEN + Prefetch enable. + 8 + 1 + read-write + + + B_0x0 + prefetch disabled. + 0x0 + + + B_0x1 + prefetch enabled when latency is at least one wait state. + 0x1 + + + + + + + FLASH_NSKEYR + FLASH_NSKEYR + FLASH non-secure key register + 0x004 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + NSKEY + Non-volatile memory non-secure configuration access unlock key + 0 + 32 + write-only + + + + + FLASH_SECKEYR + FLASH_SECKEYR + FLASH secure key register + 0x008 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SECKEY + Non-volatile memory secure configuration access unlock key + 0 + 32 + write-only + + + + + FLASH_OPTKEYR + FLASH_OPTKEYR + FLASH option key register + 0x00C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + OPTKEY + FLASH option bytes control access unlock key + 0 + 32 + write-only + + + + + FLASH_NSOBKKEYR + FLASH_NSOBKKEYR + FLASH non-secure OBK key register + 0x0010 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + NSOBKKEY + FLASH non-secure option bytes keys control access unlock key + 0 + 32 + write-only + + + + + FLASH_SECOBKKEYR + FLASH_SECOBKKEYR + FLASH secure OBK key register + 0x0014 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SECOBKKEY + FLASH secure option bytes keys control access unlock key + 0 + 32 + write-only + + + + + FLASH_OPSR + FLASH_OPSR + FLASH operation status register + 0x0018 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + ADDR_OP + Interrupted operation address + 0 + 20 + read-only + + + DATA_OP + Flash high-cycle data area operation interrupted + + 21 + 1 + read-only + + + BK_OP + Interrupted operation bank + + 22 + 1 + read-only + + + SYSF_OP + Operation in system flash memory interrupted + + 23 + 1 + read-only + + + OTP_OP + OTP operation interrupted + + 24 + 1 + read-only + + + CODE_OP + Flash memory operation code + 29 + 3 + read-only + + + B_0x0 + No flash operation on going during previous reset + 0x0 + + + B_0x1 + Single write operation interrupted + 0x1 + + + B_0x2 + OBK alternate sector erase + 0x2 + + + B_0x3 + Sector erase operation interrupted + 0x3 + + + B_0x4 + Bank erase operation interrupted + 0x4 + + + B_0x5 + Mass erase operation interrupted + 0x5 + + + B_0x6 + Option change operation interrupted + 0x6 + + + B_0x7 + OBK swap sector request + 0x7 + + + + + + + FLASH_OPTCR + FLASH_OPTCR + FLASH option control register + 0x01C + 0x20 + read-write + 0x00000001 + 0x0FFFFFFF + + + OPTLOCK + FLASH_OPTCR lock option configuration bit + + 0 + 1 + read-write + + + B_0x0 + FLASH_OPTCR register unlocked + 0x0 + + + B_0x1 + FLASH_OPTCR register locked. + 0x1 + + + + + OPTSTRT + Option byte start change option configuration bit + + 1 + 1 + read-write + + + SWAP_BANK + Bank swapping option configuration bit + + 31 + 1 + read-only + + + B_0x0 + Bank1 and Bank2 not swapped + 0x0 + + + B_0x1 + Bank1 and Bank2 swapped + 0x1 + + + + + + + FLASH_NSSR + FLASH_NSSR + FLASH non-secure status register + 0x020 + 0x20 + read-only + 0x00000000 + 0xFFFFFFF0 + + + BSY + busy flag + + 0 + 1 + read-only + + + B_0x0 + no programming, erase or option byte change operation being executed + 0x0 + + + B_0x1 + programming, erase or option byte change operation being executed + 0x1 + + + + + WBNE + write buffer not empty flag + + 1 + 1 + read-only + + + B_0x0 + write buffer empty or full + 0x0 + + + B_0x1 + write buffer waiting data to complete + 0x1 + + + + + DBNE + data buffer not empty flag + + 3 + 1 + read-only + + + B_0x0 + data buffer not used + 0x0 + + + B_0x1 + data buffer used, wait + 0x1 + + + + + EOP + end of operation flag + + 16 + 1 + read-only + + + B_0x0 + no operation completed + 0x0 + + + B_0x1 + a operation completed + 0x1 + + + + + WRPERR + write protection error flag + + 17 + 1 + read-only + + + B_0x0 + no write protection error occurred + 0x0 + + + B_0x1 + a write protection error occurred + 0x1 + + + + + PGSERR + programming sequence error flag + + 18 + 1 + read-only + + + B_0x0 + no sequence error occurred + 0x0 + + + B_0x1 + a sequence error occurred + 0x1 + + + + + STRBERR + strobe error flag + + 19 + 1 + read-only + + + B_0x0 + no strobe error occurred + 0x0 + + + B_0x1 + a strobe error occurred + 0x1 + + + + + INCERR + inconsistency error flag + + 20 + 1 + read-only + + + B_0x0 + no inconsistency error occurs + 0x0 + + + B_0x1 + a inconsistency error occurs + 0x1 + + + + + OBKERR + OBK general error flag + + 21 + 1 + read-only + + + B_0x0 + no OBK general error occurred + 0x0 + + + B_0x1 + an OBK general error occurred + 0x1 + + + + + OBKWERR + OBK write error flag + + 22 + 1 + read-only + + + B_0x0 + no OBK write error occurred + 0x0 + + + B_0x1 + an OBK write error occurred + 0x1 + + + + + OPTCHANGEERR + Option byte change error flag + + 23 + 1 + read-only + + + B_0x0 + no option byte change errors occurred + 0x0 + + + B_0x1 + one or more errors occurred during an option byte change operation. + 0x1 + + + + + + + FLASH_SECSR + FLASH_SECSR + FLASH secure status register + 0x024 + 0x20 + read-only + 0x00000000 + 0xFFFFFFF0 + + + BSY + busy flag + + 0 + 1 + read-only + + + B_0x0 + no programming, erase or option byte change operation being executed + 0x0 + + + B_0x1 + programming, erase or option byte change operation being executed + 0x1 + + + + + WBNE + write buffer not empty flag + + 1 + 1 + read-only + + + B_0x0 + write buffer empty or full + 0x0 + + + B_0x1 + write buffer waiting data to complete + 0x1 + + + + + DBNE + data buffer not empty flag + + 3 + 1 + read-only + + + B_0x0 + data buffer not used + 0x0 + + + B_0x1 + data buffer used, wait + 0x1 + + + + + EOP + end of operation flag + + 16 + 1 + read-only + + + B_0x0 + no operation completed + 0x0 + + + B_0x1 + a operation completed + 0x1 + + + + + WRPERR + write protection error flag + + 17 + 1 + read-only + + + B_0x0 + no write protection error occurred + 0x0 + + + B_0x1 + a write protection error occurred + 0x1 + + + + + PGSERR + programming sequence error flag + + 18 + 1 + read-only + + + B_0x0 + no sequence error occurred + 0x0 + + + B_0x1 + a sequence error occurred + 0x1 + + + + + STRBERR + strobe error flag + + 19 + 1 + read-only + + + B_0x0 + no strobe error occurred + 0x0 + + + B_0x1 + a strobe error occurred + 0x1 + + + + + INCERR + inconsistency error flag + + 20 + 1 + read-only + + + B_0x0 + no inconsistency error occurred + 0x0 + + + B_0x1 + a inconsistency error occurred + 0x1 + + + + + OBKERR + OBK general error flag + + 21 + 1 + read-only + + + B_0x0 + no OBK general error occurred + 0x0 + + + B_0x1 + an OBK general error occurred + 0x1 + + + + + OBKWERR + OBK write error flag + + 22 + 1 + read-only + + + B_0x0 + no OBK write error occurred + 0x0 + + + B_0x1 + an OBK write error occurred + 0x1 + + + + + + + FLASH_NSCR + FLASH_NSCR + FLASH non-secure control register + 0x028 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + LOCK + configuration lock bit + + 0 + 1 + read-write + + + B_0x0 + FLASH_NSCR register unlocked + 0x0 + + + B_0x1 + FLASH_NSCR register locked + 0x1 + + + + + PG + programming control bit + + 1 + 1 + read-write + + + B_0x0 + programming disabled + 0x0 + + + B_0x1 + programming enabled + 0x1 + + + + + SER + sector erase request + + 2 + 1 + read-write + + + B_0x0 + sector erase not requested + 0x0 + + + B_0x1 + sector erase requested + 0x1 + + + + + BER + erase request + + 3 + 1 + read-write + + + B_0x0 + bank erase not requested + 0x0 + + + B_0x1 + bank erase requested + 0x1 + + + + + FW + write forcing control bit + + 4 + 1 + read-write + + + STRT + erase start control bit + + 5 + 1 + read-write + + + SNB + sector erase selection number + + 6 + 7 + read-write + + + B_0x00 + Sector 0 selected + 0x00 + + + B_0x01 + Sector 1 selected + 0x01 + + + B_0x7F + Sector 127 selected + 0x7F + + + + + MER + mass erase request + + 15 + 1 + read-write + + + B_0x0 + mass erase not requested + 0x0 + + + B_0x1 + mass erase requested + 0x1 + + + + + EOPIE + end of operation interrupt control bit + + 16 + 1 + read-write + + + B_0x0 + no interrupt generated at the end of operation. + 0x0 + + + B_0x1 + interrupt enabled when at the end of operation + 0x1 + + + + + WRPERRIE + write protection error interrupt enable bit + + 17 + 1 + read-write + + + B_0x0 + no interrupt generated when a protection error occurs + 0x0 + + + B_0x1 + interrupt generated when a protection error occurs + 0x1 + + + + + PGSERRIE + programming sequence error interrupt enable bit + + 18 + 1 + read-write + + + B_0x0 + no interrupt generated when a sequence error occurs + 0x0 + + + B_0x1 + interrupt generated when sequence error occurs + 0x1 + + + + + STRBERRIE + strobe error interrupt enable bit + + 19 + 1 + read-write + + + B_0x0 + no interrupt generated when a strobe error occurs + 0x0 + + + B_0x1 + interrupt generated when strobe error occurs. + 0x1 + + + + + INCERRIE + inconsistency error interrupt enable bit + + 20 + 1 + read-write + + + B_0x0 + no interrupt generated when a inconsistency error occurs + 0x0 + + + B_0x1 + interrupt generated when a inconsistency error occurs. + 0x1 + + + + + OBKERRIE + OBK general error interrupt enable bit + + 21 + 1 + read-write + + + B_0x0 + no interrupt is generated on OBK general access error + 0x0 + + + B_0x1 + an interrupt is generated on OBK general access error + 0x1 + + + + + OBKWERRIE + OBK write error interrupt enable bit + + 22 + 1 + read-write + + + B_0x0 + no interrupt is generated on OBK write error + 0x0 + + + B_0x1 + an interrupt is generated on OBK write error + 0x1 + + + + + OPTCHANGEERRIE + Option byte change error interrupt enable bit + + 23 + 1 + read-write + + + B_0x0 + no interrupt is generated when an error occurs during an option byte change + 0x0 + + + B_0x1 + an interrupt is generated when and error occurs during an option byte change. + 0x1 + + + + + BKSEL + Bank selector bit + + 31 + 1 + read-write + + + B_0x0 + Bank1 is selected for Bank erase / sector erase / interrupt enable + 0x0 + + + B_0x1 + Bank2 is selected for BER / SER + 0x1 + + + + + + + FLASH_SECCR + FLASH_SECCR + FLASH secure control register + 0x02C + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + LOCK + configuration lock bit + + 0 + 1 + read-write + + + B_0x0 + FLASH_SECCR register unlocked + 0x0 + + + B_0x1 + FLASH_SECCR register locked + 0x1 + + + + + PG + programming control bit + + 1 + 1 + read-write + + + B_0x0 + programming disabled + 0x0 + + + B_0x1 + programming enabled + 0x1 + + + + + SER + sector erase request + + 2 + 1 + read-write + + + B_0x0 + sector erase not requested + 0x0 + + + B_0x1 + sector erase requested + 0x1 + + + + + BER + erase request + + 3 + 1 + read-write + + + B_0x0 + bank erase not requested + 0x0 + + + B_0x1 + bank erase requested + 0x1 + + + + + FW + write forcing control bit + + 4 + 1 + read-write + + + STRT + erase start control bit + + 5 + 1 + read-write + + + SNB + sector erase selection number + + 6 + 7 + read-write + + + B_0x00 + Sector 0 selected + 0x00 + + + B_0x01 + Sector 1 selected + 0x01 + + + B_0x7F + Sector 127 selected + 0x7F + + + + + MER + mass erase request + + 15 + 1 + read-write + + + B_0x0 + mass erase not requested + 0x0 + + + B_0x1 + mass erase requested + 0x1 + + + + + EOPIE + end of operation interrupt control bit + + 16 + 1 + read-write + + + B_0x0 + no interrupt generated at the end of operation. + 0x0 + + + B_0x1 + interrupt enabled when at the end of operation + 0x1 + + + + + WRPERRIE + write protection error interrupt enable bit + + 17 + 1 + read-write + + + B_0x0 + no interrupt generated when a protection error occurs + 0x0 + + + B_0x1 + interrupt generated when a protection error occurs + 0x1 + + + + + PGSERRIE + programming sequence error interrupt enable bit + + 18 + 1 + read-write + + + B_0x0 + no interrupt generated when a sequence error occurs + 0x0 + + + B_0x1 + interrupt generated when sequence error occurs + 0x1 + + + + + STRBERRIE + strobe error interrupt enable bit + + 19 + 1 + read-write + + + B_0x0 + no interrupt generated when a strobe error occurs + 0x0 + + + B_0x1 + interrupt generated when strobe error occurs. + 0x1 + + + + + INCERRIE + inconsistency error interrupt enable bit + + 20 + 1 + read-write + + + B_0x0 + no interrupt generated when a inconsistency error occurs + 0x0 + + + B_0x1 + interrupt generated when a inconsistency error occurs. + 0x1 + + + + + OBKERRIE + OBK general error interrupt enable bit + + 21 + 1 + read-write + + + B_0x0 + no interrupt is generated on OBK general access error + 0x0 + + + B_0x1 + an interrupt is generated on OBK general access error + 0x1 + + + + + OBKWERRIE + OBK write error interrupt enable bit + + 22 + 1 + read-write + + + B_0x0 + no interrupt is generated on OBK write error + 0x0 + + + B_0x1 + an interrupt is generated on OBK write error + 0x1 + + + + + INV + Flash memory security state invert. + 29 + 1 + read-write + + + BKSEL + Bank selector bit + + 31 + 1 + read-write + + + B_0x0 + Bank1 is selected for Bank erase / sector erase / interrupt enable + 0x0 + + + B_0x1 + Bank2 is selected for BER / SER + 0x1 + + + + + + + FLASH_NSCCR + FLASH_NSCCR + FLASH non-secure clear control register + 0x030 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CLR_EOP + EOP flag clear bit + + 16 + 1 + write-only + + + CLR_WRPERR + WRPERR flag clear bit + + 17 + 1 + write-only + + + CLR_PGSERR + PGSERR flag clear bit + + 18 + 1 + write-only + + + CLR_STRBERR + STRBERR flag clear bit + + 19 + 1 + write-only + + + CLR_INCERR + INCERR flag clear bit + + 20 + 1 + write-only + + + CLR_OBKERR + OBKERR flag clear bit. + 21 + 1 + write-only + + + CLR_OBKWERR + OBKWERR flag clear bit. + 22 + 1 + write-only + + + CLR_OPTCHANGEERR + Clear the flag corresponding flag in FLASH_NSSR by writing this bit. + 23 + 1 + write-only + + + + + FLASH_SECCCR + FLASH_SECCCR + FLASH secure clear control register + 0x034 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CLR_EOP + EOP flag clear bit + + 16 + 1 + write-only + + + CLR_WRPERR + WRPERR flag clear bit + + 17 + 1 + write-only + + + CLR_PGSERR + PGSERR flag clear bit + + 18 + 1 + write-only + + + CLR_STRBERR + STRBERR flag clear bit + + 19 + 1 + write-only + + + CLR_INCERR + INCERR flag clear bit + + 20 + 1 + write-only + + + CLR_OBKERR + OBKWERR flag clear bit + + 21 + 1 + write-only + + + CLR_OBKWERR + OBKWERR flag clear bit + + 22 + 1 + write-only + + + + + FLASH_PRIVCFGR + FLASH_PRIVCFGR + FLASH privilege configuration register + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPRIV + privilege attribute for secure registers + 0 + 1 + read-write + + + B_0x0 + access to secure registers is always granted + 0x0 + + + B_0x1 + access to secure registers is denied in case of unprivileged access. + 0x1 + + + + + NSPRIV + privilege attribute for non secure registers + 1 + 1 + read-write + + + B_0x0 + access to non secure registers is always granted + 0x0 + + + B_0x1 + access to non secure registers is denied in case of unprivileged access. + 0x1 + + + + + + + FLASH_NSOBKCFGR + FLASH_NSOBKCFGR + FLASH non-secure OBK configuration register + 0x040 + 0x20 + read-write + 0x01FF0000 + 0xFFFFFFFF + + + LOCK + OBKCFGR lock option configuration bit + + 0 + 1 + read-write + + + B_0x0 + FLASH_NSOBKCFGR register unlocked + 0x0 + + + B_0x1 + FLASH_NSOBKCFGR register locked + 0x1 + + + + + SWAP_SECT_REQ + OBK swap sector request bit + + 1 + 1 + read-write + + + B_0x0 + no swap requested + 0x0 + + + B_0x1 + launch the sector swap + 0x1 + + + + + ALT_SECT + alternate sector bit + + 2 + 1 + read-write + + + B_0x0 + current OBK sector is mapped to OBK address range for access + 0x0 + + + B_0x1 + alternate OBK sector is mapped to OBK address range for access + 0x1 + + + + + ALT_SECT_ERASE + alternate sector erase bit + + 3 + 1 + read-write + + + B_0x0 + do not touch OBK sector + 0x0 + + + B_0x1 + erase the alternate OBK sector + 0x1 + + + + + SWAP_OFFSET + Key index (offset /16 bits) pointing for next swap. + 16 + 9 + read-write + + + B_0x00 + means that no OBK is copied from current to alternate OBK sector during SWAP operation. + 0x00 + + + B_0x1FF + means that all OBK data (511) are copied + 0x1FF + + + + + + + FLASH_SECOBKCFGR + FLASH_SECOBKCFGR + FLASH secure OBK configuration register + 0x044 + 0x20 + read-write + 0x01FF0000 + 0xFFFFFFFF + + + LOCK + OBKCFGR lock option configuration bit + + 0 + 1 + read-write + + + B_0x0 + FLASH_OBKCFGR register unlocked + 0x0 + + + B_0x1 + FLASH_OBKCFGR register locked + 0x1 + + + + + SWAP_SECT_REQ + OBK swap sector request bit + + 1 + 1 + read-write + + + B_0x0 + no swap requested + 0x0 + + + B_0x1 + launch the sector swap + 0x1 + + + + + ALT_SECT + alternate sector bit + + 2 + 1 + read-write + + + B_0x0 + current OBK sector is mapped to OBK address range for access + 0x0 + + + B_0x1 + alternate OBK sector is mapped to OBK address range for access + 0x1 + + + + + ALT_SECT_ERASE + alternate sector erase bit + + 3 + 1 + read-write + + + B_0x0 + do not touch OBK sector + 0x0 + + + B_0x1 + erase the alternate OBK sector + 0x1 + + + + + SWAP_OFFSET + key index (offset /16 bits) pointing for next swap. + 16 + 9 + read-write + + + B_0x0 + no OBK is copied from current to alternate OBK sector during SWAP operation. + 0x0 + + + B_0x1 + only the first OBK data (128 bits) are copied from current to alternate OBK sector + 0x1 + + + B_0x2 + the two first OBK data are copied + 0x2 + + + B_0x1FF + the 511 first OBK data are copied + 0x1FF + + + + + + + FLASH_HDPEXTR + FLASH_HDPEXTR + FLASH HDP extension register + 0x048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HDP1_EXT + HDP area extension in 8 Kbytes sectors in Bank1. + 0 + 7 + read-write + + + HDP2_EXT + HDP area extension in 8 Kbytes sectors in Bank2. + 16 + 7 + read-write + + + + + FLASH_OPTSR_CUR + FLASH_OPTSR_CUR + FLASH option status register + 0x050 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + BOR_LEV + Brownout level option status bit + + 0 + 2 + read-only + + + B_0x1 + BOR Level 2, the threshold level is medium (around 2. + 0x1 + + + B_0x2 + BOR Level 3, the threshold level is high (around 2. + 0x2 + + + + + BORH_EN + Brownout high enable + 2 + 1 + read-only + + + B_0x0 + disable + 0x0 + + + B_0x1 + enable + 0x1 + + + + + IWDG_SW + IWDG control mode option status bit + 3 + 1 + read-only + + + B_0x0 + IWDG watchdog is controlled by hardware + 0x0 + + + B_0x1 + IWDG watchdog is controlled by software + 0x1 + + + + + WWDG_SW + WWDG control mode option status bit + 4 + 1 + read-only + + + B_0x0 + WWDG watchdog is controlled by hardware + 0x0 + + + B_0x1 + WWDG watchdog is controlled by software + 0x1 + + + + + NRST_STOP + Core domain Stop entry reset option status bit + 6 + 1 + read-only + + + B_0x0 + a reset is generated when entering Stop mode on core domain + 0x0 + + + B_0x1 + no reset generated when entering Stop mode on core domain. + 0x1 + + + + + NRST_STDBY + Core domain Standby entry reset option status bit + 7 + 1 + read-only + + + B_0x0 + a reset is generated when entering Standby mode on core domain + 0x0 + + + B_0x1 + no reset generated when entering Standby mode on core domain. + 0x1 + + + + + PRODUCT_STATE + Life state code (based on Hamming 8,4). + 8 + 8 + read-only + + + IO_VDD_HSLV + High-speed IO at low Vless thansub>DDless than/sub> voltage configuration bit. + 16 + 1 + read-only + + + B_0x0 + High-speed IO at low Vless thansub>DDless than/sub> voltage feature disabled (Vless thansub>DDless than/sub> can exceed 2. + 0x0 + + + B_0x1 + High-speed IO at low Vless thansub>DDless than/sub> voltage feature enabled (Vless thansub>DDless than/sub> remains below 2. + 0x1 + + + + + IO_VDDIO2_HSLV + High-speed IO at low Vless thansub>DDIO2less than/sub> voltage configuration bit. + 17 + 1 + read-only + + + B_0x0 + High-speed IO at low Vless thansub>DDIO2less than/sub> voltage feature disabled (Vless thansub>DDIO2less than/sub> can exceed 2. + 0x0 + + + B_0x1 + High-speed IO at low Vless thansub>DDIO2less than/sub> voltage feature enabled (Vless thansub>DDIO2less than/sub> remains below 2. + 0x1 + + + + + IWDG_STOP + IWDG Stop mode freeze option status bit + + 20 + 1 + read-only + + + B_0x0 + Independent watchdog frozen in system Stop mode + 0x0 + + + B_0x1 + Independent watchdog keep running in system Stop mode. + 0x1 + + + + + IWDG_STDBY + IWDG Standby mode freeze option status bit + + 21 + 1 + read-only + + + B_0x0 + Independent watchdog frozen in Standby mode + 0x0 + + + B_0x1 + Independent watchdog keep running in Standby mode. + 0x1 + + + + + BOOT_UBE + Available only on cryptography enabled devices. + 22 + 8 + read-only + + + B_0xC3 + ST-iRoT (system flash) selected + 0xC3 + + + B_0xB4 + OEM-iRoT (user flash) selected. + 0xB4 + + + + + SWAP_BANK + Bank swapping option status bit + + 31 + 1 + read-only + + + B_0x0 + Bank1 and Bank2 not swapped + 0x0 + + + B_0x1 + Bank1 and Bank2 swapped + 0x1 + + + + + + + FLASH_OPTSR_PRG + FLASH_OPTSR_PRG + FLASH option status register + 0x054 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + BOR_LEV + Brownout level option configuration bit + + 0 + 2 + read-write + + + B_0x1 + BOR Level 2, the threshold level is medium (around 2. + 0x1 + + + B_0x2 + BOR Level 3, the threshold level is high (around 2. + 0x2 + + + + + BORH_EN + Brownout high enable configuration bit + 2 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + IWDG_SW + IWDG control mode option configuration bit + 3 + 1 + read-write + + + B_0x0 + IWDG watchdog is controlled by hardware + 0x0 + + + B_0x1 + IWDG watchdog is controlled by software + 0x1 + + + + + WWDG_SW + WWDG control mode option configuration bit + 4 + 1 + read-write + + + B_0x0 + WWDG watchdog is controlled by hardware + 0x0 + + + B_0x1 + WWDG watchdog is controlled by software + 0x1 + + + + + NRST_STOP + Core domain Stop entry reset option configuration bit + 6 + 1 + read-write + + + B_0x0 + a reset is generated when entering Stop mode on core domain + 0x0 + + + B_0x1 + no reset generated when entering Stop mode on core domain. + 0x1 + + + + + NRST_STDBY + Core domain Standby entry reset option configuration bit + 7 + 1 + read-write + + + B_0x0 + a reset is generated when entering Standby mode on core domain + 0x0 + + + B_0x1 + no reset generated when entering Standby mode on core domain. + 0x1 + + + + + PRODUCT_STATE + Life state code (based on Hamming 8,4). + 8 + 8 + read-write + + + IO_VDD_HSLV + High-speed IO at low VDD voltage configuration bit. + 16 + 1 + read-write + + + B_0x0 + High-speed IO at low Vless thansub>DDless than/sub> voltage feature disabled (Vless thansub>DDless than/sub> can exceed 2. + 0x0 + + + B_0x1 + High-speed IO at low Vless thansub>DDless than/sub> voltage feature enabled (Vless thansub>DDless than/sub> remains below 2. + 0x1 + + + + + IO_VDDIO2_HSLV + High-speed IO at low Vless thansub>DDIO2less than/sub> voltage configuration bit. + 17 + 1 + read-write + + + B_0x0 + High-speed IO at low Vless thansub>DDIO2less than/sub> voltage feature disabled (Vless thansub>DDIO2less than/sub> can exceed 2. + 0x0 + + + B_0x1 + High-speed IO at low Vless thansub>DDIO2less than/sub> voltage feature enabled (Vless thansub>DDIO2less than/sub> remains below 2. + 0x1 + + + + + IWDG_STOP + IWDG Stop mode freeze option status bit + + 20 + 1 + read-write + + + B_0x0 + Independent watchdog frozen in system Stop mode + 0x0 + + + B_0x1 + Independent watchdog keep running in system Stop mode. + 0x1 + + + + + IWDG_STDBY + IWDG Standby mode freeze option status bit + + 21 + 1 + read-write + + + B_0x0 + Independent watchdog frozen in Standby mode + 0x0 + + + B_0x1 + Independent watchdog keep running in Standby mode. + 0x1 + + + + + BOOT_UBE + Available only on cryptography enabled devices. + 22 + 8 + read-write + + + B_0xC3 + ST-iRoT (system flash) selected + 0xC3 + + + B_0xB4 + OEM-iRoT (user flash) selected. + 0xB4 + + + + + SWAP_BANK + Bank swapping option configuration bit + + 31 + 1 + read-write + + + B_0x0 + Bank1 and Bank2 not swapped + 0x0 + + + B_0x1 + Bank1 and Bank2 swapped + 0x1 + + + + + + + FLASH_NSEPOCHR_CUR + FLASH_NSEPOCHR_CUR + FLASH non-secure EPOCH register + 0x060 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + NS_EPOCH + Non-volatile non-secure EPOCH counter + 0 + 24 + read-only + + + + + FLASH_SECEPOCHR_CUR + FLASH_SECEPOCHR_CUR + FLASH secure EPOCH register + 0x068 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + SEC_EPOCH + Non-volatile secure EPOCH counter + 0 + 24 + read-only + + + + + FLASH_OPTSR2_CUR + FLASH_OPTSR2_CUR + FLASH option status register 2 + 0x070 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + SRAM13_RST + SRAM1 and SRAM3 erase upon system reset + 2 + 1 + read-only + + + B_0x0 + SRAM1 and SRAM3 erased when a system reset occurs + 0x0 + + + B_0x1 + SRAM1 and SRAM3 not erased when a system reset occurs + 0x1 + + + + + SRAM2_RST + SRAM2 erase when system reset + 3 + 1 + read-only + + + B_0x0 + SRAM2 erased when a system reset occurs + 0x0 + + + B_0x1 + SRAM2 not erased when a system reset occurs. + 0x1 + + + + + BKPRAM_ECC + Backup RAM ECC detection and correction disable + 4 + 1 + read-only + + + B_0x0 + BKPRAM ECC check enabled + 0x0 + + + B_0x1 + BKPRAM ECC check disabled + 0x1 + + + + + SRAM3_ECC + SRAM3 ECC detection and correction disable + 5 + 1 + read-only + + + B_0x0 + SRAM3 ECC check enabled + 0x0 + + + B_0x1 + SRAM3 ECC check disabled + 0x1 + + + + + SRAM2_ECC + SRAM2 ECC detection and correction disable + 6 + 1 + read-only + + + B_0x0 + SRAM2 ECC check enabled + 0x0 + + + B_0x1 + SRAM2 ECC check disabled + 0x1 + + + + + USBPD_DIS + USB power delivery configuration option bit + 8 + 1 + read-only + + + B_0x0 + Enabled + 0x0 + + + B_0x1 + Disabled + 0x1 + + + + + TZEN + TrustZone enable configuration bits + + 24 + 8 + read-only + + + B_0xC3 + TrustZone disabled + 0xC3 + + + B_0xB4 + TrustZone enabled. + 0xB4 + + + + + + + FLASH_OPTSR2_PRG + FLASH_OPTSR2_PRG + FLASH option status register 2 + 0x074 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + SRAM1_3_RST + SRAM1 and SRAM3 erase upon system reset + + 2 + 1 + read-write + + + B_0x0 + SRAM1 and SRAM3 erased when a system reset occurs + 0x0 + + + B_0x1 + SRAM1 and SRAM3 not erased when a system reset occurs + 0x1 + + + + + SRAM2_RST + SRAM2 erase when system reset + + 3 + 1 + read-write + + + B_0x0 + SRAM2 erased when a system reset occurs + 0x0 + + + B_0x1 + SRAM2 not erased when a system reset occurs. + 0x1 + + + + + BKPRAM_ECC + Backup RAM ECC detection and correction disable + 4 + 1 + read-write + + + B_0x0 + BKPRAM ECC check enabled + 0x0 + + + B_0x1 + BKPRAM ECC check disabled + 0x1 + + + + + SRAM3_ECC + SRAM3 ECC detection and correction disable + 5 + 1 + read-write + + + B_0x0 + SRAM3 ECC check enabled + 0x0 + + + B_0x1 + SRAM3 ECC check disabled + 0x1 + + + + + SRAM2_ECC + SRAM2 ECC detection and correction disable + 6 + 1 + read-write + + + B_0x0 + SRAM2 ECC check enabled + 0x0 + + + B_0x1 + SRAM2 ECC check disabled + 0x1 + + + + + USBPD_DIS + USB power delivery configuration option bit + 8 + 1 + read-write + + + B_0x0 + Enabled + 0x0 + + + B_0x1 + Disabled + 0x1 + + + + + TZEN + TrustZone enable configuration bits + + 24 + 8 + read-write + + + B_0xC3 + TrustZone disabled + 0xC3 + + + B_0xB4 + TrustZone enabled + 0xB4 + + + + + + + FLASH_NSBOOTR_CUR + FLASH_NSBOOTR_CUR + FLASH non-secure boot register + 0x080 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + NSBOOT_LOCK + Field locking the values of SWAP_BANK, and NSBOOTADD settings. + 0 + 8 + read-only + + + B_0xC3 + SWAP_BANK and NSBOOTADD can still be modified following their individual rules. + 0xC3 + + + B_0xB4 + NSBOOTADD is frozen. + 0xB4 + + + + + NSBOOTADD + Non secure unique boot entry address + + 8 + 24 + read-only + + + + + FLASH_NSBOOTR_PRG + FLASH_NSBOOTR_PRG + FLASH non-secure boot register + 0x084 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + NSBOOT_LOCK + Field locking the values of SWAP_ BANK, and NSBOOTADD settings. + 0 + 8 + read-write + + + B_0xC3 + SWAP_ BANK and NSBOOTADD can still be modified following their individual rules. + 0xC3 + + + B_0xB4 + NSBOOTADD is frozen. + 0xB4 + + + + + NSBOOTADD + Non secure unique boot entry address + + 8 + 24 + read-write + + + + + FLASH_SECBOOTR_CUR + FLASH_SECBOOTR_CUR + FLASH secure boot register + 0x088 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + SECBOOT_LOCK + Field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. + 0 + 8 + read-only + + + B_0xC3 + BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. + 0xC3 + + + B_0xB4 + BOOT_UBE and SECBOOTADD are frozen. + 0xB4 + + + + + SECBOOTADD + Unique boot entry secure address + + 8 + 24 + read-only + + + + + FLASH_BOOTR_PRG + FLASH_BOOTR_PRG + FLASH secure boot register + 0x08C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + SECBOOT_LOCK + Field locking the values of UBE, SWAP_ BANK, and SECBOOTADD setting. + 0 + 8 + read-write + + + B_0xC3 + BOOT_UBE, SWAP_ BANK and SECBOOTADD can still be modified following their individual rules. + 0xC3 + + + B_0xB4 + BOOT_UBE and SECBOOTADD are frozen. + 0xB4 + + + + + SECBOOTADD + Secure unique boot entry address. + 8 + 24 + read-write + + + + + FLASH_OTPBLR_CUR + FLASH_OTPBLR_CUR + FLASH non-secure OTP block lock + 0x090 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + LOCKBL + OTP block lock + + 0 + 32 + read-only + + + + + FLASH_OTPBLR_PRG + FLASH_OTPBLR_PRG + FLASH non-secure OTP block lock + 0x094 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + LOCKBL + OTP block lock + + 0 + 32 + read-write + + + + + FLASH_SECBB1R1 + FLASH_SECBB1R1 + FLASH secure block based register for Bank1 + 0xA0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB1 + Secure/non-secure 8 Kbytes flash Bank1 sector attributes + 0 + 32 + read-write + + + B_0x0 + sector (32 * (x-1) + y) in Bank1 is non secure. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is secure. + 0x1 + + + + + + + FLASH_SECBB1R2 + FLASH_SECBB1R2 + FLASH secure block based register for Bank1 + 0xA4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB1 + Secure/non-secure 8 Kbytes flash Bank1 sector attributes + 0 + 32 + read-write + + + B_0x0 + sector (32 * (x-1) + y) in Bank1 is non secure. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is secure. + 0x1 + + + + + + + FLASH_SECBB1R3 + FLASH_SECBB1R3 + FLASH secure block based register for Bank1 + 0xA8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB1 + Secure/non-secure 8 Kbytes flash Bank1 sector attributes + 0 + 32 + read-write + + + B_0x0 + sector (32 * (x-1) + y) in Bank1 is non secure. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is secure. + 0x1 + + + + + + + FLASH_SECBB1R4 + FLASH_SECBB1R4 + FLASH secure block based register for Bank1 + 0xAC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB1 + Secure/non-secure 8 Kbytes flash Bank1 sector attributes + 0 + 32 + read-write + + + B_0x0 + sector (32 * (x-1) + y) in Bank1 is non secure. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is secure. + 0x1 + + + + + + + FLASH_PRIVBB1R1 + FLASH_PRIVBB1R1 + FLASH privilege block based register for Bank1 + 0xC0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB1 + Privileged/unprivileged 8-Kbyte flash Bank1 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank1 is unprivileged. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is privileged. + 0x1 + + + + + + + FLASH_PRIVBB1R2 + FLASH_PRIVBB1R2 + FLASH privilege block based register for Bank1 + 0xC4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB1 + Privileged/unprivileged 8-Kbyte flash Bank1 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank1 is unprivileged. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is privileged. + 0x1 + + + + + + + FLASH_PRIVBB1R3 + FLASH_PRIVBB1R3 + FLASH privilege block based register for Bank1 + 0xC8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB1 + Privileged/unprivileged 8-Kbyte flash Bank1 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank1 is unprivileged. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is privileged. + 0x1 + + + + + + + FLASH_PRIVBB1R4 + FLASH_PRIVBB1R4 + FLASH privilege block based register for Bank1 + 0xCC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB1 + Privileged/unprivileged 8-Kbyte flash Bank1 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank1 is unprivileged. + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank1 is privileged. + 0x1 + + + + + + + FLASH_SECWM1R_CUR + FLASH_SECWM1R_CUR + FLASH security watermark for Bank1 + 0x0E0 + 0x20 + read-only + 0x00000000 + 0xFF00FF00 + + + SECWM1_STRT + Bank1 security WM area 1 start sector + + 0 + 7 + read-only + + + SECWM1_END + Bank1 security WM area 1 end sector + + 16 + 7 + read-only + + + + + FLASH_SECWM1R_PRG + FLASH_SECWM1R_PRG + FLASH security watermark for Bank1 + 0x0E4 + 0x20 + read-write + 0x00000000 + 0xFF00FF00 + + + SECWM1_STRT + Bank1 security WM area 1 start sector + + 0 + 7 + read-write + + + SECWM1_END + Bank1 security WM area 1 end sector + + 16 + 7 + read-write + + + + + FLASH_WRP1R_CUR + FLASH_WRP1R_CUR + FLASH write sector group protection for Bank1 + 0x0E8 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + WRPSG1 + Bank1 sector group protection option status byte + + 0 + 32 + read-only + + + + + FLASH_WRP1R_PRG + FLASH_WRP1R_PRG + FLASH write sector group protection for Bank1 + 0x0EC + 0x20 + read-write + 0x00000000 + 0x00000000 + + + WRPSG1 + Bank1 sector group protection option status byte + + 0 + 32 + read-write + + + + + FLASH_EDATA1R_CUR + FLASH_EDATA1R_CUR + FLASH data sector configuration Bank1 + 0x0F0 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + EDATA1_STRT + EDATA1_STRT contains the start sectors of the flash high-cycle data area in Bank1 There is no hardware effect to those bits. + 0 + 3 + read-only + + + B_0x0 + The last sector of Bank1 is reserved for flash high-cycle data + 0x0 + + + B_0x1 + The two last sectors of Bank1 are reserved for flash high-cycle data + 0x1 + + + B_0x2 + The three last sectors of Bank1 are reserved for flash high-cycle data + 0x2 + + + B_0x7 + The eight last sectors of Bank1 are reserved for flash high-cycle data + 0x7 + + + + + EDATA1_EN + Bank1 flash high-cycle data enable + 15 + 1 + read-only + + + B_0x0 + No flash high-cycle data area + 0x0 + + + B_0x1 + Flash high-cycle data is used + 0x1 + + + + + + + FLASH_EDATA1R_PRG + FLASH_EDATA1R_PRG + FLASH data sector configuration Bank1 + 0xF4 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + EDATA1_STRT + EDATA1_STRT contains the start sectors of the flash high-cycle data area in Bank1 There is no hardware effect to those bits. + 0 + 3 + read-write + + + B_0x0 + The last sector of Bank1 is reserved for flash high-cycle data + 0x0 + + + B_0x1 + The two last sectors of Bank1 are reserved for flash high-cycle data + 0x1 + + + B_0x2 + The three last sectors of Bank1 are reserved for flash high-cycle data + 0x2 + + + + + EDATA1_EN + Bank1 flash high-cycle data enable + 15 + 1 + read-write + + + B_0x0 + No flash high-cycle data area + 0x0 + + + B_0x1 + Flash high-cycle data is used + 0x1 + + + + + + + FLASH_HDP1R_CUR + FLASH_HDP1R_CUR + FLASH HDP Bank1 configuration + 0x0F8 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + HDP1_STRT + HDPL barrier start set in number of 8-Kbyte sectors + + 0 + 7 + read-only + + + HDP1_END + HDPL barrier end set in number of 8-Kbyte sectors + + 16 + 7 + read-only + + + + + FLASH_HDP1R_PRG + FLASH_HDP1R_PRG + FLASH HDP Bank1 configuration + 0x0FC + 0x20 + read-write + 0x00000000 + 0x00000000 + + + HDP1_STRT + HDPL barrier start set in number of 8-Kbyte sectors + + 0 + 7 + read-write + + + HDP1_END + HDPL barrier end set in number of 8-Kbyte sectors + + 16 + 7 + read-write + + + + + FLASH_ECCCORR + FLASH_ECCCORR + FLASH ECC correction register + 0x100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADDR_ECC + ECC error address + + 0 + 16 + read-only + + + OBK_ECC + Single ECC error corrected in flash OB Keys storage area. + 20 + 1 + read-only + + + EDATA_ECC + ECC fail for corrected ECC error in flash high-cycle data area + + 21 + 1 + read-only + + + BK_ECC + ECC fail bank for corrected ECC error + + 22 + 1 + read-only + + + SYSF_ECC + ECC fail for corrected ECC error in system flash memory + + 23 + 1 + read-only + + + OTP_ECC + OTP ECC error bit + + 24 + 1 + read-only + + + ECCCIE + ECC single correction error interrupt enable bit + + 25 + 1 + read-write + + + B_0x0 + no interrupt generated when an ECC single correction error occurs + 0x0 + + + B_0x1 + non-secure interrupt generated when an ECC single correction error occurs + 0x1 + + + + + ECCC + ECC correction set by hardware when single ECC error has been detected and corrected. + 30 + 1 + read-write + + + + + FLASH_ECCDETR + FLASH_ECCDETR + FLASH ECC detection register + 0x104 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADDR_ECC + ECC error address + + 0 + 16 + read-only + + + OBK_ECC + ECC fail double ECC error in flash OB Keys storage area. + 20 + 1 + read-only + + + EDATA_ECC + ECC fail double ECC error in flash high-cycle data area + + 21 + 1 + read-only + + + BK_ECC + ECC fail bank for double ECC error + + 22 + 1 + read-only + + + SYSF_ECC + ECC fail for double ECC error in system flash memory + + 23 + 1 + read-only + + + OTP_ECC + OTP ECC error bit + + 24 + 1 + read-only + + + ECCD + ECC detection + + 31 + 1 + read-write + + + + + FLASH_ECCDR + FLASH_ECCDR + FLASH ECC data + 0x108 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DATA_ECC + ECC error data + + 0 + 16 + read-only + + + + + FLASH_SECBB2R1 + FLASH_SECBB2R1 + FLASH secure block-based register for Bank2 + 0x1A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB2 + Secure/non-secure flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is non secure + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is secure + 0x1 + + + + + + + FLASH_SECBB2R2 + FLASH_SECBB2R2 + FLASH secure block-based register for Bank2 + 0x1A4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB2 + Secure/non-secure flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is non secure + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is secure + 0x1 + + + + + + + FLASH_SECBB2R3 + FLASH_SECBB2R3 + FLASH secure block-based register for Bank2 + 0x1A8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB2 + Secure/non-secure flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is non secure + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is secure + 0x1 + + + + + + + FLASH_SECBB2R4 + FLASH_SECBB2R4 + FLASH secure block-based register for Bank2 + 0x1AC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SECBB2 + Secure/non-secure flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is non secure + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is secure + 0x1 + + + + + + + FLASH_PRIVBB2R1 + FLASH_PRIVBB2R1 + FLASH privilege block-based register for Bank2 + 0x1C0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB2 + Privileged / non-privileged 8-Kbyte flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is unprivileged + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is privileged + 0x1 + + + + + + + FLASH_PRIVBB2R2 + FLASH_PRIVBB2R2 + FLASH privilege block-based register for Bank2 + 0x1C4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB2 + Privileged / non-privileged 8-Kbyte flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is unprivileged + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is privileged + 0x1 + + + + + + + FLASH_PRIVBB2R3 + FLASH_PRIVBB2R3 + FLASH privilege block-based register for Bank2 + 0x1C8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB2 + Privileged / non-privileged 8-Kbyte flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is unprivileged + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is privileged + 0x1 + + + + + + + FLASH_PRIVBB2R4 + FLASH_PRIVBB2R4 + FLASH privilege block-based register for Bank2 + 0x1CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIVBB2 + Privileged / non-privileged 8-Kbyte flash Bank2 sector attribute + 0 + 32 + read-write + + + B_0x0 + sectors (32 * (x-1) + y) in Bank2 is unprivileged + 0x0 + + + B_0x1 + sector (32 * (x-1) + y) in Bank2 is privileged + 0x1 + + + + + + + FLASH_SECWM2R_CUR + FLASH_SECWM2R_CUR + FLASH security watermark for Bank2 + 0x1E0 + 0x20 + read-only + 0x00000000 + 0xFF00FF00 + + + SECWM2_STRT + Bank2 security WM area start sector + + 0 + 7 + read-only + + + SECWM2_END + Bank2 security WM end sector + + 16 + 7 + read-only + + + + + FLASH_SECWM2R_PRG + FLASH_SECWM2R_PRG + FLASH security watermark for Bank2 + 0x1E4 + 0x20 + read-write + 0x00000000 + 0xFF00FF00 + + + SECWM2_STRT + Bank2 security WM area start sector + + 0 + 7 + read-write + + + SECWM2_END + Bank2 security WM area end sector + + 16 + 7 + read-write + + + + + FLASH_WRP2R_CUR + FLASH_WRP2R_CUR + FLASH write sector group protection for Bank2 + 0x1E8 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + WRPSG2 + Bank2 sector group protection option status byte + + 0 + 32 + read-only + + + + + FLASH_WRP2R_PRG + FLASH_WRP2R_PRG + FLASH write sector group protection for Bank2 + 0x1EC + 0x20 + read-write + 0x00000000 + 0x00000000 + + + WRPSG2 + Bank2 sector group protection option status byte + + 0 + 32 + read-write + + + + + FLASH_EDATA2R_CUR + FLASH_EDATA2R_CUR + FLASH data sectors configuration Bank2 + 0x1F0 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + EDATA2_STRT + EDATA2_STRT contains the start sectors of the flash high-cycle data area in Bank2 There is no hardware effect to those bits. + 0 + 3 + read-only + + + B_0x0 + The last sector of Bank2 is reserved for flash high-cycle data + 0x0 + + + B_0x1 + The two last sectors of Bank2 are reserved for flash high-cycle data + 0x1 + + + B_0x2 + The three last sectors of Bank2 are reserved for flash high-cycle data + 0x2 + + + + + EDATA2_EN + Bank2 flash high-cycle data enable + 15 + 1 + read-only + + + B_0x0 + No flash high-cycle data area + 0x0 + + + B_0x1 + Flash high-cycle data is used + 0x1 + + + + + + + FLASH_EDATA2R_PRG + FLASH_EDATA2R_PRG + FLASH data sector configuration Bank2 + 0x1F4 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + EDATA2_STRT + EDATA2_STRT contains the start sectors of the flash high-cycle data area in Bank2 There is no hardware effect to those bits. + 0 + 3 + read-write + + + B_0x0 + The last sector of Bank2 is reserved for flash high-cycle data. + 0x0 + + + B_0x1 + The two last sectors of Bank2 are reserved for flash high-cycle data. + 0x1 + + + B_0x2 + The three last sectors of Bank2 are reserved for flash high-cycle data. + 0x2 + + + + + EDATA2_EN + Bank2 flash high-cycle data enable + 15 + 1 + read-write + + + B_0x0 + No flash high-cycle data area + 0x0 + + + B_0x1 + Flash high-cycle data is used + 0x1 + + + + + + + FLASH_HDP2R_CUR + FLASH_HDP2R_CUR + FLASH HDP Bank2 configuration + 0x1F8 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + HDP2_STRT + HDPL barrier start set in number of 8-Kbyte sectors + + 0 + 7 + read-only + + + HDP2_END + HDPL barrier end set in number of 8-Kbyte sectors + + 16 + 7 + read-only + + + + + FLASH_HDP2R_PRG + FLASH_HDP2R_PRG + FLASH HDP Bank2 configuration + 0x1FC + 0x20 + read-write + 0x00000000 + 0x00000000 + + + HDP2_STRT + HDPL barrier start set in number of 8-Kbyte sectors + + 0 + 7 + read-write + + + HDP2_END + HDPL barrier end set in number of 8-Kbyte sectors + + 16 + 7 + read-write + + + + + + + FLASH_S + 0x50022000 + + FLASH_S + Flash secure global interrupt + 7 + + + + FMC + FMC address block description + FMC + 0x47000400 + + 0x0 + 0x15C + registers + + + FMC + FMC global interrupt + 77 + + + + FMC_BCR1 + FMC_BCR1 + SRAM/NOR-flash chip-select control register for bank 1 + 0x0 + 0x20 + read-write + 0x000030DB + 0xFFFFFFFF + + + MBKEN + Memory bank enable bit + + 0 + 1 + read-write + + + B_0x0 + Corresponding memory bank is disabled. + 0x0 + + + B_0x1 + Corresponding memory bank is enabled. + 0x1 + + + + + MUXEN + Address/data multiplexing enable bit + + 1 + 1 + read-write + + + B_0x0 + Address/data non multiplexed + 0x0 + + + B_0x1 + Address/data multiplexed on databus (default after reset) + 0x1 + + + + + MTYP + Memory type + + 2 + 2 + read-write + + + B_0x0 + SRAM/FRAM (default after reset for Bank 2. + 0x0 + + + B_0x1 + PSRAM (CRAM) / FRAM + 0x1 + + + B_0x2 + NOR flash/OneNAND flash (default after reset for Bank 1) + 0x2 + + + + + MWID + Memory data bus width + + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits (default after reset) + 0x1 + + + + + FACCEN + Flash access enable + + 6 + 1 + read-write + + + B_0x0 + Corresponding NOR flash memory access is disabled. + 0x0 + + + B_0x1 + Corresponding NOR flash memory access is enabled (default after reset). + 0x1 + + + + + BURSTEN + Burst enable bit + + 8 + 1 + read-write + + + B_0x0 + Burst mode disabled (default after reset). + 0x0 + + + B_0x1 + Burst mode enable. + 0x1 + + + + + WAITPOL + Wait signal polarity bit + + 9 + 1 + read-write + + + B_0x0 + NWAIT active low (default after reset) + 0x0 + + + B_0x1 + NWAIT active high + 0x1 + + + + + WAITCFG + Wait timing configuration + + 11 + 1 + read-write + + + B_0x0 + NWAIT signal is active one data cycle before wait state (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is active during wait state (not used for PSRAM). + 0x1 + + + + + WREN + Write enable bit + + 12 + 1 + read-write + + + B_0x0 + Write operations are disabled in the bank by the FMC, an AHB error is reported. + 0x0 + + + B_0x1 + Write operations are enabled for the bank by the FMC (default after reset). + 0x1 + + + + + WAITEN + Wait enable bit + + 13 + 1 + read-write + + + B_0x0 + NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period). + 0x0 + + + B_0x1 + NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset). + 0x1 + + + + + EXTMOD + Extended mode enable + + 14 + 1 + read-write + + + B_0x0 + values inside FMC_BWTR register are not taken into account (default after reset) + 0x0 + + + B_0x1 + values inside FMC_BWTR register are taken into account + 0x1 + + + + + ASYNCWAIT + Wait signal during asynchronous transfers + + 15 + 1 + read-write + + + B_0x0 + NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is taken in to account when running an asynchronous protocol. + 0x1 + + + + + CPSIZE + CRAM page size + + 16 + 3 + read-write + + + B_0x0 + No burst split when crossing page boundary (default after reset) + 0x0 + + + B_0x1 + 128 bytes + 0x1 + + + B_0x2 + 256 bytes + 0x2 + + + B_0x3 + 512 bytes + 0x3 + + + B_0x4 + 1024 bytes + 0x4 + + + + + CBURSTRW + Write burst enable + + 19 + 1 + read-write + + + B_0x0 + Write operations are always performed in Asynchronous mode. + 0x0 + + + B_0x1 + Write operations are performed in Synchronous mode. + 0x1 + + + + + CCLKEN + Continuous clock enable + + 20 + 1 + read-write + + + B_0x0 + The FMC_CLK is only generated during the synchronous memory access (read/write transaction). + 0x0 + + + B_0x1 + The FMC_CLK is generated continuously during asynchronous and synchronous access. + 0x1 + + + + + WFDIS + Write FIFO disable + + 21 + 1 + read-write + + + B_0x0 + Write FIFO enabled (Default after reset) + 0x0 + + + B_0x1 + Write FIFO disabled + 0x1 + + + + + NBLSET + Byte lane (NBL) setup + + 22 + 2 + read-write + + + B_0x0 + NBL setup time is 0 AHB clock cycle + 0x0 + + + B_0x1 + NBL setup time is 1 AHB clock cycle + 0x1 + + + B_0x2 + NBL setup time is 2 AHB clock cycles + 0x2 + + + B_0x3 + NBL setup time is 3 AHB clock cycles + 0x3 + + + + + FMCEN + FMC controller enable + + 31 + 1 + read-write + + + B_0x0 + Disable the FMC controller + 0x0 + + + B_0x1 + Enable the FMC controller + 0x1 + + + + + + + FMC_BTR1 + FMC_BTR1 + SRAM/NOR-flash chip-select timing register for bank 1 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration + + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration + + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration =1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration + + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + + 20 + 4 + read-write + + + B_0x0 + FMC_CLK period= 1x HCLK period + 0x0 + + + B_0x1 + FMC_CLK period = 2 HCLK periods + 0x1 + + + B_0x2 + FMC_CLK period = 3 HCLK periods + 0x2 + + + B_0xF + FMC_CLK period = 16 HCLK periods (default value after reset) + 0xF + + + + + DATLAT + (see note below bit descriptions): Data latency for synchronous memory + + 24 + 4 + read-write + + + B_0x0 + Data latency of 2 CLK clock cycles for first burst access + 0x0 + + + B_0xF + Data latency of 17 CLK clock cycles for first burst access (default value after reset) + 0xF + + + + + ACCMOD + Access mode + + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_BCR2 + FMC_BCR2 + SRAM/NOR-flash chip-select control register for bank 2 + 0x8 + 0x20 + read-write + 0x000030D2 + 0xFFFFFFFF + + + MBKEN + Memory bank enable bit + + 0 + 1 + read-write + + + B_0x0 + Corresponding memory bank is disabled. + 0x0 + + + B_0x1 + Corresponding memory bank is enabled. + 0x1 + + + + + MUXEN + Address/data multiplexing enable bit + + 1 + 1 + read-write + + + B_0x0 + Address/data non multiplexed + 0x0 + + + B_0x1 + Address/data multiplexed on databus (default after reset) + 0x1 + + + + + MTYP + Memory type + + 2 + 2 + read-write + + + B_0x0 + SRAM/FRAM (default after reset for Bank 2. + 0x0 + + + B_0x1 + PSRAM (CRAM) / FRAM + 0x1 + + + B_0x2 + NOR flash/OneNAND flash (default after reset for Bank 1) + 0x2 + + + + + MWID + Memory data bus width + + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits (default after reset) + 0x1 + + + + + FACCEN + Flash access enable + + 6 + 1 + read-write + + + B_0x0 + Corresponding NOR flash memory access is disabled. + 0x0 + + + B_0x1 + Corresponding NOR flash memory access is enabled (default after reset). + 0x1 + + + + + BURSTEN + Burst enable bit + + 8 + 1 + read-write + + + B_0x0 + Burst mode disabled (default after reset). + 0x0 + + + B_0x1 + Burst mode enable. + 0x1 + + + + + WAITPOL + Wait signal polarity bit + + 9 + 1 + read-write + + + B_0x0 + NWAIT active low (default after reset) + 0x0 + + + B_0x1 + NWAIT active high + 0x1 + + + + + WAITCFG + Wait timing configuration + + 11 + 1 + read-write + + + B_0x0 + NWAIT signal is active one data cycle before wait state (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is active during wait state (not used for PSRAM). + 0x1 + + + + + WREN + Write enable bit + + 12 + 1 + read-write + + + B_0x0 + Write operations are disabled in the bank by the FMC, an AHB error is reported. + 0x0 + + + B_0x1 + Write operations are enabled for the bank by the FMC (default after reset). + 0x1 + + + + + WAITEN + Wait enable bit + + 13 + 1 + read-write + + + B_0x0 + NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period). + 0x0 + + + B_0x1 + NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset). + 0x1 + + + + + EXTMOD + Extended mode enable + + 14 + 1 + read-write + + + B_0x0 + values inside FMC_BWTR register are not taken into account (default after reset) + 0x0 + + + B_0x1 + values inside FMC_BWTR register are taken into account + 0x1 + + + + + ASYNCWAIT + Wait signal during asynchronous transfers + + 15 + 1 + read-write + + + B_0x0 + NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is taken in to account when running an asynchronous protocol. + 0x1 + + + + + CPSIZE + CRAM page size + + 16 + 3 + read-write + + + B_0x0 + No burst split when crossing page boundary (default after reset) + 0x0 + + + B_0x1 + 128 bytes + 0x1 + + + B_0x2 + 256 bytes + 0x2 + + + B_0x3 + 512 bytes + 0x3 + + + B_0x4 + 1024 bytes + 0x4 + + + + + CBURSTRW + Write burst enable + + 19 + 1 + read-write + + + B_0x0 + Write operations are always performed in Asynchronous mode. + 0x0 + + + B_0x1 + Write operations are performed in Synchronous mode. + 0x1 + + + + + CCLKEN + Continuous clock enable + + 20 + 1 + read-write + + + B_0x0 + The FMC_CLK is only generated during the synchronous memory access (read/write transaction). + 0x0 + + + B_0x1 + The FMC_CLK is generated continuously during asynchronous and synchronous access. + 0x1 + + + + + WFDIS + Write FIFO disable + + 21 + 1 + read-write + + + B_0x0 + Write FIFO enabled (Default after reset) + 0x0 + + + B_0x1 + Write FIFO disabled + 0x1 + + + + + NBLSET + Byte lane (NBL) setup + + 22 + 2 + read-write + + + B_0x0 + NBL setup time is 0 AHB clock cycle + 0x0 + + + B_0x1 + NBL setup time is 1 AHB clock cycle + 0x1 + + + B_0x2 + NBL setup time is 2 AHB clock cycles + 0x2 + + + B_0x3 + NBL setup time is 3 AHB clock cycles + 0x3 + + + + + FMCEN + FMC controller enable + + 31 + 1 + read-write + + + B_0x0 + Disable the FMC controller + 0x0 + + + B_0x1 + Enable the FMC controller + 0x1 + + + + + + + FMC_BTR2 + FMC_BTR2 + SRAM/NOR-flash chip-select timing register for bank 2 + 0xC + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration + + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration + + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration =1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration + + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + + 20 + 4 + read-write + + + B_0x0 + FMC_CLK period= 1x HCLK period + 0x0 + + + B_0x1 + FMC_CLK period = 2 HCLK periods + 0x1 + + + B_0x2 + FMC_CLK period = 3 HCLK periods + 0x2 + + + B_0xF + FMC_CLK period = 16 HCLK periods (default value after reset) + 0xF + + + + + DATLAT + (see note below bit descriptions): Data latency for synchronous memory + + 24 + 4 + read-write + + + B_0x0 + Data latency of 2 CLK clock cycles for first burst access + 0x0 + + + B_0xF + Data latency of 17 CLK clock cycles for first burst access (default value after reset) + 0xF + + + + + ACCMOD + Access mode + + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_BCR3 + FMC_BCR3 + SRAM/NOR-flash chip-select control register for bank 3 + 0x10 + 0x20 + read-write + 0x000030D2 + 0xFFFFFFFF + + + MBKEN + Memory bank enable bit + + 0 + 1 + read-write + + + B_0x0 + Corresponding memory bank is disabled. + 0x0 + + + B_0x1 + Corresponding memory bank is enabled. + 0x1 + + + + + MUXEN + Address/data multiplexing enable bit + + 1 + 1 + read-write + + + B_0x0 + Address/data non multiplexed + 0x0 + + + B_0x1 + Address/data multiplexed on databus (default after reset) + 0x1 + + + + + MTYP + Memory type + + 2 + 2 + read-write + + + B_0x0 + SRAM/FRAM (default after reset for Bank 2. + 0x0 + + + B_0x1 + PSRAM (CRAM) / FRAM + 0x1 + + + B_0x2 + NOR flash/OneNAND flash (default after reset for Bank 1) + 0x2 + + + + + MWID + Memory data bus width + + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits (default after reset) + 0x1 + + + + + FACCEN + Flash access enable + + 6 + 1 + read-write + + + B_0x0 + Corresponding NOR flash memory access is disabled. + 0x0 + + + B_0x1 + Corresponding NOR flash memory access is enabled (default after reset). + 0x1 + + + + + BURSTEN + Burst enable bit + + 8 + 1 + read-write + + + B_0x0 + Burst mode disabled (default after reset). + 0x0 + + + B_0x1 + Burst mode enable. + 0x1 + + + + + WAITPOL + Wait signal polarity bit + + 9 + 1 + read-write + + + B_0x0 + NWAIT active low (default after reset) + 0x0 + + + B_0x1 + NWAIT active high + 0x1 + + + + + WAITCFG + Wait timing configuration + + 11 + 1 + read-write + + + B_0x0 + NWAIT signal is active one data cycle before wait state (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is active during wait state (not used for PSRAM). + 0x1 + + + + + WREN + Write enable bit + + 12 + 1 + read-write + + + B_0x0 + Write operations are disabled in the bank by the FMC, an AHB error is reported. + 0x0 + + + B_0x1 + Write operations are enabled for the bank by the FMC (default after reset). + 0x1 + + + + + WAITEN + Wait enable bit + + 13 + 1 + read-write + + + B_0x0 + NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period). + 0x0 + + + B_0x1 + NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset). + 0x1 + + + + + EXTMOD + Extended mode enable + + 14 + 1 + read-write + + + B_0x0 + values inside FMC_BWTR register are not taken into account (default after reset) + 0x0 + + + B_0x1 + values inside FMC_BWTR register are taken into account + 0x1 + + + + + ASYNCWAIT + Wait signal during asynchronous transfers + + 15 + 1 + read-write + + + B_0x0 + NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is taken in to account when running an asynchronous protocol. + 0x1 + + + + + CPSIZE + CRAM page size + + 16 + 3 + read-write + + + B_0x0 + No burst split when crossing page boundary (default after reset) + 0x0 + + + B_0x1 + 128 bytes + 0x1 + + + B_0x2 + 256 bytes + 0x2 + + + B_0x3 + 512 bytes + 0x3 + + + B_0x4 + 1024 bytes + 0x4 + + + + + CBURSTRW + Write burst enable + + 19 + 1 + read-write + + + B_0x0 + Write operations are always performed in Asynchronous mode. + 0x0 + + + B_0x1 + Write operations are performed in Synchronous mode. + 0x1 + + + + + CCLKEN + Continuous clock enable + + 20 + 1 + read-write + + + B_0x0 + The FMC_CLK is only generated during the synchronous memory access (read/write transaction). + 0x0 + + + B_0x1 + The FMC_CLK is generated continuously during asynchronous and synchronous access. + 0x1 + + + + + WFDIS + Write FIFO disable + + 21 + 1 + read-write + + + B_0x0 + Write FIFO enabled (Default after reset) + 0x0 + + + B_0x1 + Write FIFO disabled + 0x1 + + + + + NBLSET + Byte lane (NBL) setup + + 22 + 2 + read-write + + + B_0x0 + NBL setup time is 0 AHB clock cycle + 0x0 + + + B_0x1 + NBL setup time is 1 AHB clock cycle + 0x1 + + + B_0x2 + NBL setup time is 2 AHB clock cycles + 0x2 + + + B_0x3 + NBL setup time is 3 AHB clock cycles + 0x3 + + + + + FMCEN + FMC controller enable + + 31 + 1 + read-write + + + B_0x0 + Disable the FMC controller + 0x0 + + + B_0x1 + Enable the FMC controller + 0x1 + + + + + + + FMC_BTR3 + FMC_BTR3 + SRAM/NOR-flash chip-select timing register for bank 3 + 0x14 + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration + + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration + + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration =1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration + + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + + 20 + 4 + read-write + + + B_0x0 + FMC_CLK period= 1x HCLK period + 0x0 + + + B_0x1 + FMC_CLK period = 2 HCLK periods + 0x1 + + + B_0x2 + FMC_CLK period = 3 HCLK periods + 0x2 + + + B_0xF + FMC_CLK period = 16 HCLK periods (default value after reset) + 0xF + + + + + DATLAT + (see note below bit descriptions): Data latency for synchronous memory + + 24 + 4 + read-write + + + B_0x0 + Data latency of 2 CLK clock cycles for first burst access + 0x0 + + + B_0xF + Data latency of 17 CLK clock cycles for first burst access (default value after reset) + 0xF + + + + + ACCMOD + Access mode + + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_BCR4 + FMC_BCR4 + SRAM/NOR-flash chip-select control register for bank 4 + 0x18 + 0x20 + read-write + 0x000030D2 + 0xFFFFFFFF + + + MBKEN + Memory bank enable bit + + 0 + 1 + read-write + + + B_0x0 + Corresponding memory bank is disabled. + 0x0 + + + B_0x1 + Corresponding memory bank is enabled. + 0x1 + + + + + MUXEN + Address/data multiplexing enable bit + + 1 + 1 + read-write + + + B_0x0 + Address/data non multiplexed + 0x0 + + + B_0x1 + Address/data multiplexed on databus (default after reset) + 0x1 + + + + + MTYP + Memory type + + 2 + 2 + read-write + + + B_0x0 + SRAM/FRAM (default after reset for Bank 2. + 0x0 + + + B_0x1 + PSRAM (CRAM) / FRAM + 0x1 + + + B_0x2 + NOR flash/OneNAND flash (default after reset for Bank 1) + 0x2 + + + + + MWID + Memory data bus width + + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits (default after reset) + 0x1 + + + + + FACCEN + Flash access enable + + 6 + 1 + read-write + + + B_0x0 + Corresponding NOR flash memory access is disabled. + 0x0 + + + B_0x1 + Corresponding NOR flash memory access is enabled (default after reset). + 0x1 + + + + + BURSTEN + Burst enable bit + + 8 + 1 + read-write + + + B_0x0 + Burst mode disabled (default after reset). + 0x0 + + + B_0x1 + Burst mode enable. + 0x1 + + + + + WAITPOL + Wait signal polarity bit + + 9 + 1 + read-write + + + B_0x0 + NWAIT active low (default after reset) + 0x0 + + + B_0x1 + NWAIT active high + 0x1 + + + + + WAITCFG + Wait timing configuration + + 11 + 1 + read-write + + + B_0x0 + NWAIT signal is active one data cycle before wait state (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is active during wait state (not used for PSRAM). + 0x1 + + + + + WREN + Write enable bit + + 12 + 1 + read-write + + + B_0x0 + Write operations are disabled in the bank by the FMC, an AHB error is reported. + 0x0 + + + B_0x1 + Write operations are enabled for the bank by the FMC (default after reset). + 0x1 + + + + + WAITEN + Wait enable bit + + 13 + 1 + read-write + + + B_0x0 + NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period). + 0x0 + + + B_0x1 + NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset). + 0x1 + + + + + EXTMOD + Extended mode enable + + 14 + 1 + read-write + + + B_0x0 + values inside FMC_BWTR register are not taken into account (default after reset) + 0x0 + + + B_0x1 + values inside FMC_BWTR register are taken into account + 0x1 + + + + + ASYNCWAIT + Wait signal during asynchronous transfers + + 15 + 1 + read-write + + + B_0x0 + NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset). + 0x0 + + + B_0x1 + NWAIT signal is taken in to account when running an asynchronous protocol. + 0x1 + + + + + CPSIZE + CRAM page size + + 16 + 3 + read-write + + + B_0x0 + No burst split when crossing page boundary (default after reset) + 0x0 + + + B_0x1 + 128 bytes + 0x1 + + + B_0x2 + 256 bytes + 0x2 + + + B_0x3 + 512 bytes + 0x3 + + + B_0x4 + 1024 bytes + 0x4 + + + + + CBURSTRW + Write burst enable + + 19 + 1 + read-write + + + B_0x0 + Write operations are always performed in Asynchronous mode. + 0x0 + + + B_0x1 + Write operations are performed in Synchronous mode. + 0x1 + + + + + CCLKEN + Continuous clock enable + + 20 + 1 + read-write + + + B_0x0 + The FMC_CLK is only generated during the synchronous memory access (read/write transaction). + 0x0 + + + B_0x1 + The FMC_CLK is generated continuously during asynchronous and synchronous access. + 0x1 + + + + + WFDIS + Write FIFO disable + + 21 + 1 + read-write + + + B_0x0 + Write FIFO enabled (Default after reset) + 0x0 + + + B_0x1 + Write FIFO disabled + 0x1 + + + + + NBLSET + Byte lane (NBL) setup + + 22 + 2 + read-write + + + B_0x0 + NBL setup time is 0 AHB clock cycle + 0x0 + + + B_0x1 + NBL setup time is 1 AHB clock cycle + 0x1 + + + B_0x2 + NBL setup time is 2 AHB clock cycles + 0x2 + + + B_0x3 + NBL setup time is 3 AHB clock cycles + 0x3 + + + + + FMCEN + FMC controller enable + + 31 + 1 + read-write + + + B_0x0 + Disable the FMC controller + 0x0 + + + B_0x1 + Enable the FMC controller + 0x1 + + + + + + + FMC_BTR4 + FMC_BTR4 + SRAM/NOR-flash chip-select timing register for bank 4 + 0x1C + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration + + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration + + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration =1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration + + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + + 20 + 4 + read-write + + + B_0x0 + FMC_CLK period= 1x HCLK period + 0x0 + + + B_0x1 + FMC_CLK period = 2 HCLK periods + 0x1 + + + B_0x2 + FMC_CLK period = 3 HCLK periods + 0x2 + + + B_0xF + FMC_CLK period = 16 HCLK periods (default value after reset) + 0xF + + + + + DATLAT + (see note below bit descriptions): Data latency for synchronous memory + + 24 + 4 + read-write + + + B_0x0 + Data latency of 2 CLK clock cycles for first burst access + 0x0 + + + B_0xF + Data latency of 17 CLK clock cycles for first burst access (default value after reset) + 0xF + + + + + ACCMOD + Access mode + + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_PCSCNTR + FMC_PCSCNTR + PSRAM chip select counter register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSCOUNT + Chip select counter. + 0 + 16 + read-write + + + CNTB1EN + Counter Bank 1 enable + + 16 + 1 + read-write + + + B_0x0 + Counter disabled for Bank 1 + 0x0 + + + B_0x1 + Counter enabled for Bank 1 + 0x1 + + + + + CNTB2EN + Counter Bank 2 enable + + 17 + 1 + read-write + + + B_0x0 + Counter disabled for Bank 2 + 0x0 + + + B_0x1 + Counter enabled for Bank 2 + 0x1 + + + + + CNTB3EN + Counter Bank 3 enable + + 18 + 1 + read-write + + + B_0x0 + Counter disabled for Bank 3. + 0x0 + + + B_0x1 + Counter enabled for Bank 3 + 0x1 + + + + + CNTB4EN + Counter Bank 4 enable + + 19 + 1 + read-write + + + B_0x0 + Counter disabled for Bank 4 + 0x0 + + + B_0x1 + Counter enabled for Bank 4 + 0x1 + + + + + + + FMC_PCR + FMC_PCR + NAND flash control registers + 0x80 + 0x20 + read-write + 0x00000018 + 0xFFFFFFFF + + + PWAITEN + Wait feature enable bit + + 1 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + PBKEN + NAND flash memory bank enable bit + + 2 + 1 + read-write + + + B_0x0 + Corresponding memory bank is disabled (default after reset) + 0x0 + + + B_0x1 + Corresponding memory bank is enabled + 0x1 + + + + + PTYP + Memory type + + 3 + 1 + read-write + + + B_0x1 + NAND flash (default after reset) + 0x1 + + + + + PWID + Data bus width + + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits (default after reset). + 0x1 + + + + + ECCEN + ECC computation logic enable bit + 6 + 1 + read-write + + + B_0x0 + ECC logic is disabled and reset (default after reset), + 0x0 + + + B_0x1 + ECC logic is enabled. + 0x1 + + + + + TCLR + CLE to RE delay + + 9 + 4 + read-write + + + B_0x0 + 1 HCLK cycle (default) + 0x0 + + + B_0xF + 16 HCLK cycles + 0xF + + + + + TAR + ALE to RE delay + + 13 + 3 + read-write + + + B_0x0 + 1 HCLK cycle (default) + 0x0 + + + + + TAR3 + ALE to RE delay + + 16 + 1 + read-write + + + B_0x0 + 1 HCLK cycle (default) + 0x0 + + + + + ECCPS + ECC page size + + 17 + 3 + read-write + + + B_0x0 + 256 bytes + 0x0 + + + B_0x1 + 512 bytes + 0x1 + + + B_0x2 + 1024 bytes + 0x2 + + + B_0x3 + 2048 bytes + 0x3 + + + B_0x4 + 4096 bytes + 0x4 + + + B_0x5 + 8192 bytes + 0x5 + + + + + + + FMC_SR + FMC_SR + FIFO status and interrupt register + 0x84 + 0x20 + read-write + 0x00000040 + 0xFFFFFFFF + + + IRS + Interrupt rising edge status + + 0 + 1 + read-write + + + B_0x0 + No interrupt rising edge occurred + 0x0 + + + B_0x1 + Interrupt rising edge occurred + 0x1 + + + + + ILS + Interrupt high-level status + + 1 + 1 + read-write + + + B_0x0 + No Interrupt high-level occurred + 0x0 + + + B_0x1 + Interrupt high-level occurred + 0x1 + + + + + IFS + Interrupt falling edge status + + 2 + 1 + read-write + + + B_0x0 + No interrupt falling edge occurred + 0x0 + + + B_0x1 + Interrupt falling edge occurred + 0x1 + + + + + IREN + Interrupt rising edge detection enable bit + 3 + 1 + read-write + + + B_0x0 + Interrupt rising edge detection request disabled + 0x0 + + + B_0x1 + Interrupt rising edge detection request enabled + 0x1 + + + + + ILEN + Interrupt high-level detection enable bit + 4 + 1 + read-write + + + B_0x0 + Interrupt high-level detection request disabled + 0x0 + + + B_0x1 + Interrupt high-level detection request enabled + 0x1 + + + + + IFEN + Interrupt falling edge detection enable bit + 5 + 1 + read-write + + + B_0x0 + Interrupt falling edge detection request disabled + 0x0 + + + B_0x1 + Interrupt falling edge detection request enabled + 0x1 + + + + + FEMPT + FIFO empty + + 6 + 1 + read-only + + + B_0x0 + FIFO not empty + 0x0 + + + B_0x1 + FIFO empty + 0x1 + + + + + + + FMC_PMEM + FMC_PMEM + Common memory space timing register + 0x88 + 0x20 + read-write + 0xFCFCFCFC + 0xFFFFFFFF + + + MEMSET + Common memory x setup time + + 0 + 8 + read-write + + + B_0x0 + 1 HCLK cycle + 0x0 + + + B_0xFE + 255 HCLK cycles + 0xFE + + + + + MEMWAIT + Common memory wait time + + 8 + 8 + read-write + + + B_0x1 + 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT) + 0x1 + + + B_0xFE + 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) + 0xFE + + + + + MEMHOLD + Common memory hold time + + 16 + 8 + read-write + + + B_0x1 + 1 HCLK cycle for write access / 3 HCLK cycles for read access + 0x1 + + + B_0xFE + 254 HCLK cycles for write access / 256 HCLK cycles for read access + 0xFE + + + + + MEMHIZ + Common memory x data bus Hi-Z time + + 24 + 8 + read-write + + + B_0x0 + 1 HCLK cycle + 0x0 + + + B_0xFE + 255 HCLK cycles + 0xFE + + + + + + + FMC_PATT + FMC_PATT + Attribute memory space timing register + 0x8C + 0x20 + read-write + 0xFCFCFCFC + 0xFFFFFFFF + + + ATTSET + Attribute memory setup time + + 0 + 8 + read-write + + + B_0x0 + 1 HCLK cycle + 0x0 + + + B_0xFE + 255 HCLK cycles + 0xFE + + + + + ATTWAIT + Attribute memory wait time + + 8 + 8 + read-write + + + B_0x1 + 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) + 0x1 + + + B_0xFE + 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) + 0xFE + + + + + ATTHOLD + Attribute memory hold time + + 16 + 8 + read-write + + + B_0x1 + 1 HCLK cycle for write access / 3 HCLK cycles for read access + 0x1 + + + B_0xFE + 254 HCLK cycles for write access / 256 HCLK cycles for read access + 0xFE + + + + + ATTHIZ + Attribute memory data bus Hi-Z time + + 24 + 8 + read-write + + + B_0x0 + 0 HCLK cycle + 0x0 + + + B_0xFE + 255 HCLK cycles + 0xFE + + + + + + + FMC_ECCR + FMC_ECCR + ECC result registers + 0x94 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ECC + ECC result + + 0 + 32 + read-only + + + + + FMC_BWTR1 + FMC_BWTR1 + SRAM/NOR-flash write timing registers 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration. + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration. + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration = 1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration. + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + ACCMOD + Access mode. + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_BWTR2 + FMC_BWTR2 + SRAM/NOR-flash write timing registers 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration. + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration. + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration = 1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration. + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + ACCMOD + Access mode. + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_BWTR3 + FMC_BWTR3 + SRAM/NOR-flash write timing registers 3 + 0x114 + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration. + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration. + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration = 1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration. + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + ACCMOD + Access mode. + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_BWTR4 + FMC_BWTR4 + SRAM/NOR-flash write timing registers 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + ADDSET + Address setup phase duration. + 0 + 4 + read-write + + + B_0x0 + ADDSET phase duration = 0 HCLK clock cycle + 0x0 + + + B_0xF + ADDSET phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + ADDHLD + Address-hold phase duration. + 4 + 4 + read-write + + + B_0x1 + ADDHLD phase duration = 1 HCLK clock cycle + 0x1 + + + B_0x2 + ADDHLD phase duration = 2 HCLK clock cycle + 0x2 + + + B_0xF + ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) + 0xF + + + + + DATAST + Data-phase duration. + 8 + 8 + read-write + + + B_0x1 + DATAST phase duration = 1 HCLK clock cycles + 0x1 + + + B_0x2 + DATAST phase duration = 2 HCLK clock cycles + 0x2 + + + B_0xFF + DATAST phase duration = 255 HCLK clock cycles (default value after reset) + 0xFF + + + + + BUSTURN + Bus turnaround phase duration + + 16 + 4 + read-write + + + B_0x0 + BUSTURN phase duration = 1 HCLK clock cycle added + 0x0 + + + B_0xF + BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) + 0xF + + + + + ACCMOD + Access mode. + 28 + 2 + read-write + + + B_0x0 + Access mode A + 0x0 + + + B_0x1 + Access mode B + 0x1 + + + B_0x2 + Access mode C + 0x2 + + + B_0x3 + Access mode D + 0x3 + + + + + DATAHLD + Data hold phase duration + + 30 + 2 + read-write + + + B_0x0 + DATAHLD phase duration = 1 HCLK clock cycle (default) + 0x0 + + + B_0x1 + DATAHLD phase duration = 2 HCLK clock cycle + 0x1 + + + B_0x2 + DATAHLD phase duration = 3 HCLK clock cycle + 0x2 + + + B_0x3 + DATAHLD phase duration = 4 HCLK clock cycle + 0x3 + + + + + + + FMC_SDCR1 + FMC_SDCR1 + SDRAM control registers 1,2 + 0x140 + 0x20 + read-write + 0x000002D0 + 0xFFFFFFFF + + + NC + Number of column address bits + + 0 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 9 bits + 0x1 + + + B_0x2 + 10 bits + 0x2 + + + B_0x3 + 11 bits. + 0x3 + + + + + NR + Number of row address bits + + 2 + 2 + read-write + + + B_0x0 + 11 bit + 0x0 + + + B_0x1 + 12 bits + 0x1 + + + B_0x2 + 13 bits + 0x2 + + + + + MWID + Memory data bus width. + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + + + NB + Number of internal banks + + 6 + 1 + read-write + + + B_0x0 + Two internal Banks + 0x0 + + + B_0x1 + Four internal Banks + 0x1 + + + + + CAS + CAS Latency + + 7 + 2 + read-write + + + B_0x1 + 1 cycle + 0x1 + + + B_0x2 + 2 cycles + 0x2 + + + B_0x3 + 3 cycles + 0x3 + + + + + WP + Write protection + + 9 + 1 + read-write + + + B_0x0 + Write accesses allowed + 0x0 + + + B_0x1 + Write accesses ignored + 0x1 + + + + + SDCLK + SDRAM clock configuration + + 10 + 2 + read-write + + + B_0x0 + SDCLK clock disabled + 0x0 + + + B_0x1 + SDCLK period = 1x HCLK periods + 0x1 + + + B_0x2 + SDCLK period = 2 x HCLK periods + 0x2 + + + B_0x3 + SDCLK period = 3 x HCLK periods + 0x3 + + + + + RBURST + Burst read + + 12 + 1 + read-write + + + B_0x0 + single read requests are not managed as bursts + 0x0 + + + B_0x1 + single read requests are always managed as bursts + 0x1 + + + + + RPIPE + Read pipe + + 13 + 2 + read-write + + + B_0x0 + No clock cycle delay + 0x0 + + + B_0x1 + One clock cycle delay + 0x1 + + + B_0x2 + Two clock cycle delay + 0x2 + + + + + + + FMC_SDCR2 + FMC_SDCR2 + SDRAM control registers 1,2 + 0x144 + 0x20 + read-write + 0x000002D0 + 0xFFFFFFFF + + + NC + Number of column address bits + + 0 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 9 bits + 0x1 + + + B_0x2 + 10 bits + 0x2 + + + B_0x3 + 11 bits. + 0x3 + + + + + NR + Number of row address bits + + 2 + 2 + read-write + + + B_0x0 + 11 bit + 0x0 + + + B_0x1 + 12 bits + 0x1 + + + B_0x2 + 13 bits + 0x2 + + + + + MWID + Memory data bus width. + 4 + 2 + read-write + + + B_0x0 + 8 bits + 0x0 + + + B_0x1 + 16 bits + 0x1 + + + + + NB + Number of internal banks + + 6 + 1 + read-write + + + B_0x0 + Two internal Banks + 0x0 + + + B_0x1 + Four internal Banks + 0x1 + + + + + CAS + CAS Latency + + 7 + 2 + read-write + + + B_0x1 + 1 cycle + 0x1 + + + B_0x2 + 2 cycles + 0x2 + + + B_0x3 + 3 cycles + 0x3 + + + + + WP + Write protection + + 9 + 1 + read-write + + + B_0x0 + Write accesses allowed + 0x0 + + + B_0x1 + Write accesses ignored + 0x1 + + + + + SDCLK + SDRAM clock configuration + + 10 + 2 + read-write + + + B_0x0 + SDCLK clock disabled + 0x0 + + + B_0x1 + SDCLK period = 1x HCLK periods + 0x1 + + + B_0x2 + SDCLK period = 2 x HCLK periods + 0x2 + + + B_0x3 + SDCLK period = 3 x HCLK periods + 0x3 + + + + + RBURST + Burst read + + 12 + 1 + read-write + + + B_0x0 + single read requests are not managed as bursts + 0x0 + + + B_0x1 + single read requests are always managed as bursts + 0x1 + + + + + RPIPE + Read pipe + + 13 + 2 + read-write + + + B_0x0 + No clock cycle delay + 0x0 + + + B_0x1 + One clock cycle delay + 0x1 + + + B_0x2 + Two clock cycle delay + 0x2 + + + + + + + FMC_SDTR1 + FMC_SDTR1 + SDRAM timing registers 1,2 + 0x148 + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + TMRD + Load Mode Register to Active + + 0 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TXSR + Exit Self-refresh delay + + 4 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRAS + Self refresh time + + 8 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRC + Row cycle delay + + 12 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TWR + Recovery delay + + 16 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRP + Row precharge delay + + 20 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRCD + Row to column delay + + 24 + 4 + read-write + + + B_0x0 + 1 cycle. + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + + + FMC_SDTR2 + FMC_SDTR2 + SDRAM timing registers 1,2 + 0x14C + 0x20 + read-write + 0x0FFFFFFF + 0xFFFFFFFF + + + TMRD + Load Mode Register to Active + + 0 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TXSR + Exit Self-refresh delay + + 4 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRAS + Self refresh time + + 8 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRC + Row cycle delay + + 12 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TWR + Recovery delay + + 16 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRP + Row precharge delay + + 20 + 4 + read-write + + + B_0x0 + 1 cycle + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + TRCD + Row to column delay + + 24 + 4 + read-write + + + B_0x0 + 1 cycle. + 0x0 + + + B_0x1 + 2 cycles + 0x1 + + + B_0xF + 16 cycles + 0xF + + + + + + + FMC_SDCMR + FMC_SDCMR + SDRAM Command Mode register + 0x150 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MODE + Command mode + + 0 + 3 + read-write + + + B_0x0 + Normal Mode + 0x0 + + + B_0x1 + Clock Configuration Enable + 0x1 + + + B_0x2 + PALL (All Bank Precharge) command + 0x2 + + + B_0x3 + Auto-refresh command + 0x3 + + + B_0x4 + Load Mode Register + 0x4 + + + B_0x5 + Self-refresh command + 0x5 + + + B_0x6 + Power-down command + 0x6 + + + + + CTB2 + Command Target Bank 2 + + 3 + 1 + read-write + + + B_0x0 + Command not issued to SDRAM Bank 2 + 0x0 + + + B_0x1 + Command issued to SDRAM Bank 2 + 0x1 + + + + + CTB1 + Command Target Bank 1 + + 4 + 1 + read-write + + + B_0x0 + Command not issued to SDRAM Bank 1 + 0x0 + + + B_0x1 + Command issued to SDRAM Bank 1 + 0x1 + + + + + NRFS + Number of Auto-refresh + + 5 + 4 + read-write + + + B_0x0 + 1 Auto-refresh cycle + 0x0 + + + B_0x1 + 2 Auto-refresh cycles + 0x1 + + + B_0xE + 15 Auto-refresh cycles + 0xE + + + B_0xF + 16 Auto-refresh cycles + 0xF + + + + + MRD + Mode Register definition + + 9 + 13 + read-write + + + + + FMC_SDRTR + FMC_SDRTR + SDRAM refresh timer register + 0x154 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CRE + Clear Refresh error flag + + 0 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + Refresh Error flag is cleared + 0x1 + + + + + COUNT + Refresh Timer Count + + 1 + 13 + read-write + + + REIE + RES Interrupt Enable + 14 + 1 + read-write + + + B_0x0 + Interrupt is disabled + 0x0 + + + B_0x1 + An Interrupt is generated if RE = 1 + 0x1 + + + + + + + FMC_SDSR + FMC_SDSR + SDRAM status register + 0x158 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RE + Refresh error flag + + 0 + 1 + read-only + + + B_0x0 + No refresh error has been detected + 0x0 + + + B_0x1 + A refresh error has been detected + 0x1 + + + + + MODES1 + Status Mode for Bank 1 + + 1 + 2 + read-only + + + B_0x0 + Normal Mode + 0x0 + + + B_0x1 + Self-refresh mode + 0x1 + + + B_0x2 + Power-down mode + 0x2 + + + + + MODES2 + Status Mode for Bank 2 + + 3 + 2 + read-only + + + B_0x0 + Normal Mode + 0x0 + + + B_0x1 + Self-refresh mode + 0x1 + + + B_0x2 + Power-down mode + 0x2 + + + + + BUSY + Busy status + + 5 + 1 + read-only + + + B_0x0 + SDRAM Controller is ready to accept a new request + 0x0 + + + + + + + + + FMC_S + 0X57000400 + + + GPDMA + GPDMA register block + GPDMA + 0x40020000 + + 0x0 + 0x1000 + registers + + + GPDMA1_CH7 + GPDMA1 channel7 global interrupt + 34 + + + GPDMA1_CH6 + GPDMA1 channel6 global interrupt + 33 + + + GPDMA1_CH5 + GPDMA1 channel5 global interrupt + 32 + + + GPDMA1_CH4 + GPDMA1 channel4 global interrupt + 31 + + + GPDMA1_CH3 + GPDMA1 channel3 global interrupt + 30 + + + GPDMA1_CH2 + GPDMA1 channel2 global interrupt + 29 + + + GPDMA1_CH1 + GPDMA1 channel1 global interrupt + 28 + + + GPDMA1_CH0 + GPDMA1 channel0 global interrupt + 27 + + + + GPDMA_SECCFGR + GPDMA_SECCFGR + GPDMA secure configuration register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEC0 + secure state of channel x + 0 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC1 + secure state of channel x + 1 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC2 + secure state of channel x + 2 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC3 + secure state of channel x + 3 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC4 + secure state of channel x + 4 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC5 + secure state of channel x + 5 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC6 + secure state of channel x + 6 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SEC7 + secure state of channel x + 7 + 1 + read-write + + + B_0x0 + nonsecure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + + + GPDMA_PRIVCFGR + GPDMA_PRIVCFGR + GPDMA privileged configuration register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIV0 + privileged state of channel x + 0 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV1 + privileged state of channel x + 1 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV2 + privileged state of channel x + 2 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV3 + privileged state of channel x + 3 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV4 + privileged state of channel x + 4 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV5 + privileged state of channel x + 5 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV6 + privileged state of channel x + 6 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PRIV7 + privileged state of channel x + 7 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + + + GPDMA_RCFGLOCKR + GPDMA_RCFGLOCKR + GPDMA configuration lock register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LOCK0 + lock the configuration of GPDMA_SECCFGR. + 0 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK1 + lock the configuration of GPDMA_SECCFGR. + 1 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK2 + lock the configuration of GPDMA_SECCFGR. + 2 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK3 + lock the configuration of GPDMA_SECCFGR. + 3 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK4 + lock the configuration of GPDMA_SECCFGR. + 4 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK5 + lock the configuration of GPDMA_SECCFGR. + 5 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK6 + lock the configuration of GPDMA_SECCFGR. + 6 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + LOCK7 + lock the configuration of GPDMA_SECCFGR. + 7 + 1 + read-write + + + B_0x0 + secure privilege configuration of the channel x is writable. + 0x0 + + + B_0x1 + secure privilege configuration of the channel x is not writable. + 0x1 + + + + + + + GPDMA_MISR + GPDMA_MISR + GPDMA nonsecure masked interrupt status register + 0x0C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + MIS0 + masked interrupt status of channel x + 0 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS1 + masked interrupt status of channel x + 1 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS2 + masked interrupt status of channel x + 2 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS3 + masked interrupt status of channel x + 3 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS4 + masked interrupt status of channel x + 4 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS5 + masked interrupt status of channel x + 5 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS6 + masked interrupt status of channel x + 6 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + MIS7 + masked interrupt status of channel x + 7 + 1 + read-only + + + B_0x0 + no interrupt occurred on channel x + 0x0 + + + B_0x1 + an interrupt occurred on channel x + 0x1 + + + + + + + GPDMA_SMISR + GPDMA_SMISR + GPDMA secure masked interrupt status register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + MIS0 + masked interrupt status of the secure channel x + 0 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS1 + masked interrupt status of the secure channel x + 1 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS2 + masked interrupt status of the secure channel x + 2 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS3 + masked interrupt status of the secure channel x + 3 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS4 + masked interrupt status of the secure channel x + 4 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS5 + masked interrupt status of the secure channel x + 5 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS6 + masked interrupt status of the secure channel x + 6 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + MIS7 + masked interrupt status of the secure channel x + 7 + 1 + read-only + + + B_0x0 + no interrupt occurred on the secure channel x + 0x0 + + + B_0x1 + an interrupt occurred on the secure channel x + 0x1 + + + + + + + GPDMA_C0LBAR + GPDMA_C0LBAR + GPDMA channel 0 linked-list base address register + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C0FCR + GPDMA_C0FCR + GPDMA channel 0 flag clear register + 0x5C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C0SR + GPDMA_C0SR + GPDMA channel 0 status register + 0x60 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C0CR + GPDMA_C0CR + GPDMA channel 0 control register + 0x64 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C0TR1 + GPDMA_C0TR1 + GPDMA channel 0 transfer register 1 + 0x90 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C0TR2 + GPDMA_C0TR2 + GPDMA channel 0 transfer register 2 + 0x94 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C0BR1 + GPDMA_C0BR1 + GPDMA channel 0 block register 1 + 0x98 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + + + GPDMA_C0SAR + GPDMA_C0SAR + GPDMA channel 0 source address register + 0x9C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C0DAR + GPDMA_C0DAR + GPDMA channel 0 destination address register + 0xA0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C0LLR + GPDMA_C0LLR + GPDMA channel 0 linked-list address register + 0xCC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C1LBAR + GPDMA_C1LBAR + GPDMA channel 1 linked-list base address register + 0xD0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C1FCR + GPDMA_C1FCR + GPDMA channel 1 flag clear register + 0xDC + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C1SR + GPDMA_C1SR + GPDMA channel 1 status register + 0xE0 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C1CR + GPDMA_C1CR + GPDMA channel 1 control register + 0xE4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C1TR1 + GPDMA_C1TR1 + GPDMA channel 1 transfer register 1 + 0x110 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C1TR2 + GPDMA_C1TR2 + GPDMA channel 1 transfer register 2 + 0x114 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C1BR1 + GPDMA_C1BR1 + GPDMA channel 1 block register 1 + 0x118 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + + + GPDMA_C1SAR + GPDMA_C1SAR + GPDMA channel 1 source address register + 0x11C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C1DAR + GPDMA_C1DAR + GPDMA channel 1 destination address register + 0x120 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C1LLR + GPDMA_C1LLR + GPDMA channel 1 linked-list address register + 0x14C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C2LBAR + GPDMA_C2LBAR + GPDMA channel 2 linked-list base address register + 0x150 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C2FCR + GPDMA_C2FCR + GPDMA channel 2 flag clear register + 0x15C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C2SR + GPDMA_C2SR + GPDMA channel 2 status register + 0x160 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C2CR + GPDMA_C2CR + GPDMA channel 2 control register + 0x164 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C2TR1 + GPDMA_C2TR1 + GPDMA channel 2 transfer register 1 + 0x190 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C2TR2 + GPDMA_C2TR2 + GPDMA channel 2 transfer register 2 + 0x194 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C2BR1 + GPDMA_C2BR1 + GPDMA channel 2 block register 1 + 0x198 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + + + GPDMA_C2SAR + GPDMA_C2SAR + GPDMA channel 2 source address register + 0x19C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C2DAR + GPDMA_C2DAR + GPDMA channel 2 destination address register + 0x1A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C2LLR + GPDMA_C2LLR + GPDMA channel 2 linked-list address register + 0x1CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C3LBAR + GPDMA_C3LBAR + GPDMA channel 3 linked-list base address register + 0x1D0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C3FCR + GPDMA_C3FCR + GPDMA channel 3 flag clear register + 0x1DC + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C3SR + GPDMA_C3SR + GPDMA channel 3 status register + 0x1E0 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C3CR + GPDMA_C3CR + GPDMA channel 3 control register + 0x1E4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C3TR1 + GPDMA_C3TR1 + GPDMA channel 3 transfer register 1 + 0x210 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C3TR2 + GPDMA_C3TR2 + GPDMA channel 3 transfer register 2 + 0x214 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C3BR1 + GPDMA_C3BR1 + GPDMA channel 3 block register 1 + 0x218 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + + + GPDMA_C3SAR + GPDMA_C3SAR + GPDMA channel 3 source address register + 0x21C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C3DAR + GPDMA_C3DAR + GPDMA channel 3 destination address register + 0x220 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C3LLR + GPDMA_C3LLR + GPDMA channel 3 linked-list address register + 0x24C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C4LBAR + GPDMA_C4LBAR + GPDMA channel 4 linked-list base address register + 0x250 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C4FCR + GPDMA_C4FCR + GPDMA channel 4 flag clear register + 0x25C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C4SR + GPDMA_C4SR + GPDMA channel 4 status register + 0x260 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C4CR + GPDMA_C4CR + GPDMA channel 4 control register + 0x264 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C4TR1 + GPDMA_C4TR1 + GPDMA channel 4 transfer register 1 + 0x290 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C4TR2 + GPDMA_C4TR2 + GPDMA channel 4 transfer register 2 + 0x294 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C4BR1 + GPDMA_C4BR1 + GPDMA channel 4 block register 1 + 0x298 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + + + GPDMA_C4SAR + GPDMA_C4SAR + GPDMA channel 4 source address register + 0x29C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C4DAR + GPDMA_C4DAR + GPDMA channel 4 destination address register + 0x2A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C4LLR + GPDMA_C4LLR + GPDMA channel 4 linked-list address register + 0x2CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C5LBAR + GPDMA_C5LBAR + GPDMA channel 5 linked-list base address register + 0x2D0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C5FCR + GPDMA_C5FCR + GPDMA channel 5 flag clear register + 0x2DC + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C5SR + GPDMA_C5SR + GPDMA channel 5 status register + 0x2E0 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C5CR + GPDMA_C5CR + GPDMA channel 5 control register + 0x2E4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C5TR1 + GPDMA_C5TR1 + GPDMA channel 5 transfer register 1 + 0x310 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C5TR2 + GPDMA_C5TR2 + GPDMA channel 5 transfer register 2 + 0x314 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C5BR1 + GPDMA_C5BR1 + GPDMA channel 5 block register 1 + 0x318 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + + + GPDMA_C5SAR + GPDMA_C5SAR + GPDMA channel 5 source address register + 0x31C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C5DAR + GPDMA_C5DAR + GPDMA channel 5 destination address register + 0x320 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C5LLR + GPDMA_C5LLR + GPDMA channel 5 linked-list address register + 0x34C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C6LBAR + GPDMA_C6LBAR + GPDMA channel 6 linked-list base address register + 0x350 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C6FCR + GPDMA_C6FCR + GPDMA channel 6 flag clear register + 0x35C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C6SR + GPDMA_C6SR + GPDMA channel 6 status register + 0x360 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C6CR + GPDMA_C6CR + GPDMA channel 6 control register + 0x364 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C6TR1 + GPDMA_C6TR1 + GPDMA channel 6 transfer register 1 + 0x390 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C6TR2 + GPDMA_C6TR2 + GPDMA channel 6 transfer register 2 + 0x394 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C6BR1 + GPDMA_C6BR1 + GPDMA channel 6 alternate block register 1 + 0x398 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + BRC + Block repeat counter + + 16 + 11 + read-write + + + SDEC + source address decrement + 28 + 1 + read-write + + + B_0x0 + At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3. + 0x0 + + + B_0x1 + At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3. + 0x1 + + + + + DDEC + destination address decrement + 29 + 1 + read-write + + + B_0x0 + At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3. + 0x0 + + + B_0x1 + At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3. + 0x1 + + + + + BRSDEC + Block repeat source address decrement + + 30 + 1 + read-write + + + B_0x0 + at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2. + 0x0 + + + B_0x1 + at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2. + 0x1 + + + + + BRDDEC + Block repeat destination address decrement + + 31 + 1 + read-write + + + B_0x0 + at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2. + 0x0 + + + B_0x1 + at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2. + 0x1 + + + + + + + GPDMA_C6SAR + GPDMA_C6SAR + GPDMA channel 6 source address register + 0x39C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C6DAR + GPDMA_C6DAR + GPDMA channel 6 destination address register + 0x3A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C6TR3 + GPDMA_C6TR3 + GPDMA channel 6 transfer register 3 + 0x3A4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SAO + source address offset increment + + 0 + 13 + read-write + + + DAO + destination address offset increment + + 16 + 13 + read-write + + + + + GPDMA_C6BR2 + GPDMA_C6BR2 + GPDMA channel 6 block register 2 + 0x3A8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRSAO + Block repeated source address offset + + 0 + 16 + read-write + + + BRDAO + Block repeated destination address offset + + 16 + 16 + read-write + + + + + GPDMA_C6LLR + GPDMA_C6LLR + GPDMA channel 6 alternate linked-list address register + 0x3CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UB2 + Update GPDMA_CxBR2 from memory + + 25 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR2 update + 0x0 + + + B_0x1 + GPDMA_CxBR2 update + 0x1 + + + + + UT3 + Update GPDMA_CxTR3 from memory + + 26 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR3 update + 0x0 + + + B_0x1 + GPDMA_CxTR3 update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + GPDMA_C7LBAR + GPDMA_C7LBAR + GPDMA channel 7 linked-list base address register + 0x3D0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LBA + linked-list base address of GPDMA channel x + 16 + 16 + read-write + + + + + GPDMA_C7FCR + GPDMA_C7FCR + GPDMA channel 7 flag clear register + 0x3DC + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TCF + transfer complete flag clear + 8 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TCF flag cleared + 0x1 + + + + + HTF + half transfer flag clear + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding HTF flag cleared + 0x1 + + + + + DTEF + data transfer error flag clear + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding DTEF flag cleared + 0x1 + + + + + ULEF + update link transfer error flag clear + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding ULEF flag cleared + 0x1 + + + + + USEF + user setting error flag clear + 12 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding USEF flag cleared + 0x1 + + + + + SUSPF + completed suspension flag clear + 13 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding SUSPF flag cleared + 0x1 + + + + + TOF + trigger overrun flag clear + 14 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + corresponding TOF flag cleared + 0x1 + + + + + + + GPDMA_C7SR + GPDMA_C7SR + GPDMA channel 7 status register + 0x3E0 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + IDLEF + idle flag + + 0 + 1 + read-only + + + B_0x0 + channel not in idle state + 0x0 + + + B_0x1 + channel in idle state + 0x1 + + + + + TCF + transfer complete flag + + 8 + 1 + read-only + + + B_0x0 + no transfer complete event + 0x0 + + + B_0x1 + a transfer complete event occurred + 0x1 + + + + + HTF + half transfer flag + + 9 + 1 + read-only + + + B_0x0 + no half transfer event + 0x0 + + + B_0x1 + a half transfer event occurred + 0x1 + + + + + DTEF + data transfer error flag + 10 + 1 + read-only + + + B_0x0 + no data transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred on a data transfer + 0x1 + + + + + ULEF + update link transfer error flag + 11 + 1 + read-only + + + B_0x0 + no update link transfer error event + 0x0 + + + B_0x1 + a master bus error event occurred while updating a linked-list register from memory + 0x1 + + + + + USEF + user setting error flag + 12 + 1 + read-only + + + B_0x0 + no user setting error event + 0x0 + + + B_0x1 + a user setting error event occurred + 0x1 + + + + + SUSPF + completed suspension flag + 13 + 1 + read-only + + + B_0x0 + no completed suspension event + 0x0 + + + B_0x1 + a completed suspension event occurred + 0x1 + + + + + TOF + trigger overrun flag + 14 + 1 + read-only + + + B_0x0 + no trigger overrun event + 0x0 + + + B_0x1 + a trigger overrun event occurred + 0x1 + + + + + FIFOL + monitored FIFO level + + 16 + 8 + read-only + + + + + GPDMA_C7CR + GPDMA_C7CR + GPDMA channel 7 control register + 0x3E4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + enable + + 0 + 1 + read-write + + + B_0x0 + write: ignored, read: channel disabled + 0x0 + + + B_0x1 + write: enable channel, read: channel enabled + 0x1 + + + + + RESET + reset + + 1 + 1 + write-only + + + B_0x0 + no channel reset + 0x0 + + + B_0x1 + channel reset + 0x1 + + + + + SUSP + suspend + + 2 + 1 + read-write + + + B_0x0 + write: resume channel, read: channel not suspended + 0x0 + + + B_0x1 + write: suspend channel, read: channel suspended. + 0x1 + + + + + TCIE + transfer complete interrupt enable + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HTIE + half transfer complete interrupt enable + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTEIE + data transfer error interrupt enable + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ULEIE + update link transfer error interrupt enable + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USEIE + user setting error interrupt enable + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SUSPIE + completed suspension interrupt enable + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TOIE + trigger overrun interrupt enable + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LSM + Link step mode + + 16 + 1 + read-write + + + B_0x0 + channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). + 0x0 + + + B_0x1 + channel executed once for the current LLI + 0x1 + + + + + LAP + linked-list allocated port + + 17 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + PRIO + priority level of the channel x GPDMA transfer versus others + + 22 + 2 + read-write + + + B_0x0 + low priority, low weight + 0x0 + + + B_0x1 + low priority, mid weight + 0x1 + + + B_0x2 + low priority, high weight + 0x2 + + + B_0x3 + high priority + 0x3 + + + + + + + GPDMA_C7TR1 + GPDMA_C7TR1 + GPDMA channel 7 transfer register 1 + 0x410 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDW_LOG2 + binary logarithm of the source data width of a burst in bytes + + 0 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + SINC + source incrementing burst + + 3 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + SBL_1 + source burst length minus 1, between 0 and 63 + + 4 + 6 + read-write + + + PAM + padding/alignment mode + + 11 + 2 + read-write + + + B_0x0_PAM_1 + source data is transferred as right aligned, padded with 0s up to the destination data width + 0x0 + + + B_0x1_PAM_1 + source data is transferred as right aligned, sign extended up to the destination data width + 0x1 + + + B_0x2_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x2 + + + B_0x3_PAM_1 + successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer + 0x3 + + + + + SBX + source byte exchange within the unaligned half-word of each source word + + 13 + 1 + read-write + + + B_0x0 + no byte-based exchange within the unaligned half-word of each source word + 0x0 + + + B_0x1 + the two consecutive bytes within the unaligned half-word of each source word are exchanged. + 0x1 + + + + + SAP + source allocated port + + 14 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + SSEC + security attribute of the GPDMA transfer from the source + + 15 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + DDW_LOG2 + binary logarithm of the destination data width of a burst, in bytes + + 16 + 2 + read-write + + + B_0x0 + byte + 0x0 + + + B_0x1 + half-word (2 bytes) + 0x1 + + + B_0x2 + word (4 bytes) + 0x2 + + + B_0x3 + user setting error reported and no transfer issued + 0x3 + + + + + DINC + destination incrementing burst + + 19 + 1 + read-write + + + B_0x0 + fixed burst + 0x0 + + + B_0x1 + contiguously incremented burst + 0x1 + + + + + DBL_1 + destination burst length minus 1, between 0 and 63 + + 20 + 6 + read-write + + + DBX + destination byte exchange + + 26 + 1 + read-write + + + B_0x0 + no byte-based exchange within half-word + 0x0 + + + B_0x1 + the two consecutive (post PAM) bytes are exchanged in each destination half-word. + 0x1 + + + + + DHX + destination half-word exchange + + 27 + 1 + read-write + + + B_0x0 + no halfword-based exchanged within word + 0x0 + + + B_0x1 + the two consecutive (post PAM) half-words are exchanged in each destination word. + 0x1 + + + + + DAP + destination allocated port + + 30 + 1 + read-write + + + B_0x0 + port 0 (AHB) allocated + 0x0 + + + B_0x1 + port 1 (AHB) allocated + 0x1 + + + + + DSEC + security attribute of the GPDMA transfer to the destination + + 31 + 1 + read-write + + + B_0x0 + GPDMA transfer nonsecure + 0x0 + + + B_0x1 + GPDMA transfer secure + 0x1 + + + + + + + GPDMA_C7TR2 + GPDMA_C7TR2 + GPDMA channel 7 transfer register 2 + 0x414 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REQSEL + GPDMA hardware request selection + + 0 + 8 + read-write + + + SWREQ + software request + + 9 + 1 + read-write + + + B_0x0 + no software request. + 0x0 + + + B_0x1 + software request for a memory-to-memory transfer. + 0x1 + + + + + DREQ + destination hardware request + + 10 + 1 + read-write + + + B_0x0 + selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) + 0x0 + + + B_0x1 + selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) + 0x1 + + + + + BREQ + Block hardware request + + 11 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. + 0x1 + + + + + PFREQ + Hardware request in peripheral flow control mode + + 12 + 1 + read-write + + + B_0x0 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. + 0x0 + + + B_0x1 + the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. + 0x1 + + + + + TRIGM + trigger mode + + 14 + 2 + read-write + + + B_0x0 + at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. + 0x1 + + + B_0x2 + at link level: a LLI link transfer is conditioned by one hit trigger. + 0x2 + + + B_0x3 + at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. + 0x3 + + + + + TRIGSEL + trigger event input selection + + 16 + 6 + read-write + + + TRIGPOL + trigger event polarity + + 24 + 2 + read-write + + + B_0x0 + no trigger (masked trigger event) + 0x0 + + + B_0x1 + trigger on the rising edge + 0x1 + + + B_0x2 + trigger on the falling edge + 0x2 + + + B_0x3 + same as 00 + 0x3 + + + + + TCEM + transfer complete event mode + + 30 + 2 + read-write + + + B_0x0 + at block level (when GPDMA_CxBR1. + 0x0 + + + B_0x1 + channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. + 0x1 + + + B_0x2 + at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. + 0x2 + + + B_0x3 + at channel level: the complete transfer event is generated at the end of the last LLI transfer. + 0x3 + + + + + + + GPDMA_C7BR1 + GPDMA_C7BR1 + GPDMA channel 7 alternate block register 1 + 0x418 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BNDT + block number of data bytes to transfer from the source + + 0 + 16 + read-write + + + BRC + Block repeat counter + + 16 + 11 + read-write + + + SDEC + source address decrement + 28 + 1 + read-write + + + B_0x0 + At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3. + 0x0 + + + B_0x1 + At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3. + 0x1 + + + + + DDEC + destination address decrement + 29 + 1 + read-write + + + B_0x0 + At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3. + 0x0 + + + B_0x1 + At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3. + 0x1 + + + + + BRSDEC + Block repeat source address decrement + + 30 + 1 + read-write + + + B_0x0 + at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2. + 0x0 + + + B_0x1 + at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2. + 0x1 + + + + + BRDDEC + Block repeat destination address decrement + + 31 + 1 + read-write + + + B_0x0 + at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2. + 0x0 + + + B_0x1 + at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2. + 0x1 + + + + + + + GPDMA_C7SAR + GPDMA_C7SAR + GPDMA channel 7 source address register + 0x41C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SA + source address + + 0 + 32 + read-write + + + + + GPDMA_C7DAR + GPDMA_C7DAR + GPDMA channel 7 destination address register + 0x420 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + destination address + + 0 + 32 + read-write + + + + + GPDMA_C7TR3 + GPDMA_C7TR3 + GPDMA channel 7 transfer register 3 + 0x424 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SAO + source address offset increment + + 0 + 13 + read-write + + + DAO + destination address offset increment + + 16 + 13 + read-write + + + + + GPDMA_C7BR2 + GPDMA_C7BR2 + GPDMA channel 7 block register 2 + 0x428 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRSAO + Block repeated source address offset + + 0 + 16 + read-write + + + BRDAO + Block repeated destination address offset + + 16 + 16 + read-write + + + + + GPDMA_C7LLR + GPDMA_C7LLR + GPDMA channel 7 alternate linked-list address register + 0x44C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LA + pointer (16-bit low-significant address) to the next linked-list data structure + + 2 + 14 + read-write + + + ULL + Update GPDMA_CxLLR register from memory + + 16 + 1 + read-write + + + B_0x0 + no GPDMA_CxLLR update + 0x0 + + + B_0x1 + GPDMA_CxLLR update + 0x1 + + + + + UB2 + Update GPDMA_CxBR2 from memory + + 25 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR2 update + 0x0 + + + B_0x1 + GPDMA_CxBR2 update + 0x1 + + + + + UT3 + Update GPDMA_CxTR3 from memory + + 26 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR3 update + 0x0 + + + B_0x1 + GPDMA_CxTR3 update + 0x1 + + + + + UDA + Update GPDMA_CxDAR register from memory + + 27 + 1 + read-write + + + B_0x0 + no GPDMA_CxDAR update + 0x0 + + + B_0x1 + GPDMA_CxDAR update + 0x1 + + + + + USA + update GPDMA_CxSAR from memory + + 28 + 1 + read-write + + + B_0x0 + no GPDMA_CxSAR update + 0x0 + + + B_0x1 + GPDMA_CxSAR update + 0x1 + + + + + UB1 + Update GPDMA_CxBR1 from memory + + 29 + 1 + read-write + + + B_0x0 + no GPDMA_CxBR1 update from memory (GPDMA_CxBR1. + 0x0 + + + B_0x1 + GPDMA_CxBR1 update + 0x1 + + + + + UT2 + Update GPDMA_CxTR2 from memory + + 30 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR2 update + 0x0 + + + B_0x1 + GPDMA_CxTR2 update + 0x1 + + + + + UT1 + Update GPDMA_CxTR1 from memory + + 31 + 1 + read-write + + + B_0x0 + no GPDMA_CxTR1 update + 0x0 + + + B_0x1 + GPDMA_CxTR1 update + 0x1 + + + + + + + + + GPDMA_S + 0x50020000 + + + GPDMA2 + 0X40021000 + + GPDMA2_CH7 + GPDMA2 channel7 global interrupt + 97 + + + GPDMA2_CH6 + GPDMA2 channel6 global interrupt + 96 + + + GPDMA2_CH5 + GPDMA2 channel5 global interrupt + 95 + + + GPDMA2_CH4 + GPDMA2 channel4 global interrupt + 94 + + + GPDMA2_CH3 + GPDMA2 channe3 global interrupt + 93 + + + GPDMA2_CH2 + GPDMA2 channel2 global interrupt + 92 + + + GPDMA2_CH1 + GPDMA2 channel1 global interrupt + 91 + + + GPDMA2_CH0 + GPDMA2 channel0 global interrupt + 90 + + + + GPDMA2_S + 0X50021000 + + + GPIOA + GPIOA address block description + GPIOA + 0x42020000 + + 0x0 + 0x34 + registers + + + + GPIOA_MODER + GPIOA_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOA_OTYPER + GPIOA_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOA_OSPEEDR + GPIOA_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOA_PUPDR + GPIOA_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOA_IDR + GPIOA_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOA_ODR + GPIOA_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOA_BSRR + GPIOA_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOA_LCKR + GPIOA_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOA_AFRL + GPIOA_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_AFRH + GPIOA_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOA_BRR + GPIOA_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOA_HSLVR + GPIOA_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOA_SECCFGR + GPIOA_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOA_S + 0X52020000 + + + GPIOB + GPIOB address block description + GPIOB + 0x42020400 + + 0x0 + 0x34 + registers + + + + GPIOB_MODER + GPIOB_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOB_OTYPER + GPIOB_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOB_OSPEEDR + GPIOB_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOB_PUPDR + GPIOB_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOB_IDR + GPIOB_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOB_ODR + GPIOB_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOB_BSRR + GPIOB_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOB_LCKR + GPIOB_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOB_AFRL + GPIOB_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOB_AFRH + GPIOB_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOB_BRR + GPIOB_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOB_HSLVR + GPIOB_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOB_SECCFGR + GPIOB_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOB_S + 0X52020400 + + + GPIOC + GPIOC address block description + GPIOC + 0x42020800 + + 0x0 + 0x34 + registers + + + + GPIOC_MODER + GPIOC_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOC_OTYPER + GPIOC_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOC_OSPEEDR + GPIOC_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOC_PUPDR + GPIOC_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOC_IDR + GPIOC_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOC_ODR + GPIOC_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOC_BSRR + GPIOC_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOC_LCKR + GPIOC_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOC_AFRL + GPIOC_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOC_AFRH + GPIOC_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOC_BRR + GPIOC_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOC_HSLVR + GPIOC_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOC_SECCFGR + GPIOC_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOC_S + 0X52020800 + + + GPIOD + GPIOD address block description + GPIOD + 0x42020c00 + + 0x0 + 0x34 + registers + + + + GPIOD_MODER + GPIOD_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOD_OTYPER + GPIOD_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOD_OSPEEDR + GPIOD_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOD_PUPDR + GPIOD_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOD_IDR + GPIOD_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOD_ODR + GPIOD_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOD_BSRR + GPIOD_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOD_LCKR + GPIOD_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOD_AFRL + GPIOD_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOD_AFRH + GPIOD_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOD_BRR + GPIOD_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOD_HSLVR + GPIOD_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOD_SECCFGR + GPIOD_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOD_S + 0X52020C00 + + + GPIOE + GPIOE address block description + GPIOE + 0x42021000 + + 0x0 + 0x34 + registers + + + + GPIOE_MODER + GPIOE_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOE_OTYPER + GPIOE_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOE_OSPEEDR + GPIOE_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOE_PUPDR + GPIOE_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOE_IDR + GPIOE_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOE_ODR + GPIOE_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOE_BSRR + GPIOE_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOE_LCKR + GPIOE_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOE_AFRL + GPIOE_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOE_AFRH + GPIOE_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOE_BRR + GPIOE_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOE_HSLVR + GPIOE_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOE_SECCFGR + GPIOE_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOE_S + 0X52021000 + + + GPIOF + GPIOF address block description + GPIOF + 0x42021400 + + 0x0 + 0x34 + registers + + + + GPIOF_MODER + GPIOF_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOF_OTYPER + GPIOF_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOF_OSPEEDR + GPIOF_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOF_PUPDR + GPIOF_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOF_IDR + GPIOF_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOF_ODR + GPIOF_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOF_BSRR + GPIOF_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOF_LCKR + GPIOF_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOF_AFRL + GPIOF_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOF_AFRH + GPIOF_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOF_BRR + GPIOF_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOF_HSLVR + GPIOF_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOF_SECCFGR + GPIOF_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOF_S + 0X52021400 + + + GPIOG + GPIOG address block description + GPIOG + 0x42021800 + + 0x0 + 0x34 + registers + + + + GPIOG_MODER + GPIOG_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOG_OTYPER + GPIOG_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOG_OSPEEDR + GPIOG_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOG_PUPDR + GPIOG_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOG_IDR + GPIOG_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOG_ODR + GPIOG_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOG_BSRR + GPIOG_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOG_LCKR + GPIOG_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOG_AFRL + GPIOG_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOG_AFRH + GPIOG_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOG_BRR + GPIOG_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOG_HSLVR + GPIOG_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOG_SECCFGR + GPIOG_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOG_S + 0X52021800 + + + GPIOH + GPIOH address block description + GPIOH + 0x42021c00 + + 0x0 + 0x34 + registers + + + + GPIOH_MODER + GPIOH_MODER + GPIO port mode register + 0x00 + 0x20 + read-write + 0x00FFFFFF + 0xFFFFFFFF + + + MODE0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + MODE15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Input mode + 0x0 + + + B_0x1 + General purpose output mode + 0x1 + + + B_0x2 + Alternate function mode + 0x2 + + + B_0x3 + Analog mode (reset state) + 0x3 + + + + + + + GPIOH_OTYPER + GPIOH_OTYPER + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OT0 + Port x configuration I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT1 + Port x configuration I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT2 + Port x configuration I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT3 + Port x configuration I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT4 + Port x configuration I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT5 + Port x configuration I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT6 + Port x configuration I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT7 + Port x configuration I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT8 + Port x configuration I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT9 + Port x configuration I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT10 + Port x configuration I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT11 + Port x configuration I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT12 + Port x configuration I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT13 + Port x configuration I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT14 + Port x configuration I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + OT15 + Port x configuration I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Output push-pull (reset state) + 0x0 + + + B_0x1 + Output open-drain + 0x1 + + + + + + + GPIOH_OSPEEDR + GPIOH_OSPEEDR + GPIO port output speed register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OSPEED0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + OSPEED15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + Low speed + 0x0 + + + B_0x1 + Medium speed + 0x1 + + + B_0x2 + High speed + 0x2 + + + B_0x3 + Very-high speed + 0x3 + + + + + + + GPIOH_PUPDR + GPIOH_PUPDR + GPIO port pull-up/pull-down register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PUPD0 + Port x configuration I/O pin y + + 0 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD1 + Port x configuration I/O pin y + + 2 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD2 + Port x configuration I/O pin y + + 4 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD3 + Port x configuration I/O pin y + + 6 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD4 + Port x configuration I/O pin y + + 8 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD5 + Port x configuration I/O pin y + + 10 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD6 + Port x configuration I/O pin y + + 12 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD7 + Port x configuration I/O pin y + + 14 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD8 + Port x configuration I/O pin y + + 16 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD9 + Port x configuration I/O pin y + + 18 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD10 + Port x configuration I/O pin y + + 20 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD11 + Port x configuration I/O pin y + + 22 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD12 + Port x configuration I/O pin y + + 24 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD13 + Port x configuration I/O pin y + + 26 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD14 + Port x configuration I/O pin y + + 28 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + PUPD15 + Port x configuration I/O pin y + + 30 + 2 + read-write + + + B_0x0 + No pull-up, pull-down + 0x0 + + + B_0x1 + Pull-up + 0x1 + + + B_0x2 + Pull-down + 0x2 + + + + + + + GPIOH_IDR + GPIOH_IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFF0000 + + + ID0 + Port x input data I/O pin y + + 0 + 1 + read-only + + + ID1 + Port x input data I/O pin y + + 1 + 1 + read-only + + + ID2 + Port x input data I/O pin y + + 2 + 1 + read-only + + + ID3 + Port x input data I/O pin y + + 3 + 1 + read-only + + + ID4 + Port x input data I/O pin y + + 4 + 1 + read-only + + + ID5 + Port x input data I/O pin y + + 5 + 1 + read-only + + + ID6 + Port x input data I/O pin y + + 6 + 1 + read-only + + + ID7 + Port x input data I/O pin y + + 7 + 1 + read-only + + + ID8 + Port x input data I/O pin y + + 8 + 1 + read-only + + + ID9 + Port x input data I/O pin y + + 9 + 1 + read-only + + + ID10 + Port x input data I/O pin y + + 10 + 1 + read-only + + + ID11 + Port x input data I/O pin y + + 11 + 1 + read-only + + + ID12 + Port x input data I/O pin y + + 12 + 1 + read-only + + + ID13 + Port x input data I/O pin y + + 13 + 1 + read-only + + + ID14 + Port x input data I/O pin y + + 14 + 1 + read-only + + + ID15 + Port x input data I/O pin y + + 15 + 1 + read-only + + + + + GPIOH_ODR + GPIOH_ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OD0 + Port output data I/O pin y + + 0 + 1 + read-write + + + OD1 + Port output data I/O pin y + + 1 + 1 + read-write + + + OD2 + Port output data I/O pin y + + 2 + 1 + read-write + + + OD3 + Port output data I/O pin y + + 3 + 1 + read-write + + + OD4 + Port output data I/O pin y + + 4 + 1 + read-write + + + OD5 + Port output data I/O pin y + + 5 + 1 + read-write + + + OD6 + Port output data I/O pin y + + 6 + 1 + read-write + + + OD7 + Port output data I/O pin y + + 7 + 1 + read-write + + + OD8 + Port output data I/O pin y + + 8 + 1 + read-write + + + OD9 + Port output data I/O pin y + + 9 + 1 + read-write + + + OD10 + Port output data I/O pin y + + 10 + 1 + read-write + + + OD11 + Port output data I/O pin y + + 11 + 1 + read-write + + + OD12 + Port output data I/O pin y + + 12 + 1 + read-write + + + OD13 + Port output data I/O pin y + + 13 + 1 + read-write + + + OD14 + Port output data I/O pin y + + 14 + 1 + read-write + + + OD15 + Port output data I/O pin y + + 15 + 1 + read-write + + + + + GPIOH_BSRR + GPIOH_BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BS0 + Port x set I/O pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS1 + Port x set I/O pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS2 + Port x set I/O pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS3 + Port x set I/O pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS4 + Port x set I/O pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS5 + Port x set I/O pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS6 + Port x set I/O pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS7 + Port x set I/O pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS8 + Port x set I/O pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS9 + Port x set I/O pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS10 + Port x set I/O pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS11 + Port x set I/O pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS12 + Port x set I/O pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS13 + Port x set I/O pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS14 + Port x set I/O pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BS15 + Port x set I/O pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Sets the corresponding ODy bit + 0x1 + + + + + BR0 + Port x reset I/O pin y + + 16 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset I/O pin y + + 17 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset I/O pin y + + 18 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset I/O pin y + + 19 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset I/O pin y + + 20 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset I/O pin y + + 21 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset I/O pin y + + 22 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset I/O pin y + + 23 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset I/O pin y + + 24 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset I/O pin y + + 25 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset I/O pin y + + 26 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset I/O pin y + + 27 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset I/O pin y + + 28 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset I/O pin y + + 29 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset I/O pin y + + 30 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset I/O pin y + + 31 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Resets the corresponding ODy bit + 0x1 + + + + + + + GPIOH_LCKR + GPIOH_LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK0 + Port x lock I/O pin y + + 0 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK1 + Port x lock I/O pin y + + 1 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK2 + Port x lock I/O pin y + + 2 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK3 + Port x lock I/O pin y + + 3 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK4 + Port x lock I/O pin y + + 4 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK5 + Port x lock I/O pin y + + 5 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK6 + Port x lock I/O pin y + + 6 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK7 + Port x lock I/O pin y + + 7 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK8 + Port x lock I/O pin y + + 8 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK9 + Port x lock I/O pin y + + 9 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK10 + Port x lock I/O pin y + + 10 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK11 + Port x lock I/O pin y + + 11 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK12 + Port x lock I/O pin y + + 12 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK13 + Port x lock I/O pin y + + 13 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK14 + Port x lock I/O pin y + + 14 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCK15 + Port x lock I/O pin y + + 15 + 1 + read-write + + + B_0x0 + Port configuration not locked + 0x0 + + + B_0x1 + Port configuration locked + 0x1 + + + + + LCKK + Lock key + + 16 + 1 + read-write + + + B_0x0 + Port configuration lock key not active + 0x0 + + + B_0x1 + Port configuration lock key active. + 0x1 + + + + + + + GPIOH_AFRL + GPIOH_AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL0 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL1 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL2 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL3 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL4 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL5 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL6 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL7 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOH_AFRH + GPIOH_AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AFSEL8 + Alternate function selection for port x I/O pin y + + 0 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL9 + Alternate function selection for port x I/O pin y + + 4 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL10 + Alternate function selection for port x I/O pin y + + 8 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL11 + Alternate function selection for port x I/O pin y + + 12 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL12 + Alternate function selection for port x I/O pin y + + 16 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL13 + Alternate function selection for port x I/O pin y + + 20 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL14 + Alternate function selection for port x I/O pin y + + 24 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + AFSEL15 + Alternate function selection for port x I/O pin y + + 28 + 4 + read-write + + + B_0x0 + AF0 + 0x0 + + + B_0x1 + AF1 + 0x1 + + + B_0x2 + AF2 + 0x2 + + + B_0x3 + AF3 + 0x3 + + + B_0x4 + AF4 + 0x4 + + + B_0x5 + AF5 + 0x5 + + + B_0x6 + AF6 + 0x6 + + + B_0x7 + AF7 + 0x7 + + + B_0x8 + AF8 + 0x8 + + + B_0x9 + AF9 + 0x9 + + + B_0xA + AF10 + 0xA + + + B_0xB + AF11 + 0xB + + + B_0xC + AF12 + 0xC + + + B_0xD + AF13 + 0xD + + + B_0xE + AF14 + 0xE + + + B_0xF + AF15 + 0xF + + + + + + + GPIOH_BRR + GPIOH_BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + BR0 + Port x reset IO pin y + + 0 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR1 + Port x reset IO pin y + + 1 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR2 + Port x reset IO pin y + + 2 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR3 + Port x reset IO pin y + + 3 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR4 + Port x reset IO pin y + + 4 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR5 + Port x reset IO pin y + + 5 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR6 + Port x reset IO pin y + + 6 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR7 + Port x reset IO pin y + + 7 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR8 + Port x reset IO pin y + + 8 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR9 + Port x reset IO pin y + + 9 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR10 + Port x reset IO pin y + + 10 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR11 + Port x reset IO pin y + + 11 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR12 + Port x reset IO pin y + + 12 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR13 + Port x reset IO pin y + + 13 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR14 + Port x reset IO pin y + + 14 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + BR15 + Port x reset IO pin y + + 15 + 1 + write-only + + + B_0x0 + No action on the corresponding ODy bit + 0x0 + + + B_0x1 + Reset the corresponding ODy bit + 0x1 + + + + + + + GPIOH_HSLVR + GPIOH_HSLVR + GPIO high-speed low-voltage register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSLV0 + Port x high-speed low-voltage configuration + + 0 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV1 + Port x high-speed low-voltage configuration + + 1 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV2 + Port x high-speed low-voltage configuration + + 2 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV3 + Port x high-speed low-voltage configuration + + 3 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV4 + Port x high-speed low-voltage configuration + + 4 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV5 + Port x high-speed low-voltage configuration + + 5 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV6 + Port x high-speed low-voltage configuration + + 6 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV7 + Port x high-speed low-voltage configuration + + 7 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV8 + Port x high-speed low-voltage configuration + + 8 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV9 + Port x high-speed low-voltage configuration + + 9 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV10 + Port x high-speed low-voltage configuration + + 10 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV11 + Port x high-speed low-voltage configuration + + 11 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV12 + Port x high-speed low-voltage configuration + + 12 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV13 + Port x high-speed low-voltage configuration + + 13 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV14 + Port x high-speed low-voltage configuration + + 14 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + HSLV15 + Port x high-speed low-voltage configuration + + 15 + 1 + read-write + + + B_0x0 + I/O speed optimization disabled + 0x0 + + + B_0x1 + I/O speed optimization enabled + 0x1 + + + + + + + GPIOH_SECCFGR + GPIOH_SECCFGR + GPIO secure configuration register + 0x30 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + SEC0 + I/O pin of Port x secure bit enable y + + 0 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC1 + I/O pin of Port x secure bit enable y + + 1 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC2 + I/O pin of Port x secure bit enable y + + 2 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC3 + I/O pin of Port x secure bit enable y + + 3 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC4 + I/O pin of Port x secure bit enable y + + 4 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC5 + I/O pin of Port x secure bit enable y + + 5 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC6 + I/O pin of Port x secure bit enable y + + 6 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC7 + I/O pin of Port x secure bit enable y + + 7 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC8 + I/O pin of Port x secure bit enable y + + 8 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC9 + I/O pin of Port x secure bit enable y + + 9 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC10 + I/O pin of Port x secure bit enable y + + 10 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC11 + I/O pin of Port x secure bit enable y + + 11 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC12 + I/O pin of Port x secure bit enable y + + 12 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC13 + I/O pin of Port x secure bit enable y + + 13 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC14 + I/O pin of Port x secure bit enable y + + 14 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + SEC15 + I/O pin of Port x secure bit enable y + + 15 + 1 + read-write + + + B_0x0 + The I/O pin is non-secure + 0x0 + + + B_0x1 + The I/O pin is secure. + 0x1 + + + + + + + + + GPIOH_S + 0X52021C00 + + + GTZC1_TZIC + GTZC1_MPCBBz register block + GTZC1 + 0x40032400 + + 0x0 + 0x30 + registers + + + GTZC + GTZC global interrupt + 8 + + + + GTZC1_TZIC_IER1 + GTZC1_TZIC_IER1 + GTZC1 TZIC interrupt enable register 1 + GTZC1_TZSC_CR + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM2IE + illegal access interrupt enable for TIM2 + 0 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM3IE + illegal access interrupt enable for TIM3 + 1 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM4IE + illegal access interrupt enable for TIM4 + 2 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM5IE + illegal access interrupt enable for TIM5 + 3 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM6IE + illegal access interrupt enable for TIM6 + 4 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM7IE + illegal access interrupt enable for TIM7 + 5 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM12IE + illegal access interrupt enable for TIM12 + 6 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + WWDGIE + illegal access interrupt enable for WWDG + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + IWDGIE + illegal access interrupt enable for IWDG + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SPI2IE + illegal access interrupt enable for SPI2 + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SPI3IE + illegal access interrupt enable for SPI3 + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USART2IE + illegal access interrupt enable for USART2 + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USART3IE + illegal access interrupt enable for USART3 + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UART4IE + illegal access interrupt enable for UART4 + 15 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UART5IE + illegal access interrupt enable for UART5 + 16 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + I2C1IE + illegal access interrupt enable for I2C1 + 17 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + I2C2IE + illegal access interrupt enable for I2C2 + 18 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + I3C1IE + illegal access interrupt enable for I3C1 + 19 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + CRSIE + illegal access interrupt enable for CRS + 20 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USART6IE + illegal access interrupt enable for USART6 + 21 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USART10IE + illegal access interrupt enable for USART10 + 22 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USART11IE + illegal access interrupt enable for USART11 + 23 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HDMICECIE + illegal access interrupt enable for HDMICEC + 24 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DAC1IE + illegal access interrupt enable for DAC1 + 25 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UART7IE + illegal access interrupt enable for UART7 + 26 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UART8IE + illegal access interrupt enable for UART8 + 27 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UART9IE + illegal access interrupt enable for UART9 + 28 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UART12IE + illegal access interrupt enable for UART12 + 29 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DTSIE + illegal access interrupt enable for DTS + 30 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPTIM2IE + illegal access interrupt enable for LPTIM2 + 31 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + + + GTZC1_TZIC_IER2 + GTZC1_TZIC_IER2 + GTZC1 TZIC interrupt enable register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FDCAN1IE + illegal access interrupt enable for FDCAN1 + 0 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FDCAN2IE + illegal access interrupt enable for FDCAN2 + 1 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + UCPDIE + illegal access interrupt enable for UCPD + 2 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM1IE + illegal access interrupt enable for TIM1 + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SPI1IE + illegal access interrupt enable for SPI1 + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM8IE + illegal access interrupt enable for TIM8 + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USART1IE + illegal access interrupt enable for USART1 + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TIM15IE + illegal access interrupt enable for TIM15 + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SPI4IE + illegal access interrupt enable for SPI4 + 15 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SPI6IE + illegal access interrupt enable for SPI6 + 16 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SAI1IE + illegal access interrupt enable for SAI1 + 17 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SAI2IE + illegal access interrupt enable for SAI2 + 18 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + USBIE + illegal access interrupt enable for USB + 19 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPUART1IE + illegal access interrupt enable for LPUART + 25 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + I2C3IE + illegal access interrupt enable for I2C3 + 26 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPTIM1IE + illegal access interrupt enable for LPTIM1 + 28 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPTIM3IE + illegal access interrupt enable for LPTIM3 + 29 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPTIM4IE + illegal access interrupt enable for LPTIM4 + 30 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + LPTIM5IE + illegal access interrupt enable for LPTIM5 + 31 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + + + GTZC1_TZIC_IER3 + GTZC1_TZIC_IER3 + GTZC1 TZIC interrupt enable register 3 + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LPTIM6IE + illegal access interrupt enable for LPTIM6 + 0 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + VREFBUFIE + illegal access interrupt enable for VREFBUF + 1 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + I3C2IE + illegal access interrupt enable for I3C2 + 2 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + CRCIE + illegal access interrupt enable for CRC + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + CORDICIE + illegal access interrupt enable for CORDIC + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FMACIE + illegal access interrupt enable for FMAC + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ETHIE + illegal access interrupt enable for register of ETH + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ICACHEIE + illegal access interrupt enable for ICACHE + 12 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DCACHEIE + illegal access interrupt enable for DCACHE + 13 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ADC12IE + illegal access interrupt enable for ADC1 and ADC2 + 14 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DCMIIE + illegal access interrupt enable for DCMI + 15 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + AESIE + illegal access interrupt enable for AES + 16 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HASHIE + illegal access interrupt enable for HASH + 17 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RNGIE + illegal access interrupt enable for RNG + 18 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SAESIE + illegal access interrupt enable for SAES + 19 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + PKAIE + illegal access interrupt enable for PKA + 20 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SDMMC1IE + illegal access interrupt enable for SDMMC1 + 21 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FMCIE + illegal access interrupt enable for FMC + 23 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + OCTOSPI1IE + illegal access interrupt enable for OCTOSPI1 + 24 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RAMCFGIE + illegal access interrupt enable for RAMSCFG + 26 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + + + GTZC1_TZIC_IER4 + GTZC1_TZIC_IER4 + GTZC1 TZIC interrupt enable register 4 + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + GPDMA1IE + illegal access interrupt enable for GPDMA1 + 0 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + GPDMA2IE + illegal access interrupt enable for GPDMA2 + 1 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FLASH_REGIE + illegal access interrupt enable for FLASH registers + 2 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FLASHIE + illegal access interrupt enable for FLASH memory + 3 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + OTFDEC1IE + illegal access interrupt enable for OTFDEC1 + 4 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SBSIE + illegal access interrupt enable for SBS + 6 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RTCIE + illegal access interrupt enable for RTC + 7 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TAMPIE + illegal access interrupt enable for TAMP + 8 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + PWRIE + illegal access interrupt enable for PWR + 9 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RCCIE + illegal access interrupt enable for RCC + 10 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + EXTIIE + illegal access interrupt enable for EXTI + 11 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TZSC1IE + illegal access interrupt enable for GTZC1 TZSC registers + 16 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TZIC1IE + illegal access interrupt enable for GTZC1 TZIC registers + 17 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + OCTOSPI1_MEMIE + illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank + 18 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FMC_MEMIE + illegal access interrupt enable for MPCWM2 (FMC_NOR bank), MPCWM3 (FMC_NAND bank and FMC_SDRAM bank 1), and MPCWM4 (FMC_SDRAM bank 2) + 19 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + BKPSRAMIE + illegal access interrupt enable for MPCWM4 (BKPSRAM) memory bank + 20 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SRAM1IE + illegal access interrupt enable for SRAM1 + 24 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + MPCBB1_REGIE + illegal access interrupt enable for MPCBB1 registers + 25 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SRAM2IE + illegal access interrupt enable for SRAM2 + 26 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + MPCBB2_REGIE + illegal access interrupt enable for MPCBB2 registers + 27 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SRAM3IE + illegal access interrupt enable for SRAM3 + 28 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + MPCBB3_REGIE + illegal access interrupt enable for MPCBB3 registers + 29 + 1 + read-write + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + + + GTZC1_TZIC_SR1 + GTZC1_TZIC_SR1 + GTZC1 TZIC status register 1 + GTZC1_TZSC_SECCFGR1 + 0x010 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TIM2F + illegal access flag for TIM2 + 0 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM3F + illegal access flag for TIM3 + 1 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM4F + illegal access flag for TIM4 + 2 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM5F + illegal access flag for TIM5 + 3 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM6F + illegal access flag for TIM6 + 4 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM7F + illegal access flag for TIM7 + 5 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM12F + illegal access flag for TIM12 + 6 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + WWDGF + illegal access flag for WWDG + 9 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + IWDGF + illegal access flag for IWDG + 10 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SPI2F + illegal access flag for SPI2 + 11 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SPI3F + illegal access flag for SPI3 + 12 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USART2F + illegal access flag for USART2 + 13 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USART3F + illegal access flag for USART3 + 14 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UART4F + illegal access flag for UART4 + 15 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UART5F + illegal access flag for UART5 + 16 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + I2C1F + illegal access flag for I2C1 + 17 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + I2C2F + illegal access flag for I2C2 + 18 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + I3C1F + illegal access flag for I3C1 + 19 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + CRSF + illegal access flag for CRS + 20 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USART6F + illegal access flag for USART6 + 21 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USART10F + illegal access flag for USART10 + 22 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USART11F + illegal access flag for USART11 + 23 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + HDMICECF + illegal access flag for HDMICEC + 24 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + DAC1F + illegal access flag for DAC1 + 25 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UART7F + illegal access flag for UART7 + 26 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UART8F + illegal access flag for UART8 + 27 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UART9F + illegal access flag for UART9 + 28 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UART12F + illegal access flag for UART12 + 29 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + DTSF + illegal access flag for DTS + 30 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + LPTIM2F + illegal access flag for LPTIM2 + 31 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + + + GTZC1_TZIC_SR2 + GTZC1_TZIC_SR2 + GTZC1 TZIC status register 2 + GTZC1_TZSC_SECCFGR2 + 0x014 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + FDCAN1F + illegal access flag for FDCAN1 + 0 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + FDCAN2F + illegal access flag for FDCAN2 + 1 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + UCPDF + illegal access flag for UCPD + 2 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM1F + illegal access flag for TIM1 + 8 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SPI1F + illegal access flag for SPI1 + 9 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM8F + illegal access flag for TIM8 + 10 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USART1F + illegal access flag for USART1 + 11 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TIM15F + illegal access flag for TIM15 + 12 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SPI4F + illegal access flag for SPI4 + 15 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SPI6F + illegal access flag for SPI6 + 16 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SAI1F + illegal access flag for SAI1 + 17 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SAI2F + illegal access flag for SAI2 + 18 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + USBF + illegal access flag for USB + 19 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + LPUART1F + illegal access flag for LPUART + 25 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + I2C3F + illegal access flag for I2C3 + 26 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + LPTIM1F + illegal access flag for LPTIM1 + 28 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + LPTIM3F + illegal access flag for LPTIM3 + 29 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + LPTIM4F + illegal access flag for LPTIM4 + 30 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + LPTIM5F + illegal access flag for LPTIM5 + 31 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + + + GTZC1_TZIC_SR3 + GTZC1_TZIC_SR3 + GTZC1 TZIC status register 3 + GTZC1_TZSC_SECCFGR3 + 0x018 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + LPTIM6F + illegal access flag for LPTIM6 + 0 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + VREFBUFF + illegal access flag for VREFBUF + 1 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + I3C2F + illegal access flag for I3C2 + 2 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + CRCF + illegal access flag for CRC + 8 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + CORDICF + illegal access flag for CORDIC + 9 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + FMACF + illegal access flag for FMAC + 10 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + ETHF + illegal access flag for register of ETH + 11 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + ICACHEF + illegal access flag for ICACHE + 12 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + DCACHEF + illegal access flag for DCACHE + 13 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + ADC12F + illegal access flag for ADC1 and ADC2 + 14 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + DCMIF + illegal access flag for DCMI + 15 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + AESF + illegal access flag for AES + 16 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + HASHF + illegal access flag for HASH + 17 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + RNGF + illegal access flag for RNG + 18 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SAESF + illegal access flag for SAES + 19 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + PKAF + illegal access flag for PKA + 20 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SDMMC1F + illegal access flag for SDMMC1 + 21 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + FMCF + illegal access flag for FMC + 23 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + OCTOSPI1F + illegal access flag for OCTOSPI1 + 24 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + RAMCFGF + illegal access flag for RAMSCFG + 26 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + + + GTZC1_TZIC_SR4 + GTZC1_TZIC_SR4 + GTZC1 TZIC status register 4 + 0x01C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + GPDMA1F + illegal access flag for GPDMA1 + 0 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + GPDMA2F + illegal access flag for GPDMA2 + 1 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + FLASH_REGF + illegal access flag for FLASH registers + 2 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + FLASHF + illegal access flag for FLASH memory + 3 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + OTFDEC1F + illegal access flag for OTFDEC1 + 4 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SBSF + illegal access flag for SBS + 6 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + RTCF + illegal access flag for RTC + 7 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TAMPF + illegal access flag for TAMP + 8 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + PWRF + illegal access flag for PWR + 9 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + RCCF + illegal access flag for RCC + 10 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + EXTIF + illegal access flag for EXTI + 11 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TZSC1F + illegal access flag for GTZC1 TZSC registers + 16 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + TZIC1F + illegal access flag for GTZC1 TZIC registers + 17 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + OCTOSPI1_MEMF + illegal access flag for MPCWM1 (OCTOSPI1) memory bank + 18 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + FMC_MEMF + illegal access flag for MPCWM2 (FMC_NOR bank), MPCWM3 (FMC_NAND bank and FMC_SDRAM bank 1), and MPCWM4 (FMC_SDRAM bank 2) + 19 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + BKPSRAMF + illegal access flag for MPCWM4 (BKPSRAM) memory bank + 20 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SRAM1F + illegal access flag for SRAM1 + 24 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + MPCBB1_REGF + illegal access flag for MPCBB1 registers + 25 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SRAM2F + illegal access flag for SRAM2 + 26 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + MPCBB2_REGF + illegal access flag for MPCBB2 registers + 27 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + SRAM3F + illegal access flag for SRAM3 + 28 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + MPCBB3_REGF + illegal access flag for MPCBB3 registers + 29 + 1 + read-only + + + B_0x0 + no illegal access event + 0x0 + + + B_0x1 + illegal access event + 0x1 + + + + + + + GTZC1_TZIC_FCR1 + GTZC1_TZIC_FCR1 + GTZC1 TZIC flag clear register 1 + GTZC1_TZSC_PRIVCFGR1 + 0x020 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CTIM2F + clear the illegal access flag for TIM2 + 0 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM3F + clear the illegal access flag for TIM3 + 1 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM4F + clear the illegal access flag for TIM4 + 2 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM5F + clear the illegal access flag for TIM5 + 3 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM6F + clear the illegal access flag for TIM6 + 4 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM7F + clear the illegal access flag for TIM7 + 5 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM12F + clear the illegal access flag for TIM12 + 6 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM13F + clear the illegal access flag for TIM13 + 7 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM14F + clear the illegal access flag for TIM14 + 8 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CWWDGF + clear the illegal access flag for WWDG + 9 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CIWDGF + clear the illegal access flag for IWDG + 10 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSPI2F + clear the illegal access flag for SPI2 + 11 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSPI3F + clear the illegal access flag for SPI3 + 12 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSART2F + clear the illegal access flag for USART2 + 13 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSART3F + clear the illegal access flag for USART3 + 14 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUART4F + clear the illegal access flag for UART4 + 15 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUART5F + clear the illegal access flag for UART5 + 16 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CI2C1F + clear the illegal access flag for I2C1 + 17 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CI2C2F + clear the illegal access flag for I2C2 + 18 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CI3C1F + clear the illegal access flag for I3C1 + 19 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CCRSF + clear the illegal access flag for CRS + 20 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSART6F + clear the illegal access flag for USART6 + 21 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSART10F + clear the illegal access flag for USART10 + 22 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSART11F + clear the illegal access flag for USART11 + 23 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CHDMICECF + clear the illegal access flag for HDMICEC + 24 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CDAC1F + clear the illegal access flag for DAC1 + 25 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUART7F + clear the illegal access flag for UART7 + 26 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUART8F + clear the illegal access flag for UART8 + 27 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUART9F + clear the illegal access flag for UART9 + 28 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUART12F + clear the illegal access flag for UART12 + 29 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CDTSF + clear the illegal access flag for DTS + 30 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CLPTIM2F + clear the illegal access flag for LPTIM2 + 31 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + + + GTZC1_TZIC_FCR2 + GTZC1_TZIC_FCR2 + GTZC1 TZIC flag clear register 2 + GTZC1_TZSC_PRIVCFGR2 + 0x024 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CFDCAN1F + clear the illegal access flag for FDCAN1 + 0 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CFDCAN2F + clear the illegal access flag for FDCAN2 + 1 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUCPDF + clear the illegal access flag for UCPD + 2 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM1F + clear the illegal access flag for TIM1 + 8 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSPI1F + clear the illegal access flag for SPI1 + 9 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM8F + clear the illegal access flag for TIM8 + 10 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSART1F + clear the illegal access flag for USART1 + 11 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM15F + clear the illegal access flag for TIM15 + 12 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM16F + clear the illegal access flag for TIM16 + 13 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTIM17F + clear the illegal access flag for TIM17 + 14 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSPI4F + clear the illegal access flag for SPI4 + 15 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSPI6F + clear the illegal access flag for SPI6 + 16 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSAI1F + clear the illegal access flag for SAI1 + 17 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSAI2F + clear the illegal access flag for SAI2 + 18 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CUSBF + clear the illegal access flag for USB + 19 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSPI5F + clear the illegal access flag for SPI5 + 24 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CLPUART1F + clear the illegal access flag for LPUART + 25 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CI2C3F + clear the illegal access flag for I2C3 + 26 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CI2C4F + clear the illegal access flag for I2C4 + 27 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CLPTIM1F + clear the illegal access flag for LPTIM1 + 28 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CLPTIM3F + clear the illegal access flag for LPTIM3 + 29 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CLPTIM4F + clear the illegal access flag for LPTIM4 + 30 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CLPTIM5F + clear the illegal access flag for LPTIM5 + 31 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + + + GTZC1_TZIC_FCR3 + GTZC1_TZIC_FCR3 + GTZC1 TZIC flag clear register 3 + GTZC1_TZSC_PRIVCFGR3 + 0x028 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CLPTIM6F + clear illegal access flag for LPTIM6 + 0 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CVREFBUFF + clear illegal access flag for VREFBUF + 1 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CI3C2F + clear illegal access flag for I3C2 + 2 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CCRCF + clear illegal access flag for CRC + 8 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CCORDICF + clear illegal access flag for CORDIC + 9 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CFMACF + clear illegal access flag for FMAC + 10 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CETHF + clear illegal access flag for register of ETH + 11 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CICACHEF + clear illegal access flag for ICACHE + 12 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CDCACHEF + clear illegal access flag for DCACHE + 13 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CADC12F + clear illegal access flag for ADC1 and ADC2 + 14 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CDCMIF + clear illegal access flag for DCMI + 15 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CAESF + clear illegal access flag for AES + 16 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CHASHF + clear illegal access flag for HASH + 17 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CRNGF + clear illegal access flag for RNG + 18 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSAESF + clear illegal access flag for SAES + 19 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CPKAF + clear illegal access flag for PKA + 20 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSDMMC1F + clear illegal access flag for SDMMC1 + 21 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSDMMC2F + clear illegal access flag for SDMMC2 + 22 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CFMCF + clear illegal access flag for FMC + 23 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + COCTOSPI1F + clear illegal access flag for OCTOSPI1 + 24 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CRAMCFGF + clear illegal access flag for RAMSCFG + 26 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + + + GTZC1_TZIC_FCR4 + GTZC1_TZIC_FCR4 + GTZC1 TZIC flag clear register 4 + 0x02C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CGPDMA1F + clear the illegal access flag for GPDMA1 + 0 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CGPDMA2F + clear the illegal access flag for GPDMA2 + 1 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CFLASH_REGF + clear the illegal access flag for FLASH registers + 2 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CFLASHF + clear the illegal access flag for FLASH memory + 3 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + COTFDEC1F + clear the illegal access flag for OTFDEC1 + 4 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSBSF + clear the illegal access flag for SBS + 6 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CRTCF + clear the illegal access flag for RTC + 7 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTAMPF + clear the illegal access flag for TAMP + 8 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CPWRF + clear the illegal access flag for PWR + 9 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CRCCF + clear the illegal access flag for RCC + 10 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CEXTIF + clear the illegal access flag for EXTI + 11 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTZSC1F + clear the illegal access flag for GTZC1 TZSC registers + 16 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CTZIC1F + clear the illegal access flag for GTZC1 TZIC registers + 17 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + COCTOSPI1_MEMF + clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank + 18 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CFMC_MEMF + clear the illegal access flag for MPCWM2 (FMC_NOR bank), MPCWM3 (FMC_NAND bank and FMC_SDRAM bank 1), and MPCWM4 (FMC_SDRAM bank 2) + 19 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CBKPSRAMF + clear the illegal access flag for MPCWM4 (BKPSRAM) memory bank + 20 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSRAM1F + clear the illegal access flag for SRAM1 + 24 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CMPCBB1_REGF + clear the illegal access flag for MPCBB1 registers + 25 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSRAM2F + clear the illegal access flag for SRAM2 + 26 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CMPCBB2_REGF + clear the illegal access flag for MPCBB2 registers + 27 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CSRAM3F + clear the illegal access flag for SRAM3 + 28 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + CMPCBB3_REGF + clear the illegal access flag for MPCBB3 registers + 29 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + status flag cleared + 0x1 + + + + + + + + + GTZC1_TZIC_S + 0X50032400 + + + GTZC1_TZSC + GTZC1_MPCBBz register block + GTZC1 + 0x40036400 + + 0x0 + 0x80 + registers + + + + GTZC1_TZSC_CR + GTZC1_TZSC_CR + GTZC1 TZSC control register + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCK + lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx until next reset + + 0 + 1 + read-write + + + B_0x0 + configuration of all GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx not locked + 0x0 + + + B_0x1 + configuration of all GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx locked + 0x1 + + + + + + + GTZC1_TZSC_SECCFGR1 + GTZC1_TZSC_SECCFGR1 + GTZC1 TZSC secure configuration register 1 + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM2SEC + secure access mode for TIM2 + 0 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM3SEC + secure access mode for TIM3 + 1 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM4SEC + secure access mode for TIM4 + 2 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM5SEC + secure access mode for TIM5 + 3 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM6SEC + secure access mode for TIM6 + 4 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM7SEC + secure access mode for TIM7 + 5 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM12SEC + secure access mode for TIM12 + 6 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + WWDGSEC + secure access mode for WWDG + 9 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + IWDGSEC + secure access mode for IWDG + 10 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SPI2SEC + secure access mode for SPI2 + 11 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SPI3SEC + secure access mode for SPI3 + 12 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USART2SEC + secure access mode for USART2 + 13 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USART3SEC + secure access mode for USART3 + 14 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UART4SEC + secure access mode for UART4 + 15 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UART5SEC + secure access mode for UART5 + 16 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + I2C1SEC + secure access mode for I2C1 + 17 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + I2C2SEC + secure access mode for I2C2 + 18 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + I3C1SEC + secure access mode for I3C1 + 19 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + CRSSEC + secure access mode for CRS + 20 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USART6SEC + secure access mode for USART6 + 21 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USART10SEC + secure access mode for USART10 + 22 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USART11SEC + secure access mode for USART11 + 23 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + HDMICECSEC + secure access mode for HDMICEC + 24 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + DAC1SEC + secure access mode for DAC1 + 25 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UART7SEC + secure access mode for UART7 + 26 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UART8SEC + secure access mode for UART8 + 27 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UART9SEC + secure access mode for UART9 + 28 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UART12SEC + secure access mode for UART12 + 29 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + DTSSEC + secure access mode for DTS + 30 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LPTIM2SEC + secure access mode for LPTIM2 + 31 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + + + GTZC1_TZSC_SECCFGR2 + GTZC1_TZSC_SECCFGR2 + GTZC1 TZSC secure configuration register 2 + 0x014 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FDCAN1SEC + secure access mode for FDCAN1 + 0 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + FDCAN2SEC + secure access mode for FDCAN2 + 1 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + UCPDSEC + secure access mode for UCPD + 2 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM1SEC + secure access mode for TIM1 + 8 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SPI1SEC + secure access mode for SPI1 + 9 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM8SEC + secure access mode for TIM8 + 10 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USART1SEC + secure access mode for USART1 + 11 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + TIM15SEC + secure access mode for TIM15 + 12 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SPI4SEC + secure access mode for SPI4 + 15 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SPI6SEC + secure access mode for SPI6 + 16 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SAI1SEC + secure access mode for SAI1 + 17 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SAI2SEC + secure access mode for SAI2 + 18 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + USBSEC + secure access mode for USB + 19 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LPUART1SEC + secure access mode for LPUART + 25 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + I2C3SEC + secure access mode for I2C3 + 26 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LPTIM1SEC + secure access mode for LPTIM1 + 28 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LPTIM3SEC + secure access mode for LPTIM3 + 29 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LPTIM4SEC + secure access mode for LPTIM4 + 30 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LPTIM5SEC + secure access mode for LPTIM5 + 31 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + + + GTZC1_TZSC_SECCFGR3 + GTZC1_TZSC_SECCFGR3 + GTZC1 TZSC secure configuration register 3 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LPTIM6SEC + secure access mode for LPTIM6 + 0 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + VREFBUFSEC + secure access mode for VREFBUF + 1 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + I3C2SEC + secure access mode for I3C2 + 2 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + CRCSEC + secure access mode for CRC + 8 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + CORDICSEC + secure access mode for CORDIC + 9 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + FMACSEC + secure access mode for FMAC + 10 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + ETHSEC + secure access mode for register of ETH + 11 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + ICACHESEC + secure access mode for ICACHE + 12 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + DCACHESEC + secure access mode for DCACHE + 13 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + ADC12SEC + secure access mode for ADC1 and ADC2 + 14 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + DCMISEC + secure access mode for DCMI + 15 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + AESSEC + secure access mode for AES + 16 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + HASHSEC + secure access mode for HASH + 17 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + RNGSEC + secure access mode for RNG + 18 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SAESSEC + secure access mode for SAES + 19 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PKASEC + secure access mode for PKA + 20 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SDMMC1SEC + secure access mode for SDMMC1 + 21 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + FMCSEC + secure access mode for FMC + 23 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + OCTOSPI1SEC + secure access mode for OCTOSPI1 + 24 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + RAMCFGSEC + secure access mode for RAMSCFG + 26 + 1 + read-write + + + B_0x0 + non-secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + + + GTZC1_TZSC_PRIVCFGR1 + GTZC1_TZSC_PRIVCFGR1 + GTZC1 TZSC privilege configuration register 1 + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM2PRIV + privileged access mode for TIM2 + 0 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM3PRIV + privileged access mode for TIM3 + 1 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM4PRIV + privileged access mode for TIM4 + 2 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM5PRIV + privileged access mode for TIM5 + 3 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM6PRIV + privileged access mode for TIM6 + 4 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM7PRIV + privileged access mode for TIM7 + 5 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + WWDGPRIV + privileged access mode for WWDG + 9 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + IWDGPRIV + privileged access mode for IWDG + 10 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SPI2PRIV + privileged access mode for SPI2 + 11 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SPI3PRIV + privileged access mode for SPI3 + 12 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USART2PRIV + privileged access mode for USART2 + 13 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USART3PRIV + privileged access mode for USART3 + 14 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UART4PRIV + privileged access mode for UART4 + 15 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UART5PRIV + privileged access mode for UART5 + 16 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + I2C1PRIV + privileged access mode for I2C1 + 17 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + I2C2PRIV + privileged access mode for I2C2 + 18 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + I3C1PRIV + privileged access mode for I3C1 + 19 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + CRSPRIV + privileged access mode for CRS + 20 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USART6PRIV + privileged access mode for USART6 + 21 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USART10PRIV + privileged access mode for USART10 + 22 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USART11PRIV + privileged access mode for USART11 + 23 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + HDMICECPRIV + privileged access mode for HDMICEC + 24 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + DAC1PRIV + privileged access mode for DAC1 + 25 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UART7PRIV + privileged access mode for UART7 + 26 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UART8PRIV + privileged access mode for UART8 + 27 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UART9PRIV + privileged access mode for UART9 + 28 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UART12PRIV + privileged access mode for UART12 + 29 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + DTSPRIV + privileged access mode for DTS + 30 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + LPTIM2PRIV + privileged access mode for LPTIM2 + 31 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + + + GTZC1_TZSC_PRIVCFGR2 + GTZC1_TZSC_PRIVCFGR2 + GTZC1 TZSC privilege configuration register 2 + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FDCAN1PRIV + privileged access mode for FDCAN1 + 0 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + FDCAN2PRIV + privileged access mode for FDCAN2 + 1 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + UCPDPRIV + privileged access mode for UCPD + 2 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM1PRIV + privileged access mode for TIM1 + 8 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SPI1PRIV + privileged access mode for SPI1 + 9 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM8PRIV + privileged access mode for TIM8 + 10 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USART1PRIV + privileged access mode for USART1 + 11 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM15PRIV + privileged access mode for TIM15 + 12 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + TIM16PRIV + privileged access mode for TIM16 + 13 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SPI4PRIV + privileged access mode for SPI4 + 15 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SPI6PRIV + privileged access mode for SPI6 + 16 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SAI1PRIV + privileged access mode for SAI1 + 17 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SAI2PRIV + privileged access mode for SAI2 + 18 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + USBPRIV + privileged access mode for USB + 19 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + LPUART1PRIV + privileged access mode for LPUART + 25 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + I2C3PRIV + privileged access mode for I2C3 + 26 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + LPTIM1PRIV + privileged access mode for LPTIM1 + 28 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + LPTIM3PRIV + privileged access mode for LPTIM3 + 29 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + LPTIM4PRIV + privileged access mode for LPTIM4 + 30 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + LPTIM5PRIV + privileged access mode for LPTIM5 + 31 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + + + GTZC1_TZSC_PRIVCFGR3 + GTZC1_TZSC_PRIVCFGR3 + GTZC1 TZSC privilege configuration register 3 + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LPTIM6PRIV + privileged access mode for LPTIM6 + 0 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + VREFBUFPRIV + privileged access mode for VREFBUF + 1 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + I3C2PRIV + privileged access mode for I3C2 + 2 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + CRCPRIV + privileged access mode for CRC + 8 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + CORDICPRIV + privileged access mode for CORDIC + 9 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + FMACPRIV + privileged access mode for FMAC + 10 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + ETHPRIV + privileged access mode for register of ETH + 11 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + ICACHEPRIV + privileged access mode for ICACHE + 12 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + DCACHEPRIV + privileged access mode for DCACHE + 13 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + ADC12PRIV + privileged access mode for ADC1 and ADC2 + 14 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + DCMIPRIV + privileged access mode for DCMI + 15 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + AESPRIV + privileged access mode for AES + 16 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + HASHPRIV + privileged access mode for HASH + 17 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + RNGPRIV + privileged access mode for RNG + 18 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SAESPRIV + privileged access mode for SAES + 19 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + PKAPRIV + privileged access mode for PKA + 20 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + SDMMC1PRIV + privileged access mode for SDMMC1 + 21 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + FMCPRIV + privileged access mode for FMC + 23 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + OCTOSPI1PRIV + privileged access mode for OCTOSPI1 + 24 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + RAMCFGPRIV + privileged access mode for RAMSCFG + 26 + 1 + read-write + + + B_0x0 + unprivileged + 0x0 + + + B_0x1 + privileged + 0x1 + + + + + + + GTZC1_TZSC_MPCWM1ACFGR + GTZC1_TZSC_MPCWM1ACFGR + GTZC1 TZSC memory 1 subregion A watermark configuration register + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion A enable + + 0 + 1 + read-write + + + B_0x0 + subregion A is disabled. + 0x0 + + + B_0x1 + subregion A of region x is enabled. + 0x1 + + + + + SRLOCK + subregion A lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion A of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion A of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion A of region x. + 0x1 + + + + + PRIV + Privileged subregion A of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion A. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion A of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM1AR + GTZC1_TZSC_MPCWM1AR + GTZC1 TZSC memory 1 subregion A watermark register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBA_START + Start of subregion A in region x + + 0 + 11 + read-write + + + SUBA_LENGTH + Length of subregion A in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM1BCFGR + GTZC1_TZSC_MPCWM1BCFGR + GTZC1 TZSC memory 1 subregion B watermark configuration register + 0x48 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion B enable + + 0 + 1 + read-write + + + B_0x0 + subregion B is disabled. + 0x0 + + + B_0x1 + subregion B of region B is enabled. + 0x1 + + + + + SRLOCK + subregion B lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion B of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion B of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion B of region x. + 0x1 + + + + + PRIV + Privileged subregion B of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion B. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion B of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM1BR + GTZC1_TZSC_MPCWM1BR + GTZC1 TZSC memory 1 subregion B watermark register + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBB_START + Start of subregion B in region x + + 0 + 11 + read-write + + + SUBB_LENGTH + Length of subregion B in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM2ACFGR + GTZC1_TZSC_MPCWM2ACFGR + GTZC1 TZSC memory 2 subregion A watermark configuration register + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion A enable + + 0 + 1 + read-write + + + B_0x0 + subregion A is disabled. + 0x0 + + + B_0x1 + subregion A of region x is enabled. + 0x1 + + + + + SRLOCK + subregion A lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion A of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion A of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion A of region x. + 0x1 + + + + + PRIV + Privileged subregion A of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion A. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion A of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM2AR + GTZC1_TZSC_MPCWM2AR + GTZC1 TZSC memory 2 subregion A watermark register + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBA_START + Start of subregion A in region x + + 0 + 11 + read-write + + + SUBA_LENGTH + Length of subregion A in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM2BCFGR + GTZC1_TZSC_MPCWM2BCFGR + GTZC1 TZSC memory 2 subregion B watermark configuration register + 0x58 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion B enable + + 0 + 1 + read-write + + + B_0x0 + subregion B is disabled. + 0x0 + + + B_0x1 + subregion B of region B is enabled. + 0x1 + + + + + SRLOCK + subregion B lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion B of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion B of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion B of region x. + 0x1 + + + + + PRIV + Privileged subregion B of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion B. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion B of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM2BR + GTZC1_TZSC_MPCWM2BR + GTZC1 TZSC memory 2 subregion B watermark register + 0x5C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBB_START + Start of subregion B in region x + + 0 + 11 + read-write + + + SUBB_LENGTH + Length of subregion B in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM3ACFGR + GTZC1_TZSC_MPCWM3ACFGR + GTZC1 TZSC memory 3 subregion A watermark configuration register + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion A enable + + 0 + 1 + read-write + + + B_0x0 + subregion A is disabled. + 0x0 + + + B_0x1 + subregion A of region x is enabled. + 0x1 + + + + + SRLOCK + subregion A lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion A of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion A of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion A of region x. + 0x1 + + + + + PRIV + Privileged subregion A of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion A. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion A of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM3AR + GTZC1_TZSC_MPCWM3AR + GTZC1 TZSC memory 3 subregion A watermark register + 0x64 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBA_START + Start of subregion A in region x + + 0 + 11 + read-write + + + SUBA_LENGTH + Length of subregion A in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM3BCFGR + GTZC1_TZSC_MPCWM3BCFGR + GTZC1 TZSC memory 3 subregion B watermark configuration register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion B enable + + 0 + 1 + read-write + + + B_0x0 + subregion B is disabled. + 0x0 + + + B_0x1 + subregion B of region B is enabled. + 0x1 + + + + + SRLOCK + subregion B lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion B of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion B of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion B of region x. + 0x1 + + + + + PRIV + Privileged subregion B of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion B. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion B of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM3BR + GTZC1_TZSC_MPCWM3BR + GTZC1 TZSC memory 3 subregion B watermark register + 0x6C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBB_START + Start of subregion B in region x + + 0 + 11 + read-write + + + SUBB_LENGTH + Length of subregion B in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM4ACFGR + GTZC1_TZSC_MPCWM4ACFGR + GTZC1 TZSC memory 4 subregion A watermark configuration register + 0x70 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion A enable + + 0 + 1 + read-write + + + B_0x0 + subregion A is disabled. + 0x0 + + + B_0x1 + subregion A of region x is enabled. + 0x1 + + + + + SRLOCK + subregion A lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion A of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion A of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion A of region x. + 0x1 + + + + + PRIV + Privileged subregion A of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion A. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion A of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM4AR + GTZC1_TZSC_MPCWM4AR + GTZC1 TZSC memory 4 subregion A watermark register + 0x74 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBA_START + Start of subregion A in region x + + 0 + 11 + read-write + + + SUBA_LENGTH + Length of subregion A in region x + + 16 + 12 + read-write + + + + + GTZC1_TZSC_MPCWM4BCFGR + GTZC1_TZSC_MPCWM4BCFGR + GTZC1 TZSC memory 4 subregion B watermark configuration register + 0x78 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SREN + subregion B enable + + 0 + 1 + read-write + + + B_0x0 + subregion B is disabled. + 0x0 + + + B_0x1 + subregion B of region B is enabled. + 0x1 + + + + + SRLOCK + subregion B lock + + 1 + 1 + read-write + + + B_0x0 + GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. + 0x0 + + + B_0x1 + Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. + 0x1 + + + + + SEC + Secure subregion B of base region x + + 8 + 1 + read-write + + + B_0x0 + Only non-secure data accesses are granted to subregion B of region x. + 0x0 + + + B_0x1 + Only secure data accesses are granted to subregion B of region x. + 0x1 + + + + + PRIV + Privileged subregion B of base region x + + 9 + 1 + read-write + + + B_0x0 + Privileged and unprivileged accesses are granted in subregion B. + 0x0 + + + B_0x1 + Only privileged accesses are granted in subregion B of region x. + 0x1 + + + + + + + GTZC1_TZSC_MPCWM4BR + GTZC1_TZSC_MPCWM4BR + GTZC1 TZSC memory 4 subregion B watermark register + 0x7C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUBB_START + Start of subregion B in region x + + 0 + 11 + read-write + + + SUBB_LENGTH + Length of subregion B in region x + + 16 + 12 + read-write + + + + + + + GTZC1_TZSC_S + 0x50036400 + + + HASH + HASH register bank + HASH + 0x420c0400 + + 0x0 + 0x400 + registers + + + HASH + HASH interrupt + 117 + + + + HASH_CR + HASH_CR + HASH control register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + INIT + Initialize message digest calculation + + 2 + 1 + read-write + + + DMAE + DMA enable + + 3 + 1 + read-write + + + B_0x0 + DMA transfers disabled + 0x0 + + + B_0x1 + DMA transfers enabled. + 0x1 + + + + + DATATYPE + Data type selection + + 4 + 2 + read-write + + + B_0x0 + 32-bit data. + 0x0 + + + B_0x1 + 16-bit data or half-word. + 0x1 + + + B_0x2 + 8-bit data or bytes. + 0x2 + + + B_0x3 + bit data or bit string. + 0x3 + + + + + MODE + Mode selection + + 6 + 1 + read-write + + + B_0x0 + Hash mode selected + 0x0 + + + B_0x1 + HMAC mode selected. + 0x1 + + + + + NBW + Number of words already pushed + + 8 + 4 + read-only + + + DINNE + DIN not empty + + 12 + 1 + read-only + + + MDMAT + Multiple DMA transfers + + 13 + 1 + read-write + + + B_0x0 + DCAL is automatically set at the end of a DMA transfer. + 0x0 + + + B_0x1 + DCAL is not automatically set at the end of a DMA transfer. + 0x1 + + + + + LKEY + Long key selection + + 16 + 1 + read-write + + + B_0x0 + HMAC key is shorter or equal to the block size (short key). + 0x0 + + + B_0x1 + HMAC key is longer than the block size (long key). + 0x1 + + + + + ALGO + Algorithm selection + + 17 + 4 + read-write + + + B_0x0 + SHA-1 + 0x0 + + + B_0x2 + SHA2-224 + 0x2 + + + B_0x3 + SHA2-256 + 0x3 + + + B_0xC + SHA2-384 + 0xC + + + B_0xD + SHA2-512/224 + 0xD + + + B_0xE + SHA2-512/256 + 0xE + + + B_0xF + SHA2-512 + 0xF + + + + + + + HASH_DIN + HASH_DIN + HASH data input register + 0x04 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + DATAIN + Data input + + 0 + 32 + write-only + + + + + HASH_STR + HASH_STR + HASH start register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + NBLW + Number of valid bits in the last word + + 0 + 5 + read-write + + + B_0x00 + All the 32 bits of the last data written are valid message bits, that is M[31:0] + 0x00 + + + B_0x01 + Only one bit of the last data written (after swapping) is valid, that is M[0] + 0x01 + + + B_0x02 + Only two bits of the last data written (after swapping) are valid, that is M[1:0] + 0x02 + + + B_0x03 + Only three bits of the last data written (after swapping) are valid that is M[2:0] + 0x03 + + + B_0x1F + Only 31 bits of the last data written (after swapping) are valid that is M[30:0] + 0x1F + + + + + DCAL + Digest calculation + + 8 + 1 + read-write + + + + + HASH_HRA0 + HASH_HRA0 + HASH aliased digest register 0 + 0xC + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H0 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HRA1 + HASH_HRA1 + HASH aliased digest register 1 + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H1 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HRA2 + HASH_HRA2 + HASH aliased digest register 2 + 0x14 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H2 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HRA3 + HASH_HRA3 + HASH aliased digest register 3 + 0x18 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H3 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HRA4 + HASH_HRA4 + HASH aliased digest register 4 + 0x1C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H4 + Hash data x + + 0 + 32 + read-only + + + + + HASH_IMR + HASH_IMR + HASH interrupt enable register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DINIE + Data input interrupt enable + 0 + 1 + read-write + + + B_0x0 + Data input interrupt disabled + 0x0 + + + B_0x1 + Data input interrupt enabled + 0x1 + + + + + DCIE + Digest calculation completion interrupt enable + 1 + 1 + read-write + + + B_0x0 + Digest calculation completion interrupt disabled + 0x0 + + + B_0x1 + Digest calculation completion interrupt enabled. + 0x1 + + + + + + + HASH_SR + HASH_SR + HASH status register + 0x24 + 0x20 + read-write + 0x00110001 + 0xFFFFFFFF + + + DINIS + Data input interrupt status + + 0 + 1 + read-write + + + B_0x0 + Less than 16 locations are free in the input buffer + 0x0 + + + B_0x1 + A new block can be entered into the input buffer. + 0x1 + + + + + DCIS + Digest calculation completion interrupt status + + 1 + 1 + read-write + + + B_0x0 + No digest available in the HASH_HRx registers (zeros are returned) + 0x0 + + + B_0x1 + Digest calculation complete, a digest is available in the HASH_HRx registers. + 0x1 + + + + + DMAS + DMA Status + + 2 + 1 + read-only + + + B_0x0 + DMA interface is disabled (DMAE = 0) and no transfer is ongoing + 0x0 + + + B_0x1 + DMA interface is enabled (DMAE = 1) or a transfer is ongoing + 0x1 + + + + + BUSY + Busy bit + 3 + 1 + read-only + + + B_0x0 + No block is currently being processed + 0x0 + + + B_0x1 + The hash core is processing a block of data + 0x1 + + + + + NBWP + Number of words already pushed + + 9 + 5 + read-only + + + DINNE + DIN not empty + + 15 + 1 + read-only + + + B_0x0 + No data are present in the data input buffer + 0x0 + + + B_0x1 + The input buffer contains at least one word of data + 0x1 + + + + + NBWE + Number of words expected + + 16 + 5 + read-only + + + + + HASH_CSR0 + HASH_CSR0 + HASH context swap register 0 + 0xF8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS0 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR1 + HASH_CSR1 + HASH context swap register 1 + 0xFC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS1 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR2 + HASH_CSR2 + HASH context swap register 2 + 0x100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS2 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR3 + HASH_CSR3 + HASH context swap register 3 + 0x104 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS3 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR4 + HASH_CSR4 + HASH context swap register 4 + 0x108 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS4 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR5 + HASH_CSR5 + HASH context swap register 5 + 0x10C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS5 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR6 + HASH_CSR6 + HASH context swap register 6 + 0x110 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS6 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR7 + HASH_CSR7 + HASH context swap register 7 + 0x114 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS7 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR8 + HASH_CSR8 + HASH context swap register 8 + 0x118 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS8 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR9 + HASH_CSR9 + HASH context swap register 9 + 0x11C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS9 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR10 + HASH_CSR10 + HASH context swap register 10 + 0x120 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS10 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR11 + HASH_CSR11 + HASH context swap register 11 + 0x124 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS11 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR12 + HASH_CSR12 + HASH context swap register 12 + 0x128 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS12 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR13 + HASH_CSR13 + HASH context swap register 13 + 0x12C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS13 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR14 + HASH_CSR14 + HASH context swap register 14 + 0x130 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS14 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR15 + HASH_CSR15 + HASH context swap register 15 + 0x134 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS15 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR16 + HASH_CSR16 + HASH context swap register 16 + 0x138 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS16 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR17 + HASH_CSR17 + HASH context swap register 17 + 0x13C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS17 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR18 + HASH_CSR18 + HASH context swap register 18 + 0x140 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS18 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR19 + HASH_CSR19 + HASH context swap register 19 + 0x144 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS19 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR20 + HASH_CSR20 + HASH context swap register 20 + 0x148 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS20 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR21 + HASH_CSR21 + HASH context swap register 21 + 0x14C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS21 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR22 + HASH_CSR22 + HASH context swap register 22 + 0x150 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS22 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR23 + HASH_CSR23 + HASH context swap register 23 + 0x154 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS23 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR24 + HASH_CSR24 + HASH context swap register 24 + 0x158 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS24 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR25 + HASH_CSR25 + HASH context swap register 25 + 0x15C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS25 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR26 + HASH_CSR26 + HASH context swap register 26 + 0x160 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS26 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR27 + HASH_CSR27 + HASH context swap register 27 + 0x164 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS27 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR28 + HASH_CSR28 + HASH context swap register 28 + 0x168 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS28 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR29 + HASH_CSR29 + HASH context swap register 29 + 0x16C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS29 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR30 + HASH_CSR30 + HASH context swap register 30 + 0x170 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS30 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR31 + HASH_CSR31 + HASH context swap register 31 + 0x174 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS31 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR32 + HASH_CSR32 + HASH context swap register 32 + 0x178 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS32 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR33 + HASH_CSR33 + HASH context swap register 33 + 0x17C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS33 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR34 + HASH_CSR34 + HASH context swap register 34 + 0x180 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS34 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR35 + HASH_CSR35 + HASH context swap register 35 + 0x184 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS35 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR36 + HASH_CSR36 + HASH context swap register 36 + 0x188 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS36 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR37 + HASH_CSR37 + HASH context swap register 37 + 0x18C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS37 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR38 + HASH_CSR38 + HASH context swap register 38 + 0x190 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS38 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR39 + HASH_CSR39 + HASH context swap register 39 + 0x194 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS39 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR40 + HASH_CSR40 + HASH context swap register 40 + 0x198 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS40 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR41 + HASH_CSR41 + HASH context swap register 41 + 0x19C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS41 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR42 + HASH_CSR42 + HASH context swap register 42 + 0x1A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS42 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR43 + HASH_CSR43 + HASH context swap register 43 + 0x1A4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS43 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR44 + HASH_CSR44 + HASH context swap register 44 + 0x1A8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS44 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR45 + HASH_CSR45 + HASH context swap register 45 + 0x1AC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS45 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR46 + HASH_CSR46 + HASH context swap register 46 + 0x1B0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS46 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR47 + HASH_CSR47 + HASH context swap register 47 + 0x1B4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS47 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR48 + HASH_CSR48 + HASH context swap register 48 + 0x1B8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS48 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR49 + HASH_CSR49 + HASH context swap register 49 + 0x1BC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS49 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR50 + HASH_CSR50 + HASH context swap register 50 + 0x1C0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS50 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR51 + HASH_CSR51 + HASH context swap register 51 + 0x1C4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS51 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR52 + HASH_CSR52 + HASH context swap register 52 + 0x1C8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS52 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR53 + HASH_CSR53 + HASH context swap register 53 + 0x1CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS53 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR54 + HASH_CSR54 + HASH context swap register 54 + 0x1D0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS54 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR55 + HASH_CSR55 + HASH context swap register 55 + 0x1D4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS55 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR56 + HASH_CSR56 + HASH context swap register 56 + 0x1D8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS56 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR57 + HASH_CSR57 + HASH context swap register 57 + 0x1DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS57 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR58 + HASH_CSR58 + HASH context swap register 58 + 0x1E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS58 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR59 + HASH_CSR59 + HASH context swap register 59 + 0x1E4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS59 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR60 + HASH_CSR60 + HASH context swap register 60 + 0x1E8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS60 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR61 + HASH_CSR61 + HASH context swap register 61 + 0x1EC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS61 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR62 + HASH_CSR62 + HASH context swap register 62 + 0x1F0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS62 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR63 + HASH_CSR63 + HASH context swap register 63 + 0x1F4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS63 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR64 + HASH_CSR64 + HASH context swap register 64 + 0x1F8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS64 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR65 + HASH_CSR65 + HASH context swap register 65 + 0x1FC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS65 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR66 + HASH_CSR66 + HASH context swap register 66 + 0x200 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS66 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR67 + HASH_CSR67 + HASH context swap register 67 + 0x204 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS67 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR68 + HASH_CSR68 + HASH context swap register 68 + 0x208 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS68 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR69 + HASH_CSR69 + HASH context swap register 69 + 0x20C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS69 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR70 + HASH_CSR70 + HASH context swap register 70 + 0x210 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS70 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR71 + HASH_CSR71 + HASH context swap register 71 + 0x214 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS71 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR72 + HASH_CSR72 + HASH context swap register 72 + 0x218 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS72 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR73 + HASH_CSR73 + HASH context swap register 73 + 0x21C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS73 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR74 + HASH_CSR74 + HASH context swap register 74 + 0x220 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS74 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR75 + HASH_CSR75 + HASH context swap register 75 + 0x224 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS75 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR76 + HASH_CSR76 + HASH context swap register 76 + 0x228 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS76 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR77 + HASH_CSR77 + HASH context swap register 77 + 0x22C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS77 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR78 + HASH_CSR78 + HASH context swap register 78 + 0x230 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS78 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR79 + HASH_CSR79 + HASH context swap register 79 + 0x234 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS79 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR80 + HASH_CSR80 + HASH context swap register 80 + 0x238 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS80 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR81 + HASH_CSR81 + HASH context swap register 81 + 0x23C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS81 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR82 + HASH_CSR82 + HASH context swap register 82 + 0x240 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS82 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR83 + HASH_CSR83 + HASH context swap register 83 + 0x244 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS83 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR84 + HASH_CSR84 + HASH context swap register 84 + 0x248 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS84 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR85 + HASH_CSR85 + HASH context swap register 85 + 0x24C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS85 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR86 + HASH_CSR86 + HASH context swap register 86 + 0x250 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS86 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR87 + HASH_CSR87 + HASH context swap register 87 + 0x254 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS87 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR88 + HASH_CSR88 + HASH context swap register 88 + 0x258 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS88 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR89 + HASH_CSR89 + HASH context swap register 89 + 0x25C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS89 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR90 + HASH_CSR90 + HASH context swap register 90 + 0x260 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS90 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR91 + HASH_CSR91 + HASH context swap register 91 + 0x264 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS91 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR92 + HASH_CSR92 + HASH context swap register 92 + 0x268 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS92 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR93 + HASH_CSR93 + HASH context swap register 93 + 0x26C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS93 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR94 + HASH_CSR94 + HASH context swap register 94 + 0x270 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS94 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR95 + HASH_CSR95 + HASH context swap register 95 + 0x274 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS95 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR96 + HASH_CSR96 + HASH context swap register 96 + 0x278 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS96 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR97 + HASH_CSR97 + HASH context swap register 97 + 0x27C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS97 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR98 + HASH_CSR98 + HASH context swap register 98 + 0x280 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS98 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR99 + HASH_CSR99 + HASH context swap register 99 + 0x284 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS99 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR100 + HASH_CSR100 + HASH context swap register 100 + 0x288 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS100 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR101 + HASH_CSR101 + HASH context swap register 101 + 0x28C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS101 + Context swap x + + 0 + 32 + read-write + + + + + HASH_CSR102 + HASH_CSR102 + HASH context swap register 102 + 0x290 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CS102 + Context swap x + + 0 + 32 + read-write + + + + + HASH_HR0 + HASH_HR0 + HASH digest register 0 + 0x310 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H0 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR1 + HASH_HR1 + HASH digest register 1 + 0x314 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H1 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR2 + HASH_HR2 + HASH digest register 2 + 0x318 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H2 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR3 + HASH_HR3 + HASH digest register 3 + 0x31C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H3 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR4 + HASH_HR4 + HASH digest register 4 + 0x320 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H4 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR5 + HASH_HR5 + HASH supplementary digest register 5 + 0x324 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H5 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR6 + HASH_HR6 + HASH supplementary digest register 6 + 0x328 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H6 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR7 + HASH_HR7 + HASH supplementary digest register 7 + 0x32C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H7 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR8 + HASH_HR8 + HASH supplementary digest register 8 + 0x330 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H8 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR9 + HASH_HR9 + HASH supplementary digest register 9 + 0x334 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H9 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR10 + HASH_HR10 + HASH supplementary digest register 10 + 0x338 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H10 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR11 + HASH_HR11 + HASH supplementary digest register 11 + 0x33C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H11 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR12 + HASH_HR12 + HASH supplementary digest register 12 + 0x340 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H12 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR13 + HASH_HR13 + HASH supplementary digest register 13 + 0x344 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H13 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR14 + HASH_HR14 + HASH supplementary digest register 14 + 0x348 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H14 + Hash data x + + 0 + 32 + read-only + + + + + HASH_HR15 + HASH_HR15 + HASH supplementary digest register 15 + 0x34C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + H15 + Hash data x + + 0 + 32 + read-only + + + + + + + HASH_S + 0X520C0400 + + + I2C + I2C address block description + I2C + 0x40005400 + + 0x0 + 0x2C + registers + + + I2C1_ERR + I2C1 error interrupt + 52 + + + I2C1_EV + I2C1 event interrupt + 51 + + + + I2C_CR1 + I2C_CR1 + I2C control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PE + Peripheral enable + + 0 + 1 + read-write + + + B_0x0 + Peripheral disabled + 0x0 + + + B_0x1 + Peripheral enabled + 0x1 + + + + + TXIE + TX interrupt enable + 1 + 1 + read-write + + + B_0x0 + Transmit (TXIS) interrupt disabled + 0x0 + + + B_0x1 + Transmit (TXIS) interrupt enabled + 0x1 + + + + + RXIE + RX interrupt enable + 2 + 1 + read-write + + + B_0x0 + Receive (RXNE) interrupt disabled + 0x0 + + + B_0x1 + Receive (RXNE) interrupt enabled + 0x1 + + + + + ADDRIE + Address match interrupt enable (slave only) + 3 + 1 + read-write + + + B_0x0 + Address match (ADDR) interrupts disabled + 0x0 + + + B_0x1 + Address match (ADDR) interrupts enabled + 0x1 + + + + + NACKIE + Not acknowledge received interrupt enable + 4 + 1 + read-write + + + B_0x0 + Not acknowledge (NACKF) received interrupts disabled + 0x0 + + + B_0x1 + Not acknowledge (NACKF) received interrupts enabled + 0x1 + + + + + STOPIE + Stop detection interrupt enable + 5 + 1 + read-write + + + B_0x0 + Stop detection (STOPF) interrupt disabled + 0x0 + + + B_0x1 + Stop detection (STOPF) interrupt enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Transfer complete interrupt disabled + 0x0 + + + B_0x1 + Transfer complete interrupt enabled + 0x1 + + + + + ERRIE + Error interrupts enable + + 7 + 1 + read-write + + + B_0x0 + Error detection interrupts disabled + 0x0 + + + B_0x1 + Error detection interrupts enabled + 0x1 + + + + + DNF + Digital noise filter + + 8 + 4 + read-write + + + B_0x0 + Digital filter disabled + 0x0 + + + B_0x1 + Digital filter enabled and filtering capability up to one tless thansub>I2CCLKless than/sub> + 0x1 + + + B_0xF + digital filter enabled and filtering capability up to fifteen tless thansub>I2CCLKless than/sub> + 0xF + + + + + ANFOFF + Analog noise filter OFF + + 12 + 1 + read-write + + + B_0x0 + Analog noise filter enabled + 0x0 + + + B_0x1 + Analog noise filter disabled + 0x1 + + + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + read-write + + + B_0x0 + DMA mode disabled for transmission + 0x0 + + + B_0x1 + DMA mode enabled for transmission + 0x1 + + + + + RXDMAEN + DMA reception requests enable + 15 + 1 + read-write + + + B_0x0 + DMA mode disabled for reception + 0x0 + + + B_0x1 + DMA mode enabled for reception + 0x1 + + + + + SBC + Slave byte control + + 16 + 1 + read-write + + + B_0x0 + Slave byte control disabled + 0x0 + + + B_0x1 + Slave byte control enabled + 0x1 + + + + + NOSTRETCH + Clock stretching disable + + 17 + 1 + read-write + + + B_0x0 + Clock stretching enabled + 0x0 + + + B_0x1 + Clock stretching disabled + 0x1 + + + + + WUPEN + Wake-up from Stop mode enable + + 18 + 1 + read-write + + + B_0x0 + Wake-up from Stop mode disabled. + 0x0 + + + B_0x1 + Wake-up from Stop mode enabled. + 0x1 + + + + + GCEN + General call enable + 19 + 1 + read-write + + + B_0x0 + General call disabled. + 0x0 + + + B_0x1 + General call enabled. + 0x1 + + + + + SMBHEN + SMBus host address enable + + 20 + 1 + read-write + + + B_0x0 + Host address disabled. + 0x0 + + + B_0x1 + Host address enabled. + 0x1 + + + + + SMBDEN + SMBus device default address enable + + 21 + 1 + read-write + + + B_0x0 + Device default address disabled. + 0x0 + + + B_0x1 + Device default address enabled. + 0x1 + + + + + ALERTEN + SMBus alert enable + + 22 + 1 + read-write + + + B_0x0 + The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN = 1). + 0x0 + + + B_0x1 + The SMBus alert pin is supported in host mode (SMBHEN = 1). + 0x1 + + + + + PECEN + PEC enable + + 23 + 1 + read-write + + + B_0x0 + PEC calculation disabled + 0x0 + + + B_0x1 + PEC calculation enabled + 0x1 + + + + + FMP + Fast-mode Plus 20 mA drive enable + 24 + 1 + read-write + + + B_0x0 + 20 mA I/O drive disabled + 0x0 + + + B_0x1 + 20 mA I/O drive enabled + 0x1 + + + + + ADDRACLR + Address match flag (ADDR) automatic clear + 30 + 1 + read-write + + + B_0x0 + ADDR flag is set by hardware, cleared by software by setting ADDRCF bit. + 0x0 + + + B_0x1 + ADDR flag remains cleared by hardware. + 0x1 + + + + + STOPFACLR + STOP detection flag (STOPF) automatic clear + 31 + 1 + read-write + + + B_0x0 + STOPF flag is set by hardware, cleared by software by setting STOPCF bit. + 0x0 + + + B_0x1 + STOPF flag remains cleared by hardware. + 0x1 + + + + + + + I2C_CR2 + I2C_CR2 + I2C control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SADD + Slave address (master mode) + + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) + + 10 + 1 + read-write + + + B_0x0 + Master requests a write transfer + 0x0 + + + B_0x1 + Master requests a read transfer + 0x1 + + + + + ADD10 + 10-bit addressing mode (master mode) + + 11 + 1 + read-write + + + B_0x0 + The master operates in 7-bit addressing mode + 0x0 + + + B_0x1 + The master operates in 10-bit addressing mode + 0x1 + + + + + HEAD10R + 10-bit address header only read direction (master receiver mode) + + 12 + 1 + read-write + + + B_0x0 + The master sends the complete 10-bit slave address read sequence: Start + 2 bytes 10-bit address in write direction + restart + first seven bits of the 10-bit address in read direction. + 0x0 + + + B_0x1 + The master sends only the first seven bits of the 10-bit address, followed by read direction. + 0x1 + + + + + START + Start generation + + 13 + 1 + read-write + + + B_0x0 + No Start generation + 0x0 + + + B_0x1 + Restart/Start generation: + 0x1 + + + + + STOP + Stop generation (master mode) + + 14 + 1 + read-write + + + B_0x0 + No Stop generation + 0x0 + + + B_0x1 + Stop generation after current byte transfer + 0x1 + + + + + NACK + NACK generation (slave mode) + + 15 + 1 + read-write + + + B_0x0 + an ACK is sent after current received byte. + 0x0 + + + B_0x1 + a NACK is sent after current received byte. + 0x1 + + + + + NBYTES + Number of bytes + + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode + + 24 + 1 + read-write + + + B_0x0 + The transfer is completed after the NBYTES data transfer (STOP or RESTART follows). + 0x0 + + + B_0x1 + The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). + 0x1 + + + + + AUTOEND + Automatic end mode (master mode) + + 25 + 1 + read-write + + + B_0x0 + software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + 0x0 + + + B_0x1 + Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + 0x1 + + + + + PECBYTE + Packet error checking byte + + 26 + 1 + read-write + + + B_0x0 + No PEC transfer + 0x0 + + + B_0x1 + PEC transmission/reception is requested + 0x1 + + + + + + + I2C_OAR1 + I2C_OAR1 + I2C own address 1 register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA1 + Interface own slave address + + 0 + 10 + read-write + + + OA1MODE + Own address 1 10-bit mode + + 10 + 1 + read-write + + + B_0x0 + Own address 1 is a 7-bit address. + 0x0 + + + B_0x1 + Own address 1 is a 10-bit address. + 0x1 + + + + + OA1EN + Own address 1 enable + 15 + 1 + read-write + + + B_0x0 + Own address 1 disabled. + 0x0 + + + B_0x1 + Own address 1 enabled. + 0x1 + + + + + + + I2C_OAR2 + I2C_OAR2 + I2C own address 2 register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OA2 + Interface address + + 1 + 7 + read-write + + + OA2MSK + Own address 2 masks + + 8 + 3 + read-write + + + B_0x0 + No mask + 0x0 + + + B_0x1 + OA2[1] is masked and don't care. + 0x1 + + + B_0x2 + OA2[2:1] are masked and don't care. + 0x2 + + + B_0x3 + OA2[3:1] are masked and don't care. + 0x3 + + + B_0x4 + OA2[4:1] are masked and don't care. + 0x4 + + + B_0x5 + OA2[5:1] are masked and don't care. + 0x5 + + + B_0x6 + OA2[6:1] are masked and don't care. + 0x6 + + + B_0x7 + OA2[7:1] are masked and don't care. + 0x7 + + + + + OA2EN + Own address 2 enable + 15 + 1 + read-write + + + B_0x0 + Own address 2 disabled. + 0x0 + + + B_0x1 + Own address 2 enabled. + 0x1 + + + + + + + I2C_TIMINGR + I2C_TIMINGR + I2C timing register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SCLL + SCL low period (master mode) + + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) + + 8 + 8 + read-write + + + SDADEL + Data hold time + + 16 + 4 + read-write + + + SCLDEL + Data setup time + + 20 + 4 + read-write + + + PRESC + Timing prescaler + + 28 + 4 + read-write + + + + + I2C_TIMEOUTR + I2C_TIMEOUTR + I2C timeout register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIMEOUTA + Bus timeout A + + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection + + 12 + 1 + read-write + + + B_0x0 + TIMEOUTA is used to detect SCL low timeout + 0x0 + + + B_0x1 + TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) + 0x1 + + + + + TIMOUTEN + Clock timeout enable + 15 + 1 + read-write + + + B_0x0 + SCL timeout detection is disabled + 0x0 + + + B_0x1 + SCL timeout detection is enabled. + 0x1 + + + + + TIMEOUTB + Bus timeout B + + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable + 31 + 1 + read-write + + + B_0x0 + Extended clock timeout detection is disabled + 0x0 + + + B_0x1 + Extended clock timeout detection is enabled. + 0x1 + + + + + + + I2C_ISR + I2C_ISR + I2C interrupt and status register + 0x18 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + TXE + Transmit data register empty (transmitters) + + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) + + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) + + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) + + 3 + 1 + read-only + + + NACKF + Not acknowledge received flag + + 4 + 1 + read-only + + + STOPF + Stop detection flag + + 5 + 1 + read-only + + + TC + Transfer complete (master mode) + + 6 + 1 + read-only + + + TCR + Transfer complete reload + + 7 + 1 + read-only + + + BERR + Bus error + + 8 + 1 + read-only + + + ARLO + Arbitration lost + + 9 + 1 + read-only + + + OVR + Overrun/underrun (slave mode) + + 10 + 1 + read-only + + + PECERR + PEC error in reception + + 11 + 1 + read-only + + + TIMEOUT + Timeout or tless thansub>LOWless than/sub> detection flag + + 12 + 1 + read-only + + + ALERT + SMBus alert + + 13 + 1 + read-only + + + BUSY + Bus busy + + 15 + 1 + read-only + + + DIR + Transfer direction (slave mode) + + 16 + 1 + read-only + + + B_0x0 + Write transfer, slave enters receiver mode. + 0x0 + + + B_0x1 + Read transfer, slave enters transmitter mode. + 0x1 + + + + + ADDCODE + Address match code (slave mode) + + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ADDRCF + Address matched flag clear + + 3 + 1 + write-only + + + NACKCF + Not acknowledge flag clear + + 4 + 1 + write-only + + + STOPCF + STOP detection flag clear + + 5 + 1 + write-only + + + BERRCF + Bus error flag clear + + 8 + 1 + write-only + + + ARLOCF + Arbitration lost flag clear + + 9 + 1 + write-only + + + OVRCF + Overrun/underrun flag clear + + 10 + 1 + write-only + + + PECCF + PEC error flag clear + + 11 + 1 + write-only + + + TIMOUTCF + Timeout detection flag clear + + 12 + 1 + write-only + + + ALERTCF + Alert flag clear + + 13 + 1 + write-only + + + + + I2C_PECR + I2C_PECR + I2C PEC register + 0x20 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PEC + Packet error checking register + + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXDATA + 8-bit receive data + + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXDATA + 8-bit transmit data + + 0 + 8 + read-write + + + + + + + I2C_S + 0X50005400 + + + I2C2 + 0x40005800 + + I2C2_ERR + I2C2 error interrupt + 54 + + + I2C2_EV + I2C2 event interrupt + 53 + + + + I2C2_S + 0x50005800 + + + I2C3 + 0x44002800 + + I2C3_ERR + I2C3 error interrupt + 81 + + + I2C3_EV + I2C3 event interrupt + 80 + + + + I2C3_S + 0x54002800 + + + I3C + I3C register block + I3C + 0x40005c00 + + 0x0 + 0x400 + registers + + + I3C1_ERR + I3C1 error interrupt + 124 + + + I3C1_EV + I3C1 event interrupt + 123 + + + + I3C_CR + I3C_CR + I3C message control register + 0x000 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + DCNT + Count of data to transfer during a read or write message, in bytes (whatever I3C acts as controller/target) + + 0 + 16 + write-only + + + B_0x0000 + no data to transfer + 0x0000 + + + B_0x0001 + 1 byte + 0x0001 + + + B_0x0002 + 2 bytes + 0x0002 + + + B_0xFFFF + 64 Kbytes - 1 byte + 0xFFFF + + + + + RNW + Read / non-write message (when I3C acts as controller) + + 16 + 1 + write-only + + + B_0x0 + write message + 0x0 + + + B_0x1 + read message + 0x1 + + + + + ADD + 7-bit I3C dynamic / Iless thansup>2less than/sup>C static target address (when I3C acts as controller) + + 17 + 7 + write-only + + + MTYPE + Message type (whatever I3C acts as controller/target) + + 27 + 4 + write-only + + + B_0x0_WHEN_I3C_ACTS_AS_I3C_CONTROLLER + SCL clock is forced to stop until a next control word is executed + 0x0 + + + B_0x1_WHEN_I3C_ACTS_AS_I3C_CONTROLLER + header message + 0x1 + + + B_0x2_WHEN_I3C_ACTS_AS_I3C_CONTROLLER + private message (refer to Figure 665) + 0x2 + + + B_0x3_WHEN_I3C_ACTS_AS_I3C_CONTROLLER + direct message (second part of an I3C SDR direct CCC command) (refer to Figure 658) + 0x3 + + + B_0x4_WHEN_I3C_ACTS_AS_I3C_CONTROLLER + legacy Iless thansup>2less than/sup>C message (refer to Figure 667) + 0x4 + + + B_0x8_WHEN_I3C_ACTS_AS_I3C_TARGET + hot-join request (W) (refer to Figure 669) + 0x8 + + + B_0x9_WHEN_I3C_ACTS_AS_I3C_TARGET + controller-role request (W) (refer to Figure 670) + 0x9 + + + B_0xA_WHEN_I3C_ACTS_AS_I3C_TARGET + IBI (in-band interrupt) request (R) (refer to Figure 668) + 0xA + + + + + MEND + Message end type/last message of a frame (when the I3C acts as controller) + 31 + 1 + write-only + + + B_0x0 + this message from controller is followed by a repeated start (Sr), before another message must be emitted + 0x0 + + + B_0x1 + this message from controller ends with a stop (P), being the last message of a frame + 0x1 + + + + + + + I3C_CR_ALTERNATE1 + I3C_CR_ALTERNATE1 + I3C message control register + I3C_CR + 0x000 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + DCNT + Count of related data to the CCC command to transfer as CCC defining bytes, or CCC sub-command bytes, or CCC data bytes, in bytes + + 0 + 16 + write-only + + + B_0x0000 + no data to transfer. + 0x0000 + + + B_0x0001 + 1 byte + 0x0001 + + + B_0x0002 + 2 bytes + 0x0002 + + + B_0xFFFF + 64 Kbytes - 1 byte + 0xFFFF + + + + + CCC + 8-bit CCC code (when I3C acts as controller) + + 16 + 8 + write-only + + + MTYPE + Message type (when I3C acts as controller) + + 27 + 4 + write-only + + + B_0x6_WHEN_I3C_ACTS_AS_I3C_CONTROLLER + broadcast/direct CCC command (refer to Table 540, Figure 658, Figure 659, Figure 660) + 0x6 + + + + + MEND + Message end type/last message of a frame (when I3C acts as controller) + 31 + 1 + write-only + + + B_0x0 + this message from controller is followed by a repeated start (Sr), before another message must be emitted + 0x0 + + + B_0x1 + the message from the controller ends with a stop (P), being the last message of a frame + 0x1 + + + + + + + I3C_CFGR + I3C_CFGR + I3C configuration register + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + I3C enable (whatever I3C acts as controller/target) + + 0 + 1 + read-write + + + B_0x0 + I3C is disabled + 0x0 + + + B_0x1 + I3C is enabled + 0x1 + + + + + CRINIT + Initial controller/target role + + 1 + 1 + read-write + + + B_0x0 + target role + 0x0 + + + B_0x1 + controller role + 0x1 + + + + + NOARBH + No arbitrable header after a start (when I3C acts as a controller) + + 2 + 1 + read-write + + + B_0x0 + An arbitrable header (0b111_1110 + RnW = 0) is emitted after a start and before a legacy Iless thansup>2less than/sup>C message or an I3C SDR private read/write message (default). + 0x0 + + + B_0x1 + No arbitrable header + 0x1 + + + + + RSTPTRN + HDR reset pattern enable (when I3C acts as a controller) + + 3 + 1 + read-write + + + B_0x0 + standard stop emitted at the end of a frame + 0x0 + + + B_0x1 + HDR reset pattern is inserted before the stop of any emitted frame that includes a RSTACT CCC command + 0x1 + + + + + EXITPTRN + HDR exit pattern enable (when I3C acts as a controller) + + 4 + 1 + read-write + + + B_0x0 + HDR exit pattern is not sent after the issued message header (MTYPE[3:0] = 0001 in the I3C_CR register). + 0x0 + + + B_0x1 + HDR exit pattern is sent after the issued message header (MTYPE[3:0] = 0001). + 0x1 + + + + + HKSDAEN + High-keeper enable on SDA line (when I3C acts as a controller) + + 5 + 1 + read-write + + + B_0x0 + High-keeper is disabled + 0x0 + + + B_0x1 + High-keeper is enabled, and the weak pull-up is effective on the T bit, instead of the open-drain class pull-up. + 0x1 + + + + + HJACK + Hot-join request acknowledge (when I3C acts as a controller) + + 7 + 1 + read-write + + + B_0x0 + hot-join request is not acknowledged + 0x0 + + + B_0x1 + hot-join request is acknowledged + 0x1 + + + + + RXDMAEN + RX-FIFO DMA request enable (whatever I3C acts as controller/target) + + 8 + 1 + read-write + + + B_0x0 + DMA mode is disabled for RX-FIFO + 0x0 + + + B_0x1 + DMA mode is enabled for RX-FIFO + 0x1 + + + + + RXFLUSH + RX-FIFO flush (whatever I3C acts as controller/target) + + 9 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + flush RX-FIFO + 0x1 + + + + + RXTHRES + RX-FIFO threshold (whatever I3C acts as controller/target) + + 10 + 1 + read-write + + + B_0x0 + 1-byte threshold + 0x0 + + + B_0x1 + 1-word/4-bytes threshold + 0x1 + + + + + TXDMAEN + TX-FIFO DMA request enable (whatever I3C acts as controller/target) + + 12 + 1 + read-write + + + B_0x0 + DMA mode is disabled for TX-FIFO + 0x0 + + + B_0x1 + DMA mode is enabled for TX-FIFO + 0x1 + + + + + TXFLUSH + TX-FIFO flush (whatever I3C acts as controller/target) + + 13 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + flush TX-FIFO + 0x1 + + + + + TXTHRES + TX-FIFO threshold (whatever I3C acts as controller/target) + + 14 + 1 + read-write + + + B_0x0 + 1-byte threshold + 0x0 + + + B_0x1 + 1-word / 4-byte threshold + 0x1 + + + + + SDMAEN + S-FIFO DMA request enable (when I3C acts as controller) + + 16 + 1 + read-write + + + B_0x0 + DMA mode is disabled for reading status register I3C_SR + 0x0 + + + B_0x1 + DMA mode is enabled for reading status register I3C_SR + 0x1 + + + + + SFLUSH + S-FIFO flush (when I3C acts as controller) + + 17 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + flush S-FIFO + 0x1 + + + + + SMODE + S-FIFO enable / status receive mode (when I3C acts as controller) + + 18 + 1 + read-write + + + B_0x0 + S-FIFO is disabled + 0x0 + + + B_0x1 + S-FIFO is enabled. + 0x1 + + + + + TMODE + Transmit mode (when I3C acts as controller) + + 19 + 1 + read-write + + + B_0x0 + C-FIFO and TX-FIFO are not preloaded before starting to emit a frame transfer. + 0x0 + + + B_0x1 + C-FIFO and TX-FIFO are first preloaded (also TX-FIFO if needed, depending on the frame format) before starting to emit a frame transfer. + 0x1 + + + + + CDMAEN + C-FIFO DMA request enable (when I3C acts as controller) + + 20 + 1 + read-write + + + B_0x0 + DMA mode is disabled for C-FIFO + 0x0 + + + B_0x1 + DMA mode is enabled for C-FIFO + 0x1 + + + + + CFLUSH + C-FIFO flush (when I3C acts as controller) + + 21 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + flush C-FIFO + 0x1 + + + + + TSFSET + Frame transfer set (software trigger) (when I3C acts as controller) + + 30 + 1 + write-only + + + B_0x0 + no action + 0x0 + + + B_0x1 + setting this bit initiates a frame transfer by causing the hardware to assert the flag CFNFF in the I3C_EVR register (C-FIFO not full and a control word is needed) + 0x1 + + + + + + + I3C_RDR + I3C_RDR + I3C receive data byte register + 0x010 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDB0 + 8-bit received data on I3C bus. + 0 + 8 + read-only + + + + + I3C_RDWR + I3C_RDWR + I3C receive data word register + 0x014 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDB0 + 8-bit received data (earliest byte on I3C bus). + 0 + 8 + read-only + + + RDB1 + 8-bit received data (next byte after RDB0 on I3C bus). + 8 + 8 + read-only + + + RDB2 + 8-bit received data (next byte after RDB1 on I3C bus). + 16 + 8 + read-only + + + RDB3 + 8-bit received data (latest byte on I3C bus). + 24 + 8 + read-only + + + + + I3C_TDR + I3C_TDR + I3C transmit data byte register + 0x018 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TDB0 + 8-bit data to transmit on I3C bus. + 0 + 8 + write-only + + + + + I3C_TDWR + I3C_TDWR + I3C transmit data word register + 0x01C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TDB0 + 8-bit transmit data (earliest byte on I3C bus) + 0 + 8 + write-only + + + TDB1 + 8-bit transmit data (next byte after TDB0[7:0] on I3C bus). + 8 + 8 + write-only + + + TDB2 + 8-bit transmit data (next byte after TDB1[7:0] on I3C bus). + 16 + 8 + write-only + + + TDB3 + 8-bit transmit data (latest byte on I3C bus). + 24 + 8 + write-only + + + + + I3C_IBIDR + I3C_IBIDR + I3C IBI payload data register + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IBIDB0 + 8-bit IBI payload data (earliest byte on I3C bus, MDB[7:0] mandatory data byte). + 0 + 8 + read-write + + + IBIDB1 + 8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0]). + 8 + 8 + read-write + + + IBIDB2 + 8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0]). + 16 + 8 + read-write + + + IBIDB3 + 8-bit IBI payload data (latest byte on I3C bus). + 24 + 8 + read-write + + + + + I3C_TGTTDR + I3C_TGTTDR + I3C target transmit configuration register + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TGTTDCNT + Transmit data counter, in bytes (when I3C is configured as target) + + 0 + 16 + read-write + + + PRELOAD + Preload of the TX-FIFO (when I3C is configured as target) + + 16 + 1 + read-write + + + B_0x0 + no TX-FIFO preload + 0x0 + + + B_0x1 + TX-FIFO preload + 0x1 + + + + + + + I3C_SR + I3C_SR + I3C status register + 0x030 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + XDCNT + Data counter + + 0 + 16 + read-only + + + ABT + A private read message is ended prematurely by the target (when the I3C acts as controller) + + 17 + 1 + read-only + + + B_0x0 + no early completion from the target + 0x0 + + + B_0x1 + early completion from the target + 0x1 + + + + + DIR + Message direction + + 18 + 1 + read-only + + + B_0x0 + write + 0x0 + + + B_0x1 + read + 0x1 + + + + + MID + Message identifier/counter of a given frame (when the I3C acts as controller) + + 24 + 8 + read-only + + + + + I3C_SER + I3C_SER + I3C status error register + 0x034 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CODERR + Protocol error code/type + + 0 + 4 + read-only + + + B_0x0 + CE0 error (transaction after sending CCC): + 0x0 + + + B_0x1 + CE1 error (monitoring error): + 0x1 + + + B_0x2 + CE2 error (no response to broadcast address): + 0x2 + + + B_0x3 + CE3 error (failed controller-role hand-off): + 0x3 + + + B_0x8 + TE0 error (invalid broadcast address 0b111_1110 + W): + 0x8 + + + B_0x9 + TE1 error (CCC code): + 0x9 + + + B_0xA + TE2 error (write data): + 0xA + + + B_0xB + TE3 error (assigned address during dynamic address arbitration): + 0xB + + + B_0xC + TE4 error (0b111_1110 + R missing after Sr during dynamic address arbitration): + 0xC + + + B_0xD + TE5 error (transaction after detecting CCC): + 0xD + + + B_0xE + TE6 error (monitoring error): + 0xE + + + + + PERR + Protocol error + 4 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + whatever controller or target, hardware detected a protocol error, as detailed in CODERR[3:0] + 0x1 + + + + + STALL + SCL stall error (when the I3C acts as target) + 5 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + target detected that SCL was stable for more than 125 s during an I3C SDR data read (during a direct CCC read, a private read, or an IB) + 0x1 + + + + + DOVR + RX-FIFO overrun or TX-FIFO underrun + + 6 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + whatever controller or target, hardware detected either: + 0x1 + + + + + COVR + C-FIFO underrun or S-FIFO overrun (when the I3C acts as controller) + + 7 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + controller detected either: + 0x1 + + + + + ANACK + Address not acknowledged (when the I3C is configured as controller) + + 8 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + controller detected that the static/dynamic address was not acknowledged by a target, either during: + 0x1 + + + + + DNACK + Data not acknowledged (when the I3C acts as controller) + + 9 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + controller detected that a data byte is not acknowledged by a target, either during: + 0x1 + + + + + DERR + Data error (when the I3C acts as controller) + 10 + 1 + read-only + + + B_0x0 + no detected error + 0x0 + + + B_0x1 + controller detected a data error during the controller-role hand-off procedure (GETACCCR CCC, formerly known as GETACCMST) when the received target address or/and the parity bit do no match. + 0x1 + + + + + + + I3C_RMR + I3C_RMR + I3C received message register + 0x040 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + IBIRDCNT + IBI received payload data count (when the I3C is configured as controller) + + 0 + 3 + read-only + + + RCODE + Received CCC code (when the I3C is configured as target) + + 8 + 8 + read-only + + + RADD + Received target address (when the I3C is configured as controller) + + 17 + 7 + read-only + + + + + I3C_EVR + I3C_EVR + I3C event register + 0x050 + 0x20 + read-only + 0x00000003 + 0xFFFFFFFF + + + CFEF + C-FIFO empty flag (whatever the I3C acts as controller) + + 0 + 1 + read-only + + + TXFEF + TX-FIFO empty flag (whatever the I3C acts as controller/target) + + 1 + 1 + read-only + + + CFNFF + C-FIFO not full flag (when the I3C acts as controller) + + 2 + 1 + read-only + + + SFNEF + S-FIFO not empty flag (when the I3C acts as controller) + + 3 + 1 + read-only + + + TXFNFF + TX-FIFO not full flag (whatever the I3C acts as controller/target) + + 4 + 1 + read-only + + + RXFNEF + RX-FIFO not empty flag (whatever the I3C acts as controller/target) + + 5 + 1 + read-only + + + TXLASTF + Last written data byte/word flag (whatever the I3C acts as controller/target) + + 6 + 1 + read-only + + + RXLASTF + Last read data byte/word flag (when the I3C acts as controller) + + 7 + 1 + read-only + + + FCF + Frame complete flag (whatever the I3C acts as controller/target) + + 9 + 1 + read-only + + + RXTGTENDF + Target-initiated read end flag (when the I3C acts as controller) + + 10 + 1 + read-only + + + ERRF + Flag (whatever the I3C acts as controller/target) + + 11 + 1 + read-only + + + IBIF + IBI flag (when the I3C acts as controller) + + 15 + 1 + read-only + + + IBIENDF + IBI end flag (when the I3C acts as target) + + 16 + 1 + read-only + + + CRF + Controller-role request flag (when the I3C acts as controller) + + 17 + 1 + read-only + + + CRUPDF + Controller-role update flag (when the I3C acts as target) + + 18 + 1 + read-only + + + HJF + Hot-join flag (when the I3C acts as controller) + + 19 + 1 + read-only + + + WKPF + Wake-up/missed start flag (when the I3C acts as target) + + 21 + 1 + read-only + + + GETF + Get flag (when the I3C acts as target) + + 22 + 1 + read-only + + + STAF + Get status flag (when the I3C acts as target) + + 23 + 1 + read-only + + + DAUPDF + Dynamic address update flag (when the I3C acts as target) + + 24 + 1 + read-only + + + MWLUPDF + Maximum write length update flag (when the I3C acts as target) + + 25 + 1 + read-only + + + MRLUPDF + Maximum read length update flag (when the I3C acts as target) + + 26 + 1 + read-only + + + RSTF + Reset pattern flag (when the I3C acts as target) + + 27 + 1 + read-only + + + ASUPDF + Activity state update flag (when the I3C acts as target) + + 28 + 1 + read-only + + + INTUPDF + Interrupt/controller-role/hot-join update flag (when the I3C acts as target) + + 29 + 1 + read-only + + + DEFF + DEFTGTS flag (when the I3C acts as target) + + 30 + 1 + read-only + + + GRPF + Group addressing flag (when the I3C acts as target) + + 31 + 1 + read-only + + + + + I3C_IER + I3C_IER + I3C interrupt enable register + 0x054 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CFNFIE + C-FIFO not full interrupt enable when the I3C acts as controller + 2 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + SFNEIE + S-FIFO not empty interrupt enable when the I3C acts as controller + 3 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + TXFNFIE + TX-FIFO not full interrupt enable (whatever the I3C acts as controller/target) + 4 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RXFNEIE + RX-FIFO not empty interrupt enable (whatever the I3C acts as controller/target) + 5 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + FCIE + frame complete interrupt enable (whatever the I3C acts as controller/target) + 9 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RXTGTENDIE + target-initiated read end interrupt enable (when the I3C acts as controller) + 10 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ERRIE + error interrupt enable (whatever the I3C acts as controller/target) + 11 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + IBIIE + IBI request interrupt enable (when the I3C acts as controller) + 15 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + IBIENDIE + IBI end interrupt enable (when the I3C acts as target) + 16 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + CRIE + Controller-role request interrupt enable (when the I3C acts as controller) + 17 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + CRUPDIE + Controller-role update interrupt enable (when the I3C acts as target) + 18 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + HJIE + Hot-join interrupt enable (when the I3C acts as controller) + 19 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + WKPIE + Wake-up interrupt enable (when the I3C acts as target) + 21 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + GETIE + GETxxx CCC interrupt enable (except GETSTATUS of format 1) (when the I3C acts as target) + 22 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + STAIE + format 1 GETSTATUS CCC interrupt enable (when the I3C acts as target) + 23 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DAUPDIE + ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C acts as target) + 24 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + MWLUPDIE + SETMWL CCC interrupt enable (when the I3C acts as target) + 25 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + MRLUPDIE + SETMRL CCC interrupt enable (when the I3C acts as target) + 26 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + RSTIE + reset pattern interrupt enable (when the I3C acts as target) + 27 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + ASUPDIE + ENTASx CCC interrupt enable (when the I3C acts as target) + 28 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + INTUPDIE + ENEC/DISEC CCC interrupt enable (when the I3C acts as target) + 29 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + DEFIE + DEFTGTS CCC interrupt enable (when the I3C acts as target) + 30 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + GRPIE + DEFGRPA CCC interrupt enable (when the I3C acts as target) + 31 + 1 + read-only + + + B_0x0 + interrupt disabled + 0x0 + + + B_0x1 + interrupt enabled + 0x1 + + + + + + + I3C_CEVR + I3C_CEVR + I3C clear event register + 0x058 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CFCF + Clear frame complete flag (whatever the I3C acts as controller/target) + 9 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear FCF + 0x1 + + + + + CRXTGTENDF + Clear target-initiated read end flag (when the I3C acts as controller) + 10 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear RXTGTENDF + 0x1 + + + + + CERRF + Clear error flag (whatever the I3C acts as controller/target) + 11 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear ERRF + 0x1 + + + + + CIBIF + Clear IBI request flag (when the I3C acts as controller) + 15 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear IBIF + 0x1 + + + + + CIBIENDF + Clear IBI end flag (when the I3C acts as target) + 16 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear IBIENDF + 0x1 + + + + + CCRF + Clear controller-role request flag (when the I3C acts as controller) + 17 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear CRF + 0x1 + + + + + CCRUPDF + Clear controller-role update flag (when the I3C acts as target) + 18 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear CRUPDF + 0x1 + + + + + CHJF + Clear hot-join flag (when the I3C acts as controller) + 19 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear HJF + 0x1 + + + + + CWKPF + Clear wake-up flag (when the I3C acts as target) + 21 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear WKPF + 0x1 + + + + + CGETF + Clear GETxxx CCC flag (except GETSTATUS of format 1) (when the I3C acts as target) + 22 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear GETF + 0x1 + + + + + CSTAF + Clear format 1 GETSTATUS CCC flag (when the I3C acts as target) + 23 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear STAF + 0x1 + + + + + CDAUPDF + Clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C acts as target) + 24 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear DAUPDF + 0x1 + + + + + CMWLUPDF + Clear SETMWL CCC flag (when the I3C acts as target) + 25 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear MWLUPDF + 0x1 + + + + + CMRLUPDF + Clear SETMRL CCC flag (when the I3C acts as target) + 26 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear MRLUPDF + 0x1 + + + + + CRSTF + Clear reset pattern flag (when the I3C acts as target) + 27 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear RSTF + 0x1 + + + + + CASUPDF + Clear ENTASx CCC flag (when the I3C acts as target) + 28 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear ASUPDF + 0x1 + + + + + CINTUPDF + Clear ENEC/DISEC CCC flag (when the I3C acts as target) + 29 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear CINTUPDF + 0x1 + + + + + CDEFF + Clear DEFTGTS CCC flag (when the I3C acts as target) + 30 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear DEFF + 0x1 + + + + + CGRPF + Clear DEFGRPA CCC flag (when the I3C acts as target) + 31 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clear GRPF + 0x1 + + + + + + + I3C_DEVR0 + I3C_DEVR0 + I3C own device characteristics register + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DAVAL + Dynamic address is valid (when the I3C acts as target) + + 0 + 1 + read-write + + + DA + 7-bit dynamic address + + 1 + 7 + read-write + + + IBIEN + IBI request enable (when the I3C acts as target) + + 16 + 1 + read-write + + + B_0x0 + IBI request disabled + 0x0 + + + B_0x1 + IBI request enabled + 0x1 + + + + + CREN + Controller-role request enable (when the I3C acts as target) + + 17 + 1 + read-write + + + B_0x0 + controller-role request disabled + 0x0 + + + B_0x1 + controller-role request enabled + 0x1 + + + + + HJEN + Hot-join request enable (when the I3C acts as target) + + 19 + 1 + read-write + + + B_0x0 + hot-join request disabled + 0x0 + + + B_0x1 + hot-join request enabled + 0x1 + + + + + AS + Activity state (when the I3C acts as target) + + 20 + 2 + read-only + + + B_0x0 + activity state 0 + 0x0 + + + B_0x1 + activity state 1 + 0x1 + + + B_0x2 + activity state 2 + 0x2 + + + B_0x3 + activity state 3 + 0x3 + + + + + RSTACT + Reset action/level on received reset pattern (when the I3C acts as target) + + 22 + 2 + read-only + + + B_0x0 + no reset action + 0x0 + + + B_0x1 + first level of reset: the application software must either: + 0x1 + + + B_0x2 + second level of reset: the application software must issue a warm reset, also known as a system reset. + 0x2 + + + B_0x3 + no reset action + 0x3 + + + + + RSTVAL + Reset action is valid (when the I3C acts as target) + + 24 + 1 + read-only + + + + + I3C_DEVR1 + I3C_DEVR1 + I3C device 1 characteristics register + 0x64 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + Assigned I3C dynamic address to target x (when the I3C acts as controller) + + 1 + 7 + read-write + + + IBIACK + IBI request acknowledge (when the I3C acts as controller) + + 16 + 1 + read-write + + + B_0x0 + an IBI request from target x must be NACK-ed + 0x0 + + + B_0x1 + an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + CRACK + Controller-role request acknowledge (when the I3C acts as controller) + + 17 + 1 + read-write + + + B_0x0 + a controller-role request from target x must be NACK-ed + 0x0 + + + B_0x1 + a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + IBIDEN + IBI data enable (when the I3C acts as controller) + + 18 + 1 + read-write + + + B_0x0 + no data byte follows the acknowledged IBI from target x + 0x0 + + + B_0x1 + the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x + 0x1 + + + + + SUSP + Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) + + 19 + 1 + read-write + + + B_0x0 + C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted + 0x0 + + + B_0x1 + I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x + 0x1 + + + + + DIS + DA[6:0] write disabled (when the I3C acts as controller) + + 31 + 1 + read-only + + + B_0x0 + write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed + 0x0 + + + B_0x1 + write to DA[7:0] and to IBIDEN is disabled/locked + 0x1 + + + + + + + I3C_DEVR2 + I3C_DEVR2 + I3C device 2 characteristics register + 0x68 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + Assigned I3C dynamic address to target x (when the I3C acts as controller) + + 1 + 7 + read-write + + + IBIACK + IBI request acknowledge (when the I3C acts as controller) + + 16 + 1 + read-write + + + B_0x0 + an IBI request from target x must be NACK-ed + 0x0 + + + B_0x1 + an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + CRACK + Controller-role request acknowledge (when the I3C acts as controller) + + 17 + 1 + read-write + + + B_0x0 + a controller-role request from target x must be NACK-ed + 0x0 + + + B_0x1 + a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + IBIDEN + IBI data enable (when the I3C acts as controller) + + 18 + 1 + read-write + + + B_0x0 + no data byte follows the acknowledged IBI from target x + 0x0 + + + B_0x1 + the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x + 0x1 + + + + + SUSP + Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) + + 19 + 1 + read-write + + + B_0x0 + C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted + 0x0 + + + B_0x1 + I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x + 0x1 + + + + + DIS + DA[6:0] write disabled (when the I3C acts as controller) + + 31 + 1 + read-only + + + B_0x0 + write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed + 0x0 + + + B_0x1 + write to DA[7:0] and to IBIDEN is disabled/locked + 0x1 + + + + + + + I3C_DEVR3 + I3C_DEVR3 + I3C device 3 characteristics register + 0x6C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + Assigned I3C dynamic address to target x (when the I3C acts as controller) + + 1 + 7 + read-write + + + IBIACK + IBI request acknowledge (when the I3C acts as controller) + + 16 + 1 + read-write + + + B_0x0 + an IBI request from target x must be NACK-ed + 0x0 + + + B_0x1 + an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + CRACK + Controller-role request acknowledge (when the I3C acts as controller) + + 17 + 1 + read-write + + + B_0x0 + a controller-role request from target x must be NACK-ed + 0x0 + + + B_0x1 + a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + IBIDEN + IBI data enable (when the I3C acts as controller) + + 18 + 1 + read-write + + + B_0x0 + no data byte follows the acknowledged IBI from target x + 0x0 + + + B_0x1 + the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x + 0x1 + + + + + SUSP + Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) + + 19 + 1 + read-write + + + B_0x0 + C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted + 0x0 + + + B_0x1 + I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x + 0x1 + + + + + DIS + DA[6:0] write disabled (when the I3C acts as controller) + + 31 + 1 + read-only + + + B_0x0 + write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed + 0x0 + + + B_0x1 + write to DA[7:0] and to IBIDEN is disabled/locked + 0x1 + + + + + + + I3C_DEVR4 + I3C_DEVR4 + I3C device 4 characteristics register + 0x70 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DA + Assigned I3C dynamic address to target x (when the I3C acts as controller) + + 1 + 7 + read-write + + + IBIACK + IBI request acknowledge (when the I3C acts as controller) + + 16 + 1 + read-write + + + B_0x0 + an IBI request from target x must be NACK-ed + 0x0 + + + B_0x1 + an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + CRACK + Controller-role request acknowledge (when the I3C acts as controller) + + 17 + 1 + read-write + + + B_0x0 + a controller-role request from target x must be NACK-ed + 0x0 + + + B_0x1 + a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed + 0x1 + + + + + IBIDEN + IBI data enable (when the I3C acts as controller) + + 18 + 1 + read-write + + + B_0x0 + no data byte follows the acknowledged IBI from target x + 0x0 + + + B_0x1 + the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x + 0x1 + + + + + SUSP + Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) + + 19 + 1 + read-write + + + B_0x0 + C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted + 0x0 + + + B_0x1 + I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x + 0x1 + + + + + DIS + DA[6:0] write disabled (when the I3C acts as controller) + + 31 + 1 + read-only + + + B_0x0 + write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed + 0x0 + + + B_0x1 + write to DA[7:0] and to IBIDEN is disabled/locked + 0x1 + + + + + + + I3C_MAXRLR + I3C_MAXRLR + I3C maximum read length register + 0x090 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MRL + Maximum data read length (when I3C acts as target) + + 0 + 16 + read-write + + + IBIP + IBI payload data maximum size, in bytes (when I3C acts as target) + + 16 + 3 + read-write + + + B_0x0 + null payload data size (only allowed when BCR2 = 0 in the I3C_BCR register) + 0x0 + + + B_0x1 + 1 byte (mandatory data byte MDB[7:0] + 0x1 + + + B_0x2 + 2 bytes (including first MDB[7:0]) + 0x2 + + + B_0x3 + 3 bytes (including first MDB[7:0]) + 0x3 + + + B_0x4 + 4 bytes (including first MDB[7:0]) + 0x4 + + + + + + + I3C_MAXWLR + I3C_MAXWLR + I3C maximum write length register + 0x094 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MWL + Maximum data write length (when I3C acts as target) + + 0 + 16 + read-write + + + + + I3C_TIMINGR0 + I3C_TIMINGR0 + I3C timing register 0 + 0x0A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SCLL_PP + SCL low duration in I3C push-pull phases, in number of kernel clocks cycles: + + 0 + 8 + read-write + + + SCLH_I3C + SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles: + + 8 + 8 + read-write + + + SCLL_OD + SCL low duration in open-drain phases, used for legacy Iless thansup>2less than/sup>C messages and for I3C open-drain phases (address phase following a start, ACK phase during controller-initiated messages, and T bit phase during direct/private/IBI payload), in number of kernel clocks cycles: + + 16 + 8 + read-write + + + SCLH_I2C + SCL high duration, used for legacy Iless thansup>2less than/sup>C messages, in number of kernel clocks cycles: + + 24 + 8 + read-write + + + + + I3C_TIMINGR1 + I3C_TIMINGR1 + I3C timing register 1 + 0x0A4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AVAL + Number of kernel clock cycles to set a time unit of 1 s, whatever I3C acts as controller or target. + 0 + 8 + read-write + + + ASNCR + Activity state of the new controller (when I3C acts as active controller) + + 8 + 2 + read-write + + + FREE + Number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C acts as controller) + + 16 + 7 + read-write + + + SDA_HD + SDA hold time (when the I3C acts as controller), in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull tless thansub>HD_PPless than/sub>): + + 28 + 1 + read-write + + + + + I3C_TIMINGR2 + I3C_TIMINGR2 + I3C timing register 2 + 0x0A8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + STALLT + Controller clock stall enable on T-bit phase of data (and on the ACK/NACK phase of data byte of a legacy Iless thansup>2less than/sup>C read) + + 0 + 1 + read-write + + + B_0x0 + no stall + 0x0 + + + B_0x1 + stall enabled + 0x1 + + + + + STALLD + Controller clock stall enable on PAR phase of Data + + 1 + 1 + read-write + + + B_0x0 + no stall + 0x0 + + + B_0x1 + stall enabled + 0x1 + + + + + STALLC + Controller clock stall enable on PAR phase of CCC + + 2 + 1 + read-write + + + B_0x0 + no stall + 0x0 + + + B_0x1 + stall enabled + 0x1 + + + + + STALLA + Controller clock stall enable on ACK phase + + 3 + 1 + read-write + + + B_0x0 + no stall + 0x0 + + + B_0x1 + stall enabled + 0x1 + + + + + STALL + Controller clock stall time, in number of kernel clock cycles + + 8 + 8 + read-write + + + + + I3C_BCR + I3C_BCR + I3C bus characteristics register + 0x0C0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BCR0 + max data speed limitation + 0 + 1 + read-write + + + B_0x0 + no limitation + 0x0 + + + B_0x1 + limitation, as described by I3C_GETMXDSR. + 0x1 + + + + + BCR2 + in-band interrupt (IBI) payload + 2 + 1 + read-write + + + B_0x0 + no data byte follows the accepted IBI + 0x0 + + + B_0x1 + at least one mandatory data byte follows the accepted IBI (and at most 4 data bytes) + 0x1 + + + + + BCR6 + Controller capable + 6 + 1 + read-write + + + B_0x0 + I3C target (no controller capable) + 0x0 + + + B_0x1 + I3C controller capable + 0x1 + + + + + + + I3C_DCR + I3C_DCR + I3C device characteristics register + 0x0C4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DCR + device characteristics ID + + 0 + 8 + read-write + + + B_0x00 + generic device (for v1. + 0x00 + + + + + + + I3C_GETCAPR + I3C_GETCAPR + I3C get capability register + 0x0C8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CAPPEND + IBI MDB support for pending read notification + + 14 + 1 + read-write + + + B_0x0 + this I3C when acting as target sends an IBI request without a mandatory data byte value indicating a pending read notification + 0x0 + + + B_0x1 + this I3C when acting as target sends an IBI request with a mandatory data byte value (MDB[7:5] = 101), indicating a pending read notification + 0x1 + + + + + + + I3C_CRCAPR + I3C_CRCAPR + I3C controller-role capability register + 0x0CC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CAPDHOFF + delayed controller-role hand-off + + 3 + 1 + read-write + + + B_0x0 + this I3C does not needs additional time to process a controller-role hand-off + 0x0 + + + B_0x1 + this I3C needs additional time to process a controller-role hand-off + 0x1 + + + + + CAPGRP + group management support (when acting as controller) + + 9 + 1 + read-write + + + B_0x0 + this I3C does not support group address capabilities + 0x0 + + + B_0x1 + this I3C supports group address capabilities (when becoming controller) + 0x1 + + + + + + + I3C_GETMXDSR + I3C_GETMXDSR + I3C get max data speed register + 0x0D0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HOFFAS + Controller hand-off activity state + + 0 + 2 + read-write + + + B_0x0 + activity state 0 is the initial activity state of this I3C before and when becoming controller + 0x0 + + + B_0x1 + activity state 1 is the initial activity state of this I3C when becoming controller + 0x1 + + + B_0x2 + activity state 2 is the initial activity state of this I3C when becoming controller + 0x2 + + + B_0x3 + activity state 3 is the initial activity state of this I3C when becoming controller + 0x3 + + + + + FMT + GETMXDS CCC format + + 8 + 2 + read-write + + + B_0x0 + format 1 (2 bytes with MaxWr with no defining byte, MaxRd) + 0x0 + + + B_0x1 + format 2: (5 bytes w. + 0x1 + + + B_0x2 + format 2 (5 bytes with MaxWr with no defining byte, MaxRd, and middle byte of MaxRdTurn) + 0x2 + + + B_0x3 + format 2 (5 bytes with MaxWr with no defining byte, MaxRd, MSB of MaxRdTurn) + 0x3 + + + + + RDTURN + programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte) + + 16 + 8 + read-write + + + TSCO + clock-to-data turnaround time (tless thansub>SCOless than/sub>) + + 24 + 1 + read-write + + + B_0x0 + tless thansub>SCOless than/sub> less than or equal to 12 ns + 0x0 + + + B_0x1 + tless thansub>SCOless than/sub> > 12 ns (refer to the datasheet for more details) + 0x1 + + + + + + + I3C_EPIDR + I3C_EPIDR + I3C extended provisioned ID register + 0xD4 + 0x20 + read-write + 0x02080000 + 0xFFFFFFFF + + + MIPIID + 4-bit MIPI Instance ID + + 12 + 4 + read-write + + + IDTSEL + provisioned ID type selector + + 16 + 1 + read-only + + + MIPIMID + 15-bit MIPI manufacturer ID + + 17 + 15 + read-only + + + + + + + I3C_S + 0X50005C00 + + + I3C2 + 0x44003000 + + I3C2_ERR + I3C2 error interrupt + 132 + + + I3C2_EV + I3C2 event interrupt + 131 + + + + I3C2_S + 0x54003000 + + + ICACHE + ICACHE register block + ICACHE + 0x40030400 + + 0x0 + 0x400 + registers + + + ICACHE + Instruction cache global interrupt + 104 + + + + ICACHE_CR + ICACHE_CR + ICACHE control register + 0x000 + 0x20 + read-write + 0x00000004 + 0xFFFFFFFF + + + EN + enable + 0 + 1 + read-write + + + B_0x0 + cache disabled + 0x0 + + + B_0x1 + cache enabled + 0x1 + + + + + CACHEINV + cache invalidation + + 1 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + invalidate entire cache (all cache lines valid bit = 0) + 0x1 + + + + + WAYSEL + cache associativity mode selection + + 2 + 1 + read-write + + + B_0x0 + direct mapped cache (1-way cache) + 0x0 + + + B_0x1 + n-way set associative cache (reset value) + 0x1 + + + + + HITMEN + hit monitor enable + 16 + 1 + read-write + + + B_0x0 + cache hit monitor switched off. + 0x0 + + + B_0x1 + cache hit monitor enabled + 0x1 + + + + + MISSMEN + miss monitor enable + 17 + 1 + read-write + + + B_0x0 + cache miss monitor switched off. + 0x0 + + + B_0x1 + cache miss monitor enabled + 0x1 + + + + + HITMRST + hit monitor reset + 18 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + reset cache hit monitor + 0x1 + + + + + MISSMRST + miss monitor reset + 19 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + reset cache miss monitor + 0x1 + + + + + + + ICACHE_SR + ICACHE_SR + ICACHE status register + 0x004 + 0x20 + read-only + 0x00000001 + 0xFFFFFFFF + + + BUSYF + busy flag + 0 + 1 + read-only + + + B_0x0 + cache not busy on a CACHEINV operation + 0x0 + + + B_0x1 + cache executing a full invalidate CACHEINV operation + 0x1 + + + + + BSYENDF + busy end flag + 1 + 1 + read-only + + + B_0x0 + cache busy + 0x0 + + + B_0x1 + full invalidate CACHEINV operation finished + 0x1 + + + + + ERRF + cache error flag + 2 + 1 + read-only + + + B_0x0 + no error + 0x0 + + + B_0x1 + an error occurred during the operation (cacheable write) + 0x1 + + + + + + + ICACHE_IER + ICACHE_IER + ICACHE interrupt enable register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BSYENDIE + interrupt enable on busy end + + 1 + 1 + read-write + + + B_0x0 + interrupt disabled on busy end + 0x0 + + + B_0x1 + interrupt enabled on busy end + 0x1 + + + + + ERRIE + interrupt enable on cache error + + 2 + 1 + read-write + + + B_0x0 + interrupt disabled on error + 0x0 + + + B_0x1 + interrupt enabled on error + 0x1 + + + + + + + ICACHE_FCR + ICACHE_FCR + ICACHE flag clear register + 0x00C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CBSYENDF + clear busy end flag + + 1 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears BSYENDF flag in ICACHE_SR. + 0x1 + + + + + CERRF + clear cache error flag + + 2 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + clears ERRF flag in ICACHE_SR + 0x1 + + + + + + + ICACHE_HMONR + ICACHE_HMONR + ICACHE hit monitor register + 0x010 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + HITMON + cache hit monitor counter + 0 + 32 + read-only + + + + + ICACHE_MMONR + ICACHE_MMONR + ICACHE miss monitor register + 0x014 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + MISSMON + cache miss monitor counter + 0 + 16 + read-only + + + + + ICACHE_CRR0 + ICACHE_CRR0 + ICACHE region 0 configuration register + 0x20 + 0x20 + read-write + 0x00000200 + 0xFFFFFFFF + + + BASEADDR + base address for region x + + 0 + 8 + read-write + + + RSIZE + size for region x + 9 + 3 + read-write + + + B_0x1 + 2 Mbytes + 0x1 + + + B_0x2 + 4 Mbytes + 0x2 + + + B_0x3 + 8 Mbytes + 0x3 + + + B_0x4 + 16 Mbytes + 0x4 + + + B_0x5 + 32 Mbytes + 0x5 + + + B_0x6 + 64 Mbytes + 0x6 + + + B_0x7 + 128 Mbytes + 0x7 + + + + + REN + enable for region x + 15 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + REMAPADDR + remapped address for region x + + 16 + 11 + read-write + + + MSTSEL + AHB cache master selection for region x + 28 + 1 + read-write + + + B_0x0 + no action (master1 selected by default) + 0x0 + + + B_0x1 + master2 selected + 0x1 + + + + + HBURST + output burst type for region x + 31 + 1 + read-write + + + B_0x0 + WRAP + 0x0 + + + B_0x1 + INCR + 0x1 + + + + + + + ICACHE_CRR1 + ICACHE_CRR1 + ICACHE region 1 configuration register + 0x24 + 0x20 + read-write + 0x00000200 + 0xFFFFFFFF + + + BASEADDR + base address for region x + + 0 + 8 + read-write + + + RSIZE + size for region x + 9 + 3 + read-write + + + B_0x1 + 2 Mbytes + 0x1 + + + B_0x2 + 4 Mbytes + 0x2 + + + B_0x3 + 8 Mbytes + 0x3 + + + B_0x4 + 16 Mbytes + 0x4 + + + B_0x5 + 32 Mbytes + 0x5 + + + B_0x6 + 64 Mbytes + 0x6 + + + B_0x7 + 128 Mbytes + 0x7 + + + + + REN + enable for region x + 15 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + REMAPADDR + remapped address for region x + + 16 + 11 + read-write + + + MSTSEL + AHB cache master selection for region x + 28 + 1 + read-write + + + B_0x0 + no action (master1 selected by default) + 0x0 + + + B_0x1 + master2 selected + 0x1 + + + + + HBURST + output burst type for region x + 31 + 1 + read-write + + + B_0x0 + WRAP + 0x0 + + + B_0x1 + INCR + 0x1 + + + + + + + ICACHE_CRR2 + ICACHE_CRR2 + ICACHE region 2 configuration register + 0x28 + 0x20 + read-write + 0x00000200 + 0xFFFFFFFF + + + BASEADDR + base address for region x + + 0 + 8 + read-write + + + RSIZE + size for region x + 9 + 3 + read-write + + + B_0x1 + 2 Mbytes + 0x1 + + + B_0x2 + 4 Mbytes + 0x2 + + + B_0x3 + 8 Mbytes + 0x3 + + + B_0x4 + 16 Mbytes + 0x4 + + + B_0x5 + 32 Mbytes + 0x5 + + + B_0x6 + 64 Mbytes + 0x6 + + + B_0x7 + 128 Mbytes + 0x7 + + + + + REN + enable for region x + 15 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + REMAPADDR + remapped address for region x + + 16 + 11 + read-write + + + MSTSEL + AHB cache master selection for region x + 28 + 1 + read-write + + + B_0x0 + no action (master1 selected by default) + 0x0 + + + B_0x1 + master2 selected + 0x1 + + + + + HBURST + output burst type for region x + 31 + 1 + read-write + + + B_0x0 + WRAP + 0x0 + + + B_0x1 + INCR + 0x1 + + + + + + + ICACHE_CRR3 + ICACHE_CRR3 + ICACHE region 3 configuration register + 0x2C + 0x20 + read-write + 0x00000200 + 0xFFFFFFFF + + + BASEADDR + base address for region x + + 0 + 8 + read-write + + + RSIZE + size for region x + 9 + 3 + read-write + + + B_0x1 + 2 Mbytes + 0x1 + + + B_0x2 + 4 Mbytes + 0x2 + + + B_0x3 + 8 Mbytes + 0x3 + + + B_0x4 + 16 Mbytes + 0x4 + + + B_0x5 + 32 Mbytes + 0x5 + + + B_0x6 + 64 Mbytes + 0x6 + + + B_0x7 + 128 Mbytes + 0x7 + + + + + REN + enable for region x + 15 + 1 + read-write + + + B_0x0 + disabled + 0x0 + + + B_0x1 + enabled + 0x1 + + + + + REMAPADDR + remapped address for region x + + 16 + 11 + read-write + + + MSTSEL + AHB cache master selection for region x + 28 + 1 + read-write + + + B_0x0 + no action (master1 selected by default) + 0x0 + + + B_0x1 + master2 selected + 0x1 + + + + + HBURST + output burst type for region x + 31 + 1 + read-write + + + B_0x0 + WRAP + 0x0 + + + B_0x1 + INCR + 0x1 + + + + + + + + + ICACHE_S + 0X50030400 + + + IWDG + IWDG address block description + IWDG + 0x40003000 + + 0x0 + 0x18 + registers + + + IWDG + Independent watchdog interrupt + 35 + + + + IWDG_KR + IWDG_KR + IWDG key register + 0x00 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Key value (write only, read 0x0000) + + 0 + 16 + write-only + + + + + IWDG_PR + IWDG_PR + IWDG prescaler register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PR + Prescaler divider + + 0 + 4 + read-write + + + B_0x0 + divider / 4 + 0x0 + + + B_0x1 + divider / 8 + 0x1 + + + B_0x2 + divider / 16 + 0x2 + + + B_0x3 + divider / 32 + 0x3 + + + B_0x4 + divider / 64 + 0x4 + + + B_0x5 + divider / 128 + 0x5 + + + B_0x6 + divider / 256 + 0x6 + + + B_0x7 + divider / 512 + 0x7 + + + + + + + IWDG_RLR + IWDG_RLR + IWDG reload register + 0x08 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + RL + Watchdog counter reload value + + 0 + 12 + read-write + + + + + IWDG_SR + IWDG_SR + IWDG status register + 0x0C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PVU + Watchdog prescaler value update + + 0 + 1 + read-only + + + RVU + Watchdog counter reload value update + + 1 + 1 + read-only + + + WVU + Watchdog counter window value update + + 2 + 1 + read-only + + + EWU + Watchdog interrupt comparator value update + + 3 + 1 + read-only + + + ONF + Watchdog enable status bit + + 8 + 1 + read-only + + + B_0x0 + The IWDG is not activated + 0x0 + + + B_0x1 + The IWDG is activated and needs to be refreshed regularly by the application + 0x1 + + + + + EWIF + Watchdog early interrupt flag + + 14 + 1 + read-only + + + + + IWDG_WINR + IWDG_WINR + IWDG window register + 0x10 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + WIN + Watchdog counter window value + + 0 + 12 + read-write + + + + + IWDG_EWCR + IWDG_EWCR + IWDG early wake-up interrupt register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EWIT + Watchdog counter window value + + 0 + 12 + read-write + + + EWIC + Watchdog early interrupt acknowledge + + 14 + 1 + write-only + + + EWIE + Watchdog early interrupt enable + + 15 + 1 + read-write + + + B_0x0 + The early interrupt interface is disabled. + 0x0 + + + B_0x1 + The early interrupt interface is enabled. + 0x1 + + + + + + + + + IWDG_S + 0X50003000 + + + LPTIM1 + LPTIM1 address block description + LPTIM1 + 0x44004400 + + 0x0 + 0x38 + registers + + + LPTIM1 + LPTIM1 global interrupt OR LPTimer1 AIT through EXTI line + 64 + + + + LPTIM1_ISR + LPTIM1_ISR + LPTIM1 interrupt and status register [alternate] + 0x000 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CC1IF + Compare 1 interrupt flag + + 0 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value + 0x1 + + + + + ARRM + Autoreload match + + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event + + 2 + 1 + read-only + + + CMP1OK + Compare register 1 update OK + + 3 + 1 + read-only + + + ARROK + Autoreload register update OK + + 4 + 1 + read-only + + + UP + Counter direction change down to up + + 5 + 1 + read-only + + + DOWN + Counter direction change up to down + + 6 + 1 + read-only + + + UE + LPTIM update event occurred + + 7 + 1 + read-only + + + REPOK + Repetition register update OK + + 8 + 1 + read-only + + + CC2IF + Compare 2 interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value + 0x1 + + + + + CMP2OK + Compare register 2 update OK + + 19 + 1 + read-only + + + DIEROK + Interrupt enable register update OK + + 24 + 1 + read-only + + + + + LPTIM1_ISR_ALTERNATE1 + LPTIM1_ISR_ALTERNATE1 + LPTIM1 interrupt and status register + LPTIM1_ISR + 0x000 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CC1IF + capture 1 interrupt flag + + 0 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR1 register. + 0x1 + + + + + ARRM + Autoreload match + + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event + + 2 + 1 + read-only + + + ARROK + Autoreload register update OK + + 4 + 1 + read-only + + + UP + Counter direction change down to up + + 5 + 1 + read-only + + + DOWN + Counter direction change up to down + + 6 + 1 + read-only + + + UE + LPTIM update event occurred + + 7 + 1 + read-only + + + REPOK + Repetition register update OK + + 8 + 1 + read-only + + + CC2IF + Capture 2 interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR2 register. + 0x1 + + + + + CC1OF + Capture 1 over-capture flag + + 12 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set. + 0x1 + + + + + CC2OF + Capture 2 over-capture flag + + 13 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set. + 0x1 + + + + + DIEROK + Interrupt enable register update OK + + 24 + 1 + read-only + + + + + LPTIM1_ICR + LPTIM1_ICR + LPTIM1 interrupt clear register [alternate] + 0x004 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag + + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag + + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag + + 2 + 1 + write-only + + + CMP1OKCF + Compare register 1 update OK clear flag + + 3 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag + + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag + + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag + + 6 + 1 + write-only + + + UECF + Update event clear flag + + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag + + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag + + 9 + 1 + write-only + + + CMP2OKCF + Compare register 2 update OK clear flag + + 19 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag + + 24 + 1 + write-only + + + + + LPTIM1_ICR_ALTERNATE1 + LPTIM1_ICR_ALTERNATE1 + LPTIM1 interrupt clear register + LPTIM1_ICR + 0x004 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag + + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag + + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag + + 2 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag + + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag + + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag + + 6 + 1 + write-only + + + UECF + Update event clear flag + + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag + + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag + + 9 + 1 + write-only + + + CC1OCF + Capture/compare 1 over-capture clear flag + + 12 + 1 + write-only + + + CC2OCF + Capture/compare 2 over-capture clear flag + + 13 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag + + 24 + 1 + write-only + + + + + LPTIM1_DIER + LPTIM1_DIER + LPTIM1 interrupt enable register [alternate] + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + CMP1OKIE + Compare register 1 update OK interrupt enable + 3 + 1 + read-write + + + B_0x0 + CMPOK register 1 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 1 interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable + + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable + + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable + + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CMP2OKIE + Compare register 2 update OK interrupt enable + + 19 + 1 + read-write + + + B_0x0 + CMPOK register 2 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 2 interrupt enabled + 0x1 + + + + + UEDE + Update event DMA request enable + + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + + + LPTIM1_DIER_ALTERNATE1 + LPTIM1_DIER_ALTERNATE1 + LPTIM1 interrupt enable register + LPTIM1_DIER + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable + + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable + + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable + + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC1OIE + Capture/compare 1 over-capture interrupt enable + + 12 + 1 + read-write + + + B_0x0 + CC1 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC1 over-capture interrupt enabled + 0x1 + + + + + CC2OIE + Capture/compare 2 over-capture interrupt enable + + 13 + 1 + read-write + + + B_0x0 + CC2 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC2 over-capture interrupt enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable + + 16 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + UEDE + Update event DMA request enable + + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable + + 25 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + + + LPTIM_CFGR + LPTIM_CFGR + LPTIM configuration register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CKSEL + Clock selector + + 0 + 1 + read-write + + + B_0x0 + LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + 0x0 + + + B_0x1 + LPTIM is clocked by an external clock source through the LPTIM external Input1 + 0x1 + + + + + CKPOL + Clock Polarity + + 1 + 2 + read-write + + + B_0x0 + the rising edge is the active edge used for counting. + 0x0 + + + B_0x1 + the falling edge is the active edge used for counting. + 0x1 + + + B_0x2 + both edges are active edges. + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CKFLT + Configurable digital filter for external clock + + 3 + 2 + read-write + + + B_0x0 + any external clock signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + TRGFLT + Configurable digital filter for trigger + + 6 + 2 + read-write + + + B_0x0 + any trigger active level change is considered as a valid trigger + 0x0 + + + B_0x1 + trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. + 0x1 + + + B_0x2 + trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. + 0x2 + + + B_0x3 + trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. + 0x3 + + + + + PRESC + Clock prescaler + + 9 + 3 + read-write + + + B_0x0 + /1 + 0x0 + + + B_0x1 + /2 + 0x1 + + + B_0x2 + /4 + 0x2 + + + B_0x3 + /8 + 0x3 + + + B_0x4 + /16 + 0x4 + + + B_0x5 + /32 + 0x5 + + + B_0x6 + /64 + 0x6 + + + B_0x7 + /128 + 0x7 + + + + + TRIGSEL + Trigger selector + + 13 + 3 + read-write + + + B_0x0 + lptim_ext_trig0 + 0x0 + + + B_0x1 + lptim_ext_trig1 + 0x1 + + + B_0x2 + lptim_ext_trig2 + 0x2 + + + B_0x3 + lptim_ext_trig3 + 0x3 + + + B_0x4 + lptim_ext_trig4 + 0x4 + + + B_0x5 + lptim_ext_trig5 + 0x5 + + + B_0x6 + lptim_ext_trig6 + 0x6 + + + B_0x7 + lptim_ext_trig7 + 0x7 + + + + + TRIGEN + Trigger enable and polarity + + 17 + 2 + read-write + + + B_0x0 + software trigger (counting start is initiated by software) + 0x0 + + + B_0x1 + rising edge is the active edge + 0x1 + + + B_0x2 + falling edge is the active edge + 0x2 + + + B_0x3 + both edges are active edges + 0x3 + + + + + TIMOUT + Timeout enable + + 19 + 1 + read-write + + + B_0x0 + A trigger event arriving when the timer is already started is ignored + 0x0 + + + B_0x1 + A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter + 0x1 + + + + + WAVE + Waveform shape + + 20 + 1 + read-write + + + B_0x0 + Deactivate Set-once mode + 0x0 + + + B_0x1 + Activate the Set-once mode + 0x1 + + + + + WAVPOL + Waveform shape polarity + + 21 + 1 + read-write + + + B_0x0 + The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers + 0x0 + + + B_0x1 + The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers + 0x1 + + + + + PRELOAD + Registers update mode + + 22 + 1 + read-write + + + B_0x0 + Registers are updated after each APB bus write access + 0x0 + + + B_0x1 + Registers are updated at the end of the current LPTIM period + 0x1 + + + + + COUNTMODE + counter mode enabled + + 23 + 1 + read-write + + + B_0x0 + the counter is incremented following each internal clock pulse + 0x0 + + + B_0x1 + the counter is incremented following each valid clock pulse on the LPTIM external Input1 + 0x1 + + + + + ENC + Encoder mode enable + + 24 + 1 + read-write + + + B_0x0 + Encoder mode disabled + 0x0 + + + B_0x1 + Encoder mode enabled + 0x1 + + + + + + + LPTIM_CR + LPTIM_CR + LPTIM control register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ENABLE + LPTIM enable + + 0 + 1 + read-write + + + B_0x0 + LPTIM is disabled. + 0x0 + + + B_0x1 + LPTIM is enabled + 0x1 + + + + + SNGSTRT + LPTIM start in Single mode + + 1 + 1 + read-write + + + CNTSTRT + Timer start in Continuous mode + + 2 + 1 + read-write + + + COUNTRST + Counter reset + + 3 + 1 + read-write + + + RSTARE + Reset after read enable + + 4 + 1 + read-write + + + + + LPTIM_CCR1 + LPTIM_CCR1 + LPTIM compare register 1 + 0x014 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 16 + read-write + + + + + LPTIM_ARR + LPTIM_ARR + LPTIM autoreload register + 0x018 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + ARR + Auto reload value + + 0 + 16 + read-write + + + + + LPTIM_CNT + LPTIM_CNT + LPTIM counter register + 0x01C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-only + + + + + LPTIM_CFGR2 + LPTIM_CFGR2 + LPTIM configuration register 2 + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IN1SEL + LPTIM input 1 selection + + 0 + 2 + read-write + + + B_0x0 + lptim_in1_mux0 + 0x0 + + + B_0x1 + lptim_in1_mux1 + 0x1 + + + B_0x2 + lptim_in1_mux2 + 0x2 + + + B_0x3 + lptim_in1_mux3 + 0x3 + + + + + IN2SEL + LPTIM input 2 selection + + 4 + 2 + read-write + + + B_0x0 + lptim_in2_mux0 + 0x0 + + + B_0x1 + lptim_in2_mux1 + 0x1 + + + B_0x2 + lptim_in2_mux2 + 0x2 + + + B_0x3 + lptim_in2_mux3 + 0x3 + + + + + IC1SEL + LPTIM input capture 1 selection + + 16 + 2 + read-write + + + B_0x0 + lptim_ic1_mux0 + 0x0 + + + B_0x1 + lptim_ic1_mux1 + 0x1 + + + B_0x2 + lptim_ic1_mux2 + 0x2 + + + B_0x3 + lptim_ic1_mux3 + 0x3 + + + + + IC2SEL + LPTIM input capture 2 selection + + 20 + 2 + read-write + + + B_0x0 + lptim_ic2_mux0 + 0x0 + + + B_0x1 + lptim_ic2_mux1 + 0x1 + + + B_0x2 + lptim_ic2_mux2 + 0x2 + + + B_0x3 + lptim_ic2_mux3 + 0x3 + + + + + + + LPTIM_RCR + LPTIM_RCR + LPTIM repetition register + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REP + Repetition register value + + 0 + 8 + read-write + + + + + LPTIM_CCMR1 + LPTIM_CCMR1 + LPTIM capture/compare mode register 1 + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1SEL + Capture/compare 1 selection + + 0 + 1 + read-write + + + B_0x0 + CC1 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC1 channel is configured in input capture mode + 0x1 + + + + + CC1E + Capture/compare 1 output enable. + 1 + 1 + read-write + + + B_0x0_CC1_AS_OUTPUT + Off - OC1 is not active. + 0x0 + + + B_0x1_CC1_AS_OUTPUT + On - OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/compare 1 output polarity. + 2 + 2 + read-write + + + B_0x0_CC1_AS_OUTPUT + OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers + 0x0 + + + B_0x1_CC1_AS_OUTPUT + OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers + 0x1 + + + B_0x3_CC1_AS_INPUT + both edges, circuit is sensitive to both IC1 rising and falling edges. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC2SEL + Capture/compare 2 selection + + 16 + 1 + read-write + + + B_0x0 + CC2 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC2 channel is configured in input capture mode + 0x1 + + + + + CC2E + Capture/compare 2 output enable. + 17 + 1 + read-write + + + B_0x0_CC2_AS_OUTPUT + Off - OC2 is not active. + 0x0 + + + B_0x1_CC2_AS_OUTPUT + On - OC2 signal is output on the corresponding output pin + 0x1 + + + + + CC2P + Capture/compare 2 output polarity. + 18 + 2 + read-write + + + B_0x0_CC2_AS_OUTPUT + OC2 active high + 0x0 + + + B_0x1_CC2_AS_OUTPUT + OC2 active low + 0x1 + + + B_0x3_CC2_AS_INPUT + both edges, circuit is sensitive to both IC2 rising and falling edges. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC2F + Input capture 2 filter + + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM_CCR2 + LPTIM_CCR2 + LPTIM compare register 2 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 16 + read-write + + + + + + + LPTIM1_S + 0x54004400 + + + LPTIM2 + LPTIM2 address block description + LPTIM2 + 0x40009400 + + 0x0 + 0x38 + registers + + + LPTIM2 + LPTIM2 global interrupt OR LPTimer2 AIT through EXTI line + 70 + + + + LPTIM2_ISR + LPTIM2_ISR + LPTIM2 interrupt and status register [alternate] + 0x000 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CC1IF + Compare 1 interrupt flag + + 0 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register's value + 0x1 + + + + + ARRM + Autoreload match + + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event + + 2 + 1 + read-only + + + CMP1OK + Compare register 1 update OK + + 3 + 1 + read-only + + + ARROK + Autoreload register update OK + + 4 + 1 + read-only + + + UP + Counter direction change down to up + + 5 + 1 + read-only + + + DOWN + Counter direction change up to down + + 6 + 1 + read-only + + + UE + LPTIM update event occurred + + 7 + 1 + read-only + + + REPOK + Repetition register update OK + + 8 + 1 + read-only + + + CC2IF + Compare 2 interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No match + 0x0 + + + B_0x1 + The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register's value + 0x1 + + + + + CMP2OK + Compare register 2 update OK + + 19 + 1 + read-only + + + DIEROK + Interrupt enable register update OK + + 24 + 1 + read-only + + + + + LPTIM2_ISR_ALTERNATE1 + LPTIM2_ISR_ALTERNATE1 + LPTIM2 interrupt and status register + LPTIM2_ISR + 0x000 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CC1IF + capture 1 interrupt flag + + 0 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR1 register. + 0x1 + + + + + ARRM + Autoreload match + + 1 + 1 + read-only + + + EXTTRIG + External trigger edge event + + 2 + 1 + read-only + + + ARROK + Autoreload register update OK + + 4 + 1 + read-only + + + UP + Counter direction change down to up + + 5 + 1 + read-only + + + DOWN + Counter direction change up to down + + 6 + 1 + read-only + + + UE + LPTIM update event occurred + + 7 + 1 + read-only + + + REPOK + Repetition register update OK + + 8 + 1 + read-only + + + CC2IF + Capture 2 interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No input capture occurred + 0x0 + + + B_0x1 + The counter value has been captured in the LPTIM_CCR2 register. + 0x1 + + + + + CC1OF + Capture 1 over-capture flag + + 12 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set. + 0x1 + + + + + CC2OF + Capture 2 over-capture flag + + 13 + 1 + read-only + + + B_0x0 + No over-capture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set. + 0x1 + + + + + DIEROK + Interrupt enable register update OK + + 24 + 1 + read-only + + + + + LPTIM2_ICR + LPTIM2_ICR + LPTIM2 interrupt clear register [alternate] + 0x004 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag + + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag + + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag + + 2 + 1 + write-only + + + CMP1OKCF + Compare register 1 update OK clear flag + + 3 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag + + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag + + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag + + 6 + 1 + write-only + + + UECF + Update event clear flag + + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag + + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag + + 9 + 1 + write-only + + + CMP2OKCF + Compare register 2 update OK clear flag + + 19 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag + + 24 + 1 + write-only + + + + + LPTIM2_ICR_ALTERNATE1 + LPTIM2_ICR_ALTERNATE1 + LPTIM2 interrupt clear register + LPTIM2_ICR + 0x004 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CC1CF + Capture/compare 1 clear flag + + 0 + 1 + write-only + + + ARRMCF + Autoreload match clear flag + + 1 + 1 + write-only + + + EXTTRIGCF + External trigger valid edge clear flag + + 2 + 1 + write-only + + + ARROKCF + Autoreload register update OK clear flag + + 4 + 1 + write-only + + + UPCF + Direction change to UP clear flag + + 5 + 1 + write-only + + + DOWNCF + Direction change to down clear flag + + 6 + 1 + write-only + + + UECF + Update event clear flag + + 7 + 1 + write-only + + + REPOKCF + Repetition register update OK clear flag + + 8 + 1 + write-only + + + CC2CF + Capture/compare 2 clear flag + + 9 + 1 + write-only + + + CC1OCF + Capture/compare 1 over-capture clear flag + + 12 + 1 + write-only + + + CC2OCF + Capture/compare 2 over-capture clear flag + + 13 + 1 + write-only + + + DIEROKCF + Interrupt enable register update OK clear flag + + 24 + 1 + write-only + + + + + LPTIM2_DIER + LPTIM2_DIER + LPTIM2 interrupt enable register [alternate] + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + CMP1OKIE + Compare register 1 update OK interrupt enable + 3 + 1 + read-write + + + B_0x0 + CMPOK register 1 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 1 interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable + + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable + + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable + + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CMP2OKIE + Compare register 2 update OK interrupt enable + + 19 + 1 + read-write + + + B_0x0 + CMPOK register 2 interrupt disabled + 0x0 + + + B_0x1 + CMPOK register 2 interrupt enabled + 0x1 + + + + + UEDE + Update event DMA request enable + + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + + + LPTIM2_DIER_ALTERNATE1 + LPTIM2_DIER_ALTERNATE1 + LPTIM2 interrupt enable register + LPTIM2_DIER + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1IE + Capture/compare 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Capture/compare 1 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 1 interrupt enabled + 0x1 + + + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + read-write + + + B_0x0 + ARRM interrupt disabled + 0x0 + + + B_0x1 + ARRM interrupt enabled + 0x1 + + + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + read-write + + + B_0x0 + EXTTRIG interrupt disabled + 0x0 + + + B_0x1 + EXTTRIG interrupt enabled + 0x1 + + + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + read-write + + + B_0x0 + ARROK interrupt disabled + 0x0 + + + B_0x1 + ARROK interrupt enabled + 0x1 + + + + + UPIE + Direction change to UP Interrupt Enable + + 5 + 1 + read-write + + + B_0x0 + UP interrupt disabled + 0x0 + + + B_0x1 + UP interrupt enabled + 0x1 + + + + + DOWNIE + Direction change to down Interrupt Enable + + 6 + 1 + read-write + + + B_0x0 + DOWN interrupt disabled + 0x0 + + + B_0x1 + DOWN interrupt enabled + 0x1 + + + + + UEIE + Update event interrupt enable + 7 + 1 + read-write + + + B_0x0 + Update event interrupt disabled + 0x0 + + + B_0x1 + Update event interrupt enabled + 0x1 + + + + + REPOKIE + Repetition register update OK interrupt Enable + 8 + 1 + read-write + + + B_0x0 + Repetition register update OK interrupt disabled + 0x0 + + + B_0x1 + Repetition register update OK interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable + + 9 + 1 + read-write + + + B_0x0 + Capture/compare 2 interrupt disabled + 0x0 + + + B_0x1 + Capture/compare 2 interrupt enabled + 0x1 + + + + + CC1OIE + Capture/compare 1 over-capture interrupt enable + + 12 + 1 + read-write + + + B_0x0 + CC1 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC1 over-capture interrupt enabled + 0x1 + + + + + CC2OIE + Capture/compare 2 over-capture interrupt enable + + 13 + 1 + read-write + + + B_0x0 + CC2 over-capture interrupt disabled + 0x0 + + + B_0x1 + CC2 over-capture interrupt enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable + + 16 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + UEDE + Update event DMA request enable + + 23 + 1 + read-write + + + B_0x0 + UE DMA request disabled. + 0x0 + + + B_0x1 + UE DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable + + 25 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + + + LPTIM_CFGR + LPTIM_CFGR + LPTIM configuration register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CKSEL + Clock selector + + 0 + 1 + read-write + + + B_0x0 + LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + 0x0 + + + B_0x1 + LPTIM is clocked by an external clock source through the LPTIM external Input1 + 0x1 + + + + + CKPOL + Clock Polarity + + 1 + 2 + read-write + + + B_0x0 + the rising edge is the active edge used for counting. + 0x0 + + + B_0x1 + the falling edge is the active edge used for counting. + 0x1 + + + B_0x2 + both edges are active edges. + 0x2 + + + B_0x3 + not allowed + 0x3 + + + + + CKFLT + Configurable digital filter for external clock + + 3 + 2 + read-write + + + B_0x0 + any external clock signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + TRGFLT + Configurable digital filter for trigger + + 6 + 2 + read-write + + + B_0x0 + any trigger active level change is considered as a valid trigger + 0x0 + + + B_0x1 + trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. + 0x1 + + + B_0x2 + trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. + 0x2 + + + B_0x3 + trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. + 0x3 + + + + + PRESC + Clock prescaler + + 9 + 3 + read-write + + + B_0x0 + /1 + 0x0 + + + B_0x1 + /2 + 0x1 + + + B_0x2 + /4 + 0x2 + + + B_0x3 + /8 + 0x3 + + + B_0x4 + /16 + 0x4 + + + B_0x5 + /32 + 0x5 + + + B_0x6 + /64 + 0x6 + + + B_0x7 + /128 + 0x7 + + + + + TRIGSEL + Trigger selector + + 13 + 3 + read-write + + + B_0x0 + lptim_ext_trig0 + 0x0 + + + B_0x1 + lptim_ext_trig1 + 0x1 + + + B_0x2 + lptim_ext_trig2 + 0x2 + + + B_0x3 + lptim_ext_trig3 + 0x3 + + + B_0x4 + lptim_ext_trig4 + 0x4 + + + B_0x5 + lptim_ext_trig5 + 0x5 + + + B_0x6 + lptim_ext_trig6 + 0x6 + + + B_0x7 + lptim_ext_trig7 + 0x7 + + + + + TRIGEN + Trigger enable and polarity + + 17 + 2 + read-write + + + B_0x0 + software trigger (counting start is initiated by software) + 0x0 + + + B_0x1 + rising edge is the active edge + 0x1 + + + B_0x2 + falling edge is the active edge + 0x2 + + + B_0x3 + both edges are active edges + 0x3 + + + + + TIMOUT + Timeout enable + + 19 + 1 + read-write + + + B_0x0 + A trigger event arriving when the timer is already started is ignored + 0x0 + + + B_0x1 + A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter + 0x1 + + + + + WAVE + Waveform shape + + 20 + 1 + read-write + + + B_0x0 + Deactivate Set-once mode + 0x0 + + + B_0x1 + Activate the Set-once mode + 0x1 + + + + + WAVPOL + Waveform shape polarity + + 21 + 1 + read-write + + + B_0x0 + The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers + 0x0 + + + B_0x1 + The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers + 0x1 + + + + + PRELOAD + Registers update mode + + 22 + 1 + read-write + + + B_0x0 + Registers are updated after each APB bus write access + 0x0 + + + B_0x1 + Registers are updated at the end of the current LPTIM period + 0x1 + + + + + COUNTMODE + counter mode enabled + + 23 + 1 + read-write + + + B_0x0 + the counter is incremented following each internal clock pulse + 0x0 + + + B_0x1 + the counter is incremented following each valid clock pulse on the LPTIM external Input1 + 0x1 + + + + + ENC + Encoder mode enable + + 24 + 1 + read-write + + + B_0x0 + Encoder mode disabled + 0x0 + + + B_0x1 + Encoder mode enabled + 0x1 + + + + + + + LPTIM_CR + LPTIM_CR + LPTIM control register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ENABLE + LPTIM enable + + 0 + 1 + read-write + + + B_0x0 + LPTIM is disabled. + 0x0 + + + B_0x1 + LPTIM is enabled + 0x1 + + + + + SNGSTRT + LPTIM start in Single mode + + 1 + 1 + read-write + + + CNTSTRT + Timer start in Continuous mode + + 2 + 1 + read-write + + + COUNTRST + Counter reset + + 3 + 1 + read-write + + + RSTARE + Reset after read enable + + 4 + 1 + read-write + + + + + LPTIM_CCR1 + LPTIM_CCR1 + LPTIM compare register 1 + 0x014 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 16 + read-write + + + + + LPTIM_ARR + LPTIM_ARR + LPTIM autoreload register + 0x018 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + ARR + Auto reload value + + 0 + 16 + read-write + + + + + LPTIM_CNT + LPTIM_CNT + LPTIM counter register + 0x01C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-only + + + + + LPTIM_CFGR2 + LPTIM_CFGR2 + LPTIM configuration register 2 + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IN1SEL + LPTIM input 1 selection + + 0 + 2 + read-write + + + B_0x0 + lptim_in1_mux0 + 0x0 + + + B_0x1 + lptim_in1_mux1 + 0x1 + + + B_0x2 + lptim_in1_mux2 + 0x2 + + + B_0x3 + lptim_in1_mux3 + 0x3 + + + + + IN2SEL + LPTIM input 2 selection + + 4 + 2 + read-write + + + B_0x0 + lptim_in2_mux0 + 0x0 + + + B_0x1 + lptim_in2_mux1 + 0x1 + + + B_0x2 + lptim_in2_mux2 + 0x2 + + + B_0x3 + lptim_in2_mux3 + 0x3 + + + + + IC1SEL + LPTIM input capture 1 selection + + 16 + 2 + read-write + + + B_0x0 + lptim_ic1_mux0 + 0x0 + + + B_0x1 + lptim_ic1_mux1 + 0x1 + + + B_0x2 + lptim_ic1_mux2 + 0x2 + + + B_0x3 + lptim_ic1_mux3 + 0x3 + + + + + IC2SEL + LPTIM input capture 2 selection + + 20 + 2 + read-write + + + B_0x0 + lptim_ic2_mux0 + 0x0 + + + B_0x1 + lptim_ic2_mux1 + 0x1 + + + B_0x2 + lptim_ic2_mux2 + 0x2 + + + B_0x3 + lptim_ic2_mux3 + 0x3 + + + + + + + LPTIM_RCR + LPTIM_RCR + LPTIM repetition register + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REP + Repetition register value + + 0 + 8 + read-write + + + + + LPTIM_CCMR1 + LPTIM_CCMR1 + LPTIM capture/compare mode register 1 + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1SEL + Capture/compare 1 selection + + 0 + 1 + read-write + + + B_0x0 + CC1 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC1 channel is configured in input capture mode + 0x1 + + + + + CC1E + Capture/compare 1 output enable. + 1 + 1 + read-write + + + B_0x0_CC1_AS_OUTPUT + Off - OC1 is not active. + 0x0 + + + B_0x1_CC1_AS_OUTPUT + On - OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/compare 1 output polarity. + 2 + 2 + read-write + + + B_0x0_CC1_AS_OUTPUT + OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers + 0x0 + + + B_0x1_CC1_AS_OUTPUT + OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers + 0x1 + + + B_0x3_CC1_AS_INPUT + both edges, circuit is sensitive to both IC1 rising and falling edges. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 8 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 12 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + CC2SEL + Capture/compare 2 selection + + 16 + 1 + read-write + + + B_0x0 + CC2 channel is configured in output PWM mode + 0x0 + + + B_0x1 + CC2 channel is configured in input capture mode + 0x1 + + + + + CC2E + Capture/compare 2 output enable. + 17 + 1 + read-write + + + B_0x0_CC2_AS_OUTPUT + Off - OC2 is not active. + 0x0 + + + B_0x1_CC2_AS_OUTPUT + On - OC2 signal is output on the corresponding output pin + 0x1 + + + + + CC2P + Capture/compare 2 output polarity. + 18 + 2 + read-write + + + B_0x0_CC2_AS_OUTPUT + OC2 active high + 0x0 + + + B_0x1_CC2_AS_OUTPUT + OC2 active low + 0x1 + + + B_0x3_CC2_AS_INPUT + both edges, circuit is sensitive to both IC2 rising and falling edges. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + + 24 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC2F + Input capture 2 filter + + 28 + 2 + read-write + + + B_0x0 + any external input capture signal level change is considered as a valid transition + 0x0 + + + B_0x1 + external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. + 0x1 + + + B_0x2 + external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. + 0x2 + + + B_0x3 + external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. + 0x3 + + + + + + + LPTIM_CCR2 + LPTIM_CCR2 + LPTIM compare register 2 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 16 + read-write + + + + + + + LPTIM2_S + 0X50009400 + + + LPUART + LPUART address block description + LPUART + 0x44002400 + + 0x0 + 0x30 + registers + + + LPUART1 + LPUART1 global interrupt OR LPUART1 R Wakeup OR LPUART1 T Wakeup Char(10)through EXTI line + 63 + + + + LPUART_CR1 + LPUART_CR1 + LPUART control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + LPUART enable + + 0 + 1 + read-write + + + B_0x0 + LPUART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + LPUART enabled + 0x1 + + + + + UESM + LPUART enable in low-power mode + + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable + + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable + + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable + + 4 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register + 0x1 + + + + + RXFNEIE + RXFIFO not empty interrupt enable + + 5 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever ORE=1 or RXFNE=1 in the LPUART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register + 0x1 + + + + + TXFNFIE + TXFIFO not full interrupt enable + + 7 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever TXFNF =1 in the LPUART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable + + 8 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register + 0x1 + + + + + PS + Parity selection + + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable + + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method + + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length + + 12 + 1 + read-write + + + MME + Mute mode enable + + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable + + 14 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register. + 0x1 + + + + + DEDT + Driver Enable deassertion time + + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time + + 21 + 5 + read-write + + + M1 + Word length + + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable + + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + TXFEIE + TXFIFO empty interrupt enable + + 30 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when TXFE=1 in the LPUART_ISR register + 0x1 + + + + + RXFFIE + RXFIFO Full interrupt enable + + 31 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when RXFF=1 in the LPUART_ISR register + 0x1 + + + + + + + LPUART_CR1_ALTERNATE1 + LPUART_CR1_ALTERNATE1 + LPUART control register 1 + LPUART_CR1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + LPUART enable + + 0 + 1 + read-write + + + B_0x0 + LPUART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + LPUART enabled + 0x1 + + + + + UESM + LPUART enable in low-power mode + + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable + + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable + + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable + + 4 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register + 0x1 + + + + + RXNEIE + Receive data register not empty + + 5 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever ORE=1 or RXNE=1 in the LPUART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register + 0x1 + + + + + TXEIE + Transmit data register empty + + 7 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated whenever TXE =1 in the LPUART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable + + 8 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register + 0x1 + + + + + PS + Parity selection + + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable + + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method + + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length + + 12 + 1 + read-write + + + MME + Mute mode enable + + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable + + 14 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register. + 0x1 + + + + + DEDT + Driver Enable deassertion time + + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time + + 21 + 5 + read-write + + + M1 + Word length + + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable + + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + + + LPUART_CR2 + LPUART_CR2 + LPUART control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + + 4 + 1 + read-write + + + B_0x0 + 4-bit address detection + 0x0 + + + B_0x1 + 7-bit address detection (in 8-bit data mode) + 0x1 + + + + + STOP + STOP bits + + 12 + 2 + read-write + + + B_0x0 + 1 stop bit + 0x0 + + + B_0x2 + 2 stop bits + 0x2 + + + + + SWAP + Swap TX/RX pins + + 15 + 1 + read-write + + + B_0x0 + TX/RX pins are used as defined in standard pinout + 0x0 + + + B_0x1 + The TX and RX pins functions are swapped. + 0x1 + + + + + RXINV + RX pin active level inversion + + 16 + 1 + read-write + + + B_0x0 + RX pin signal works using the standard logic levels (Vless thansub>DDless than/sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + RX pin signal values are inverted. + 0x1 + + + + + TXINV + TX pin active level inversion + + 17 + 1 + read-write + + + B_0x0 + TX pin signal works using the standard logic levels (Vless thansub>DDless than/sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + TX pin signal values are inverted. + 0x1 + + + + + DATAINV + Binary data inversion + + 18 + 1 + read-write + + + B_0x0 + Logical data from the data register are send/received in positive/direct logic. + 0x0 + + + B_0x1 + Logical data from the data register are send/received in negative/inverse logic. + 0x1 + + + + + MSBFIRST + Most significant bit first + + 19 + 1 + read-write + + + B_0x0 + data is transmitted/received with data bit 0 first, following the start bit. + 0x0 + + + B_0x1 + data is transmitted/received with the MSB (bit 7/8) first, following the start bit. + 0x1 + + + + + ADD + Address of the LPUART node + + 24 + 8 + read-write + + + + + LPUART_CR3 + LPUART_CR3 + LPUART control register 3 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable + + 0 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated when FE=1 or ORE=1 or NE=1 in the LPUART_ISR register. + 0x1 + + + + + HDSEL + Half-duplex selection + + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + DMAR + DMA enable receiver + + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter + + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable + + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. + 0x1 + + + + + CTSE + CTS enable + + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). + 0x1 + + + + + CTSIE + CTS interrupt enable + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the LPUART_ISR register + 0x1 + + + + + OVRDIS + Overrun Disable + + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. + 0x1 + + + + + DDRE + DMA Disable on reception Error + + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. + 0x0 + + + B_0x1 + DMA is disabled following a reception error. + 0x1 + + + + + DEM + Driver enable mode + + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. + 0x1 + + + + + DEP + Driver enable polarity selection + + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection + + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection + + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUFIE + Wake-up from low-power mode interrupt enable + + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the LPUART_ISR register + 0x1 + + + + + TXFTIE + TXFIFO threshold interrupt enable + + 23 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + A LPUART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG. + 0x1 + + + + + RXFTCFG + Receive FIFO threshold configuration + + 25 + 3 + read-write + + + B_0x0 + Receive FIFO reaches 1/8 of its depth. + 0x0 + + + B_0x1 + Receive FIFO reaches 1/4 of its depth. + 0x1 + + + B_0x6 + Receive FIFO reaches 1/2 of its depth. + 0x6 + + + B_0x3 + Receive FIFO reaches 3/4 of its depth. + 0x3 + + + B_0x4 + Receive FIFO reaches 7/8 of its depth. + 0x4 + + + B_0x5 + Receive FIFO becomes full. + 0x5 + + + + + RXFTIE + RXFIFO threshold interrupt enable + + 28 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An LPUART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG. + 0x1 + + + + + TXFTCFG + TXFIFO threshold configuration + + 29 + 3 + read-write + + + B_0x0 + TXFIFO reaches 1/8 of its depth. + 0x0 + + + B_0x1 + TXFIFO reaches 1/4 of its depth. + 0x1 + + + B_0x6 + TXFIFO reaches 1/2 of its depth. + 0x6 + + + B_0x3 + TXFIFO reaches 3/4 of its depth. + 0x3 + + + B_0x4 + TXFIFO reaches 7/8 of its depth. + 0x4 + + + B_0x5 + TXFIFO becomes empty. + 0x5 + + + + + + + LPUART_CR3_ALTERNATE1 + LPUART_CR3_ALTERNATE1 + LPUART control register 3 + LPUART_CR3 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable + + 0 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated when FE=1 or ORE=1 or NE=1 in the LPUART_ISR register. + 0x1 + + + + + HDSEL + Half-duplex selection + + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + DMAR + DMA enable receiver + + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter + + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable + + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. + 0x1 + + + + + CTSE + CTS enable + + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). + 0x1 + + + + + CTSIE + CTS interrupt enable + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the LPUART_ISR register + 0x1 + + + + + OVRDIS + Overrun Disable + + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. + 0x1 + + + + + DDRE + DMA Disable on reception Error + + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. + 0x0 + + + B_0x1 + DMA is disabled following a reception error. + 0x1 + + + + + DEM + Driver enable mode + + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. + 0x1 + + + + + DEP + Driver enable polarity selection + + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection + + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection + + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUFIE + Wake-up from low-power mode interrupt enable + + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the LPUART_ISR register + 0x1 + + + + + + + LPUART_BRR + LPUART_BRR + LPUART baud rate register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRR + LPUART baud rate division (LPUARTDIV) + 0 + 20 + read-write + + + + + LPUART_RQR + LPUART_RQR + LPUART request register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SBKRQ + Send break request + + 1 + 1 + write-only + + + MMRQ + Mute mode request + + 2 + 1 + write-only + + + RXFRQ + Receive data flush request + + 3 + 1 + write-only + + + TXFRQ + Transmit data flush request + + 4 + 1 + write-only + + + + + LPUART_ISR + LPUART_ISR + LPUART interrupt and status register + 0x1C + 0x20 + read-only + 0x008000C0 + 0xFFFFFFFF + + + PE + Parity error + + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error + + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Start bit noise detection flag + + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error + + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected + + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXFNE + RXFIFO not empty + + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete + + 6 + 1 + read-only + + + TXFNF + TXFIFO not full + + 7 + 1 + read-only + + + B_0x0 + Data register is full/Transmit FIFO is full. + 0x0 + + + B_0x1 + Data register/Transmit FIFO is not full. + 0x1 + + + + + CTSIF + CTS interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag + + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + BUSY + Busy flag + + 16 + 1 + read-only + + + B_0x0 + LPUART is idle (no reception) + 0x0 + + + B_0x1 + reception ongoing + 0x1 + + + + + CMF + Character match flag + + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag + + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from mute mode + + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag + + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag + + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag + + 22 + 1 + read-only + + + TXFE + TXFIFO Empty + + 23 + 1 + read-only + + + B_0x0 + TXFIFO is not empty. + 0x0 + + + B_0x1 + TXFIFO is empty. + 0x1 + + + + + RXFF + RXFIFO Full + + 24 + 1 + read-only + + + B_0x0 + RXFIFO is not Full. + 0x0 + + + B_0x1 + RXFIFO is Full. + 0x1 + + + + + RXFT + RXFIFO threshold flag + + 26 + 1 + read-only + + + B_0x0 + Receive FIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + Receive FIFO reached the programmed threshold. + 0x1 + + + + + TXFT + TXFIFO threshold flag + + 27 + 1 + read-only + + + B_0x0 + TXFIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + TXFIFO reached the programmed threshold. + 0x1 + + + + + + + LPUART_ISR_ALTERNATE1 + LPUART_ISR_ALTERNATE1 + LPUART interrupt and status register + LPUART_ISR + 0x1C + 0x20 + read-only + 0x000000C0 + 0xFFFFFFFF + + + PE + Parity error + + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error + + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Start bit noise detection flag + + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error + + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected + + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXNE + Read data register not empty + + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete + + 6 + 1 + read-only + + + TXE + Transmit data register empty + + 7 + 1 + read-only + + + B_0x0 + Data register full + 0x0 + + + B_0x1 + Data register empty + 0x1 + + + + + CTSIF + CTS interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag + + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + BUSY + Busy flag + + 16 + 1 + read-only + + + B_0x0 + LPUART is idle (no reception) + 0x0 + + + B_0x1 + Reception ongoing + 0x1 + + + + + CMF + Character match flag + + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag + + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from mute mode + + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag + + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag + + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag + + 22 + 1 + read-only + + + + + LPUART_ICR + LPUART_ICR + LPUART interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + PECF + Parity error clear flag + + 0 + 1 + write-only + + + FECF + Framing error clear flag + + 1 + 1 + write-only + + + NECF + Noise detected clear flag + + 2 + 1 + write-only + + + ORECF + Overrun error clear flag + + 3 + 1 + write-only + + + IDLECF + Idle line detected clear flag + + 4 + 1 + write-only + + + TCCF + Transmission complete clear flag + + 6 + 1 + write-only + + + CTSCF + CTS clear flag + + 9 + 1 + write-only + + + CMCF + Character match clear flag + + 17 + 1 + write-only + + + WUCF + Wake-up from low-power mode clear flag + + 20 + 1 + write-only + + + + + LPUART_RDR + LPUART_RDR + LPUART receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDR + Receive data value + + 0 + 9 + read-only + + + + + LPUART_TDR + LPUART_TDR + LPUART transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDR + Transmit data value + + 0 + 9 + read-write + + + + + LPUART_PRESC + LPUART_PRESC + LPUART prescaler register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler + + 0 + 4 + read-write + + + B_0x0 + input clock not divided + 0x0 + + + B_0x1 + input clock divided by 2 + 0x1 + + + B_0x2 + input clock divided by 4 + 0x2 + + + B_0x3 + input clock divided by 6 + 0x3 + + + B_0x4 + input clock divided by 8 + 0x4 + + + B_0x5 + input clock divided by 10 + 0x5 + + + B_0x6 + input clock divided by 12 + 0x6 + + + B_0x7 + input clock divided by 16 + 0x7 + + + B_0x8 + input clock divided by 32 + 0x8 + + + B_0x9 + input clock divided by 64 + 0x9 + + + B_0xA + input clock divided by 128 + 0xA + + + B_0xB + input clock divided by 256 + 0xB + + + + + + + + + LPUART_S + 0X54002400 + + + OCTOSPI + OCTOSPI register block + OCTOSPI + 0x47001400 + + 0x0 + 0x400 + registers + + + OCTOSPI1 + OCTOSPI1 global interrupt + 78 + + + + OCTOSPI_CR + OCTOSPI_CR + OCTOSPI control register + 0x0000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + Enable + + 0 + 1 + read-write + + + B_0x0 + OCTOSPI disabled + 0x0 + + + B_0x1 + OCTOSPI enabled + 0x1 + + + + + ABORT + Abort request + + 1 + 1 + read-write + + + B_0x0 + No abort requested + 0x0 + + + B_0x1 + Abort requested + 0x1 + + + + + DMAEN + DMA enable + + 2 + 1 + read-write + + + B_0x0 + DMA disabled for indirect mode + 0x0 + + + B_0x1 + DMA enabled for indirect mode + 0x1 + + + + + TCEN + Timeout counter enable + + 3 + 1 + read-write + + + B_0x0 + The timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in memory-mapped mode. + 0x0 + + + B_0x1 + The timeout counter is enabled, and thus the chip-select is released in the memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity. + 0x1 + + + + + DMM + Dual-memory configuration + + 6 + 1 + read-write + + + B_0x0 + Dual-memory configuration disabled + 0x0 + + + B_0x1 + Dual-memory configuration enabled + 0x1 + + + + + MSEL + External memory select + + 7 + 1 + read-write + + + B_0x0 + External memory 1 selected (data exchanged over IO[3:0]) + 0x0 + + + B_0x1 + External memory 2 selected (data exchanged over IO[7:4]) + 0x1 + + + + + FTHRES + FIFO threshold level + + 8 + 5 + read-write + + + B_0x0 + FTF is set if there are one or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in indirect-read mode. + 0x0 + + + B_0x1 + FTF is set if there are two or more free bytes available to be written to in the FIFO inindirect-write mode, or if there are two or more valid bytes can be read from the FIFO inindirect-read mode. + 0x1 + + + B_0x1F + FTF is set if there are 32 free bytes available to be written to in the FIFO in indirect-write mode, or if there are 32 valid bytes can be read from the FIFO in indirect-read mode. + 0x1F + + + + + TEIE + Transfer error interrupt enable + + 16 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TCIE + Transfer complete interrupt enable + + 17 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + FTIE + FIFO threshold interrupt enable + + 18 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + SMIE + Status-match interrupt enable + + 19 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + TOIE + Timeout interrupt enable + + 20 + 1 + read-write + + + B_0x0 + Interrupt disabled + 0x0 + + + B_0x1 + Interrupt enabled + 0x1 + + + + + APMS + Automatic status-polling mode stop + + 22 + 1 + read-write + + + B_0x0 + Automatic status-polling mode is stopped only by abort or by disabling the OCTOSPI. + 0x0 + + + B_0x1 + Automatic status-polling mode stops as soon as there is a match. + 0x1 + + + + + PMM + Polling match mode + + 23 + 1 + read-write + + + B_0x0 + AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register. + 0x0 + + + B_0x1 + OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register. + 0x1 + + + + + FMODE + Functional mode + + 28 + 2 + read-write + + + B_0x0 + Indirect-write mode + 0x0 + + + B_0x1 + Indirect-read mode + 0x1 + + + B_0x2 + Automatic status-polling mode (relevant in regular-command protocol only) + 0x2 + + + B_0x3 + Memory-mapped mode + 0x3 + + + + + + + OCTOSPI_DCR1 + OCTOSPI_DCR1 + OCTOSPI device configuration register 1 + 0x0008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CKMODE + Clock mode 0/mode 3 + + 0 + 1 + read-write + + + B_0x0 + CLK must stay low while NCS is high (chip-select released). + 0x0 + + + B_0x1 + CLK must stay high while NCS is high (chip-select released). + 0x1 + + + + + FRCK + Free running clock + + 1 + 1 + read-write + + + B_0x0 + CLK is not free running. + 0x0 + + + B_0x1 + CLK is free running (always provided). + 0x1 + + + + + DLYBYP + Delay block bypass + 3 + 1 + read-write + + + B_0x0 + The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the dedicated section of the reference manual as it is not part of the OCTOSPI peripheral). + 0x0 + + + B_0x1 + The delay block is bypassed, so the internal sampling clock or the DQS data strobe external signal is not affected by the delay block. + 0x1 + + + + + CSHT + Chip-select high time + + 8 + 6 + read-write + + + B_0x0 + NCS stays high for at least 1 cycle between external device commands. + 0x0 + + + B_0x1 + NCS stays high for at least 2 cycles between external device commands. + 0x1 + + + B_0x3F + NCS stays high for at least 64 cycles between external device commands. + 0x3F + + + + + DEVSIZE + Device size + + 16 + 5 + read-write + + + MTYP + Memory type + + 24 + 3 + read-write + + + B_0x0 + Micron mode, D0/D1 ordering in DTR 8-data-bit mode. + 0x0 + + + B_0x1 + Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. + 0x1 + + + B_0x2 + Standard mode + 0x2 + + + B_0x3 + Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. + 0x3 + + + B_0x4 + HyperBus memory mode, the protocol follows the HyperBusless thansup> less than/sup>specification. + 0x4 + + + B_0x5 + HyperBus register mode, addressing register space. + 0x5 + + + + + + + OCTOSPI_DCR2 + OCTOSPI_DCR2 + OCTOSPI device configuration register 2 + 0x000C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler + + 0 + 8 + read-write + + + B_0x0 + Fless thansub>CLKless than/sub> = Fless thansub>KERNELless than/sub>, kernel clock used directly as OCTOSPI CLK (prescaler bypassed). + 0x0 + + + B_0x1 + Fless thansub>CLKless than/sub> = Fless thansub>KERNELless than/sub>/2 + 0x1 + + + + + WRAPSIZE + Wrap size + + 16 + 3 + read-write + + + B_0x0 + Wrapped reads are not supported by the memory. + 0x0 + + + B_0x2 + External memory supports wrap size of 16 bytes. + 0x2 + + + B_0x3 + External memory supports wrap size of 32 bytes. + 0x3 + + + B_0x4 + External memory supports wrap size of 64 bytes. + 0x4 + + + B_0x5 + External memory supports wrap size of 128 bytes. + 0x5 + + + + + + + OCTOSPI_DCR3 + OCTOSPI_DCR3 + OCTOSPI device configuration register 3 + 0x0010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSBOUND + NCS boundary + + 16 + 5 + read-write + + + B_0x0 + NCS boundary disabled + 0x0 + + + + + + + OCTOSPI_DCR4 + OCTOSPI_DCR4 + OCTOSPI device configuration register 4 + 0x0014 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REFRESH + Refresh rate + + 0 + 32 + read-write + + + B_0x0 + Refresh disabled + 0x0 + + + + + + + OCTOSPI_SR + OCTOSPI_SR + OCTOSPI status register + 0x0020 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TEF + Transfer error flag + + 0 + 1 + read-only + + + TCF + Transfer complete flag + + 1 + 1 + read-only + + + FTF + FIFO threshold flag + + 2 + 1 + read-only + + + SMF + Status match flag + + 3 + 1 + read-only + + + TOF + Timeout flag + + 4 + 1 + read-only + + + BUSY + Busy + + 5 + 1 + read-only + + + FLEVEL + FIFO level + + 8 + 6 + read-only + + + + + OCTOSPI_FCR + OCTOSPI_FCR + OCTOSPI flag clear register + 0x0024 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CTEF + Clear transfer error flag + + 0 + 1 + write-only + + + CTCF + Clear transfer complete flag + + 1 + 1 + write-only + + + CSMF + Clear status match flag + + 3 + 1 + write-only + + + CTOF + Clear timeout flag + + 4 + 1 + write-only + + + + + OCTOSPI_DLR + OCTOSPI_DLR + OCTOSPI data length register + 0x0040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DL + Data length + + 0 + 32 + read-write + + + + + OCTOSPI_AR + OCTOSPI_AR + OCTOSPI address register + 0x0048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADDRESS + Address + + 0 + 32 + read-write + + + + + OCTOSPI_DR + OCTOSPI_DR + OCTOSPI data register + 0x0050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DATA + Data + + 0 + 32 + read-write + + + + + OCTOSPI_PSMKR + OCTOSPI_PSMKR + OCTOSPI polling status mask register + 0x0080 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MASK + Status mask + + 0 + 32 + read-write + + + B_0x0 + Bit n of the data received in automatic status-polling mode is masked and its value is not considered in the matching logic. + 0x0 + + + B_0x1 + Bit n of the data received in automatic status-polling mode is unmasked and its value is considered in the matching logic. + 0x1 + + + + + + + OCTOSPI_PSMAR + OCTOSPI_PSMAR + OCTOSPI polling status match register + 0x0088 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MATCH + Status match + + 0 + 32 + read-write + + + + + OCTOSPI_PIR + OCTOSPI_PIR + OCTOSPI polling interval register + 0x0090 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + INTERVAL + Polling interval + + 0 + 16 + read-write + + + + + OCTOSPI_CCR + OCTOSPI_CCR + OCTOSPI communication configuration register + 0x0100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IMODE + Instruction mode + + 0 + 3 + read-write + + + B_0x0 + No instruction + 0x0 + + + B_0x1 + Instruction on a single line + 0x1 + + + B_0x2 + Instruction on two lines + 0x2 + + + B_0x3 + Instruction on four lines + 0x3 + + + B_0x4 + Instruction on eight lines + 0x4 + + + + + IDTR + Instruction double transfer rate + + 3 + 1 + read-write + + + B_0x0 + DTR mode disabled for the instruction phase + 0x0 + + + B_0x1 + DTR mode enabled for the instruction phase + 0x1 + + + + + ISIZE + Instruction size + + 4 + 2 + read-write + + + B_0x0 + 8-bit instruction + 0x0 + + + B_0x1 + 16-bit instruction + 0x1 + + + B_0x2 + 24-bit instruction + 0x2 + + + B_0x3 + 32-bit instruction + 0x3 + + + + + ADMODE + Address mode + + 8 + 3 + read-write + + + B_0x0 + No address + 0x0 + + + B_0x1 + Address on a single line + 0x1 + + + B_0x2 + Address on two lines + 0x2 + + + B_0x3 + Address on four lines + 0x3 + + + B_0x4 + Address on eight lines + 0x4 + + + + + ADDTR + Address double transfer rate + + 11 + 1 + read-write + + + B_0x0 + DTR mode disabled for the address phase + 0x0 + + + B_0x1 + DTR mode enabled for the address phase + 0x1 + + + + + ADSIZE + Address size + + 12 + 2 + read-write + + + B_0x0 + 8-bit address + 0x0 + + + B_0x1 + 16-bit address + 0x1 + + + B_0x2 + 24-bit address + 0x2 + + + B_0x3 + 32-bit address + 0x3 + + + + + ABMODE + Alternate-byte mode + + 16 + 3 + read-write + + + B_0x0 + No alternate bytes + 0x0 + + + B_0x1 + Alternate bytes on a single line + 0x1 + + + B_0x2 + Alternate bytes on two lines + 0x2 + + + B_0x3 + Alternate bytes on four lines + 0x3 + + + B_0x4 + Alternate bytes on eight lines + 0x4 + + + + + ABDTR + Alternate- byte double transfer rate + + 19 + 1 + read-write + + + B_0x0 + DTR mode disabled for the alternate-byte phase + 0x0 + + + B_0x1 + DTR mode enabled for the alternate-byte phase + 0x1 + + + + + ABSIZE + Alternate-byte size + + 20 + 2 + read-write + + + B_0x0 + 8-bit alternate bytes + 0x0 + + + B_0x1 + 16-bit alternate bytes + 0x1 + + + B_0x2 + 24-bit alternate bytes + 0x2 + + + B_0x3 + 32-bit alternate bytes + 0x3 + + + + + DMODE + Data mode + + 24 + 3 + read-write + + + B_0x0 + No data + 0x0 + + + B_0x1 + Data on a single line + 0x1 + + + B_0x2 + Data on two lines + 0x2 + + + B_0x3 + Data on four lines + 0x3 + + + B_0x4 + Data on eight lines + 0x4 + + + + + DDTR + Data double transfer rate + + 27 + 1 + read-write + + + B_0x0 + DTR mode disabled for data phase + 0x0 + + + B_0x1 + DTR mode enabled for data phase + 0x1 + + + + + DQSE + DQS enable + + 29 + 1 + read-write + + + B_0x0 + DQS disabled + 0x0 + + + B_0x1 + DQS enabled + 0x1 + + + + + + + OCTOSPI_TCR + OCTOSPI_TCR + OCTOSPI timing configuration register + 0x0108 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DCYC + Number of dummy cycles + + 0 + 5 + read-write + + + DHQC + Delay hold quarter cycle + 28 + 1 + read-write + + + B_0x0 + No delay hold + 0x0 + + + B_0x1 + 1/4 cycle hold + 0x1 + + + + + SSHIFT + Sample shift + + 30 + 1 + read-write + + + B_0x0 + No shift + 0x0 + + + B_0x1 + 1/2 cycle shift + 0x1 + + + + + + + OCTOSPI_IR + OCTOSPI_IR + OCTOSPI instruction register + 0x0110 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + INSTRUCTION + Instruction + + 0 + 32 + read-write + + + + + OCTOSPI_ABR + OCTOSPI_ABR + OCTOSPI alternate bytes register + 0x0120 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALTERNATE + Alternate bytes + + 0 + 32 + read-write + + + + + OCTOSPI_LPTR + OCTOSPI_LPTR + OCTOSPI low-power timeout register + 0x00130 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIMEOUT + Timeout period + + 0 + 16 + read-write + + + + + OCTOSPI_WPCCR + OCTOSPI_WPCCR + OCTOSPI wrap communication configuration register + 0x0140 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IMODE + Instruction mode + + 0 + 3 + read-write + + + B_0x0 + No instruction + 0x0 + + + B_0x1 + Instruction on a single line + 0x1 + + + B_0x2 + Instruction on two lines + 0x2 + + + B_0x3 + Instruction on four lines + 0x3 + + + B_0x4 + Instruction on eight lines + 0x4 + + + + + IDTR + Instruction double transfer rate + + 3 + 1 + read-write + + + B_0x0 + DTR mode disabled for the instruction phase + 0x0 + + + B_0x1 + DTR mode enabled for the instruction phase + 0x1 + + + + + ISIZE + Instruction size + + 4 + 2 + read-write + + + B_0x0 + 8-bit instruction + 0x0 + + + B_0x1 + 16-bit instruction + 0x1 + + + B_0x2 + 24-bit instruction + 0x2 + + + B_0x3 + 32-bit instruction + 0x3 + + + + + ADMODE + Address mode + + 8 + 3 + read-write + + + B_0x0 + No address + 0x0 + + + B_0x1 + Address on a single line + 0x1 + + + B_0x2 + Address on two lines + 0x2 + + + B_0x3 + Address on four lines + 0x3 + + + B_0x4 + Address on eight lines + 0x4 + + + + + ADDTR + Address double transfer rate + + 11 + 1 + read-write + + + B_0x0 + DTR mode disabled for address phase + 0x0 + + + B_0x1 + DTR mode enabled for address phase + 0x1 + + + + + ADSIZE + Address size + + 12 + 2 + read-write + + + B_0x0 + 8-bit address + 0x0 + + + B_0x1 + 16-bit address + 0x1 + + + B_0x2 + 24-bit address + 0x2 + + + B_0x3 + 32-bit address + 0x3 + + + + + ABMODE + Alternate-byte mode + + 16 + 3 + read-write + + + B_0x0 + no alternate bytes + 0x0 + + + B_0x1 + alternate bytes on a single line + 0x1 + + + B_0x2 + alternate bytes on two lines + 0x2 + + + B_0x3 + alternate bytes on four lines + 0x3 + + + B_0x4 + alternate bytes on eight lines + 0x4 + + + + + ABDTR + Alternate-byte double transfer rate + + 19 + 1 + read-write + + + B_0x0 + DTR mode disabled for the alternate-byte phase + 0x0 + + + B_0x1 + DTR mode enabled for the alternate-byte phase + 0x1 + + + + + ABSIZE + Alternate-byte size + + 20 + 2 + read-write + + + B_0x0 + 8-bit alternate bytes + 0x0 + + + B_0x1 + 16-bit alternate bytes + 0x1 + + + B_0x2 + 24-bit alternate bytes + 0x2 + + + B_0x3 + 32-bit alternate bytes + 0x3 + + + + + DMODE + Data mode + + 24 + 3 + read-write + + + B_0x0 + No data + 0x0 + + + B_0x1 + Data on a single line + 0x1 + + + B_0x2 + Data on two lines + 0x2 + + + B_0x3 + Data on four lines + 0x3 + + + B_0x4 + Data on eight lines + 0x4 + + + + + DDTR + Data double transfer rate + + 27 + 1 + read-write + + + B_0x0 + DTR mode disabled for the data phase + 0x0 + + + B_0x1 + DTR mode enabled for the data phase + 0x1 + + + + + DQSE + DQS enable + + 29 + 1 + read-write + + + B_0x0 + DQS disabled + 0x0 + + + B_0x1 + DQS enabled + 0x1 + + + + + + + OCTOSPI_WPTCR + OCTOSPI_WPTCR + OCTOSPI wrap timing configuration register + 0x0148 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DCYC + Number of dummy cycles + + 0 + 5 + read-write + + + DHQC + Delay hold quarter cycle + + 28 + 1 + read-write + + + B_0x0 + No quarter cycle delay + 0x0 + + + B_0x1 + 1/4 cycle delay inserted + 0x1 + + + + + SSHIFT + Sample shift + + 30 + 1 + read-write + + + B_0x0 + No shift + 0x0 + + + B_0x1 + 1/2 cycle shift + 0x1 + + + + + + + OCTOSPI_WPIR + OCTOSPI_WPIR + OCTOSPI wrap instruction register + 0x0150 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + INSTRUCTION + Instruction + + 0 + 32 + read-write + + + + + OCTOSPI_WPABR + OCTOSPI_WPABR + OCTOSPI wrap alternate bytes register + 0x0160 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALTERNATE + Alternate bytes + + 0 + 32 + read-write + + + + + OCTOSPI_WCCR + OCTOSPI_WCCR + OCTOSPI write communication configuration register + 0x0180 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IMODE + Instruction mode + + 0 + 3 + read-write + + + B_0x0 + No instruction + 0x0 + + + B_0x1 + Instruction on a single line + 0x1 + + + B_0x2 + Instruction on two lines + 0x2 + + + B_0x3 + Instruction on four lines + 0x3 + + + B_0x4 + Instruction on eight lines + 0x4 + + + + + IDTR + Instruction double transfer rate + + 3 + 1 + read-write + + + B_0x0 + DTR mode disabled for instruction phase + 0x0 + + + B_0x1 + DTR mode enabled for instruction phase + 0x1 + + + + + ISIZE + Instruction size + + 4 + 2 + read-write + + + B_0x0 + 8-bit instruction + 0x0 + + + B_0x1 + 16-bit instruction + 0x1 + + + B_0x2 + 24-bit instruction + 0x2 + + + B_0x3 + 32-bit instruction + 0x3 + + + + + ADMODE + Address mode + + 8 + 3 + read-write + + + B_0x0 + No address + 0x0 + + + B_0x1 + Address on a single line + 0x1 + + + B_0x2 + Address on two lines + 0x2 + + + B_0x3 + Address on four lines + 0x3 + + + B_0x4 + Address on eight lines + 0x4 + + + + + ADDTR + Address double transfer rate + + 11 + 1 + read-write + + + B_0x0 + DTR mode disabled for the address phase + 0x0 + + + B_0x1 + DTR mode enabled for the address phase + 0x1 + + + + + ADSIZE + Address size + + 12 + 2 + read-write + + + B_0x0 + 8-bit address + 0x0 + + + B_0x1 + 16-bit address + 0x1 + + + B_0x2 + 24-bit address + 0x2 + + + B_0x3 + 32-bit address + 0x3 + + + + + ABMODE + Alternate-byte mode + + 16 + 3 + read-write + + + B_0x0 + No alternate bytes + 0x0 + + + B_0x1 + Alternate bytes on a single line + 0x1 + + + B_0x2 + Alternate bytes on two lines + 0x2 + + + B_0x3 + Alternate bytes on four lines + 0x3 + + + B_0x4 + Alternate bytes on eight lines + 0x4 + + + + + ABDTR + Alternate bytes double transfer rate + + 19 + 1 + read-write + + + B_0x0 + DTR mode disabled for alternate-bytes phase + 0x0 + + + B_0x1 + DTR mode enabled for alternate-bytes phase + 0x1 + + + + + ABSIZE + Alternate-byte size + + 20 + 2 + read-write + + + B_0x0 + 8-bit alternate bytes + 0x0 + + + B_0x1 + 16-bit alternate bytes + 0x1 + + + B_0x2 + 24-bit alternate bytes + 0x2 + + + B_0x3 + 32-bit alternate bytes + 0x3 + + + + + DMODE + Data mode + + 24 + 3 + read-write + + + B_0x0 + No data + 0x0 + + + B_0x1 + Data on a single line + 0x1 + + + B_0x2 + Data on two lines + 0x2 + + + B_0x3 + Data on four lines + 0x3 + + + B_0x4 + Data on eight lines + 0x4 + + + + + DDTR + data double transfer rate + + 27 + 1 + read-write + + + B_0x0 + DTR mode disabled for the data phase + 0x0 + + + B_0x1 + DTR mode enabled for the data phase + 0x1 + + + + + DQSE + DQS enable + + 29 + 1 + read-write + + + B_0x0 + DQS disabled + 0x0 + + + B_0x1 + DQS enabled + 0x1 + + + + + + + OCTOSPI_WTCR + OCTOSPI_WTCR + OCTOSPI write timing configuration register + 0x0188 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DCYC + Number of dummy cycles + + 0 + 5 + read-write + + + + + OCTOSPI_WIR + OCTOSPI_WIR + OCTOSPI write instruction register + 0x0190 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + INSTRUCTION + Instruction + + 0 + 32 + read-write + + + + + OCTOSPI_WABR + OCTOSPI_WABR + OCTOSPI write alternate bytes register + 0x01A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALTERNATE + Alternate bytes + + 0 + 32 + read-write + + + + + OCTOSPI_HLCR + OCTOSPI_HLCR + OCTOSPI HyperBus latency configuration register + 0x0200 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LM + Latency mode + + 0 + 1 + read-write + + + B_0x0 + Variable initial latency + 0x0 + + + B_0x1 + Fixed latency + 0x1 + + + + + WZL + Write zero latency + + 1 + 1 + read-write + + + B_0x0 + Latency on write accesses + 0x0 + + + B_0x1 + No latency on write accesses + 0x1 + + + + + TACC + Access time + + 8 + 8 + read-write + + + TRWR + Read-write minimum recovery time + + 16 + 8 + read-write + + + + + + + OCTOSPI_S + 0X57001400 + + + OTFDEC + OTFDEC register bank + OTFDEC + 0x46005000 + + 0x0 + 0x400 + registers + + + OTFDEC1 + OTFDEC1 secure global interrupt + 115 + + + + OTFDEC_CR + OTFDEC_CR + OTFDEC control register + 0x0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ENC + Encryption mode bit + + 0 + 1 + read-write + + + B_0x0 + OTFDEC working in decryption mode + 0x0 + + + B_0x1 + OTFDEC working in encryption mode + 0x1 + + + + + + + OTFDEC_PRIVCFGR + OTFDEC_PRIVCFGR + OTFDEC privileged access control configuration register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRIV + Privileged access protection. + 0 + 1 + read-write + + + B_0x0 + No additional protection is added on OTFDEC register accesses. + 0x0 + + + B_0x1 + An additional protection is added when accessing all registers except OTFDEC_PRIVCFGR: + 0x1 + + + + + + + OTFDEC_R1CFGR + OTFDEC_R1CFGR + OTFDEC region 1 configuration register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_EN + region on-the-fly decryption enable + + 0 + 1 + read-write + + + B_0x0 + On-the-fly decryption is disabled for this region. + 0x0 + + + B_0x1 + On-the-fly decryption is enabled for this region. + 0x1 + + + + + CONFIGLOCK + region config lock + + 1 + 1 + read-write + + + B_0x0 + Writes to this region OTFDEC_RxCFGR, OTFDEC_RxSTARTADDR, OTFDEC_RxENDADDR and OTFDEC_RxNONCERy registers are allowed. + 0x0 + + + B_0x1 + Writes to this region OTFDEC_RxCFGR, OTFDEC_RxSTARTADDR, OTFDEC_RxENDADDR and OTFDEC_RxNONCERy registers are ignored until next OTFDEC reset. + 0x1 + + + + + KEYLOCK + region key lock + + 2 + 1 + read-write + + + B_0x0 + Writes to this region KEYRx registers are allowed. + 0x0 + + + B_0x1 + Writes to this region KEYRx registers are ignored until next OTFDEC reset. + 0x1 + + + + + MODE + operating mode + + 4 + 2 + read-write + + + B_0x2 + All read accesses are decrypted (instruction or data). + 0x2 + + + B_0x3 + Enhanced encryption mode is activated, and only instruction accesses are decrypted + 0x3 + + + + + KEYCRC + region key 8-bit CRC + + 8 + 8 + read-only + + + REG_VERSION + region firmware version + + 16 + 16 + read-write + + + + + OTFDEC_R1STARTADDR + OTFDEC_R1STARTADDR + OTFDEC region 1 start address register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_START_ADDR + Region AHB start address + + 0 + 32 + read-write + + + + + OTFDEC_R1ENDADDR + OTFDEC_R1ENDADDR + OTFDEC region 1 end address register + 0x28 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + REG_END_ADDR + Region AHB end address + + 0 + 32 + read-write + + + + + OTFDEC_R1NONCER0 + OTFDEC_R1NONCER0 + OTFDEC region 1 nonce register 0 + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_NONCE + Region nonce, bits [31:0] + + 0 + 32 + read-write + + + + + OTFDEC_R1NONCER1 + OTFDEC_R1NONCER1 + OTFDEC region 1 nonce register 1 + 0x30 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_NONCE + Region nonce, bits [63:32] + + 0 + 32 + read-write + + + + + OTFDEC_R1KEYR0 + OTFDEC_R1KEYR0 + OTFDEC region 1 key register 0 + 0x34 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [31:0] + + 0 + 32 + write-only + + + + + OTFDEC_R1KEYR1 + OTFDEC_R1KEYR1 + OTFDEC region 1 key register 1 + 0x38 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [63:32] + + 0 + 32 + write-only + + + + + OTFDEC_R1KEYR2 + OTFDEC_R1KEYR2 + OTFDEC region 1 key register 2 + 0x3C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [95:64] + + 0 + 32 + write-only + + + + + OTFDEC_R1KEYR3 + OTFDEC_R1KEYR3 + OTFDEC region 1 key register 3 + 0x40 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [127:96] + + 0 + 32 + write-only + + + + + OTFDEC_R2CFGR + OTFDEC_R2CFGR + OTFDEC region 2 configuration register + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_EN + region on-the-fly decryption enable + + 0 + 1 + read-write + + + B_0x0 + On-the-fly decryption is disabled for this region. + 0x0 + + + B_0x1 + On-the-fly decryption is enabled for this region. + 0x1 + + + + + CONFIGLOCK + region config lock + + 1 + 1 + read-write + + + B_0x0 + Writes to this region OTFDEC_RxCFGR, OTFDEC_RxSTARTADDR, OTFDEC_RxENDADDR and OTFDEC_RxNONCERy registers are allowed. + 0x0 + + + B_0x1 + Writes to this region OTFDEC_RxCFGR, OTFDEC_RxSTARTADDR, OTFDEC_RxENDADDR and OTFDEC_RxNONCERy registers are ignored until next OTFDEC reset. + 0x1 + + + + + KEYLOCK + region key lock + + 2 + 1 + read-write + + + B_0x0 + Writes to this region KEYRx registers are allowed. + 0x0 + + + B_0x1 + Writes to this region KEYRx registers are ignored until next OTFDEC reset. + 0x1 + + + + + MODE + operating mode + + 4 + 2 + read-write + + + B_0x2 + All read accesses are decrypted (instruction or data). + 0x2 + + + B_0x3 + Enhanced encryption mode is activated, and only instruction accesses are decrypted + 0x3 + + + + + KEYCRC + region key 8-bit CRC + + 8 + 8 + read-only + + + REG_VERSION + region firmware version + + 16 + 16 + read-write + + + + + OTFDEC_R2STARTADDR + OTFDEC_R2STARTADDR + OTFDEC region 2 start address register + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_START_ADDR + Region AHB start address + + 0 + 32 + read-write + + + + + OTFDEC_R2ENDADDR + OTFDEC_R2ENDADDR + OTFDEC region 2 end address register + 0x58 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + REG_END_ADDR + Region AHB end address + + 0 + 32 + read-write + + + + + OTFDEC_R2NONCER0 + OTFDEC_R2NONCER0 + OTFDEC region 2 nonce register 0 + 0x5C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_NONCE + Region nonce, bits [31:0] + + 0 + 32 + read-write + + + + + OTFDEC_R2NONCER1 + OTFDEC_R2NONCER1 + OTFDEC region 2 nonce register 1 + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_NONCE + Region nonce, bits [63:32] + + 0 + 32 + read-write + + + + + OTFDEC_R2KEYR0 + OTFDEC_R2KEYR0 + OTFDEC region 2 key register 0 + 0x64 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [31:0] + + 0 + 32 + write-only + + + + + OTFDEC_R2KEYR1 + OTFDEC_R2KEYR1 + OTFDEC region 2 key register 1 + 0x68 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [63:32] + + 0 + 32 + write-only + + + + + OTFDEC_R2KEYR2 + OTFDEC_R2KEYR2 + OTFDEC region 2 key register 2 + 0x6C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [95:64] + + 0 + 32 + write-only + + + + + OTFDEC_R2KEYR3 + OTFDEC_R2KEYR3 + OTFDEC region 2 key register 3 + 0x70 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [127:96] + + 0 + 32 + write-only + + + + + OTFDEC_R3CFGR + OTFDEC_R3CFGR + OTFDEC region 3 configuration register + 0x80 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_EN + region on-the-fly decryption enable + + 0 + 1 + read-write + + + B_0x0 + On-the-fly decryption is disabled for this region. + 0x0 + + + B_0x1 + On-the-fly decryption is enabled for this region. + 0x1 + + + + + CONFIGLOCK + region config lock + + 1 + 1 + read-write + + + B_0x0 + Writes to this region OTFDEC_RxCFGR, OTFDEC_RxSTARTADDR, OTFDEC_RxENDADDR and OTFDEC_RxNONCERy registers are allowed. + 0x0 + + + B_0x1 + Writes to this region OTFDEC_RxCFGR, OTFDEC_RxSTARTADDR, OTFDEC_RxENDADDR and OTFDEC_RxNONCERy registers are ignored until next OTFDEC reset. + 0x1 + + + + + KEYLOCK + region key lock + + 2 + 1 + read-write + + + B_0x0 + Writes to this region KEYRx registers are allowed. + 0x0 + + + B_0x1 + Writes to this region KEYRx registers are ignored until next OTFDEC reset. + 0x1 + + + + + MODE + operating mode + + 4 + 2 + read-write + + + B_0x2 + All read accesses are decrypted (instruction or data). + 0x2 + + + B_0x3 + Enhanced encryption mode is activated, and only instruction accesses are decrypted + 0x3 + + + + + KEYCRC + region key 8-bit CRC + + 8 + 8 + read-only + + + REG_VERSION + region firmware version + + 16 + 16 + read-write + + + + + OTFDEC_R3STARTADDR + OTFDEC_R3STARTADDR + OTFDEC region 3 start address register + 0x84 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_START_ADDR + Region AHB start address + + 0 + 32 + read-write + + + + + OTFDEC_R3ENDADDR + OTFDEC_R3ENDADDR + OTFDEC region 3 end address register + 0x88 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + REG_END_ADDR + Region AHB end address + + 0 + 32 + read-write + + + + + OTFDEC_R3NONCER0 + OTFDEC_R3NONCER0 + OTFDEC region 3 nonce register 0 + 0x8C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_NONCE + Region nonce, bits [31:0] + + 0 + 32 + read-write + + + + + OTFDEC_R3NONCER1 + OTFDEC_R3NONCER1 + OTFDEC region 3 nonce register 1 + 0x90 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_NONCE + Region nonce, bits [63:32] + + 0 + 32 + read-write + + + + + OTFDEC_R3KEYR0 + OTFDEC_R3KEYR0 + OTFDEC region 3 key register 0 + 0x94 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [31:0] + + 0 + 32 + write-only + + + + + OTFDEC_R3KEYR1 + OTFDEC_R3KEYR1 + OTFDEC region 3 key register 1 + 0x98 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [63:32] + + 0 + 32 + write-only + + + + + OTFDEC_R3KEYR2 + OTFDEC_R3KEYR2 + OTFDEC region 3 key register 2 + 0x9C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [95:64] + + 0 + 32 + write-only + + + + + OTFDEC_R3KEYR3 + OTFDEC_R3KEYR3 + OTFDEC region 3 key register 3 + 0xA0 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [127:96] + + 0 + 32 + write-only + + + + + OTFDEC_R4CFGR + OTFDEC_R4CFGR + OTFDEC region 4 configuration register + 0xB0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_EN + region on-the-fly decryption enable + + 0 + 1 + read-write + + + B_0x0 + On-the-fly decryption is disabled for this region. + 0x0 + + + B_0x1 + On-the-fly decryption is enabled for this region. + 0x1 + + + + + CONFIGLOCK + region config lock + + 1 + 1 + read-write + + + B_0x0 + Writes to this region OTFDEC_RxCFGR, OTFDEC_RxSTARTADDR, OTFDEC_RxENDADDR and OTFDEC_RxNONCERy registers are allowed. + 0x0 + + + B_0x1 + Writes to this region OTFDEC_RxCFGR, OTFDEC_RxSTARTADDR, OTFDEC_RxENDADDR and OTFDEC_RxNONCERy registers are ignored until next OTFDEC reset. + 0x1 + + + + + KEYLOCK + region key lock + + 2 + 1 + read-write + + + B_0x0 + Writes to this region KEYRx registers are allowed. + 0x0 + + + B_0x1 + Writes to this region KEYRx registers are ignored until next OTFDEC reset. + 0x1 + + + + + MODE + operating mode + + 4 + 2 + read-write + + + B_0x2 + All read accesses are decrypted (instruction or data). + 0x2 + + + B_0x3 + Enhanced encryption mode is activated, and only instruction accesses are decrypted + 0x3 + + + + + KEYCRC + region key 8-bit CRC + + 8 + 8 + read-only + + + REG_VERSION + region firmware version + + 16 + 16 + read-write + + + + + OTFDEC_R4STARTADDR + OTFDEC_R4STARTADDR + OTFDEC region 4 start address register + 0xB4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_START_ADDR + Region AHB start address + + 0 + 32 + read-write + + + + + OTFDEC_R4ENDADDR + OTFDEC_R4ENDADDR + OTFDEC region 4 end address register + 0xB8 + 0x20 + read-write + 0x00000FFF + 0xFFFFFFFF + + + REG_END_ADDR + Region AHB end address + + 0 + 32 + read-write + + + + + OTFDEC_R4NONCER0 + OTFDEC_R4NONCER0 + OTFDEC region 4 nonce register 0 + 0xBC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_NONCE + Region nonce, bits [31:0] + + 0 + 32 + read-write + + + + + OTFDEC_R4NONCER1 + OTFDEC_R4NONCER1 + OTFDEC region 4 nonce register 1 + 0xC0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + REG_NONCE + Region nonce, bits [63:32] + + 0 + 32 + read-write + + + + + OTFDEC_R4KEYR0 + OTFDEC_R4KEYR0 + OTFDEC region 4 key register 0 + 0xC4 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [31:0] + + 0 + 32 + write-only + + + + + OTFDEC_R4KEYR1 + OTFDEC_R4KEYR1 + OTFDEC region 4 key register 1 + 0xC8 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [63:32] + + 0 + 32 + write-only + + + + + OTFDEC_R4KEYR2 + OTFDEC_R4KEYR2 + OTFDEC region 4 key register 2 + 0xCC + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [95:64] + + 0 + 32 + write-only + + + + + OTFDEC_R4KEYR3 + OTFDEC_R4KEYR3 + OTFDEC region 4 key register 3 + 0xD0 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + REG_KEY + Region key, bits [127:96] + + 0 + 32 + write-only + + + + + OTFDEC_ISR + OTFDEC_ISR + OTFDEC interrupt status register + 0x300 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SEIF + Security error interrupt flag status + + 0 + 1 + read-only + + + B_0x0 + No security error status. + 0x0 + + + B_0x1 + Security error flag status, with interrupt pending. + 0x1 + + + + + XONEIF + Execute-only execute-never error interrupt flag status + + 1 + 1 + read-only + + + B_0x0 + No execute-only error status. + 0x0 + + + B_0x1 + Read access detected on one region with MODE bits set to 11 or execute access detected while ENC = 1. + 0x1 + + + + + KEIF + Key error interrupt flag status + + 2 + 1 + read-only + + + B_0x0 + OTFDEC operates properly. + 0x0 + + + B_0x1 + Read access detected on an enabled encrypted region with its key registers null or not properly initialized (KEYCRC = 0x0). + 0x1 + + + + + + + OTFDEC_ICR + OTFDEC_ICR + OTFDEC interrupt clear register + 0x304 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SEIF + Security error interrupt flag clear + + 0 + 1 + write-only + + + B_0x0 + SEIF flag status is not affected. + 0x0 + + + B_0x1 + SEIF flag status is cleared in OTFDEC_ISR. + 0x1 + + + + + XONEIF + Execute-only execute-never error interrupt flag clear + + 1 + 1 + write-only + + + B_0x0 + XONEIF flag status is not affected. + 0x0 + + + B_0x1 + XONEIF flag status is cleared in OTFDEC_ISR. + 0x1 + + + + + KEIF + Key error interrupt flag clear + + 2 + 1 + write-only + + + B_0x0 + KEIF flag status is not affected. + 0x0 + + + B_0x1 + KEIF flag status is cleared in OTFDEC_ISR. + 0x1 + + + + + + + OTFDEC_IER + OTFDEC_IER + OTFDEC interrupt enable register + 0x308 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEIE + Security error interrupt enable + + 0 + 1 + read-write + + + B_0x0 + Interrupt generation on security error SEIF is disabled (masked). + 0x0 + + + B_0x1 + Interrupt generation on security error SEIF is enabled (not masked). + 0x1 + + + + + XONEIE + Execute-only execute-never error interrupt enable + + 1 + 1 + read-write + + + B_0x0 + Interrupt generation on execute-only error XONEIF is disabled (masked). + 0x0 + + + B_0x1 + Interrupt generation on execute-only error XONEIF is enabled (not masked). + 0x1 + + + + + KEIE + Key error interrupt enable + + 2 + 1 + read-write + + + B_0x0 + Interrupt generation on key error flag KEIF is disabled (masked). + 0x0 + + + B_0x1 + Interrupt generation on key error flag KEIF is enabled (not masked). + 0x1 + + + + + + + + + OTFDEC_S + 0X56005000 + + + PKA + PKA register blank and RAM + PKA + 0x420c2000 + + 0x0 + 0x2000 + registers + + + PKA + PKA global interrupt + 118 + + + + PKA_CR + PKA_CR + PKA control register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + PKA enable + + 0 + 1 + read-write + + + B_0x0 + Disable PKA + 0x0 + + + B_0x1 + Enable PKA. + 0x1 + + + + + START + start the operation + + 1 + 1 + read-write + + + MODE + PKA operation code + + 8 + 6 + read-write + + + B_0x0 + Montgomery parameter computation then modular exponentiation + 0x0 + + + B_0x1 + Montgomery parameter computation only + 0x1 + + + B_0x2 + Modular exponentiation only (Montgomery parameter must be loaded first) + 0x2 + + + B_0x3 + Modular exponentiation (protected, used when manipulating secrets) + 0x3 + + + B_0x20 + Montgomery parameter computation then ECC scalar multiplication (protected) + 0x20 + + + B_0x24 + ECDSA sign (protected) + 0x24 + + + B_0x26 + ECDSA verification + 0x26 + + + B_0x28 + Point on elliptic curve Fp check + 0x28 + + + B_0x7 + RSA CRT exponentiation + 0x7 + + + B_0x8 + Modular inversion + 0x8 + + + B_0x9 + Arithmetic addition + 0x9 + + + B_0xA + Arithmetic subtraction + 0xA + + + B_0xB + Arithmetic multiplication + 0xB + + + B_0xC + Arithmetic comparison + 0xC + + + B_0xD + Modular reduction + 0xD + + + B_0xE + Modular addition + 0xE + + + B_0xF + Modular subtraction + 0xF + + + B_0x10 + Montgomery multiplication + 0x10 + + + B_0x23 + ECC complete addition + 0x23 + + + B_0x27 + ECC double base ladder + 0x27 + + + B_0x2F + ECC projective to affine + 0x2F + + + + + PROCENDIE + End of operation interrupt enable + 17 + 1 + read-write + + + B_0x0 + No interrupt is generated when PROCENDF flag is set in PKA_SR. + 0x0 + + + B_0x1 + An interrupt is generated when PROCENDF flag is set in PKA_SR. + 0x1 + + + + + RAMERRIE + RAM error interrupt enable + 19 + 1 + read-write + + + B_0x0 + No interrupt is generated when RAMERRF flag is set in PKA_SR. + 0x0 + + + B_0x1 + An interrupt is generated when RAMERRF flag is set in PKA_SR. + 0x1 + + + + + ADDRERRIE + Address error interrupt enable + 20 + 1 + read-write + + + B_0x0 + No interrupt is generated when ADDRERRF flag is set in PKA_SR. + 0x0 + + + B_0x1 + An interrupt is generated when ADDRERRF flag is set in PKA_SR. + 0x1 + + + + + OPERRIE + Operation error interrupt enable + 21 + 1 + read-write + + + B_0x0 + No interrupt is generated when OPERRF flag is set in PKA_SR. + 0x0 + + + B_0x1 + An interrupt is generated when OPERRF flag is set in PKA_SR. + 0x1 + + + + + + + PKA_SR + PKA_SR + PKA status register + 0x04 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + INITOK + PKA initialization OK + + 0 + 1 + read-only + + + B_0x0 + PKA is not initialized correctly. + 0x0 + + + B_0x1 + PKA is initialized correctly and can be used normally. + 0x1 + + + + + LMF + Limited mode flag + + 1 + 1 + read-only + + + B_0x0 + All values documented in MODE bitfield can be used. + 0x0 + + + B_0x1 + Only ECDSA verification (MODE = 0x26) is supported by the PKA. + 0x1 + + + + + BUSY + Busy flag + + 16 + 1 + read-only + + + B_0x0 + No operation is in progress (default) + 0x0 + + + B_0x1 + An operation is in progress + 0x1 + + + + + PROCENDF + PKA end of operation flag + 17 + 1 + read-only + + + B_0x0 + Operation in progress + 0x0 + + + B_0x1 + PKA operation is completed. + 0x1 + + + + + RAMERRF + PKA RAM error flag + + 19 + 1 + read-only + + + B_0x0 + No PKA RAM access error + 0x0 + + + B_0x1 + An AHB access to the PKA RAM occurred while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress). + 0x1 + + + + + ADDRERRF + Address error flag + + 20 + 1 + read-only + + + B_0x0 + No address error + 0x0 + + + B_0x1 + Address access is out of range (unmapped address) + 0x1 + + + + + OPERRF + Operation error flag + + 21 + 1 + read-only + + + B_0x0 + No event error + 0x0 + + + B_0x1 + An illegal or unknown operation has been selected in PKA_CR register + 0x1 + + + + + + + PKA_CLRFR + PKA_CLRFR + PKA clear flag register + 0x08 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + PROCENDFC + Clear PKA end of operation flag + 17 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Clear the PROCENDF flag in PKA_SR + 0x1 + + + + + RAMERRFC + Clear PKA RAM error flag + 19 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Clear the RAMERRF flag in PKA_SR + 0x1 + + + + + ADDRERRFC + Clear address error flag + 20 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Clear the ADDRERRF flag in PKA_SR + 0x1 + + + + + OPERRFC + Clear operation error flag + 21 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Clear the OPERRF flag in PKA_SR + 0x1 + + + + + + + + + PKA_S + 0X520C2000 + + + PSSI + PSSI register block + PSSI + 0x4202c400 + + 0x0 + 0x400 + registers + + + + PSSI_CR + PSSI_CR + PSSI control register + 0x00 + 0x20 + read-write + 0x40000000 + 0xFFFFFFFF + + + CKPOL + Parallel data clock polarity + + 5 + 1 + read-write + + + B_0x0 + Falling edge active for inputs or rising edge active for outputs + 0x0 + + + B_0x1 + Rising edge active for inputs or falling edge active for outputs. + 0x1 + + + + + DEPOL + Data enable (PSSI_DE) polarity + + 6 + 1 + read-write + + + B_0x0 + PSSI_DE active low (0 indicates that data is valid) + 0x0 + + + B_0x1 + PSSI_DE active high (1 indicates that data is valid) + 0x1 + + + + + RDYPOL + Ready (PSSI_RDY) polarity + + 8 + 1 + read-write + + + B_0x0 + PSSI_RDY active low (0 indicates that the receiver is ready to receive) + 0x0 + + + B_0x1 + PSSI_RDY active high (1 indicates that the receiver is ready to receive) + 0x1 + + + + + EDM + Extended data mode + 10 + 2 + read-write + + + B_0x0 + Interface captures 8-bit data on every parallel data clock + 0x0 + + + B_0x3 + The interface captures 16-bit data on every parallel data clock + 0x3 + + + + + ENABLE + PSSI enable + + 14 + 1 + read-write + + + B_0x0 + PSSI disabled + 0x0 + + + B_0x1 + PSSI enabled + 0x1 + + + + + DERDYCFG + Data enable and ready configuration + + 18 + 3 + read-write + + + B_0x0 + PSSI_DE and PSSI_RDY both disabled + 0x0 + + + B_0x1 + Only PSSI_RDY enabled + 0x1 + + + B_0x2 + Only PSSI_DE enabled + 0x2 + + + B_0x3 + Both PSSI_RDY and PSSI_DE alternate functions enabled + 0x3 + + + B_0x4 + Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin (see Bidirectional PSSI_DE/PSSI_RDY signal on page 1245) + 0x4 + + + B_0x5 + Only PSSI_RDY function enabled, but mapped to PSSI_DE pin + 0x5 + + + B_0x6 + Only PSSI_DE function enabled, but mapped to PSSI_RDY pin + 0x6 + + + B_0x7 + Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin (see Bidirectional PSSI_DE/PSSI_RDY signal on page 1245) + 0x7 + + + + + DMAEN + DMA enable bit + 30 + 1 + read-write + + + B_0x0 + DMA transfers are disabled. + 0x0 + + + B_0x1 + DMA transfers are enabled (default configuration). + 0x1 + + + + + OUTEN + Data direction selection bit + 31 + 1 + read-write + + + B_0x0 + Receive mode: data is input synchronously with PSSI_PDCK + 0x0 + + + B_0x1 + Transmit mode: data is output synchronously with PSSI_PDCK + 0x1 + + + + + + + PSSI_SR + PSSI_SR + PSSI status register + 0x04 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RTT4B + FIFO is ready to transfer four bytes + 2 + 1 + read-only + + + B_0x1 + FIFO is ready for a four-byte (32-bit) transfer. + 0x1 + + + B_0x0 + FIFO is not ready for a four-byte transfer + 0x0 + + + + + RTT1B + FIFO is ready to transfer one byte + 3 + 1 + read-only + + + B_0x1 + FIFO is ready for a one byte (32-bit) transfer. + 0x1 + + + B_0x0 + FIFO is not ready for a 1-byte transfer + 0x0 + + + + + + + PSSI_RIS + PSSI_RIS + PSSI raw interrupt status register + 0x08 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + OVR_RIS + Data buffer overrun/underrun raw interrupt status + + 1 + 1 + read-only + + + B_0x0 + No overrun/underrun occurred + 0x0 + + + B_0x1 + An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode. + 0x1 + + + + + + + PSSI_IER + PSSI_IER + PSSI interrupt enable register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OVR_IE + Data buffer overrun/underrun interrupt enable + 1 + 1 + read-write + + + B_0x0 + No interrupt generation + 0x0 + + + B_0x1 + An interrupt is generated if either an overrun or an underrun error occurred. + 0x1 + + + + + + + PSSI_MIS + PSSI_MIS + PSSI masked interrupt status register + 0x10 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + OVR_MIS + Data buffer overrun/underrun masked interrupt status + + 1 + 1 + read-only + + + B_0x0 + No interrupt is generated when an overrun/underrun error occurs + 0x0 + + + B_0x1 + An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER. + 0x1 + + + + + + + PSSI_ICR + PSSI_ICR + PSSI interrupt clear register + 0x14 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + OVR_ISC + Data buffer overrun/underrun interrupt status clear + + 1 + 1 + write-only + + + + + PSSI_DR + PSSI_DR + PSSI data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BYTE0 + Data byte 0 + 0 + 8 + read-write + + + BYTE1 + Data byte 1 + 8 + 8 + read-write + + + BYTE2 + Data byte 2 + 16 + 8 + read-write + + + BYTE3 + Data byte 3 + 24 + 8 + read-write + + + + + + + PSSI_S + 0X5202C400 + + + PWR + PWR address block description + PWR + 0x44020800 + + 0x0 + 0x108 + registers + + + + PWR_PMCR + PWR_PMCR + PWR power mode control register + 0x000 + 0x20 + read-write + 0x0000000C + 0xFFFFFFFF + + + LPMS + low-power mode selection + + 0 + 1 + read-write + + + B_0x0 + keeps Stop mode when entering DeepSleep. + 0x0 + + + B_0x1 + allows Standby mode when entering DeepSleep. + 0x1 + + + + + SVOS + system Stop mode voltage scaling selection + + 2 + 2 + read-write + + + B_0x1 + SVOS5 scale 5 + 0x1 + + + B_0x2 + SVOS4 scale 4 + 0x2 + + + B_0x3 + SVOS3 scale 3 (default) + 0x3 + + + + + CSSF + clear Standby and Stop flags (always read as 0) + + 7 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + STOPF and SBF flags cleared + 0x1 + + + + + FLPS + flash memory low-power mode in Stop mode + + 9 + 1 + read-write + + + B_0x0 + flash memory remains in normal mode when the system enters Stop mode (quick restart time). + 0x0 + + + B_0x1 + flash memory enters low-power mode when the system enters Stop mode(low-power consumption). + 0x1 + + + + + BOOSTE + analog switch Vless thansub>BOOSTless than/sub> control + + 12 + 1 + read-write + + + B_0x0 + booster disabled (default) + 0x0 + + + B_0x1 + booster enabled if analog voltage ready (AVD_READY = 1) + 0x1 + + + + + AVD_READY + analog voltage ready + + 13 + 1 + read-write + + + B_0x0 + peripheral analog voltage Vless thansub>DDAless than/sub> not ready (default) + 0x0 + + + B_0x1 + peripheral analog voltage Vless thansub>DDAless than/sub> ready. + 0x1 + + + + + ETHERNETSO + ETHERNET RAM shut-off in Stop mode. + 16 + 1 + read-write + + + B_0x0 + ETHERNET RAM content is kept in Stop mode. + 0x0 + + + B_0x1 + ETHERNET RAM content is lost in Stop mode. + 0x1 + + + + + SRAM3SO + AHB SRAM3 shut-off in Stop mode. + 23 + 1 + read-write + + + B_0x0 + AHB RAM3 content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM3 content is lost in Stop mode. + 0x1 + + + + + SRAM2_16SO + AHB SRAM2 16-Kbyte shut-off in Stop mode. + 24 + 1 + read-write + + + B_0x0 + AHB RAM2 16-Kbyte content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM2 16-Kbyte content is lost in Stop mode. + 0x1 + + + + + SRAM2_48SO + AHB SRAM2 48-Kbyte shut-off in Stop mode. + 25 + 1 + read-write + + + B_0x0 + AHB RAM2 48-Kbyte content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM2 48-Kbyte content is lost in Stop mode. + 0x1 + + + + + SRAM1SO + AHB SRAM1 shut-off in Stop mode + 26 + 1 + read-write + + + B_0x0 + AHB RA. + 0x0 + + + B_0x1 + AHB RAM1 content is lost in Stop mode. + 0x1 + + + + + + + PWR_PMCR_ALTERNATE1 + PWR_PMCR_ALTERNATE1 + PWR power mode control register + PWR_PMCR + 0x000 + 0x20 + read-write + 0x0000000C + 0xFFFFFFFF + + + LPMS + low-power mode selection + + 0 + 1 + read-write + + + B_0x0 + keeps Stop mode when entering DeepSleep. + 0x0 + + + B_0x1 + allows Standby mode when entering DeepSleep. + 0x1 + + + + + SVOS + system Stop mode voltage scaling selection + + 2 + 2 + read-write + + + B_0x1 + SVOS5 scale 5 + 0x1 + + + B_0x2 + SVOS4 scale 4 + 0x2 + + + B_0x3 + SVOS3 scale 3 (default) + 0x3 + + + + + CSSF + clear Standby and Stop flags (always read as 0) + + 7 + 1 + read-write + + + B_0x0 + no effect + 0x0 + + + B_0x1 + STOPF and SBF flags cleared + 0x1 + + + + + FLPS + flash memory low-power mode in Stop mode + + 9 + 1 + read-write + + + B_0x0 + flash memory remains in normal mode when the system enters Stop mode (quick restart time). + 0x0 + + + B_0x1 + flash memory enters low-power mode when the system enters Stop mode(low-power consumption). + 0x1 + + + + + BOOSTE + analog switch Vless thansub>BOOSTless than/sub> control + + 12 + 1 + read-write + + + B_0x0 + booster disabled (default) + 0x0 + + + B_0x1 + booster enabled if analog voltage ready (AVD_READY = 1) + 0x1 + + + + + AVD_READY + analog voltage ready + + 13 + 1 + read-write + + + B_0x0 + peripheral analog voltage Vless thansub>DDAless than/sub> not ready (default) + 0x0 + + + B_0x1 + peripheral analog voltage Vless thansub>DDAless than/sub> ready. + 0x1 + + + + + SRAM3SO + AHB SRAM3 shut-off in Stop mode. + 23 + 1 + read-write + + + B_0x0 + AHB RAM3 content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM3 content is lost in Stop mode. + 0x1 + + + + + SRAM2_16LSO + AHB SRAM2 low 16-Kbyte shut-off in Stop mode. + 24 + 1 + read-write + + + B_0x0 + AHB RAM2 low 16-Kbyte content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM2 low 16-Kbyte content is lost in Stop mode. + 0x1 + + + + + SRAM2_16HSO + AHB SRAM2 high 16-Kbyte shut-off in Stop mode. + 25 + 1 + read-write + + + B_0x0 + AHB RAM2 high 16-Kbyte content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM2 ]high16-Kbyte content is lost in Stop mode. + 0x1 + + + + + SRAM2_48SO + AHB SRAM2 48-Kbyte shut-off in Stop mode. + 26 + 1 + read-write + + + B_0x0 + AHB RAM2 48-Kbyte content is kept in Stop mode. + 0x0 + + + B_0x1 + AHB RAM2 48-Kbyte content is lost in Stop mode. + 0x1 + + + + + SRAM1SO + AHB SRAM1 shut-off in Stop mode + 27 + 1 + read-write + + + B_0x0 + AHB RA. + 0x0 + + + B_0x1 + AHB RAM1 content is lost in Stop mode. + 0x1 + + + + + + + PWR_PMSR + PWR_PMSR + PWR status register + 0x004 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + STOPF + Stop flag + + 5 + 1 + read-only + + + B_0x0 + system has not been in Stop mode. + 0x0 + + + B_0x1 + system has been in Stop mode. + 0x1 + + + + + SBF + System standby flag + + 6 + 1 + read-only + + + B_0x0 + system has not been in Standby mode. + 0x0 + + + B_0x1 + system has been in Standby mode. + 0x1 + + + + + + + PWR_VOSCR + PWR_VOSCR + PWR voltage scaling control register + 0x0010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + VOS + voltage scaling selection according to performance + + 4 + 2 + read-write + + + B_0x0 + scale 3 (default) + 0x0 + + + B_0x1 + scale 2 + 0x1 + + + B_0x2 + scale 1 + 0x2 + + + B_0x3 + scale 0 + 0x3 + + + + + + + PWR_VOSSR + PWR_VOSSR + PWR voltage scaling status register + 0x0014 + 0x20 + read-only + 0x00002008 + 0xFFFFFFFF + + + VOSRDY + Ready bit for Vless thansub>COREless than/sub> voltage scaling output selection. + 3 + 1 + read-only + + + B_0x0 + Not ready, voltage level below VOS selected level + 0x0 + + + B_0x1 + Ready, voltage level at or above VOS selected level + 0x1 + + + + + ACTVOSRDY + Voltage level ready for currently used VOS + 13 + 1 + read-only + + + B_0x0 + Vless thansub>COREless than/sub> is above or below the current voltage scaling provided by ACTVOS[1:0] + 0x0 + + + B_0x1 + Vless thansub>COREless than/sub> is equal to the current voltage scaling provided by ACTVOS[1:0] + 0x1 + + + + + ACTVOS + voltage output scaling currently applied to Vless thansub>COREless than/sub> + + 14 + 2 + read-only + + + B_0x0 + VOS3 (lowest power) + 0x0 + + + B_0x1 + VOS2 + 0x1 + + + B_0x2 + VOS1 + 0x2 + + + B_0x3 + VOS0 (highest frequency) + 0x3 + + + + + + + PWR_BDCR + PWR_BDCR + PWR Backup domain control register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BREN + Backup RAM retention in Standby and Vless thansub>BATless than/sub> modes + + 0 + 1 + read-write + + + B_0x0 + Backup RAM content lost in Standby and Vless thansub>BATless than/sub> modes. + 0x0 + + + B_0x1 + Backup RAM content preserved in Standby and Vless thansub>BATless than/sub> modes + 0x1 + + + + + MONEN + Backup domain voltage and temperature monitoring enable + 1 + 1 + read-write + + + B_0x0 + Backup domain voltage and temperature monitoring disabled + 0x0 + + + B_0x1 + Backup domain voltage and temperature monitoring enabled + 0x1 + + + + + VBE + Vless thansub>BATless than/sub> charging enable + + 8 + 1 + read-write + + + B_0x0 + Vless thansub>BATless than/sub> battery charging disabled. + 0x0 + + + B_0x1 + Vless thansub>BATless than/sub> battery charging enabled. + 0x1 + + + + + VBRS + Vless thansub>BATless than/sub> charging resistor selection + 9 + 1 + read-write + + + B_0x0 + Charge Vless thansub>BATless than/sub> through a 5 kohm resistor. + 0x0 + + + B_0x1 + Charge Vless thansub>BATless than/sub> through a 1. + 0x1 + + + + + + + PWR_DBPCR + PWR_DBPCR + PWR Backup domain control register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBP + Disable Backup domain write protection + + 0 + 1 + read-write + + + B_0x0 + Write access to Backup domain disabled + 0x0 + + + B_0x1 + Write access to Backup domain enabled + 0x1 + + + + + + + PWR_BDSR + PWR_BDSR + PWR Backup domain status register + 0x028 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + BRRDY + backup regulator ready + + 16 + 1 + read-only + + + B_0x0 + backup regulator not ready + 0x0 + + + B_0x1 + backup regulator ready + 0x1 + + + + + VBATL + Vless thansub>BATless than/sub> level monitoring versus low threshold + 20 + 1 + read-only + + + B_0x0 + Vless thansub>BATless than/sub> level above low threshold level + 0x0 + + + B_0x1 + Vless thansub>BATless than/sub> level equal or below low threshold level + 0x1 + + + + + VBATH + Vless thansub>BATless than/sub> level monitoring versus high threshold + 21 + 1 + read-only + + + B_0x0 + Vless thansub>BATless than/sub> level below high threshold level + 0x0 + + + B_0x1 + Vless thansub>BATless than/sub> level equal or above high threshold level + 0x1 + + + + + TEMPL + temperature level monitoring versus low threshold + 22 + 1 + read-only + + + B_0x0 + temperature above low threshold level + 0x0 + + + B_0x1 + temperature equal or below low threshold level + 0x1 + + + + + TEMPH + temperature level monitoring versus high threshold + 23 + 1 + read-only + + + B_0x0 + temperature below high threshold level + 0x0 + + + B_0x1 + temperature equal or above high threshold level + 0x1 + + + + + + + PWR_UCPDR + PWR_UCPDR + PWR USB Type-C power delivery register + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UCPD_DBDIS + USB Type-C and power delivery dead battery disable + + 0 + 1 + read-write + + + B_0x0 + Enable USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2 pins. + 0x0 + + + B_0x1 + Disable USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2 pins. + 0x1 + + + + + UCPD_STBY + USB Type-c and Power delivery Standby mode + + 1 + 1 + read-write + + + + + PWR_SCCR + PWR_SCCR + PWR supply configuration control register + 0x030 + 0x20 + read-writeOnce + 0x00000100 + 0xFFFFFFFF + + + BYPASS + power management unit bypass + 0 + 1 + read-writeOnce + + + B_0x0 + Power management unit normal operation. + 0x0 + + + B_0x1 + Power management unit bypassed. + 0x1 + + + + + LDOEN + LDO enable + + 8 + 1 + read-only + + + SMPSEN + SMPS enable + + 9 + 1 + read-only + + + + + PWR_VMCR + PWR_VMCR + PWR voltage monitor control register + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PVDE + PVD enable + 0 + 1 + read-write + + + B_0x0 + PVD disabled + 0x0 + + + B_0x1 + PVD enabled + 0x1 + + + + + PLS + programmable voltage detector (PVD) level selection + + 1 + 3 + read-write + + + B_0x0 + PVD level0 (VPVD0 ~ 1. + 0x0 + + + B_0x1 + PVD level1 (VPVD1 ~ 2. + 0x1 + + + B_0x2 + PVD level2 (VPVD2 ~ 2. + 0x2 + + + B_0x3 + PVD level3 (VPVD3 ~ 2. + 0x3 + + + B_0x4 + PVD level4 (VPVD4 ~ 2. + 0x4 + + + B_0x5 + PVD level5 (VPVD5 ~ 2. + 0x5 + + + B_0x6 + PVD level6 (VPVD6 ~ 2. + 0x6 + + + B_0x7 + PVD_IN pin + 0x7 + + + + + AVDEN + peripheral voltage monitor on Vless thansub>DDAless than/sub> enable + 8 + 1 + read-write + + + B_0x0 + peripheral voltage monitor on Vless thansub>DDAless than/sub> disabled + 0x0 + + + B_0x1 + peripheral voltage monitor on Vless thansub>DDAless than/sub> enabled + 0x1 + + + + + ALS + analog voltage detector (AVD) level selection + + 9 + 2 + read-write + + + B_0x0 + AVD level0 (Vless thansub>AVD0less than/sub> ~ 1. + 0x0 + + + B_0x1 + AVD level1 (Vless thansub>AVD1less than/sub> ~ 2. + 0x1 + + + B_0x2 + AVD level2 (Vless thansub>AVD2less than/sub> ~ 2. + 0x2 + + + B_0x3 + AVD level3 (Vless thansub>AVD3less than/sub> ~ 2. + 0x3 + + + + + + + PWR_USBSCR + PWR_USBSCR + PWR USB supply control register + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + USB33DEN + Vless thansub>DDUSBless than/sub> voltage level detector enable + 24 + 1 + read-write + + + B_0x0 + Vless thansub>DDUSBless than/sub> voltage level detector disabled + 0x0 + + + B_0x1 + Vless thansub>DDUSBless than/sub> voltage level detector enabled + 0x1 + + + + + USB33SV + independent USB supply valid + + 25 + 1 + read-write + + + B_0x0 + Vless thansub>DDUSBless than/sub> is not present. + 0x0 + + + B_0x1 + Vless thansub>DDUSBless than/sub> is valid. + 0x1 + + + + + + + PWR_VMSR + PWR_VMSR + PWR voltage monitor status register + 0x03C + 0x20 + read-only + 0x00000000 + 0xFF0FFFFF + + + AVDO + analog voltage detector output on Vless thansub>DDAless than/sub> + + 19 + 1 + read-only + + + B_0x0 + Vless thansub>DDAless than/sub> is equal or higher than the AVD threshold selected with the ALS[2:0] bits. + 0x0 + + + B_0x1 + Vless thansub>DDAless than/sub> is lower than the AVD threshold selected with the ALS[2:0] bits. + 0x1 + + + + + VDDIO2RDY + voltage detector output on Vless thansub>DDIO2less than/sub> + + 20 + 1 + read-only + + + B_0x0 + Vless thansub>DDIO2less than/sub> is below 1. + 0x0 + + + B_0x1 + Vless thansub>DDIO2less than/sub> is above or equal to 1. + 0x1 + + + + + PVDO + programmable voltage detect output + + 22 + 1 + read-only + + + B_0x0 + Vless thansub>DDless than/sub> is equal or higher than the PVD threshold selected through the PLS[2:0] bits. + 0x0 + + + B_0x1 + Vless thansub>DDless than/sub> is lower than the PVD threshold selected through the PLS[2:0] bits. + 0x1 + + + + + USB33RDY + Vless thansub>DDUSBless than/sub> ready + 24 + 1 + read-only + + + B_0x0 + Vless thansub>DDUSBless than/sub> is below the threshold of the Vless thansub>DDUSBless than/sub> voltage monitor. + 0x0 + + + B_0x1 + Vless thansub>DDUSBless than/sub> is equal or above the threshold of the Vless thansub>DDUSBless than/sub> voltage monitor. + 0x1 + + + + + + + PWR_WUSCR + PWR_WUSCR + PWR wake-up status clear register + 0x040 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CWUF1 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 0 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF2 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 1 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF3 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 2 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF4 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 3 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF5 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 4 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF6 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 5 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF7 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 6 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + CWUF8 + clear wake-up pin flag for WUFx (x = 8 to 1) + + 7 + 1 + write-only + + + B_0x0 + no effect + 0x0 + + + B_0x1 + writing 1 clears the WUFx wake-up pin flag (bit is cleared to 0 by hardware). + 0x1 + + + + + + + PWR_WUSR + PWR_WUSR + PWR wake-up status register + 0x044 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + WUF1 + wake-up pin WUFx flag + + 0 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF2 + wake-up pin WUFx flag + + 1 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF3 + wake-up pin WUFx flag + + 2 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF4 + wake-up pin WUFx flag + + 3 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF5 + wake-up pin WUFx flag + + 4 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF6 + wake-up pin WUFx flag + + 5 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF7 + wake-up pin WUFx flag + + 6 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + WUF8 + wake-up pin WUFx flag + + 7 + 1 + read-only + + + B_0x0 + no wake-up event occurred. + 0x0 + + + B_0x1 + wake-up event received from WUFx pin. + 0x1 + + + + + + + PWR_WUCR + PWR_WUCR + PWR wake-up configuration register + 0x048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + WUPEN1 + enable wake-up pin WUPx (x = 8 to 1) + + 0 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN2 + enable wake-up pin WUPx (x = 8 to 1) + + 1 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN3 + enable wake-up pin WUPx (x = 8 to 1) + + 2 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN4 + enable wake-up pin WUPx (x = 8 to 1) + + 3 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN5 + enable wake-up pin WUPx (x = 8 to 1) + + 4 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN6 + enable wake-up pin WUPx (x = 8 to 1) + + 5 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN7 + enable wake-up pin WUPx (x = 8 to 1) + + 6 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPEN8 + enable wake-up pin WUPx (x = 8 to 1) + + 7 + 1 + read-write + + + B_0x0 + an event on WUPx pin does not wake-up the system from Standby mode. + 0x0 + + + B_0x1 + a rising or falling edge on WUPx pin wakes up the system from Standby mode. + 0x1 + + + + + WUPP1 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 8 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP2 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 9 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP3 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 10 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP4 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 11 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP5 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 12 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP6 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 13 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP7 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 14 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPP8 + wake-up pin polarity bit for WUPx (x = 8 to 1) + + 15 + 1 + read-write + + + B_0x0 + detection on high level (rising edge) + 0x0 + + + B_0x1 + detection on low level (falling edge) + 0x1 + + + + + WUPPUPD1 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 16 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD2 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 18 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD3 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 20 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD4 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 22 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD5 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 24 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD6 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 26 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD7 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 28 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + WUPPUPD8 + wake-up pin pull configuration for WKUPx (x = 8 to 1) + + 30 + 2 + read-write + + + B_0x0 + no pull-up + 0x0 + + + B_0x1 + pull-up + 0x1 + + + B_0x2 + pull-down + 0x2 + + + + + + + PWR_IORETR + PWR_IORETR + PWR I/O retention register + 0x050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IORETEN + IO retention enable + + 0 + 1 + read-write + + + B_0x0 + IO Retention mode is disabled. + 0x0 + + + B_0x1 + IO Retention mode is enabling for all IO except the IO support the standby functionality and PA13, PA14, PA15, and PB4. + 0x1 + + + + + JTAGIORETEN + IO retention enable for JTAG IOs + + 16 + 1 + read-write + + + B_0x0 + IO Retention mode is disabled. + 0x0 + + + B_0x1 + IO Retention mode is enabling for PA13, PA14, PA15, and PB4. + 0x1 + + + + + + + PWR_SECCFGR + PWR_SECCFGR + PWR security configuration register + 0x100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + WUP1SEC + WUPx secure protection (x = 8 to 1) + 0 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP2SEC + WUPx secure protection (x = 8 to 1) + 1 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP3SEC + WUPx secure protection (x = 8 to 1) + 2 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP4SEC + WUPx secure protection (x = 8 to 1) + 3 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP5SEC + WUPx secure protection (x = 8 to 1) + 4 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP6SEC + WUPx secure protection (x = 8 to 1) + 5 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP7SEC + WUPx secure protection (x = 8 to 1) + 6 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + WUP8SEC + WUPx secure protection (x = 8 to 1) + 7 + 1 + read-write + + + B_0x0 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + The bits related to the WKUPx wake-up pin in PWR_WUSCR and PWR_WUCR can be read and written only with secure access. + 0x1 + + + + + RETSEC + retention secure protection + 11 + 1 + read-write + + + B_0x0 + PWR_IORETR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_IORETR can be read and written only with secure access. + 0x1 + + + + + LPMSEC + low-power modes secure protection + 12 + 1 + read-write + + + B_0x0 + PWR_PMCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_PMCR can be read and written only with secure access. + 0x1 + + + + + SCMSEC + supply configuration and monitoring secure protection. + 13 + 1 + read-write + + + B_0x0 + PWR_SCCR and PWR_VMCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_SCCR and PWR_VMCR can be read and written only with secure access. + 0x1 + + + + + VBSEC + Backup domain secure protection + 14 + 1 + read-write + + + B_0x0 + PWR_BDCR, PWR_DBPCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_BDCR, PWR_DBPCR can be read and written only with secure access. + 0x1 + + + + + VUSBSEC + voltage USB secure protection + 15 + 1 + read-write + + + B_0x0 + PWR_USBSCR can be read and written with secure or non-secure access. + 0x0 + + + B_0x1 + PWR_USBSCR can be read and written only with secure access. + 0x1 + + + + + + + PWR_PRIVCFGR + PWR_PRIVCFGR + PWR privilege configuration register + 0x104 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPRIV + PWR secure functions privilege configuration + + 0 + 1 + read-write + + + B_0x0 + Read and write to PWR secure functions can be done by privileged or unprivileged access. + 0x0 + + + B_0x1 + Read and write to PWR secure functions can be done by privileged access only. + 0x1 + + + + + NSPRIV + PWR non-secure functions privilege configuration + + 1 + 1 + read-write + + + B_0x0 + Read and write to PWR non-secure functions can be done by privileged or unprivileged access. + 0x0 + + + B_0x1 + Read and write to PWR non-secure functions can be done by privileged access only. + 0x1 + + + + + + + + + PWR_S + 0X54020800 + + + RAMCFG + RAMCFG address block description + RAMCFG + 0x40026000 + + 0x0 + 0x12C + registers + + + RAMCFG + RAM configuration global interrupt + 5 + + + + RAMCFG_M1CR + RAMCFG_M1CR + RAMCFG memory 1 control register + 0x0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFF0 + + + ECCE + ECC enable. + 0 + 1 + read-write + + + B_0x0 + ECC disabled + 0x0 + + + B_0x1 + ECC enabled + 0x1 + + + + + ALE + Address latch enable + + 4 + 1 + read-write + + + B_0x0 + Failing address not stored in the SRAMx ECC single/double error address registers + 0x0 + + + B_0x1 + Failing address stored in the SRAMx ECC single/double error address registers + 0x1 + + + + + SRAMER + SRAM erase + + 8 + 1 + read-write + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M1ISR + RAMCFG_M1ISR + RAMCFG memory interrupt status register + 0x8 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SEDC + ECC single error detected and corrected + + 0 + 1 + read-only + + + B_0x0 + No single error + 0x0 + + + B_0x1 + Single error detected and corrected + 0x1 + + + + + DED + ECC double error detected + + 1 + 1 + read-only + + + B_0x0 + No double error + 0x0 + + + B_0x1 + Double error detected + 0x1 + + + + + SRAMBUSY + SRAM busy with erase operation + + 8 + 1 + read-only + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M1ERKEYR + RAMCFG_M1ERKEYR + RAMCFG memory 1 erase key register + 0x28 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ERASEKEY + Erase write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M2CR + RAMCFG_M2CR + RAMCFG memory 2 control register + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFF0 + + + ECCE + ECC enable. + 0 + 1 + read-write + + + B_0x0 + ECC disabled + 0x0 + + + B_0x1 + ECC enabled + 0x1 + + + + + ALE + Address latch enable + + 4 + 1 + read-write + + + B_0x0 + Failing address not stored in the SRAMx ECC single/double error address registers + 0x0 + + + B_0x1 + Failing address stored in the SRAMx ECC single/double error address registers + 0x1 + + + + + SRAMER + SRAM erase + + 8 + 1 + read-write + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M2IER + RAMCFG_M2IER + RAMCFG memory 2 interrupt enable register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEIE + ECC single error interrupt enable + 0 + 1 + read-write + + + B_0x0 + Single error interrupt disabled + 0x0 + + + B_0x1 + Single error interrupt enabled + 0x1 + + + + + DEIE + ECC double error interrupt enable + 1 + 1 + read-write + + + B_0x0 + Double error interrupt disabled + 0x0 + + + B_0x1 + Double error interrupt enabled + 0x1 + + + + + ECCNMI + Double error NMI + + 3 + 1 + read-write + + + B_0x0 + NMI not generated in case of ECC double error + 0x0 + + + B_0x1 + NMI generated in case of ECC double error + 0x1 + + + + + + + RAMCFG_M2ISR + RAMCFG_M2ISR + RAMCFG memory interrupt status register + 0x48 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SEDC + ECC single error detected and corrected + + 0 + 1 + read-only + + + B_0x0 + No single error + 0x0 + + + B_0x1 + Single error detected and corrected + 0x1 + + + + + DED + ECC double error detected + + 1 + 1 + read-only + + + B_0x0 + No double error + 0x0 + + + B_0x1 + Double error detected + 0x1 + + + + + SRAMBUSY + SRAM busy with erase operation + + 8 + 1 + read-only + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M2SEAR + RAMCFG_M2SEAR + RAMCFG memory 2 ECC single error address register + 0x4C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ESEA + ECC single error address + + 0 + 32 + read-only + + + + + RAMCFG_M2DEAR + RAMCFG_M2DEAR + RAMCFG memory 2 ECC double error address register + 0x50 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + EDEA + ECC double error address + + 0 + 32 + read-only + + + + + RAMCFG_M2ICR + RAMCFG_M2ICR + RAMCFG memory 2 interrupt clear register 2 + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSEDC + Clear ECC single error detected and corrected + + 0 + 1 + read-write + + + CDED + Clear ECC double error detected + + 1 + 1 + read-write + + + + + RAMCFG_M2WPR1 + RAMCFG_M2WPR1 + RAMCFG memory 2 write protection register 1 + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + P0WP + SRAM2 1-Kbyte page y write protection + + 0 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P1WP + SRAM2 1-Kbyte page y write protection + + 1 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P2WP + SRAM2 1-Kbyte page y write protection + + 2 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P3WP + SRAM2 1-Kbyte page y write protection + + 3 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P4WP + SRAM2 1-Kbyte page y write protection + + 4 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P5WP + SRAM2 1-Kbyte page y write protection + + 5 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P6WP + SRAM2 1-Kbyte page y write protection + + 6 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P7WP + SRAM2 1-Kbyte page y write protection + + 7 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P8WP + SRAM2 1-Kbyte page y write protection + + 8 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P9WP + SRAM2 1-Kbyte page y write protection + + 9 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P10WP + SRAM2 1-Kbyte page y write protection + + 10 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P11WP + SRAM2 1-Kbyte page y write protection + + 11 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P12WP + SRAM2 1-Kbyte page y write protection + + 12 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P13WP + SRAM2 1-Kbyte page y write protection + + 13 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P14WP + SRAM2 1-Kbyte page y write protection + + 14 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P15WP + SRAM2 1-Kbyte page y write protection + + 15 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P16WP + SRAM2 1-Kbyte page y write protection + + 16 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P17WP + SRAM2 1-Kbyte page y write protection + + 17 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P18WP + SRAM2 1-Kbyte page y write protection + + 18 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P19WP + SRAM2 1-Kbyte page y write protection + + 19 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P20WP + SRAM2 1-Kbyte page y write protection + + 20 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P21WP + SRAM2 1-Kbyte page y write protection + + 21 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P22WP + SRAM2 1-Kbyte page y write protection + + 22 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P23WP + SRAM2 1-Kbyte page y write protection + + 23 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P24WP + SRAM2 1-Kbyte page y write protection + + 24 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P25WP + SRAM2 1-Kbyte page y write protection + + 25 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P26WP + SRAM2 1-Kbyte page y write protection + + 26 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P27WP + SRAM2 1-Kbyte page y write protection + + 27 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P28WP + SRAM2 1-Kbyte page y write protection + + 28 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P29WP + SRAM2 1-Kbyte page y write protection + + 29 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P30WP + SRAM2 1-Kbyte page y write protection + + 30 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P31WP + SRAM2 1-Kbyte page y write protection + + 31 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + + + RAMCFG_M2WPR2 + RAMCFG_M2WPR2 + RAMCFG memory 2 write protection register 2 + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + P32WP + SRAM2 1-Kbyte page y write protection + + 0 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P33WP + SRAM2 1-Kbyte page y write protection + + 1 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P34WP + SRAM2 1-Kbyte page y write protection + + 2 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P35WP + SRAM2 1-Kbyte page y write protection + + 3 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P36WP + SRAM2 1-Kbyte page y write protection + + 4 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P37WP + SRAM2 1-Kbyte page y write protection + + 5 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P38WP + SRAM2 1-Kbyte page y write protection + + 6 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P39WP + SRAM2 1-Kbyte page y write protection + + 7 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P40WP + SRAM2 1-Kbyte page y write protection + + 8 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P41WP + SRAM2 1-Kbyte page y write protection + + 9 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P42WP + SRAM2 1-Kbyte page y write protection + + 10 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P43WP + SRAM2 1-Kbyte page y write protection + + 11 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P44WP + SRAM2 1-Kbyte page y write protection + + 12 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P45WP + SRAM2 1-Kbyte page y write protection + + 13 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P46WP + SRAM2 1-Kbyte page y write protection + + 14 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P47WP + SRAM2 1-Kbyte page y write protection + + 15 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P48WP + SRAM2 1-Kbyte page y write protection + + 16 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P49WP + SRAM2 1-Kbyte page y write protection + + 17 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P50WP + SRAM2 1-Kbyte page y write protection + + 18 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P51WP + SRAM2 1-Kbyte page y write protection + + 19 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P52WP + SRAM2 1-Kbyte page y write protection + + 20 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P53WP + SRAM2 1-Kbyte page y write protection + + 21 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P54WP + SRAM2 1-Kbyte page y write protection + + 22 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P55WP + SRAM2 1-Kbyte page y write protection + + 23 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P56WP + SRAM2 1-Kbyte page y write protection + + 24 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P57WP + SRAM2 1-Kbyte page y write protection + + 25 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P58WP + SRAM2 1-Kbyte page y write protection + + 26 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P59WP + SRAM2 1-Kbyte page y write protection + + 27 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P60WP + SRAM2 1-Kbyte page y write protection + + 28 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P61WP + SRAM2 1-Kbyte page y write protection + + 29 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P62WP + SRAM2 1-Kbyte page y write protection + + 30 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P63WP + SRAM2 1-Kbyte page y write protection + + 31 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + + + RAMCFG_M2WPR3 + RAMCFG_M2WPR3 + RAMCFG memory 2 write protection register 3 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + P64WP + SRAM2 1-Kbyte page y write protection + + 0 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P65WP + SRAM2 1-Kbyte page y write protection + + 1 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P66WP + SRAM2 1-Kbyte page y write protection + + 2 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P67WP + SRAM2 1-Kbyte page y write protection + + 3 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P68WP + SRAM2 1-Kbyte page y write protection + + 4 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P69WP + SRAM2 1-Kbyte page y write protection + + 5 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P70WP + SRAM2 1-Kbyte page y write protection + + 6 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P71WP + SRAM2 1-Kbyte page y write protection + + 7 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P72WP + SRAM2 1-Kbyte page y write protection + + 8 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P73WP + SRAM2 1-Kbyte page y write protection + + 9 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P74WP + SRAM2 1-Kbyte page y write protection + + 10 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P75WP + SRAM2 1-Kbyte page y write protection + + 11 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P76WP + SRAM2 1-Kbyte page y write protection + + 12 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P77WP + SRAM2 1-Kbyte page y write protection + + 13 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P78WP + SRAM2 1-Kbyte page y write protection + + 14 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + P79WP + SRAM2 1-Kbyte page y write protection + + 15 + 1 + read-write + + + B_0x0 + Write protection of SRAM2 1-Kbyte page y is disabled. + 0x0 + + + B_0x1 + Write protection of SRAM2 1-Kbyte page y is enabled. + 0x1 + + + + + + + RAMCFG_M2ECCKEYR + RAMCFG_M2ECCKEYR + RAMCFG memory 2 ECC key register + 0x64 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ECCKEY + ECC write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M2ERKEYR + RAMCFG_M2ERKEYR + RAMCFG memory 2 erase key register + 0x68 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ERASEKEY + Erase write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M3CR + RAMCFG_M3CR + RAMCFG memory 3 control register + 0x80 + 0x20 + read-write + 0x00000000 + 0xFFFFFFF0 + + + ECCE + ECC enable. + 0 + 1 + read-write + + + B_0x0 + ECC disabled + 0x0 + + + B_0x1 + ECC enabled + 0x1 + + + + + ALE + Address latch enable + + 4 + 1 + read-write + + + B_0x0 + Failing address not stored in the SRAMx ECC single/double error address registers + 0x0 + + + B_0x1 + Failing address stored in the SRAMx ECC single/double error address registers + 0x1 + + + + + SRAMER + SRAM erase + + 8 + 1 + read-write + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M3IER + RAMCFG_M3IER + RAMCFG memory 3 interrupt enable register + 0x84 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEIE + ECC single error interrupt enable + 0 + 1 + read-write + + + B_0x0 + Single error interrupt disabled + 0x0 + + + B_0x1 + Single error interrupt enabled + 0x1 + + + + + DEIE + ECC double error interrupt enable + 1 + 1 + read-write + + + B_0x0 + Double error interrupt disabled + 0x0 + + + B_0x1 + Double error interrupt enabled + 0x1 + + + + + ECCNMI + Double error NMI + + 3 + 1 + read-write + + + B_0x0 + NMI not generated in case of ECC double error + 0x0 + + + B_0x1 + NMI generated in case of ECC double error + 0x1 + + + + + + + RAMCFG_M3ISR + RAMCFG_M3ISR + RAMCFG memory interrupt status register + 0x88 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SEDC + ECC single error detected and corrected + + 0 + 1 + read-only + + + B_0x0 + No single error + 0x0 + + + B_0x1 + Single error detected and corrected + 0x1 + + + + + DED + ECC double error detected + + 1 + 1 + read-only + + + B_0x0 + No double error + 0x0 + + + B_0x1 + Double error detected + 0x1 + + + + + SRAMBUSY + SRAM busy with erase operation + + 8 + 1 + read-only + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M3SEAR + RAMCFG_M3SEAR + RAMCFG memory 3 ECC single error address register + 0x8C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ESEA + ECC single error address + + 0 + 32 + read-only + + + + + RAMCFG_M3DEAR + RAMCFG_M3DEAR + RAMCFG memory 3 ECC double error address register + 0x90 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + EDEA + ECC double error address + + 0 + 32 + read-only + + + + + RAMCFG_M3ICR + RAMCFG_M3ICR + RAMCFG memory 3 interrupt clear register 3 + 0x94 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSEDC + Clear ECC single error detected and corrected + + 0 + 1 + read-write + + + CDED + Clear ECC double error detected + + 1 + 1 + read-write + + + + + RAMCFG_M3ECCKEYR + RAMCFG_M3ECCKEYR + RAMCFG memory 3 ECC key register + 0xA4 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ECCKEY + ECC write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M3ERKEYR + RAMCFG_M3ERKEYR + RAMCFG memory 3 erase key register + 0xA8 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ERASEKEY + Erase write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M4ERKEYR + RAMCFG_M4ERKEYR + RAMCFG memory 4 erase key register + 0xE8 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ERASEKEY + Erase write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M5CR + RAMCFG_M5CR + RAMCFG memory 5 control register + 0x100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFF0 + + + ECCE + ECC enable. + 0 + 1 + read-write + + + B_0x0 + ECC disabled + 0x0 + + + B_0x1 + ECC enabled + 0x1 + + + + + ALE + Address latch enable + + 4 + 1 + read-write + + + B_0x0 + Failing address not stored in the SRAMx ECC single/double error address registers + 0x0 + + + B_0x1 + Failing address stored in the SRAMx ECC single/double error address registers + 0x1 + + + + + SRAMER + SRAM erase + + 8 + 1 + read-write + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M5IER + RAMCFG_M5IER + RAMCFG memory 5 interrupt enable register + 0x104 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEIE + ECC single error interrupt enable + 0 + 1 + read-write + + + B_0x0 + Single error interrupt disabled + 0x0 + + + B_0x1 + Single error interrupt enabled + 0x1 + + + + + DEIE + ECC double error interrupt enable + 1 + 1 + read-write + + + B_0x0 + Double error interrupt disabled + 0x0 + + + B_0x1 + Double error interrupt enabled + 0x1 + + + + + ECCNMI + Double error NMI + + 3 + 1 + read-write + + + B_0x0 + NMI not generated in case of ECC double error + 0x0 + + + B_0x1 + NMI generated in case of ECC double error + 0x1 + + + + + + + RAMCFG_M5ISR + RAMCFG_M5ISR + RAMCFG memory interrupt status register + 0x108 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SEDC + ECC single error detected and corrected + + 0 + 1 + read-only + + + B_0x0 + No single error + 0x0 + + + B_0x1 + Single error detected and corrected + 0x1 + + + + + DED + ECC double error detected + + 1 + 1 + read-only + + + B_0x0 + No double error + 0x0 + + + B_0x1 + Double error detected + 0x1 + + + + + SRAMBUSY + SRAM busy with erase operation + + 8 + 1 + read-only + + + B_0x0 + No erase operation on going + 0x0 + + + B_0x1 + Erase operation on going + 0x1 + + + + + + + RAMCFG_M5SEAR + RAMCFG_M5SEAR + RAMCFG memory 5 ECC single error address register + 0x10C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ESEA + ECC single error address + + 0 + 32 + read-only + + + + + RAMCFG_M5DEAR + RAMCFG_M5DEAR + RAMCFG memory 5 ECC double error address register + 0x110 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + EDEA + ECC double error address + + 0 + 32 + read-only + + + + + RAMCFG_M5ICR + RAMCFG_M5ICR + RAMCFG memory 5 interrupt clear register 5 + 0x114 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSEDC + Clear ECC single error detected and corrected + + 0 + 1 + read-write + + + CDED + Clear ECC double error detected + + 1 + 1 + read-write + + + + + RAMCFG_M5ECCKEYR + RAMCFG_M5ECCKEYR + RAMCFG memory 5 ECC key register + 0x124 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ECCKEY + ECC write protection key + + 0 + 8 + write-only + + + + + RAMCFG_M5ERKEYR + RAMCFG_M5ERKEYR + RAMCFG memory 5 erase key register + 0x128 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ERASEKEY + Erase write protection key + + 0 + 8 + write-only + + + + + + + RAMCFG_S + 0X50026000 + + + RCC + RCC address block description + RCC + 0x44020c00 + + 0x0 + 0x118 + registers + + + RCC_S + RCC secure global interrupt + 10 + + + RCC + RCC non-secure global interrupt + 9 + + + + RCC_CR + RCC_CR + RCC clock control register + 0x000 + 0x20 + read-write + 0x0000002B + 0xFFFFFFFF + + + HSION + HSI clock enable + + 0 + 1 + read-write + + + B_0x0 + HSI is OFF + 0x0 + + + B_0x1 + HSI is ON (default after reset) + 0x1 + + + + + HSIRDY + HSI clock ready flag + + 1 + 1 + read-only + + + B_0x0 + HSI clock is not ready (default after reset) + 0x0 + + + B_0x1 + HSI clock is ready + 0x1 + + + + + HSIKERON + HSI clock enable in Stop mode + + 2 + 1 + read-write + + + B_0x0 + no effect on HSI (default after reset) + 0x0 + + + B_0x1 + HSI is forced to ON even in Stop mode + 0x1 + + + + + HSIDIV + HSI clock divider + + 3 + 2 + read-write + + + B_0x0 + division by 1, hsi_ck, hsi_ker_ck = 64 MHz + 0x0 + + + B_0x1 + division by 2, hsi_ck, hsi_ker_ck = 32 MHz (default after reset) + 0x1 + + + B_0x2 + division by 4, hsi_ck, hsi_ker_ck = 16 MHz + 0x2 + + + B_0x3 + division by 8, hsi_ck, hsi_ker_ck = 8 MHz + 0x3 + + + + + HSIDIVF + HSI divider flag + + 5 + 1 + read-only + + + B_0x0 + new division ratio not yet propagated to hsi_ck , hsi_ker_ck (default after reset) + 0x0 + + + B_0x1 + hsi_ck , hsi_ker_ck clock frequency reflects the new HSIDIV value (default register value when the clock setting is completed). + 0x1 + + + + + CSION + CSI clock enable + + 8 + 1 + read-write + + + B_0x0 + CSI is OFF (default after reset) + 0x0 + + + B_0x1 + CSI is ON + 0x1 + + + + + CSIRDY + CSI clock ready flag + + 9 + 1 + read-only + + + B_0x0 + CSI clock is not ready (default after reset) + 0x0 + + + B_0x1 + CSI clock is ready + 0x1 + + + + + CSIKERON + CSI clock enable in Stop mode + + 10 + 1 + read-write + + + B_0x0 + no effect on CSI (default after reset) + 0x0 + + + B_0x1 + CSI is forced to ON even in Stop mode + 0x1 + + + + + HSI48ON + HSI48 clock enable + + 12 + 1 + read-write + + + B_0x0 + HSI48 is OFF (default after reset) + 0x0 + + + B_0x1 + HSI48 is ON + 0x1 + + + + + HSI48RDY + HSI48 clock ready flag + + 13 + 1 + read-only + + + B_0x0 + HSI48 clock is not ready (default after reset) + 0x0 + + + B_0x1 + HSI48 clock is ready + 0x1 + + + + + HSEON + HSE clock enable + + 16 + 1 + read-write + + + B_0x0 + HSE is OFF (default after reset) + 0x0 + + + B_0x1 + HSE is ON + 0x1 + + + + + HSERDY + HSE clock ready flag + + 17 + 1 + read-only + + + B_0x0 + HSE clock is not ready (default after reset) + 0x0 + + + B_0x1 + HSE clock is ready + 0x1 + + + + + HSEBYP + HSE clock bypass + + 18 + 1 + read-write + + + B_0x0 + HSE oscillator not bypassed (default after reset) + 0x0 + + + B_0x1 + HSE oscillator bypassed with an external clock + 0x1 + + + + + HSECSSON + HSE clock security system enable + + 19 + 1 + read-write + + + B_0x0 + CSS on HSE OFF (clock detector OFF) (default after reset) + 0x0 + + + B_0x1 + CSS on HSE ON (clock detector ON if the HSE oscillator is stable, OFF if not). + 0x1 + + + + + HSEEXT + external high speed clock type in Bypass mode + + 20 + 1 + read-write + + + B_0x0 + HSE in analog mode (default after reset) + 0x0 + + + B_0x1 + HSE in digital mode + 0x1 + + + + + PLL1ON + PLL1 enable + + 24 + 1 + read-write + + + B_0x0 + PLL1 OFF (default after reset) + 0x0 + + + B_0x1 + PLL1 ON + 0x1 + + + + + PLL1RDY + PLL1 clock ready flag + + 25 + 1 + read-only + + + B_0x0 + PLL1 unlocked (default after reset) + 0x0 + + + B_0x1 + PLL1 locked + 0x1 + + + + + PLL2ON + PLL2 enable + + 26 + 1 + read-write + + + B_0x0 + PLL2 OFF (default after reset) + 0x0 + + + B_0x1 + PLL2 ON + 0x1 + + + + + PLL2RDY + PLL2 clock ready flag + + 27 + 1 + read-only + + + B_0x0 + PLL2 unlocked + 0x0 + + + B_0x1 + PLL2 locked + 0x1 + + + + + PLL3ON + PLL3 enable + + 28 + 1 + read-write + + + B_0x0 + PLL3 OFF (default after reset) + 0x0 + + + B_0x1 + PLL3 ON + 0x1 + + + + + PLL3RDY + PLL3 clock ready flag + + 29 + 1 + read-only + + + B_0x0 + PLL3 unlocked (default after reset) + 0x0 + + + B_0x1 + PLL3 locked + 0x1 + + + + + + + RCC_HSICFGR + RCC_HSICFGR + RCC HSI calibration register + 0x010 + 0x20 + read-write + 0x00400000 + 0xFFFFF000 + + + HSICAL + HSI clock calibration + + 0 + 12 + read-only + + + HSITRIM + HSI clock trimming + + 16 + 7 + read-write + + + + + RCC_CRRCR + RCC_CRRCR + RCC clock recovery RC register + 0x014 + 0x20 + read-only + 0x00000000 + 0xFFFFF000 + + + HSI48CAL + Internal RC 48 MHz clock calibration + + 0 + 10 + read-only + + + + + RCC_CSICFGR + RCC_CSICFGR + RCC CSI calibration register + 0x018 + 0x20 + read-write + 0x00200000 + 0xFFFFF000 + + + CSICAL + CSI clock calibration + + 0 + 8 + read-write + + + CSITRIM + CSI clock trimming + + 16 + 6 + read-write + + + + + RCC_CFGR1 + RCC_CFGR1 + RCC clock configuration register1 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SW + system clock and trace clock switch + + 0 + 2 + read-write + + + B_0x0 + HSI selected as system clock (hsi_ck) (default after reset) + 0x0 + + + B_0x1 + CSI selected as system clock (csi_ck) + 0x1 + + + B_0x2 + HSE selected as system clock (hse_ck) + 0x2 + + + B_0x3 + PLL1 selected as system clock (pll1_p_ck for sys_ck) + 0x3 + + + + + SWS + system clock switch status + + 3 + 2 + read-only + + + B_0x1 + CSI used as system clock (csi_ck) + 0x1 + + + B_0x2 + HSE used as system clock (hse_ck) + 0x2 + + + B_0x3 + PLL1 used as system clock (pll1_p_ck) + 0x3 + + + + + STOPWUCK + system clock selection after a wakeup from system Stop + + 6 + 1 + read-write + + + B_0x1 + CSI selected as wakeup clock from system Stop + 0x1 + + + + + STOPKERWUCK + kernel clock selection after a wakeup from system Stop + + 7 + 1 + read-write + + + B_0x0 + HSI selected as wakeup clock from system Stop (default after reset) + 0x0 + + + B_0x1 + CSI selected as wakeup clock from system Stop + 0x1 + + + + + RTCPRE + HSE division factor for RTC clock + + 8 + 6 + read-write + + + B_0x0 + no clock (default after reset) + 0x0 + + + B_0x1 + no clock + 0x1 + + + B_0x2 + HSE/2 + 0x2 + + + B_0x3 + HSE/3 + 0x3 + + + B_0x4 + HSE/4 + 0x4 + + + B_0x3E + HSE/62 + 0x3E + + + B_0x3F + HSE/63 + 0x3F + + + + + TIMPRE + timers clocks prescaler selection + + 15 + 1 + read-write + + + B_0x0 + The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Fless thansub>rcc_pclk1less than/sub> or 2 x Fless thansub>rcc_pclk2less than/sub> (default after reset) + 0x0 + + + B_0x1 + The timers kernel clock is equal to 2 x Fless thansub>rcc_pclk1less than/sub> or 2 x Fless thansub>rcc_pclk2less than/sub> if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Fless thansub>rcc_pclk1less than/sub> or 4 x Fless thansub>rcc_pclk2less than/sub> + 0x1 + + + + + MCO1PRE + MCO1 prescaler + + 18 + 4 + read-write + + + B_0x0 + prescaler disabled (default after reset) + 0x0 + + + B_0x1 + division by 1 (bypass) + 0x1 + + + B_0x2 + division by 2 + 0x2 + + + B_0x3 + division by 3 + 0x3 + + + B_0x4 + division by 4 + 0x4 + + + B_0xF + division by 15 + 0xF + + + + + MCO1SEL + Microcontroller clock output 1 + + 22 + 3 + read-write + + + B_0x0 + HSI clock selected (hsi_ck) (default after reset) + 0x0 + + + B_0x1 + LSE oscillator clock selected (lse_ck) + 0x1 + + + B_0x2 + HSE clock selected (hse_ck) + 0x2 + + + B_0x3 + PLL1 clock selected (pll1_q_ck) + 0x3 + + + B_0x4 + HSI48 clock selected (hsi48_ck) + 0x4 + + + + + MCO2PRE + MCO2 prescaler + + 25 + 4 + read-write + + + B_0x0 + prescaler disabled (default after reset) + 0x0 + + + B_0x1 + division by 1 (bypass) + 0x1 + + + B_0x2 + division by 2 + 0x2 + + + B_0x3 + division by 3 + 0x3 + + + B_0x4 + division by 4 + 0x4 + + + B_0xF + division by 15 + 0xF + + + + + MCO2SEL + microcontroller clock output 2 + + 29 + 3 + read-write + + + B_0x0 + system clock selected (sys_ck) (default after reset) + 0x0 + + + B_0x1 + PLL2 oscillator clock selected (pll2_p_ck) + 0x1 + + + B_0x2 + HSE clock selected (hse_ck) + 0x2 + + + B_0x3 + PLL1 clock selected (pll1_p_ck) + 0x3 + + + B_0x4 + CSI clock selected (csi_ck) + 0x4 + + + B_0x5 + LSI clock selected (lsi_ck) + 0x5 + + + + + + + RCC_CFGR2 + RCC_CFGR2 + RCC CPU domain clock configuration register 2 + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HPRE + AHB prescaler + + 0 + 4 + read-write + + + B_0x8 + rcc_hclk = sys_ck / 2 + 0x8 + + + B_0x9 + rcc_hclk = sys_ck / 4 + 0x9 + + + B_0xA + rcc_hclk = sys_ck / 8 + 0xA + + + B_0xB + rcc_hclk = sys_ck / 16 + 0xB + + + B_0xC + rcc_hclk = sys_ck / 64 + 0xC + + + B_0xD + rcc_hclk = sys_ck / 128 + 0xD + + + B_0xE + rcc_hclk = sys_ck / 256 + 0xE + + + B_0xF + rcc_hclk = sys_ck / 512 + 0xF + + + + + PPRE1 + APB low-speed prescaler (APB1) + + 4 + 3 + read-write + + + B_0x4 + rcc_pclk1 = rcc_hclk1 / 2 + 0x4 + + + B_0x5 + rcc_pclk1 = rcc_hclk1 / 4 + 0x5 + + + B_0x6 + rcc_pclk1 = rcc_hclk1 / 8 + 0x6 + + + B_0x7 + rcc_pclk1 = rcc_hclk1 / 16 + 0x7 + + + + + PPRE2 + APB high-speed prescaler (APB2) + + 8 + 3 + read-write + + + B_0x4 + rcc_pclk2 = rcc_hclk1 / 2 + 0x4 + + + B_0x5 + rcc_pclk2 = rcc_hclk1 / 4 + 0x5 + + + B_0x6 + rcc_pclk2 = rcc_hclk1 / 8 + 0x6 + + + B_0x7 + rcc_pclk2 = rcc_hclk1 / 16 + 0x7 + + + + + PPRE3 + APB low-speed prescaler (APB3) + + 12 + 3 + read-write + + + B_0x4 + rcc_pclk3 = rcc_hclk1 / 2 + 0x4 + + + B_0x5 + rcc_pclk3 = rcc_hclk1 / 4 + 0x5 + + + B_0x6 + rcc_pclk3 = rcc_hclk1 / 8 + 0x6 + + + B_0x7 + rcc_pclk3 = rcc_hclk1 / 16 + 0x7 + + + + + AHB1DIS + AHB1 clock disable + + 16 + 1 + read-write + + + B_0x0 + AHB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + AHB1 clock disabled + 0x1 + + + + + AHB2DIS + AHB2 clock disable + + 17 + 1 + read-write + + + B_0x0 + AHB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + AHB2 clock disabled + 0x1 + + + + + AHB4DIS + AHB4 clock disable + + 19 + 1 + read-write + + + B_0x0 + AHB4 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + AHB4 clock disabled + 0x1 + + + + + APB1DIS + APB1 clock disable value + + 20 + 1 + read-write + + + B_0x0 + APB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + APB1 clock disabled + 0x1 + + + + + APB2DIS + APB2 clock disable value + + 21 + 1 + read-write + + + B_0x0 + APB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + APB2 clock disabled + 0x1 + + + + + APB3DIS + APB3 clock disable value. + 22 + 1 + read-write + + + B_0x0 + APB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits + 0x0 + + + B_0x1 + APB3 clock disabled + 0x1 + + + + + + + RCC_PLL1CFGR + RCC_PLL1CFGR + RCC PLL clock source selection register + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLL1SRC + PLL1M and PLLs clock source selection + + 0 + 2 + read-write + + + B_0x0 + no clock send to PLL1M divider and PLLs (default after reset). + 0x0 + + + B_0x1 + HSI selected as PLL clock (hsi_ck) + 0x1 + + + B_0x2 + CSI selected as PLL clock (csi_ck) + 0x2 + + + B_0x3 + HSE selected as PLL clock (hse_ck) + 0x3 + + + + + PLL1RGE + PLL1 input frequency range + + 2 + 2 + read-write + + + B_0x0 + PLL1 input (ref1_ck) clock range frequency between 1 and 2 MHz (default after reset) + 0x0 + + + B_0x1 + PLL1 input (ref1_ck) clock range frequency between 2 and 4 MHz + 0x1 + + + B_0x2 + PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz + 0x2 + + + B_0x3 + PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz + 0x3 + + + + + PLL1FRACEN + PLL1 fractional latch enable + + 4 + 1 + read-write + + + PLL1VCOSEL + PLL1 VCO selection + + 5 + 1 + read-write + + + B_0x0 + wide VCO range: 192 to 836 MHz (default after reset) + 0x0 + + + B_0x1 + medium VCO range: 150 to 420 MHz + 0x1 + + + + + PLL1M + prescaler for PLL1 + + 8 + 6 + read-write + + + B_0x0 + prescaler disabled (default after reset) + 0x0 + + + B_0x1 + division by 1 (bypass) + 0x1 + + + B_0x2 + division by 2 + 0x2 + + + B_0x3 + division by 3 + 0x3 + + + B_0x20 + division by 32 + 0x20 + + + B_0x3F + division by 63 + 0x3F + + + + + PLL1PEN + PLL1 DIVP divider output enable + + 16 + 1 + read-write + + + B_0x0 + pll1_p_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll1_p_ck output enabled + 0x1 + + + + + PLL1QEN + PLL1 DIVQ divider output enable + + 17 + 1 + read-write + + + B_0x0 + pll1_q_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll1_q_ck output enabled + 0x1 + + + + + PLL1REN + PLL1 DIVR divider output enable + + 18 + 1 + read-write + + + B_0x0 + pll1_r_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll1_r_ck output enabled + 0x1 + + + + + + + RCC_PLL2CFGR + RCC_PLL2CFGR + RCC PLL clock source selection register + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLL2SRC + PLL2M and PLLs clock source selection + + 0 + 2 + read-write + + + B_0x0 + no clock send to PLL2M divider and PLLs (default after reset) + 0x0 + + + B_0x1 + HSI selected as PLL clock (hsi_ck) + 0x1 + + + B_0x2 + CSI selected as PLL clock (csi_ck) + 0x2 + + + B_0x3 + HSE selected as PLL clock (hse_ck) + 0x3 + + + + + PLL2RGE + PLL2 input frequency range + + 2 + 2 + read-write + + + B_0x0 + PLL2 input (ref2_ck) clock range frequency between 1 and 2 MHz (default after reset) 01: PLL2 input (ref2_ck) clock range frequency between 2 and 4 MHz + 0x0 + + + B_0x2 + PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz + 0x2 + + + B_0x3 + PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz + 0x3 + + + + + PLL2FRACEN + PLL2 fractional latch enable + + 4 + 1 + read-write + + + B_0x0 + pll2_p_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck output enabled + 0x1 + + + + + PLL2VCOSEL + PLL2 VCO selection + + 5 + 1 + read-write + + + B_0x0 + wide VCO range 192 to 836 MHz (default after reset) + 0x0 + + + B_0x1 + medium VCO range 150 to 420 MHz + 0x1 + + + + + PLL2M + prescaler for PLL2 + + 8 + 6 + read-write + + + B_0x0 + prescaler disabled (default after reset) + 0x0 + + + B_0x1 + division by 1 (bypass) + 0x1 + + + B_0x2 + division by 2 + 0x2 + + + B_0x3 + division by 3 + 0x3 + + + B_0x20 + division by 32 + 0x20 + + + B_0x3F + division by 63 + 0x3F + + + + + PLL2PEN + PLL2 DIVP divider output enable + + 16 + 1 + read-write + + + B_0x0 + pll2_p_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck output enabled + 0x1 + + + + + PLL2QEN + PLL2 DIVQ divider output enable + + 17 + 1 + read-write + + + B_0x0 + pll2_q_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck output enabled + 0x1 + + + + + PLL2REN + PLL2 DIVR divider output enable + + 18 + 1 + read-write + + + B_0x0 + pll2_r_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll2_r_ck output enabled + 0x1 + + + + + + + RCC_PLL3CFGR + RCC_PLL3CFGR + RCC PLL clock source selection register + 0x030 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLL3SRC + PLL3M and PLLs clock source selection + + 0 + 2 + read-write + + + B_0x0 + no clock send to PLL3M divider and PLLs (default after reset) + 0x0 + + + B_0x1 + HSI selected as PLL clock (hsi_ck) + 0x1 + + + B_0x2 + CSI selected as PLL clock (csi_ck) + 0x2 + + + B_0x3 + HSE selected as PLL clock (hse_ck) + 0x3 + + + + + PLL3RGE + PLL3 input frequency range + + 2 + 2 + read-write + + + B_0x0 + PLL3 input (ref3_ck) clock range frequency between 1 and 2 MHz (default after reset) + 0x0 + + + B_0x1 + PLL3 input (ref3_ck) clock range frequency between 2 and 4 MHz + 0x1 + + + B_0x2 + PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz + 0x2 + + + B_0x3 + PLL3 input (ref3_ck) clock range frequency between 8 and 16 MHz + 0x3 + + + + + PLL3FRACEN + PLL3 fractional latch enable + + 4 + 1 + read-write + + + PLL3VCOSEL + PLL3 VCO selection + + 5 + 1 + read-write + + + B_0x0 + wide VCO range 192 to 836 MHz (default after reset) + 0x0 + + + B_0x1 + medium VCO range 150 to 420 MHz + 0x1 + + + + + PLL3M + prescaler for PLL3 + + 8 + 6 + read-write + + + B_0x0 + prescaler disabled (default after reset) + 0x0 + + + B_0x1 + division by 1 (bypass) + 0x1 + + + B_0x2 + division by 2 + 0x2 + + + B_0x3 + division by 3 + 0x3 + + + B_0x20 + division by 32 + 0x20 + + + B_0x3F + division by 63 + 0x3F + + + + + PLL3PEN + PLL3 DIVP divider output enable + + 16 + 1 + read-write + + + B_0x0 + pll3_p_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll3_p_ck output enabled + 0x1 + + + + + PLL3QEN + PLL3 DIVQ divider output enable + + 17 + 1 + read-write + + + B_0x0 + pll3_q_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll3_q_ck output enabled + 0x1 + + + + + PLL3REN + PLL3 DIVR divider output enable + + 18 + 1 + read-write + + + B_0x0 + pll3_r_ck output disabled (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck output enabled + 0x1 + + + + + + + RCC_PLL1DIVR + RCC_PLL1DIVR + RCC PLL1 dividers register + 0x034 + 0x20 + read-write + 0x01010280 + 0xFFFFFFFF + + + PLL1N + Multiplication factor for PLL1VCO + + 0 + 9 + read-write + + + B_0x003 + PLL1N = 4 + 0x003 + + + B_0x004 + PLL1N = 5 + 0x004 + + + B_0x005 + PLL1N = 6 + 0x005 + + + B_0x080 + PLL1N = 129 (default after reset) + 0x080 + + + B_0x1FF + PLL1N = 512 + 0x1FF + + + + + PLL1P + PLL1 DIVP division factor + + 9 + 7 + read-write + + + B_0x0 + Not allowed + 0x0 + + + B_0x1 + pll1_p_ck = vco1_ck / 2 (default after reset) + 0x1 + + + B_0x2 + Not allowed + 0x2 + + + B_0x3 + pll1_p_ck = vco1_ck / 4 + 0x3 + + + B_0x7F + pll1_p_ck = vco1_ck / 128 + 0x7F + + + + + PLL1Q + PLL1 DIVQ division factor + + 16 + 7 + read-write + + + B_0x0 + pll1_q_ck = vco1_ck + 0x0 + + + B_0x1 + pll1_q_ck = vco1_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll1_q_ck = vco1_ck / 3 + 0x2 + + + B_0x3 + pll1_q_ck = vco1_ck / 4 + 0x3 + + + B_0x7F + pll1_q_ck = vco1_ck / 128 + 0x7F + + + + + PLL1R + PLL1 DIVR division factor + + 24 + 7 + read-write + + + B_0x0 + pll1_r_ck = vco1_ck / 1 + 0x0 + + + B_0x1 + pll1_r_ck = vco1_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll1_r_ck = vco1_ck / 3 + 0x2 + + + B_0x3 + pll1_r_ck = vco1_ck / 4 + 0x3 + + + B_0x7F + pll1_r_ck = vco1_ck / 128 + 0x7F + + + + + + + RCC_PLL1FRACR + RCC_PLL1FRACR + RCC PLL1 fractional divider register + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLL1FRACN + fractional part of the multiplication factor for PLL1 VCO + + 3 + 13 + read-write + + + + + RCC_PLL2DIVR + RCC_PLL2DIVR + RCC PLL1 dividers register + 0x03C + 0x20 + read-write + 0x01010280 + 0xFFFFFFFF + + + PLL2N + Multiplication factor for PLL2VCO + + 0 + 9 + read-write + + + B_0x003 + PLL2N = 4 + 0x003 + + + B_0x004 + PLL2N = 5 + 0x004 + + + B_0x005 + PLL2N = 6 + 0x005 + + + B_0x080 + PLL2N = 129 (default after reset) + 0x080 + + + B_0x1FF + PLL2N = 512 + 0x1FF + + + + + PLL2P + PLL2 DIVP division factor + + 9 + 7 + read-write + + + B_0x0 + pll2_p_ck = vco2_ck + 0x0 + + + B_0x1 + pll2_p_ck = vco2_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll2_p_ck = vco2_ck / 3 + 0x2 + + + B_0x3 + pll2_p_ck = vco2_ck / 4 + 0x3 + + + B_0x7F + pll2_p_ck = vco2_ck / 128 + 0x7F + + + + + PLL2Q + PLL2 DIVQ division factor + + 16 + 7 + read-write + + + B_0x0 + pll2_q_ck = vco2_ck + 0x0 + + + B_0x1 + pll2_q_ck = vco2_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll2_q_ck = vco2_ck / 3 + 0x2 + + + B_0x3 + pll2_q_ck = vco2_ck / 4 + 0x3 + + + B_0x7F + pll2_q_ck = vco2_ck / 128 + 0x7F + + + + + PLL2R + PLL2 DIVR division factor + + 24 + 7 + read-write + + + B_0x0 + pll2_r_ck = vco2_ck + 0x0 + + + B_0x1 + pll2_r_ck = vco2_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll2_r_ck = vco2_ck / 3 + 0x2 + + + B_0x3 + pll2_r_ck = vco2_ck / 4 + 0x3 + + + B_0x7F + pll2_r_ck = vco2_ck / 128 + 0x7F + + + + + + + RCC_PLL2FRACR + RCC_PLL2FRACR + RCC PLL2 fractional divider register + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLL2FRACN + fractional part of the multiplication factor for PLL2 VCO + + 3 + 13 + read-write + + + + + RCC_PLL3DIVR + RCC_PLL3DIVR + RCC PLL3 dividers register + 0x044 + 0x20 + read-write + 0x01010280 + 0xFFFFFFFF + + + PLL3N + Multiplication factor for PLL3VCO + + 0 + 9 + read-write + + + B_0x003 + PLL3N = 4 + 0x003 + + + B_0x004 + PLL3N = 5 + 0x004 + + + B_0x005 + PLL3N = 6 + 0x005 + + + B_0x080 + PLL3N = 129 (default after reset) + 0x080 + + + B_0x1FF + PLL3N = 512 + 0x1FF + + + + + PLL3P + PLL3 DIVP division factor + + 9 + 7 + read-write + + + B_0x0 + pll3_p_ck = vco3_ck + 0x0 + + + B_0x1 + pll3_p_ck = vco3_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll3_p_ck = vco3_ck / 3 + 0x2 + + + B_0x3 + pll3_p_ck = vco3_ck / 4 + 0x3 + + + B_0x7F + pll3_p_ck = vco3_ck / 128 + 0x7F + + + + + PLL3Q + PLL3 DIVQ division factor + + 16 + 7 + read-write + + + B_0x0 + pll3_q_ck = vco3_ck + 0x0 + + + B_0x1 + pll3_q_ck = vco3_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll3_q_ck = vco3_ck / 3 + 0x2 + + + B_0x3 + pll3_q_ck = vco3_ck / 4 + 0x3 + + + B_0x7F + pll3_q_ck = vco3_ck / 128 + 0x7F + + + + + PLL3R + PLL3 DIVR division factor + + 24 + 7 + read-write + + + B_0x0 + pll3_r_ck = vco3_ck + 0x0 + + + B_0x1 + pll3_r_ck = vco3_ck / 2 (default after reset) + 0x1 + + + B_0x2 + pll3_r_ck = vco3_ck / 3 + 0x2 + + + B_0x3 + pll3_r_ck = vco3_ck / 4 + 0x3 + + + B_0x7F + pll3_r_ck = vco3_ck / 128 + 0x7F + + + + + + + RCC_PLL3FRACR + RCC_PLL3FRACR + RCC PLL3 fractional divider register + 0x048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLL3FRACN + fractional part of the multiplication factor for PLL3 VCO + + 3 + 13 + read-write + + + + + RCC_CIER + RCC_CIER + RCC clock source interrupt enable register + 0x050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LSIRDYIE + LSI ready interrupt enable + + 0 + 1 + read-write + + + B_0x0 + LSI ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + LSI ready interrupt enabled + 0x1 + + + + + LSERDYIE + LSE ready interrupt enable + + 1 + 1 + read-write + + + B_0x0 + LSE ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + LSE ready interrupt enabled + 0x1 + + + + + CSIRDYIE + CSI ready interrupt enable + + 2 + 1 + read-write + + + B_0x0 + CSI ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + CSI ready interrupt enabled + 0x1 + + + + + HSIRDYIE + HSI ready interrupt enable + + 3 + 1 + read-write + + + B_0x0 + HSI ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + HSI ready interrupt enabled + 0x1 + + + + + HSERDYIE + HSE ready interrupt enable + + 4 + 1 + read-write + + + B_0x0 + HSE ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + HSE ready interrupt enabled + 0x1 + + + + + HSI48RDYIE + HSI48 ready interrupt enable + + 5 + 1 + read-write + + + B_0x0 + HSI48 ready interrupt disabled (default after reset) + 0x0 + + + B_0x1 + HSI48 ready interrupt enabled + 0x1 + + + + + PLL1RDYIE + PLL1 ready interrupt enable + + 6 + 1 + read-write + + + B_0x0 + PLL1 lock interrupt disabled (default after reset) + 0x0 + + + B_0x1 + PLL1 lock interrupt enabled + 0x1 + + + + + PLL2RDYIE + PLL2 ready interrupt enable + + 7 + 1 + read-write + + + B_0x0 + PLL2 lock interrupt disabled (default after reset) + 0x0 + + + B_0x1 + PLL2 lock interrupt enabled + 0x1 + + + + + PLL3RDYIE + PLL3 ready interrupt enable + + 8 + 1 + read-write + + + B_0x0 + PLL3 lock interrupt disabled (default after reset) + 0x0 + + + B_0x1 + PLL3 lock interrupt enabled + 0x1 + + + + + + + RCC_CIFR + RCC_CIFR + RCC clock source interrupt flag register + 0x054 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + LSIRDYF + LSI ready interrupt flag + + 0 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by the LSI (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by the LSI + 0x1 + + + + + LSERDYF + LSE ready interrupt flag + + 1 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by the LSE (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by the LSE + 0x1 + + + + + CSIRDYF + CSI ready interrupt flag + + 2 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by the CSI (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by the CSI + 0x1 + + + + + HSIRDYF + HSI ready interrupt flag + + 3 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by the HSI (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by the HSI + 0x1 + + + + + HSERDYF + HSE ready interrupt flag + + 4 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by the HSE (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by the HSE + 0x1 + + + + + HSI48RDYF + HSI48 ready interrupt flag + + 5 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by the HSI48 oscillator (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by the HSI48 oscillator + 0x1 + + + + + PLL1RDYF + PLL1 ready interrupt flag + + 6 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by PLL1 lock (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by PLL1 lock + 0x1 + + + + + PLL2RDYF + PLL2 ready interrupt flag + + 7 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by PLL2 lock (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by PLL2 lock + 0x1 + + + + + PLL3RDYF + PLL3 ready interrupt flag + + 8 + 1 + read-only + + + B_0x0 + no clock ready interrupt caused by PLL3 lock (default after reset) + 0x0 + + + B_0x1 + clock ready interrupt caused by PLL3 lock + 0x1 + + + + + HSECSSF + HSE clock security system interrupt flag + + 10 + 1 + read-only + + + B_0x0 + no clock security interrupt caused by HSE clock failure (default after reset) + 0x0 + + + B_0x1 + clock security interrupt caused by HSE clock failure + 0x1 + + + + + + + RCC_CICR + RCC_CICR + RCC clock source interrupt clear register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LSIRDYC + LSI ready interrupt clear + + 0 + 1 + read-write + + + B_0x0 + LSIRDYF no effect (default after reset) + 0x0 + + + B_0x1 + LSIRDYF cleared + 0x1 + + + + + LSERDYC + LSE ready interrupt clear + + 1 + 1 + read-write + + + B_0x0 + LSERDYF no effect (default after reset) + 0x0 + + + B_0x1 + LSERDYF cleared + 0x1 + + + + + CSIRDYC + HSI ready interrupt clear + + 2 + 1 + read-write + + + B_0x0 + CSIRDYF no effect (default after reset) + 0x0 + + + B_0x1 + CSIRDYF cleared + 0x1 + + + + + HSIRDYC + HSI ready interrupt clear + + 3 + 1 + read-write + + + B_0x0 + HSIRDYF no effect (default after reset) + 0x0 + + + B_0x1 + HSIRDYF cleared + 0x1 + + + + + HSERDYC + HSE ready interrupt clear + + 4 + 1 + read-write + + + B_0x0 + HSERDYF no effect (default after reset) + 0x0 + + + B_0x1 + HSERDYF cleared + 0x1 + + + + + HSI48RDYC + HSI48 ready interrupt clear + + 5 + 1 + read-write + + + B_0x0 + HSI48RDYF no effect (default after reset) + 0x0 + + + B_0x1 + HSI48RDYF cleared + 0x1 + + + + + PLL1RDYC + PLL1 ready interrupt clear + + 6 + 1 + read-write + + + B_0x0 + PLL1RDYF no effect (default after reset) + 0x0 + + + B_0x1 + PLL1RDYF cleared + 0x1 + + + + + PLL2RDYC + PLL2 ready interrupt clear + + 7 + 1 + read-write + + + B_0x0 + PLL2RDYF no effect (default after reset) + 0x0 + + + B_0x1 + PLL2RDYF cleared + 0x1 + + + + + PLL3RDYC + PLL3 ready interrupt clear + + 8 + 1 + read-write + + + B_0x0 + PLL3RDYF no effect (default after reset) + 0x0 + + + B_0x1 + PLL3RDYF cleared + 0x1 + + + + + HSECSSC + HSE clock security system interrupt clear + + 10 + 1 + read-write + + + B_0x0 + HSECSSF no effect (default after reset) + 0x0 + + + B_0x1 + HSECSSF cleared + 0x1 + + + + + + + RCC_AHB1RSTR + RCC_AHB1RSTR + RCC AHB1 reset register + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + GPDMA1RST + GPDMA1 block reset + + 0 + 1 + read-write + + + B_0x0 + does not reset GPDMA1 block (default after reset) + 0x0 + + + B_0x1 + resets GPDMA1 block + 0x1 + + + + + GPDMA2RST + GPDMA2 block reset + + 1 + 1 + read-write + + + B_0x0 + does not reset GPDMA2 block (default after reset) + 0x0 + + + B_0x1 + resets GPDMA2 block + 0x1 + + + + + CRCRST + CRC block reset Set and reset by software. + 12 + 1 + read-write + + + B_0x0 + does not reset CRC block (default after reset) + 0x0 + + + B_0x1 + resets CRC block + 0x1 + + + + + CORDICRST + CORDIC block reset + + 14 + 1 + read-write + + + B_0x0 + does not reset CORDIC block (default after reset) + 0x0 + + + B_0x1 + resets CORDIC block + 0x1 + + + + + FMACRST + FMAC block reset + + 15 + 1 + read-write + + + B_0x0 + does not reset FMAC block (default after reset) + 0x0 + + + B_0x1 + resets FMAC block + 0x1 + + + + + RAMCFGRST + RAMCFG block reset + + 17 + 1 + read-write + + + B_0x0 + does not reset RAMCFG block (default after reset) + 0x0 + + + B_0x1 + resets RAMCFG block + 0x1 + + + + + ETHRST + ETHRST block reset + + 19 + 1 + read-write + + + B_0x0 + does not reset ETHRST block (default after reset) + 0x0 + + + B_0x1 + resets the ETHRST block + 0x1 + + + + + + + RCC_AHB2RSTR + RCC_AHB2RSTR + RCC AHB2 peripheral reset register + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + GPIOARST + GPIOA block reset + + 0 + 1 + read-write + + + B_0x0 + does not reset the GPIOA block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOA block + 0x1 + + + + + GPIOBRST + GPIOB block reset + + 1 + 1 + read-write + + + B_0x0 + does not reset the GPIOB block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOB block + 0x1 + + + + + GPIOCRST + GPIOC block reset + + 2 + 1 + read-write + + + B_0x0 + does not reset the GPIOC block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOC block + 0x1 + + + + + GPIODRST + GPIOD block reset + + 3 + 1 + read-write + + + B_0x0 + does not reset the GPIOD block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOD block + 0x1 + + + + + GPIOERST + GPIOE block reset + + 4 + 1 + read-write + + + B_0x0 + does not reset the GPIOE block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOE block + 0x1 + + + + + GPIOFRST + GPIOF block reset + + 5 + 1 + read-write + + + B_0x0 + does not reset the GPIOF block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOF block + 0x1 + + + + + GPIOGRST + GPIOG block reset + + 6 + 1 + read-write + + + B_0x0 + does not reset the GPIOG block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOG block + 0x1 + + + + + GPIOHRST + GPIOH block reset + + 7 + 1 + read-write + + + B_0x0 + does not reset the GPIOH block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOH block + 0x1 + + + + + GPIOIRST + GPIOI block reset + + 8 + 1 + read-write + + + B_0x0 + does not reset the GPIOI block (default after reset) + 0x0 + + + B_0x1 + resets the GPIOI block + 0x1 + + + + + ADCRST + ADC1 and 2 blocks reset + + 10 + 1 + read-write + + + B_0x0 + does not reset ADC1 and 2 blocks (default after reset) + 0x0 + + + B_0x1 + resets ADC1 and 2 blocks + 0x1 + + + + + DAC1RST + DAC block reset + + 11 + 1 + read-write + + + B_0x0 + does not reset DAC block (default after reset) + 0x0 + + + B_0x1 + resets DAC block + 0x1 + + + + + DCMI_PSSIRST + digital camera interface block reset (DCMI or PSSI depending which interface is active) + + 12 + 1 + read-write + + + B_0x0 + does not reset the DCMI/PSSI block (default after reset) + 0x0 + + + B_0x1 + resets the DCMI/PSSI block + 0x1 + + + + + AESRST + AES block reset + + 16 + 1 + read-write + + + B_0x0 + does not reset AES block (default after reset) + 0x0 + + + B_0x1 + resets AES block + 0x1 + + + + + HASHRST + HASH block reset + + 17 + 1 + read-write + + + B_0x0 + does not reset HASH block (default after reset) + 0x0 + + + B_0x1 + resets HASH block + 0x1 + + + + + RNGRST + RNG block reset + + 18 + 1 + read-write + + + B_0x0 + does not reset RNG block (default after reset) + 0x0 + + + B_0x1 + resets RNG block + 0x1 + + + + + PKARST + PKA block reset + + 19 + 1 + read-write + + + B_0x0 + does not reset PKA block (default after reset) + 0x0 + + + B_0x1 + resets PKA block + 0x1 + + + + + SAESRST + SAES block reset + + 20 + 1 + read-write + + + B_0x0 + does not reset SAES block (default after reset) + 0x0 + + + B_0x1 + resets SAES block + 0x1 + + + + + + + RCC_AHB4RSTR + RCC_AHB4RSTR + RCC AHB4 peripheral reset register + 0x06C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OTFDEC1RST + OTFDEC1 block reset + + 7 + 1 + read-write + + + B_0x0 + does not reset OTFDEC1 block (default after reset) + 0x0 + + + B_0x1 + resets OTFDEC1 block + 0x1 + + + + + SDMMC1RST + SDMMC1 and SDMMC1 delay blocks reset + + 11 + 1 + read-write + + + B_0x0 + does not reset SDMMC1 and SDMMC1 delay blocks (default after reset) + 0x0 + + + B_0x1 + resets SDMMC1 and SDMMC1 delay blocks + 0x1 + + + + + FMCRST + FMC block reset + + 16 + 1 + read-write + + + B_0x0 + does not reset FMC block (default after reset) + 0x0 + + + B_0x1 + resets FMC block + 0x1 + + + + + OCTOSPI1RST + OCTOSPI1 block reset + + 20 + 1 + read-write + + + B_0x0 + does not reset OCTOSPI1 block (default after reset) + 0x0 + + + B_0x1 + resets OCTOSPI1 block + 0x1 + + + + + + + RCC_APB1LRSTR + RCC_APB1LRSTR + RCC APB1 peripheral low reset register + 0x074 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM2RST + TIM2 block reset + + 0 + 1 + read-write + + + B_0x0 + does not reset the TIM2 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM2 block + 0x1 + + + + + TIM3RST + TIM3 block reset + + 1 + 1 + read-write + + + B_0x0 + does not reset the TIM3 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM3 block + 0x1 + + + + + TIM4RST + TIM4 block reset + + 2 + 1 + read-write + + + B_0x0 + does not reset the TIM4 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM4 block + 0x1 + + + + + TIM5RST + TIM5 block reset + + 3 + 1 + read-write + + + B_0x0 + does not reset the TIM5 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM5 block + 0x1 + + + + + TIM6RST + TIM6 block reset + + 4 + 1 + read-write + + + B_0x0 + does not reset the TIM6 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM6 block + 0x1 + + + + + TIM7RST + TIM7 block reset + + 5 + 1 + read-write + + + B_0x0 + does not reset the TIM7 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM7 block + 0x1 + + + + + TIM12RST + TIM12 block reset + + 6 + 1 + read-write + + + B_0x0 + does not reset the TIM12 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM12 block + 0x1 + + + + + SPI2RST + SPI2 block reset + + 14 + 1 + read-write + + + B_0x0 + does not reset the SPI2 block (default after reset) + 0x0 + + + B_0x1 + resets the SPI2 block + 0x1 + + + + + SPI3RST + SPI3 block reset + + 15 + 1 + read-write + + + B_0x0 + does not reset the SPI3 block (default after reset) + 0x0 + + + B_0x1 + resets the SPI3 block + 0x1 + + + + + USART2RST + USART2 block reset + + 17 + 1 + read-write + + + B_0x0 + does not reset the USART2 block (default after reset) + 0x0 + + + B_0x1 + resets the USART2 block + 0x1 + + + + + USART3RST + USART3 block reset + + 18 + 1 + read-write + + + B_0x0 + does not reset the USART3 block (default after reset) + 0x0 + + + B_0x1 + resets the USART3 block + 0x1 + + + + + UART4RST + UART4 block reset + + 19 + 1 + read-write + + + B_0x0 + does not reset the UART4 block (default after reset) + 0x0 + + + B_0x1 + resets the UART4 block + 0x1 + + + + + UART5RST + UART5 block reset + + 20 + 1 + read-write + + + B_0x0 + does not reset the UART5 block (default after reset) + 0x0 + + + B_0x1 + resets the UART5 block + 0x1 + + + + + I2C1RST + I2C1 block reset + + 21 + 1 + read-write + + + B_0x0 + does not reset the I2C1 block (default after reset) + 0x0 + + + B_0x1 + resets the I2C1 block + 0x1 + + + + + I2C2RST + I2C2 block reset + + 22 + 1 + read-write + + + B_0x0 + does not reset the I2C2 block (default after reset) + 0x0 + + + B_0x1 + resets the I2C2 block + 0x1 + + + + + I3C1RST + I3C1 block reset + + 23 + 1 + read-write + + + B_0x0 + does not reset the I3C1 block (default after reset) + 0x0 + + + B_0x1 + resets the I3C1 block + 0x1 + + + + + CRSRST + CRS block reset + + 24 + 1 + read-write + + + B_0x0 + does not reset the CRS block (default after reset) + 0x0 + + + B_0x1 + resets the CRS block + 0x1 + + + + + USART6RST + USART6 block reset + + 25 + 1 + read-write + + + B_0x0 + does not reset the USART6 block (default after reset) + 0x0 + + + B_0x1 + resets the USART6 block + 0x1 + + + + + USART10RST + USART10 block reset + + 26 + 1 + read-write + + + B_0x0 + does not reset the USART10 block (default after reset) + 0x0 + + + B_0x1 + resets the USART10 block + 0x1 + + + + + USART11RST + USART11 block reset + + 27 + 1 + read-write + + + B_0x0 + does not reset the USART11 block (default after reset) + 0x0 + + + B_0x1 + resets the USART11 block + 0x1 + + + + + CECRST + HDMI-CEC block reset + + 28 + 1 + read-write + + + B_0x0 + does not reset the HDMI-CEC block (default after reset) + 0x0 + + + B_0x1 + resets the HDMI-CEC block + 0x1 + + + + + UART7RST + UART7 block reset + + 30 + 1 + read-write + + + B_0x0 + does not reset the UART7 block (default after reset) + 0x0 + + + B_0x1 + resets the UART7 block + 0x1 + + + + + UART8RST + UART8 block reset + + 31 + 1 + read-write + + + B_0x0 + does not reset the UART8 block (default after reset) + 0x0 + + + B_0x1 + resets the UART8 block + 0x1 + + + + + + + RCC_APB1HRSTR + RCC_APB1HRSTR + RCC APB1 peripheral high reset register + 0x078 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UART9RST + UART9 block reset + + 0 + 1 + read-write + + + B_0x0 + does not reset UART9 block (default after reset) + 0x0 + + + B_0x1 + resets UART9 block + 0x1 + + + + + UART12RST + UART12 block reset + + 1 + 1 + read-write + + + B_0x0 + does not reset the UART12 block (default after reset) + 0x0 + + + B_0x1 + resets the UART12 block + 0x1 + + + + + DTSRST + DTS block reset + + 3 + 1 + read-write + + + B_0x0 + does not reset the DTS block (default after reset) + 0x0 + + + B_0x1 + resets the DTS block + 0x1 + + + + + LPTIM2RST + LPTIM2 block reset + + 5 + 1 + read-write + + + B_0x0 + does not reset the LPTIM2 block (default after reset) + 0x0 + + + B_0x1 + resets the LPTIM2 block + 0x1 + + + + + FDCANRST + FDCAN1 and FDCAN2 blocks reset + + 9 + 1 + read-write + + + B_0x0 + does not reset the FDCAN1 and FDCAN2 blocks (default after reset) + 0x0 + + + B_0x1 + resets the FDCAN1 and FDCAN2 blocks + 0x1 + + + + + UCPD1RST + UCPD1 block reset + + 23 + 1 + read-write + + + B_0x0 + does not reset the UCPD block (default after reset) + 0x0 + + + B_0x1 + resets the UCPD block + 0x1 + + + + + + + RCC_APB2RSTR + RCC_APB2RSTR + RCC APB2 peripheral reset register + 0x07C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM1RST + TIM1 block reset + + 11 + 1 + read-write + + + B_0x0 + does not reset the TIM1 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM1 block + 0x1 + + + + + SPI1RST + SPI1 block reset + + 12 + 1 + read-write + + + B_0x0 + does not reset the SPI1 block (default after reset) + 0x0 + + + B_0x1 + resets the SPI1 block + 0x1 + + + + + TIM8RST + TIM8 block reset + + 13 + 1 + read-write + + + B_0x0 + does not reset the TIM8 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM8 block + 0x1 + + + + + USART1RST + USART1 block reset + + 14 + 1 + read-write + + + B_0x0 + does not reset the USART1 block (default after reset) + 0x0 + + + B_0x1 + resets the USART1 block + 0x1 + + + + + TIM15RST + TIM15 block reset + + 16 + 1 + read-write + + + B_0x0 + does not reset the TIM15 block (default after reset) + 0x0 + + + B_0x1 + resets the TIM15 block + 0x1 + + + + + SPI4RST + SPI4 block reset + + 19 + 1 + read-write + + + B_0x0 + does not reset the SPI4 block (default after reset) + 0x0 + + + B_0x1 + resets the SPI4 block + 0x1 + + + + + SPI6RST + SPI6 block reset + + 20 + 1 + read-write + + + B_0x0 + does not reset the SPI6 block (default after reset) + 0x0 + + + B_0x1 + resets the SPI6 block + 0x1 + + + + + SAI1RST + SAI1 block reset + + 21 + 1 + read-write + + + B_0x0 + does not reset the SAI1 (default after reset) + 0x0 + + + B_0x1 + resets the SAI1 + 0x1 + + + + + SAI2RST + SAI2 block reset + + 22 + 1 + read-write + + + B_0x0 + does not reset the SAI2 block (default after reset) + 0x0 + + + B_0x1 + resets the SAI2 block + 0x1 + + + + + USBRST + USB block reset + + 24 + 1 + read-write + + + B_0x0 + does not reset the USB block (default after reset) + 0x0 + + + B_0x1 + resets the USB block + 0x1 + + + + + + + RCC_APB3RSTR + RCC_APB3RSTR + RCC APB3 peripheral reset register + 0x080 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LPUART1RST + LPUART1 block reset + + 6 + 1 + read-write + + + B_0x0 + does not reset the LPUART1 block (default after reset) + 0x0 + + + B_0x1 + resets the LPUART1 block + 0x1 + + + + + I2C3RST + I2C3 block reset + + 7 + 1 + read-write + + + B_0x0 + does not reset the I2C3 block (default after reset) + 0x0 + + + B_0x1 + resets the I2C3 block + 0x1 + + + + + I3C2RST + I3C2 block reset + + 9 + 1 + read-write + + + B_0x0 + does not reset the I3C2 block (default after reset) + 0x0 + + + B_0x1 + resets the I3C2 block + 0x1 + + + + + LPTIM1RST + LPTIM1 block reset + + 11 + 1 + read-write + + + B_0x0 + does not reset the LPTIM1 block (default after reset) + 0x0 + + + B_0x1 + resets the LPTIM1 block + 0x1 + + + + + LPTIM3RST + LPTIM3 block reset + + 12 + 1 + read-write + + + B_0x0 + does not reset the LPTIM3 block (default after reset) + 0x0 + + + B_0x1 + resets the LPTIM3 block + 0x1 + + + + + LPTIM4RST + LPTIM4 block reset + + 13 + 1 + read-write + + + B_0x0 + does not reset the LPTIM4 block (default after reset) + 0x0 + + + B_0x1 + resets the LPTIM4 block + 0x1 + + + + + LPTIM5RST + LPTIM5 block reset + + 14 + 1 + read-write + + + B_0x0 + does not reset the LPTIM5 block (default after reset) + 0x0 + + + B_0x1 + resets the LPTIM5 block + 0x1 + + + + + LPTIM6RST + LPTIM6 block reset + + 15 + 1 + read-write + + + B_0x0 + does not reset the LPTIM6 block (default after reset) + 0x0 + + + B_0x1 + resets the LPTIM6 block + 0x1 + + + + + VREFRST + VREFBUF block reset + + 20 + 1 + read-write + + + B_0x0 + does not reset the VREFBUF block (default after reset) + 0x0 + + + B_0x1 + resets the VREFBUF block + 0x1 + + + + + + + RCC_AHB1ENR + RCC_AHB1ENR + RCC AHB1 peripherals clock register + 0x088 + 0x20 + read-write + 0xD0000100 + 0xFFFFFFFF + + + GPDMA1EN + GPDMA1 clock enable + + 0 + 1 + read-write + + + B_0x0 + GPDMA1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPDMA1 peripheral clock enabled + 0x1 + + + + + GPDMA2EN + GPDMA2 clock enable + + 1 + 1 + read-write + + + B_0x0 + GPDMA2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPDMA2 peripheral clock enabled + 0x1 + + + + + FLITFEN + Flash interface clock enable + + 8 + 1 + read-write + + + B_0x0 + FLASH interface clock disabled + 0x0 + + + B_0x1 + FLASH interface clock enabled (default after reset) + 0x1 + + + + + CRCEN + CRC clock enable + + 12 + 1 + read-write + + + B_0x0 + CRC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + CRC peripheral clock enabled + 0x1 + + + + + CORDICEN + CORDIC clock enable + + 14 + 1 + read-write + + + B_0x0 + CORDIC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + CORDIC peripheral clock enabled + 0x1 + + + + + FMACEN + FMAC clock enable + + 15 + 1 + read-write + + + B_0x0 + FMAC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + FMAC peripheral clock enabled + 0x1 + + + + + RAMCFGEN + RAMCFG clock enable + + 17 + 1 + read-write + + + B_0x0 + RAMCFG peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + RAMCFG peripheral clock enabled + 0x1 + + + + + ETHEN + ETH clock enable + + 19 + 1 + read-write + + + B_0x0 + ETH peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + ETH peripheral clock enabled + 0x1 + + + + + ETHTXEN + ETHTX clock enable + + 20 + 1 + read-write + + + B_0x0 + ETHTX clock disabled (default after reset) + 0x0 + + + B_0x1 + ETHTX clock enabled + 0x1 + + + + + ETHRXEN + ETHRX clock enable + + 21 + 1 + read-write + + + B_0x0 + ETHRX clock disabled (default after reset) + 0x0 + + + B_0x1 + ETHRX clock enabled + 0x1 + + + + + TZSC1EN + TZSC1 clock enable + + 24 + 1 + read-write + + + B_0x0 + TZSC1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TZSC1 peripheral clock enabled + 0x1 + + + + + BKPRAMEN + BKPRAM clock enable + + 28 + 1 + read-write + + + B_0x0 + BKPRAM peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + BKPRAM peripheral clock enabled + 0x1 + + + + + DCACHEEN + DCACHE clock enable + + 30 + 1 + read-write + + + B_0x0 + DCACHE peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + DCACHE peripheral clock enabled + 0x1 + + + + + SRAM1EN + SRAM1 clock enable + + 31 + 1 + read-write + + + B_0x0 + SRAM1 clock disabled + 0x0 + + + B_0x1 + SRAM1 clock enabled (default after reset) + 0x1 + + + + + + + RCC_AHB2ENR + RCC_AHB2ENR + RCC AHB2 peripheral clock register + 0x08C + 0x20 + read-write + 0xC0000000 + 0xFFFFFFFF + + + GPIOAEN + GPIOA clock enable + + 0 + 1 + read-write + + + B_0x0 + GPIOA peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOA peripheral clock enabled + 0x1 + + + + + GPIOBEN + GPIOB clock enable + + 1 + 1 + read-write + + + B_0x0 + GPIOB peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOB peripheral clock enabled + 0x1 + + + + + GPIOCEN + GPIOC clock enable + + 2 + 1 + read-write + + + B_0x0 + GPIOC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOC peripheral clock enabled + 0x1 + + + + + GPIODEN + GPIOD clock enable + + 3 + 1 + read-write + + + B_0x0 + GPIOD peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOD peripheral clock enabled + 0x1 + + + + + GPIOEEN + GPIOE clock enable + + 4 + 1 + read-write + + + B_0x0 + GPIOE peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOE peripheral clock enabled + 0x1 + + + + + GPIOFEN + GPIOF clock enable + + 5 + 1 + read-write + + + B_0x0 + GPIOF peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOF peripheral clock enabled + 0x1 + + + + + GPIOGEN + GPIOG clock enable + + 6 + 1 + read-write + + + B_0x0 + GPIOG peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOG peripheral clock enabled + 0x1 + + + + + GPIOHEN + GPIOH clock enable + + 7 + 1 + read-write + + + B_0x0 + GPIOH peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOH peripheral clock enabled + 0x1 + + + + + GPIOIEN + GPIOI clock enable + + 8 + 1 + read-write + + + B_0x0 + GPIOI peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + GPIOI peripheral clock enabled + 0x1 + + + + + ADCEN + ADC1 and 2 peripherals clock enable + + 10 + 1 + read-write + + + B_0x0 + ADC1 and 2 peripherals clock disabled (default after reset) + 0x0 + + + B_0x1 + ADC1 and 2 peripherals clock enabled + 0x1 + + + + + DAC1EN + DAC clock enable + + 11 + 1 + read-write + + + B_0x0 + DAC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + DAC peripheral clock enabled + 0x1 + + + + + DCMI_PSSIEN + digital camera interface clock enable (DCMI or PSSI depending which interface is active) + + 12 + 1 + read-write + + + B_0x0 + DCMI/PSSI peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + DCMI/PSSI peripheral clock enabled + 0x1 + + + + + AESEN + AES clock enable + + 16 + 1 + read-write + + + B_0x0 + AES peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + AES peripheral clock enabled + 0x1 + + + + + HASHEN + HASH clock enable + + 17 + 1 + read-write + + + B_0x0 + HASH peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + HASH peripheral clock enabled + 0x1 + + + + + RNGEN + RNG clock enable + + 18 + 1 + read-write + + + B_0x0 + RNG peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + RNG peripheral clock enabled + 0x1 + + + + + PKAEN + PKA clock enable + + 19 + 1 + read-write + + + B_0x0 + PKA peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + PKA peripheral clock enabled + 0x1 + + + + + SAESEN + SAES clock enable + + 20 + 1 + read-write + + + B_0x0 + SAES peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SAES peripheral clock enabled + 0x1 + + + + + SRAM2EN + SRAM2 clock enable + + 30 + 1 + read-write + + + B_0x0 + SRAM2 clock disabled + 0x0 + + + B_0x1 + SRAM2 clock enabled (default after reset) + 0x1 + + + + + SRAM3EN + SRAM3 clock enable + + 31 + 1 + read-write + + + B_0x0 + SRAM3 clock disabled + 0x0 + + + B_0x1 + SRAM3 clock enabled (default after reset) + 0x1 + + + + + + + RCC_AHB4ENR + RCC_AHB4ENR + RCC AHB4 peripheral clock register + 0x094 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OTFDEC1EN + OTFDEC1 clock enable + + 7 + 1 + read-write + + + B_0x0 + OTFDEC1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + OTFDEC1 peripheral clock enabled + 0x1 + + + + + SDMMC1EN + SDMMC1 and SDMMC1 delay peripheral clock enable reset + 11 + 1 + read-write + + + B_0x0 + SDMMC1 and SDMMC1 delay peripherals clock disabled (default after reset) + 0x0 + + + B_0x1 + SDMMC1 and SDMMC1 delay peripherals clock enabled + 0x1 + + + + + FMCEN + FMC clock enable + + 16 + 1 + read-write + + + B_0x0 + FMC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + FMC peripheral clock enabled + 0x1 + + + + + OCTOSPI1EN + OCTOSPI1 clock enable + + 20 + 1 + read-write + + + B_0x0 + OCTOSPI1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + OCTOSPI1 peripheral clock enabled + 0x1 + + + + + + + RCC_APB1LENR + RCC_APB1LENR + RCC APB1 peripheral clock register + 0x09C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM2EN + TIM2 clock enable + + 0 + 1 + read-write + + + B_0x0 + TIM2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM2 peripheral clock enabled + 0x1 + + + + + TIM3EN + TIM3 clock enable + + 1 + 1 + read-write + + + B_0x0 + TIM3 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM3 peripheral clock enabled + 0x1 + + + + + TIM4EN + TIM4 clock enable + + 2 + 1 + read-write + + + B_0x0 + TIM4 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM4 peripheral clock enabled + 0x1 + + + + + TIM5EN + TIM5 clock enable + + 3 + 1 + read-write + + + B_0x0 + TIM5 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM5 peripheral clock enabled + 0x1 + + + + + TIM6EN + TIM6 clock enable + + 4 + 1 + read-write + + + B_0x0 + TIM6 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM6 peripheral clock enabled + 0x1 + + + + + TIM7EN + TIM7 clock enable + + 5 + 1 + read-write + + + B_0x0 + TIM7 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM7 peripheral clock enabled + 0x1 + + + + + TIM12EN + TIM12 clock enable + + 6 + 1 + read-write + + + B_0x0 + TIM12 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM12 peripheral clock enabled + 0x1 + + + + + WWDGEN + WWDG clock enable + + 11 + 1 + read-write + + + B_0x0 + WWDG peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + WWDG peripheral clock enabled + 0x1 + + + + + SPI2EN + SPI2 clock enable + + 14 + 1 + read-write + + + B_0x0 + SPI2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SPI2 peripheral clock enabled + 0x1 + + + + + SPI3EN + SPI3 clock enable + + 15 + 1 + read-write + + + B_0x0 + SPI3 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SPI3 peripheral clock enabled + 0x1 + + + + + USART2EN + USART2 clock enable + + 17 + 1 + read-write + + + B_0x0 + USART2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USART2 peripheral clock enabled + 0x1 + + + + + USART3EN + USART3 clock enable + + 18 + 1 + read-write + + + B_0x0 + USART3 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USART3 peripheral clock enabled + 0x1 + + + + + UART4EN + UART4 clock enable + + 19 + 1 + read-write + + + B_0x0 + UART4 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + UART4 peripheral clock enabled + 0x1 + + + + + UART5EN + UART5 clock enable + + 20 + 1 + read-write + + + B_0x0 + UART5 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + UART5 peripheral clock enabled + 0x1 + + + + + I2C1EN + I2C1 clock enable + + 21 + 1 + read-write + + + B_0x0 + I2C1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + I2C1 peripheral clock enabled + 0x1 + + + + + I2C2EN + I2C2 clock enable + + 22 + 1 + read-write + + + B_0x0 + I2C2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + I2C2 peripheral clock enabled + 0x1 + + + + + I3C1EN + I3C1 clock enable + + 23 + 1 + read-write + + + B_0x0 + I3C1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + I3C1 peripheral clock enabled + 0x1 + + + + + CRSEN + CRS clock enable + + 24 + 1 + read-write + + + B_0x0 + CRS peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + CRS peripheral clock enabled + 0x1 + + + + + USART6EN + USART6 clock enable + + 25 + 1 + read-write + + + B_0x0 + USART6 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USART6 peripheral clock enabled + 0x1 + + + + + USART10EN + USART10 clock enable + + 26 + 1 + read-write + + + B_0x0 + USART10 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USART10 peripheral clock enabled + 0x1 + + + + + USART11EN + USART11 clock enable + + 27 + 1 + read-write + + + B_0x0 + USART11 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USART11 peripheral clock enabled + 0x1 + + + + + CECEN + HDMI-CEC clock enable + + 28 + 1 + read-write + + + B_0x0 + HDMI-CEC peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + HDMI-CEC peripheral clock enabled + 0x1 + + + + + UART7EN + UART7 clock enable + + 30 + 1 + read-write + + + B_0x0 + UART7 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + UART7 peripheral clock enabled + 0x1 + + + + + UART8EN + UART8 clock enable + + 31 + 1 + read-write + + + B_0x0 + UART8 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + UART8 peripheral clock enabled + 0x1 + + + + + + + RCC_APB1HENR + RCC_APB1HENR + RCC APB1 peripheral clock register + 0x0A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UART9EN + UART9 clock enable + + 0 + 1 + read-write + + + B_0x0 + UART9 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + resets UART9 peripheral clock enabled + 0x1 + + + + + UART12EN + UART12 clock enable + + 1 + 1 + read-write + + + B_0x0 + UART12 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + UART12 peripheral clock enabled + 0x1 + + + + + DTSEN + DTS clock enable + + 3 + 1 + read-write + + + B_0x0 + DTS peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + DTS peripheral clock enabled + 0x1 + + + + + LPTIM2EN + LPTIM2 clock enable + + 5 + 1 + read-write + + + B_0x0 + LPTIM2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPTIM2 peripheral clock enabled + 0x1 + + + + + FDCANEN + FDCAN1 and FDCAN2 peripheral clock enable + + 9 + 1 + read-write + + + B_0x0 + FDCAN1 and FDCAN2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + FDCAN1 and FDCAN2 peripheral clock enabled + 0x1 + + + + + UCPD1EN + UCPD1 clock enable + + 23 + 1 + read-write + + + B_0x0 + UCPD peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + UCPD peripheral clock enabled + 0x1 + + + + + + + RCC_APB2ENR + RCC_APB2ENR + RCC APB2 peripheral clock register + 0x0A4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM1EN + TIM1 clock enable + + 11 + 1 + read-write + + + B_0x0 + TIM1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM1 peripheral clock enabled + 0x1 + + + + + SPI1EN + SPI1 clock enable + + 12 + 1 + read-write + + + B_0x0 + SPI1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SPI1 peripheral clock enabled + 0x1 + + + + + TIM8EN + TIM8 clock enable + + 13 + 1 + read-write + + + B_0x0 + TIM8 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM8 peripheral clock enabled + 0x1 + + + + + USART1EN + USART1 clock enable + + 14 + 1 + read-write + + + B_0x0 + USART1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USART1 peripheral clock enabled + 0x1 + + + + + TIM15EN + TIM15 clock enable + + 16 + 1 + read-write + + + B_0x0 + TIM15 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + TIM15 peripheral clock enabled + 0x1 + + + + + SPI4EN + SPI4 clock enable + + 19 + 1 + read-write + + + B_0x0 + SPI4 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SPI4 peripheral clock enabled + 0x1 + + + + + SPI6EN + SPI6 clock enable + + 20 + 1 + read-write + + + B_0x0 + SPI6 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SPI6 peripheral clock enabled + 0x1 + + + + + SAI1EN + SAI1 clock enable + + 21 + 1 + read-write + + + B_0x0 + SAI1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SAI1 peripheral clock enabled + 0x1 + + + + + SAI2EN + SAI2 clock enable + + 22 + 1 + read-write + + + B_0x0 + SAI2 clock disabled + 0x0 + + + B_0x1 + SAI2 clock enabled + 0x1 + + + + + USBEN + USB clock enable + + 24 + 1 + read-write + + + B_0x0 + USB peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + USB peripheral clock enabled + 0x1 + + + + + + + RCC_APB3ENR + RCC_APB3ENR + RCC APB3 peripheral clock register + 0x0A8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SBSEN + SBS clock enable + + 1 + 1 + read-write + + + B_0x0 + SBS peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + SBS peripheral clock enabled + 0x1 + + + + + LPUART1EN + LPUART1 clock enable + + 6 + 1 + read-write + + + B_0x0 + LPUART1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPUART1 peripheral clock enabled + 0x1 + + + + + I2C3EN + I2C3 clock enable + + 7 + 1 + read-write + + + B_0x0 + I2C3 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + I2C3 peripheral clock enabled + 0x1 + + + + + I3C2EN + I3C2 clock enable + + 9 + 1 + read-write + + + B_0x0 + I3C2 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + I3C2 peripheral clock enabled + 0x1 + + + + + LPTIM1EN + LPTIM1 clock enable + + 11 + 1 + read-write + + + B_0x0 + LPTIM1 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPTIM1 peripheral clock enabled + 0x1 + + + + + LPTIM3EN + LPTIM3 clock enable + + 12 + 1 + read-write + + + B_0x0 + LPTIM3 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPTIM3 peripheral clock enabled + 0x1 + + + + + LPTIM4EN + LPTIM4 clock enable + + 13 + 1 + read-write + + + B_0x0 + LPTIM4 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPTIM4 peripheral clock enabled + 0x1 + + + + + LPTIM5EN + LPTIM5 clock enable + + 14 + 1 + read-write + + + B_0x0 + LPTIM5 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPTIM5 peripheral clock enabled + 0x1 + + + + + LPTIM6EN + LPTIM6 clock enable + + 15 + 1 + read-write + + + B_0x0 + LPTIM6 peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + LPTIM6 peripheral clock enabled + 0x1 + + + + + VREFBUFEN + VREFBUF clock enable + + 20 + 1 + read-write + + + B_0x0 + VREFBUF peripheral clock disabled (default after reset) + 0x0 + + + B_0x1 + VREFBUF peripheral clock enabled + 0x1 + + + + + RTCAPBEN + RTC APB interface clock enable + + 21 + 1 + read-write + + + B_0x0 + RTC APB interface clock disabled (default after reset) + 0x0 + + + B_0x1 + RTC APB interface clock enabled + 0x1 + + + + + + + RCC_AHB1LPENR + RCC_AHB1LPENR + RCC AHB1 sleep clock register + 0x0B0 + 0x20 + read-write + 0xF1021103 + 0xFFFFFFFF + + + GPDMA1LPEN + GPDMA1 clock enable during Sleep mode + + 0 + 1 + read-write + + + B_0x0 + GPDMA1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPDMA1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPDMA2LPEN + GPDMA2 clock enable during Sleep mode + + 1 + 1 + read-write + + + B_0x0 + GPDMA2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPDMA2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + FLITFLPEN + Flash interface (FLITF) clock enable during Sleep mode + + 8 + 1 + read-write + + + B_0x0 + FLITF peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + FLITF peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + CRCLPEN + CRC clock enable during Sleep mode + + 12 + 1 + read-write + + + B_0x0 + CRC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + CRC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + CORDICLPEN + CORDIC clock enable during Sleep mode + + 14 + 1 + read-write + + + B_0x0 + CORDIC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + CORDIC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + FMACLPEN + FMAC clock enable during Sleep mode + + 15 + 1 + read-write + + + B_0x0 + FMAC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + FMAC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + RAMCFGLPEN + RAMCFG clock enable during Sleep mode + + 17 + 1 + read-write + + + B_0x0 + RAMCFG peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + RAMCFG peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + ETHLPEN + ETH clock enable during Sleep mode + + 19 + 1 + read-write + + + B_0x0 + ETH peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + ETH peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + ETHTXLPEN + ETHTX clock enable during Sleep mode + + 20 + 1 + read-write + + + B_0x0 + ETHTX clock disabled during Sleep mode + 0x0 + + + B_0x1 + ETHTX clock enabled during Sleep mode (default after reset) + 0x1 + + + + + ETHRXLPEN + ETHRX clock enable during Sleep mode + + 21 + 1 + read-write + + + B_0x0 + ETHRX clock disabled during Sleep mode + 0x0 + + + B_0x1 + ETHRX clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TZSC1LPEN + TZSC1 clock enable during Sleep mode + + 24 + 1 + read-write + + + B_0x0 + TZSC1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TZSC1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + BKPRAMLPEN + BKPRAM clock enable during Sleep mode + + 28 + 1 + read-write + + + B_0x0 + BKPRAM peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + BKPRAM peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + ICACHELPEN + ICACHE clock enable during Sleep mode + + 29 + 1 + read-write + + + B_0x0 + ICACHE peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + ICACHE peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + DCACHELPEN + DCACHE clock enable during Sleep mode + + 30 + 1 + read-write + + + B_0x0 + DCACHE peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + DCACHE peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SRAM1LPEN + SRAM1 clock enable during Sleep mode + + 31 + 1 + read-write + + + B_0x0 + SRAM1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SRAM1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_AHB2LPENR + RCC_AHB2LPENR + RCC AHB2 sleep clock register + 0x0B4 + 0x20 + read-write + 0xC01F1CFF + 0xFFFFFFFF + + + GPIOALPEN + GPIOA clock enable during Sleep mode + + 0 + 1 + read-write + + + B_0x0 + GPIOA peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOA peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOBLPEN + GPIOB clock enable during Sleep mode + + 1 + 1 + read-write + + + B_0x0 + GPIOB peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOB peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOCLPEN + GPIOC clock enable during Sleep mode + + 2 + 1 + read-write + + + B_0x0 + GPIOC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIODLPEN + GPIOD clock enable during Sleep mode + + 3 + 1 + read-write + + + B_0x0 + GPIOD peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOD peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOELPEN + GPIOE clock enable during Sleep mode + + 4 + 1 + read-write + + + B_0x0 + GPIOE peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOE peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOFLPEN + GPIOF clock enable during Sleep mode + + 5 + 1 + read-write + + + B_0x0 + GPIOF peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOF peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOGLPEN + GPIOG clock enable during Sleep mode + + 6 + 1 + read-write + + + B_0x0 + GPIOG peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOG peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOHLPEN + GPIOH clock enable during Sleep mode + + 7 + 1 + read-write + + + B_0x0 + GPIOH peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOH peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + GPIOILPEN + GPIOI clock enable during Sleep mode + + 8 + 1 + read-write + + + B_0x0 + GPIOI peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + GPIOI peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + ADCLPEN + ADC1 and 2 peripherals clock enable during Sleep mode + + 10 + 1 + read-write + + + B_0x0 + ADC1 and 2 peripherals clock disabled during Sleep mode + 0x0 + + + B_0x1 + ADC1 and 2 peripherals clock enabled during Sleep mode (default after reset) + 0x1 + + + + + DAC1LPEN + DAC clock enable during Sleep mode + + 11 + 1 + read-write + + + B_0x0 + DAC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + DAC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + DCMI_PSSILPEN + digital camera interface clock enable during Sleep mode (DCMI or PSSI depending which interface is active) + + 12 + 1 + read-write + + + B_0x0 + DCMI/PSSI peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + DCMI/PSSI peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + AESLPEN + AES clock enable during Sleep mode + + 16 + 1 + read-write + + + B_0x0 + AES peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + AES peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + HASHLPEN + HASH clock enable during Sleep mode + + 17 + 1 + read-write + + + B_0x0 + HASH peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + HASH peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + RNGLPEN + RNG clock enable during Sleep mode + + 18 + 1 + read-write + + + B_0x0 + RNG peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + RNG peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + PKALPEN + PKA clock enable during Sleep mode + + 19 + 1 + read-write + + + B_0x0 + PKA peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + PKA peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SAESLPEN + SAES clock enable during Sleep mode + + 20 + 1 + read-write + + + B_0x0 + SAES peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SAES peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SRAM2LPEN + SRAM2 clock enable during Sleep mode + + 30 + 1 + read-write + + + B_0x0 + SRAM2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SRAM2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SRAM3LPEN + SRAM3 clock enable during Sleep mode + + 31 + 1 + read-write + + + B_0x0 + SRAM3 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SRAM3 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_AHB4LPENR + RCC_AHB4LPENR + RCC AHB4 sleep clock register + 0x0BC + 0x20 + read-write + 0x00110880 + 0xFFFFFFFF + + + OTFDEC1LPEN + OTFDEC1 clock enable during Sleep mode + + 7 + 1 + read-write + + + B_0x0 + OTFDEC1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + OTFDEC1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SDMMC1LPEN + SDMMC1 and SDMMC1 delay peripheral clock enable during Sleep mode + + 11 + 1 + read-write + + + B_0x0 + SDMMC1 and SDMMC1 delay peripherals clock disabled during Sleep mode + 0x0 + + + B_0x1 + SDMMC1 and SDMMC1 delay peripherals clock enabled during Sleep mode (default after reset) + 0x1 + + + + + FMCLPEN + FMC clock enable during Sleep mode + + 16 + 1 + read-write + + + B_0x0 + FMC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + FMC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + OCTOSPI1LPEN + OCTOSPI1 clock enable during Sleep mode + + 20 + 1 + read-write + + + B_0x0 + OCTOSPI1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + OCTOSPI1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_APB1LLPENR + RCC_APB1LLPENR + RCC APB1 sleep clock register + 0x0C4 + 0x20 + read-write + 0x13FEC87F + 0xFFFFFFFF + + + TIM2LPEN + TIM2 clock enable during Sleep mode + + 0 + 1 + read-write + + + B_0x0 + TIM2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM3LPEN + TIM3 clock enable during Sleep mode + + 1 + 1 + read-write + + + B_0x0 + TIM3 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM3 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM4LPEN + TIM4 clock enable during Sleep mode + + 2 + 1 + read-write + + + B_0x0 + TIM4 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM4 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM5LPEN + TIM5 clock enable during Sleep mode + + 3 + 1 + read-write + + + B_0x0 + TIM5 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM5 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM6LPEN + TIM6 clock enable during Sleep mode + + 4 + 1 + read-write + + + B_0x0 + TIM6 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM6 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM7LPEN + TIM7 clock enable during Sleep mode + + 5 + 1 + read-write + + + B_0x0 + TIM7 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM7 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM12LPEN + TIM12 clock enable during Sleep mode + + 6 + 1 + read-write + + + B_0x0 + TIM12 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM12 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + WWDGLPEN + WWDG clock enable during Sleep mode + + 11 + 1 + read-write + + + B_0x0 + WWDG peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + WWDG peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SPI2LPEN + SPI2 clock enable during Sleep mode + + 14 + 1 + read-write + + + B_0x0 + SPI2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SPI2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SPI3LPEN + SPI3 clock enable during Sleep mode + + 15 + 1 + read-write + + + B_0x0 + SPI3 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SPI3 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USART2LPEN + USART2 clock enable during Sleep mode + + 17 + 1 + read-write + + + B_0x0 + USART2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USART2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USART3LPEN + USART3 clock enable during Sleep mode + + 18 + 1 + read-write + + + B_0x0 + USART3 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USART3 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + UART4LPEN + UART4 clock enable during Sleep mode + + 19 + 1 + read-write + + + B_0x0 + UART4 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + UART4 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + UART5LPEN + UART5 clock enable during Sleep mode + + 20 + 1 + read-write + + + B_0x0 + UART5 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + UART5 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + I2C1LPEN + I2C1 clock enable during Sleep mode + + 21 + 1 + read-write + + + B_0x0 + I2C1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + I2C1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + I2C2LPEN + I2C2 clock enable during Sleep mode + + 22 + 1 + read-write + + + B_0x0 + I2C2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + I2C2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + I3C1LPEN + I3C1 clock enable during Sleep mode + + 23 + 1 + read-write + + + B_0x0 + I3C1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + I3C1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + CRSLPEN + CRS clock enable during Sleep mode + + 24 + 1 + read-write + + + B_0x0 + CRS peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + CRS peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USART6LPEN + USART6 clock enable during Sleep mode + + 25 + 1 + read-write + + + B_0x0 + USART6 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USART6 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USART10LPEN + USART10 clock enable during Sleep mode + + 26 + 1 + read-write + + + B_0x0 + USART10 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USART10 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USART11LPEN + USART11 clock enable during Sleep mode + + 27 + 1 + read-write + + + B_0x0 + USART11 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USART11 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + CECLPEN + HDMI-CEC clock enable during Sleep mode + + 28 + 1 + read-write + + + B_0x0 + HDMI-CEC peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + HDMI-CEC peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + UART7LPEN + UART7 clock enable during Sleep mode + + 30 + 1 + read-write + + + B_0x0 + UART7 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + UART7 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + UART8LPEN + UART8 clock enable during Sleep mode + + 31 + 1 + read-write + + + B_0x0 + UART8 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + UART8 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_APB1HLPENR + RCC_APB1HLPENR + RCC APB1 sleep clock register + 0x0C8 + 0x20 + read-write + 0x40800228 + 0xFFFFFFFF + + + UART9LPEN + UART9 clock enable during Sleep mode + + 0 + 1 + read-write + + + B_0x0 + UART9 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + resets UART9 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + UART12LPEN + UART12 clock enable during Sleep mode + + 1 + 1 + read-write + + + B_0x0 + UART12 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + UART12 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + DTSLPEN + DTS clock enable during Sleep mode + + 3 + 1 + read-write + + + B_0x0 + DTS peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + DTS peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPTIM2LPEN + LPTIM2 clock enable during Sleep mode + + 5 + 1 + read-write + + + B_0x0 + LPTIM2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPTIM2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + FDCANLPEN + FDCAN1 and FDCAN2 peripheral clock enable during Sleep mode + + 9 + 1 + read-write + + + B_0x0 + FDCAN1 and FDCAN2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + FDCAN1 and FDCAN2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + UCPD1LPEN + UCPD1 clock enable during Sleep mode + + 23 + 1 + read-write + + + B_0x0 + UCPD peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + UCPD peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_APB2LPENR + RCC_APB2LPENR + RCC APB2 sleep clock register + 0x0CC + 0x20 + read-write + 0x01097800 + 0xFFFFFFFF + + + TIM1LPEN + TIM1 clock enable during Sleep mode + + 11 + 1 + read-write + + + B_0x0 + TIM1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SPI1LPEN + SPI1 clock enable during Sleep mode + + 12 + 1 + read-write + + + B_0x0 + SPI1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SPI1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM8LPEN + TIM8 clock enable during Sleep mode + + 13 + 1 + read-write + + + B_0x0 + TIM8 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM8 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USART1LPEN + USART1 clock enable during Sleep mode + + 14 + 1 + read-write + + + B_0x0 + USART1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USART1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + TIM15LPEN + TIM15 clock enable during Sleep mode + + 16 + 1 + read-write + + + B_0x0 + TIM15 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + TIM15 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SPI4LPEN + SPI4 clock enable during Sleep mode + + 19 + 1 + read-write + + + B_0x0 + SPI4 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SPI4 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SPI6LPEN + SPI6 clock enable during Sleep mode + + 20 + 1 + read-write + + + B_0x0 + SPI6 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SPI6 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SAI1LPEN + SAI1 clock enable during Sleep mode + + 21 + 1 + read-write + + + B_0x0 + SAI1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SAI1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + SAI2LPEN + SAI2 clock enable during Sleep mode + + 22 + 1 + read-write + + + B_0x0 + SAI2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SAI2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + USBLPEN + USB clock enable during Sleep mode + + 24 + 1 + read-write + + + B_0x0 + USB peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + USB peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_APB3LPENR + RCC_APB3LPENR + RCC APB3 sleep clock register + 0x0D0 + 0x20 + read-write + 0x0030FAE2 + 0xFFFFFFFF + + + SBSLPEN + SBS clock enable during Sleep mode + + 1 + 1 + read-write + + + B_0x0 + SBS peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + SBS peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPUART1LPEN + LPUART1 clock enable during Sleep mode + + 6 + 1 + read-write + + + B_0x0 + LPUART1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPUART1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + I2C3LPEN + I2C3 clock enable during Sleep mode + + 7 + 1 + read-write + + + B_0x0 + I2C3 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + I2C3 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + I3C2LPEN + I3C2 clock enable during Sleep mode + + 9 + 1 + read-write + + + B_0x0 + I3C2 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + I3C2 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPTIM1LPEN + LPTIM1 clock enable during Sleep mode + + 11 + 1 + read-write + + + B_0x0 + LPTIM1 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPTIM1 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPTIM3LPEN + LPTIM3 clock enable during Sleep mode + + 12 + 1 + read-write + + + B_0x0 + LPTIM3 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPTIM3 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPTIM4LPEN + LPTIM4 clock enable during Sleep mode + + 13 + 1 + read-write + + + B_0x0 + LPTIM4 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPTIM4 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPTIM5LPEN + LPTIM5 clock enable during Sleep mode + + 14 + 1 + read-write + + + B_0x0 + LPTIM5 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPTIM5 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + LPTIM6LPEN + LPTIM6 clock enable during Sleep mode + + 15 + 1 + read-write + + + B_0x0 + LPTIM6 peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + LPTIM6 peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + VREFLPEN + VREFBUF clock enable during Sleep mode + + 20 + 1 + read-write + + + B_0x0 + VREFBUF peripheral clock disabled during Sleep mode + 0x0 + + + B_0x1 + VREFBUF peripheral clock enabled during Sleep mode (default after reset) + 0x1 + + + + + RTCAPBLPEN + RTC APB interface clock enable during Sleep mode + + 21 + 1 + read-write + + + B_0x0 + RTC APB interface clock disabled during Sleep mode + 0x0 + + + B_0x1 + RTC APB interface clock enabled during Sleep mode (default after reset) + 0x1 + + + + + + + RCC_CCIPR1 + RCC_CCIPR1 + RCC kernel clock configuration register + 0x0D8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + USART1SEL + USART1 kernel clock source selection + + 0 + 3 + read-write + + + B_0x0 + rcc_pclk2 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + USART2SEL + USART2 kernel clock source selection + + 3 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + USART3SEL + USART3 kernel clock source selection + + 6 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + UART4SEL + UART4 kernel clock source selection + + 9 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + UART5SEL + UART5 kernel clock source selection + + 12 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + USART6SEL + USART6 kernel clock source selection + + 15 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + UART7SEL + UART7 kernel clock source selection + + 18 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + UART8SEL + UART8 kernel clock source selection + + 21 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + UART9SEL + UART9 kernel clock source selection + + 24 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + USART10SEL + USART10 kernel clock source selection + + 27 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + TIMICSEL + TIM12, TIM15 and LPTIM2 input capture source selection + + 31 + 1 + read-write + + + B_0x0 + No internal clock available for timers input capture (default after reset) + 0x0 + + + B_0x1 + hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture + 0x1 + + + + + + + RCC_CCIPR2 + RCC_CCIPR2 + RCC kernel clock configuration register + 0x0DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + USART11SEL + USART11 kernel clock source selection + + 0 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + UART12SEL + UART12 kernel clock source selection + + 4 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + LPTIM1SEL + LPTIM1 kernel clock source selection + + 8 + 3 + read-write + + + B_0x0 + rcc_pclk3 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_r_ck selected as kernel clock + 0x2 + + + B_0x3 + lse_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + lsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + per_ck selected as kernel clock + 0x5 + + + + + LPTIM2SEL + LPTIM2 kernel clock source selection + + 12 + 3 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_r_ck selected as kernel clock + 0x2 + + + B_0x3 + lse_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + lsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + per_ck selected as kernel clock + 0x5 + + + + + LPTIM3SEL + LPTIM3 kernel clock source selection + + 16 + 3 + read-write + + + B_0x0 + rcc_pclk3 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_r_ck selected as kernel clock + 0x2 + + + B_0x3 + lse_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + lsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + per_ck selected as kernel clock + 0x5 + + + + + LPTIM4SEL + LPTIM4 kernel clock source selection + + 20 + 3 + read-write + + + B_0x0 + rcc_pclk3 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_r_ck selected as kernel clock + 0x2 + + + B_0x3 + lse_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + lsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + per_ck selected as kernel clock + 0x5 + + + + + LPTIM5SEL + LPTIM5 kernel clock source selection + + 24 + 3 + read-write + + + B_0x0 + rcc_pclk3 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_r_ck selected as kernel clock + 0x2 + + + B_0x3 + lse_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + lsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + per_ck selected as kernel clock + 0x5 + + + + + LPTIM6SEL + LPTIM6 kernel clock source selection + + 28 + 3 + read-write + + + B_0x0 + rcc_pclk3 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_r_ck selected as kernel clock + 0x2 + + + B_0x3 + lse_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + lsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + per_ck selected as kernel clock + 0x5 + + + + + + + RCC_CCIPR3 + RCC_CCIPR3 + RCC kernel clock configuration register + 0x0E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPI1SEL + SPI1 kernel clock source selection + + 0 + 3 + read-write + + + B_0x0 + pll1_q_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_p_ck selected as kernel clock + 0x2 + + + B_0x3 + AUDIOCLK selected as kernel clock + 0x3 + + + B_0x4 + per_ck selected as kernel clock + 0x4 + + + + + SPI2SEL + SPI2 kernel clock source selection + + 3 + 3 + read-write + + + B_0x0 + pll1_q_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_p_ck selected as kernel clock + 0x2 + + + B_0x3 + AUDIOCLK selected as kernel clock + 0x3 + + + B_0x4 + per_ck selected as kernel clock + 0x4 + + + + + SPI3SEL + SPI3 kernel clock source selection + + 6 + 3 + read-write + + + B_0x0 + pll1_q_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_p_ck selected as kernel clock + 0x2 + + + B_0x3 + AUDIOCLK selected as kernel clock + 0x3 + + + B_0x4 + per_ck selected as kernel clock + 0x4 + + + + + SPI4SEL + SPI4 kernel clock source selection + + 9 + 3 + read-write + + + B_0x0 + rcc_pclk2 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + hse_ck selected as kernel clock + 0x5 + + + + + SPI6SEL + SPI6 kernel clock source selection + + 15 + 3 + read-write + + + B_0x0 + rcc_pclk2 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + hse_ck selected as kernel clock + 0x5 + + + + + LPUART1SEL + LPUART1 kernel clock source selection + + 24 + 3 + read-write + + + B_0x0 + rcc_pclk3 s elected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi_ker_ck selected as kernel clock + 0x3 + + + B_0x4 + csi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + lse_ck selected as kernel clock + 0x5 + + + + + + + RCC_CCIPR4 + RCC_CCIPR4 + RCC kernel clock configuration register + 0x0E4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCTOSPI1SEL + OCTOSPI1 kernel clock source selection + + 0 + 2 + read-write + + + B_0x0 + rcc_hclk4 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll1_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll2_r_ck selected as kernel clock + 0x2 + + + B_0x3 + per_ck selected as kernel clock + 0x3 + + + + + SYSTICKSEL + SYSTICK clock source selection + + 2 + 2 + read-write + + + B_0x0 + rcc_hclk/8 selected as clock source (default after reset) + 0x0 + + + B_0x1 + lsi_ker_ck[1] selected as clock source + 0x1 + + + B_0x2 + lse_ck[1] selected as clock source + 0x2 + + + + + USBSEL + USB kernel clock source selection + 4 + 2 + read-write + + + B_0x0 + no clock is selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll1_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_q_ck selected as kernel clock + 0x2 + + + B_0x3 + hsi48_ker_ck selected as kernel clock + 0x3 + + + + + SDMMC1SEL + SDMMC1 kernel clock source selection + 6 + 1 + read-write + + + B_0x0 + pll1_q_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_r_ck selected as kernel clock + 0x1 + + + + + I2C1SEL + I2C1 kernel clock source selection + 16 + 2 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck selected as kernel clock + 0x1 + + + B_0x2 + hsi_ker_ck selected as kernel clock + 0x2 + + + B_0x3 + csi_ker_ck selected as kernel clock + 0x3 + + + + + I2C2SEL + I2C2 kernel clock source selection + 18 + 2 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck selected as kernel clock + 0x1 + + + B_0x2 + hsi_ker_ck selected as kernel clock + 0x2 + + + B_0x3 + csi_ker_ck selected as kernel clock + 0x3 + + + + + I2C3SEL + I2C3 kernel clock source selection + 20 + 2 + read-write + + + B_0x0 + rcc_pclk3 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck selected as kernel clock + 0x1 + + + B_0x2 + hsi_ker_ck selected as kernel clock + 0x2 + + + B_0x3 + csi_ker_ck selected as kernel clock + 0x3 + + + + + I3C1SEL + I3C1 kernel clock source selection + 24 + 2 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck selected as kernel clock + 0x1 + + + B_0x2 + hsi_ker_ck selected as kernel clock + 0x2 + + + B_0x3 + no clock selected + 0x3 + + + + + I3C2SEL + I3C2 kernel clock source selection + 26 + 2 + read-write + + + B_0x0 + rcc_pclk1 selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll3_r_ck selected as kernel clock + 0x1 + + + B_0x2 + hsi_ker_ck selected as kernel clock + 0x2 + + + B_0x3 + no clock selected + 0x3 + + + + + + + RCC_CCIPR5 + RCC_CCIPR5 + RCC kernel clock configuration register + 0x0E8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADCDACSEL + ADC and DAC kernel clock source selection + + 0 + 3 + read-write + + + B_0x0 + rcc_hclk selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + sys_ck selected as kernel clock + 0x1 + + + B_0x2 + pll2_r_ck selected as kernel clock + 0x2 + + + B_0x3 + hse_ck selected as kernel clock + 0x3 + + + B_0x4 + hsi_ker_ck selected as kernel clock + 0x4 + + + B_0x5 + csi_ker_ck selected as kernel clock + 0x5 + + + + + DACSEL + DAC sample and hold clock + 3 + 1 + read-write + + + B_0x0 + dac_hold_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + dac_hold_ck selected as kernel clock + 0x1 + + + + + RNGSEL + RNG kernel clock source selection + 4 + 2 + read-write + + + B_0x0 + hsi48_ker_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll1_q_ck selected as kernel clock + 0x1 + + + B_0x2 + lse_ck selected as kernel clock + 0x2 + + + B_0x3 + lsi_ker_ck selected as kernel clock + 0x3 + + + + + CECSEL + HSMI-CEC kernel clock source selection + 6 + 2 + read-write + + + B_0x0 + lse_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + lsi_ker_ck selected as kernel clock + 0x1 + + + B_0x2 + csi_ker_ck/122 selected as kernel clock + 0x2 + + + + + FDCANSEL + FDCAN1 and FDCAN2 kernel clock source selection + 8 + 2 + read-write + + + B_0x0 + hse_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll1_q_ck selected as kernel clock + 0x1 + + + B_0x2 + pll2_q_ck selected as kernel clock + 0x2 + + + + + SAI1SEL + SAI1 kernel clock source selection + + 16 + 3 + read-write + + + B_0x0 + pll1_q_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_p_ck selected as kernel clock + 0x2 + + + B_0x3 + AUDIOCLK selected as kernel clock + 0x3 + + + B_0x4 + per_ck selected as kernel clock + 0x4 + + + + + SAI2SEL + SAI2 kernel clock source selection + + 19 + 3 + read-write + + + B_0x0 + pll1_q_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + pll2_p_ck selected as kernel clock + 0x1 + + + B_0x2 + pll3_p_ck selected as kernel clock + 0x2 + + + B_0x3 + AUDIOCLK selected as kernel clock + 0x3 + + + B_0x4 + per_ck selected as kernel clock + 0x4 + + + + + CKPERSEL + per_ck clock source selection + 30 + 2 + read-write + + + B_0x0 + hsi_ker_ck selected as kernel clock (default after reset) + 0x0 + + + B_0x1 + csi_ker_ck selected as kernel clock + 0x1 + + + B_0x2 + hse_ck selected as kernel clock + 0x2 + + + + + + + RCC_BDCR + RCC_BDCR + RCC Backup domain control register + 0x0F0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LSEON + LSE oscillator enabled + + 0 + 1 + read-write + + + B_0x0 + LSE oscillator OFF (default after Backup domain reset) + 0x0 + + + B_0x1 + LSE oscillator ON + 0x1 + + + + + LSERDY + LSE oscillator ready + + 1 + 1 + read-write + + + B_0x0 + LSE oscillator not ready (default after Backup domain reset) + 0x0 + + + B_0x1 + LSE oscillator ready + 0x1 + + + + + LSEBYP + LSE oscillator bypass + + 2 + 1 + read-write + + + B_0x0 + LSE oscillator not bypassed (default after Backup domain reset) + 0x0 + + + B_0x1 + LSE oscillator bypassed + 0x1 + + + + + LSEDRV + LSE oscillator driving capability + + 3 + 2 + read-write + + + B_0x0 + lowest drive (default after Backup domain reset) + 0x0 + + + B_0x1 + medium-low drive + 0x1 + + + B_0x2 + medium-high drive + 0x2 + + + B_0x3 + highest drive + 0x3 + + + + + LSECSSON + LSE clock security system enable + + 5 + 1 + read-write + + + B_0x0 + CSS on 32 kHz oscillator OFF (default after Backup domain reset) + 0x0 + + + B_0x1 + CSS on 32 kHz oscillator ON + 0x1 + + + + + LSECSSD + LSE clock security system failure detection + + 6 + 1 + read-write + + + B_0x0 + no failure detected on 32 kHz oscillator (default after Backup domain reset) + 0x0 + + + B_0x1 + failure detected on 32 kHz oscillator + 0x1 + + + + + LSEEXT + low-speed external clock type in bypass mode + + 7 + 1 + read-write + + + B_0x0 + LSE in analog mode (default after Backup domain reset) + 0x0 + + + B_0x1 + LSE in digital mode (do not use if RTC is active). + 0x1 + + + + + RTCSEL + RTC clock source selection + + 8 + 2 + read-write + + + B_0x0 + no clock (default after Backup domain reset) + 0x0 + + + B_0x1 + LSE selected as RTC clock + 0x1 + + + B_0x2 + LSI selected as RTC clock + 0x2 + + + B_0x3 + HSE divided by RTCPRE value selected as RTC clock + 0x3 + + + + + RTCEN + RTC clock enable + + 15 + 1 + read-write + + + B_0x0 + rtc_ck disabled (default after Backup domain reset) + 0x0 + + + B_0x1 + rtc_ck enabled + 0x1 + + + + + VSWRST + VSwitch domain software reset + + 16 + 1 + read-write + + + B_0x0 + reset not activated (default after Backup domain reset) + 0x0 + + + B_0x1 + resets the entire VSW domain + 0x1 + + + + + LSCOEN + Low-speed clock output (LSCO) enable + + 24 + 1 + read-write + + + B_0x0 + LSCO output disabled + 0x0 + + + B_0x1 + LSCO output enabled + 0x1 + + + + + LSCOSEL + Low-speed clock output selection + + 25 + 1 + read-write + + + B_0x0 + LSI clock selected + 0x0 + + + B_0x1 + LSE clock selected + 0x1 + + + + + LSION + LSI oscillator enable + + 26 + 1 + read-write + + + B_0x0 + LSI oscillator off + 0x0 + + + B_0x1 + LSI oscillator on + 0x1 + + + + + LSIRDY + LSI oscillator ready + + 27 + 1 + read-write + + + B_0x0 + LSI oscillator not ready + 0x0 + + + B_0x1 + LSI oscillator ready + 0x1 + + + + + + + RCC_RSR + RCC_RSR + RCC reset status register + 0x0F4 + 0x20 + read-write + 0x0C000000 + 0xFFFFFFFF + + + RMVF + remove reset flag + + 23 + 1 + read-write + + + B_0x0 + reset of the reset flags not activated (default after power-on reset) + 0x0 + + + B_0x1 + resets the value of the reset flags + 0x1 + + + + + PINRSTF + pin reset flag (NRST) + + 26 + 1 + read-write + + + B_0x0 + no reset from pin occurred + 0x0 + + + B_0x1 + reset from pin occurred (default after power-on reset) + 0x1 + + + + + BORRSTF + BOR reset flag + + 27 + 1 + read-write + + + B_0x0 + no BOR reset occurred + 0x0 + + + B_0x1 + BOR reset occurred (default after power-on reset) + 0x1 + + + + + SFTRSTF + system reset from CPU reset flag + + 28 + 1 + read-write + + + B_0x0 + no CPU software reset occurred (default after power-on reset) + 0x0 + + + B_0x1 + a system reset has been generated by the CPU + 0x1 + + + + + IWDGRSTF + independent watchdog reset flag + + 29 + 1 + read-write + + + B_0x0 + no independent watchdog reset occurred (default after power-on reset) + 0x0 + + + B_0x1 + independent watchdog reset occurred + 0x1 + + + + + WWDGRSTF + window watchdog reset flag + + 30 + 1 + read-write + + + B_0x0 + no window watchdog reset occurred from WWDG (default after power-on reset) + 0x0 + + + B_0x1 + window watchdog reset occurred from WWDG + 0x1 + + + + + LPWRRSTF + Low-power reset flag + + 31 + 1 + read-write + + + B_0x0 + No illegal low-power mode reset occurred + 0x0 + + + B_0x1 + Illegal low-power mode reset occurred + 0x1 + + + + + + + RCC_SECCFGR + RCC_SECCFGR + RCC secure configuration register + 0x110 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSISEC + HSI clock configuration and status bits security + + 0 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + HSESEC + HSE clock configuration bits, status bits and HSE_CSS security + + 1 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + CSISEC + CSI clock configuration and status bits security + + 2 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LSISEC + LSI clock configuration and status bits security + + 3 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + LSESEC + LSE clock configuration and status bits security + + 4 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + SYSCLKSEC + SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security + + 5 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PRESCSEC + AHBx/APBx prescaler configuration bits security + + 6 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PLL1SEC + PLL1 clock configuration and status bits security + + 7 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PLL2SEC + PLL2 clock configuration and status bits security + + 8 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + PLL3SEC + PLL3 clock configuration and status bits security + + 9 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + HSI48SEC + HSI48 clock configuration and status bits security + + 11 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + RMVFSEC + Remove reset flag security + + 12 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + CKPERSELSEC + per_ck selection security + + 13 + 1 + read-write + + + B_0x0 + non secure + 0x0 + + + B_0x1 + secure + 0x1 + + + + + + + RCC_PRIVCFGR + RCC_PRIVCFGR + RCC privilege configuration register + 0x114 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPRIV + RCC secure functions privilege configuration + + 0 + 1 + read-write + + + B_0x0 + Read and write to RCC secure functions can be done by privileged or unprivileged access. + 0x0 + + + B_0x1 + Read and write to RCC secure functions can be done by privileged access only + 0x1 + + + + + NSPRIV + RCC non-secure functions privilege configuration + + 1 + 1 + read-write + + + B_0x0 + Read and write to RCC non-secure functions can be done by privileged or unprivileged access. + 0x0 + + + B_0x1 + Read and write to RCC non-secure functions can be done by privileged access only + 0x1 + + + + + + + + + RCC_S + 0X54020C00 + + + RNG + RNG address block description + RNG + 0x420c0800 + + 0x0 + 0x14 + registers + + + RNG + RNG global interrupt + 114 + + + + RNG_CR + RNG_CR + RNG control register + 0x000 + 0x20 + read-write + 0x00800D00 + 0xFFFFFFFF + + + RNGEN + True random number generator enable + 2 + 1 + read-write + + + B_0x0 + True random number generator is disabled. + 0x0 + + + B_0x1 + True random number generator is enabled. + 0x1 + + + + + IE + Interrupt enable + 3 + 1 + read-write + + + B_0x0 + RNG interrupt is disabled + 0x0 + + + B_0x1 + RNG interrupt is enabled. + 0x1 + + + + + CED + Clock error detection + + 5 + 1 + read-write + + + B_0x0 + Clock error detection enabled + 0x0 + + + B_0x1 + Clock error detection is disabled + 0x1 + + + + + ARDIS + Auto reset disable + + 7 + 1 + read-write + + + B_0x0 + Auto-reset enabled + 0x0 + + + B_0x1 + Auto-reset disabled + 0x1 + + + + + RNG_CONFIG3 + RNG configuration 3 + + 8 + 4 + read-write + + + NISTC + NIST custom + + 12 + 1 + read-write + + + B_0x0 + Hardware default values for NIST compliant RNG. + 0x0 + + + B_0x1 + Custom values for NIST compliant RNG. + 0x1 + + + + + RNG_CONFIG2 + RNG configuration 2 + + 13 + 3 + read-write + + + CLKDIV + Clock divider factor + + 16 + 4 + read-write + + + B_0x0 + internal RNG clock after divider is similar to incoming RNG clock. + 0x0 + + + B_0x1 + two RNG clock cycles per internal RNG clock. + 0x1 + + + B_0x2 + 2less thansup>2less than/sup> (= 4) RNG clock cycles per internal RNG clock. + 0x2 + + + B_0xF + 2less thansup>15less than/sup> RNG clock cycles per internal clock (for example. + 0xF + + + + + RNG_CONFIG1 + RNG configuration 1 + + 20 + 6 + read-write + + + CONDRST + Conditioning soft reset + + 30 + 1 + read-write + + + CONFIGLOCK + RNG Config lock + + 31 + 1 + read-write + + + B_0x0 + Writes to the RNG_NSCR, RNG_HTCR and RNG_CR configuration bits [29:4] are allowed. + 0x0 + + + B_0x1 + Writes to the RNG_NSCR, RNG_HTCR and RNG_CR configuration bits [29:4] are ignored until the next RNG reset. + 0x1 + + + + + + + RNG_SR + RNG_SR + RNG status register + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DRDY + Data ready + + 0 + 1 + read-only + + + B_0x0 + The RNG_DR register is not yet valid, no random data is available. + 0x0 + + + B_0x1 + The RNG_DR register contains valid random data. + 0x1 + + + + + CECS + Clock error current status + + 1 + 1 + read-only + + + B_0x0 + The RNG clock is correct (fless thansub>RNGCLKless than/sub>> fless thansub>HCLKless than/sub>/32). + 0x0 + + + B_0x1 + The RNG clock is too slow (fless thansub>RNGCLKless than/sub>less than fless thansub>HCLKless than/sub>/32). + 0x1 + + + + + SECS + Seed error current status + + 2 + 1 + read-only + + + B_0x0 + No faulty sequence has currently been detected. + 0x0 + + + B_0x1 + At least one of the following faulty sequences has been detected: + 0x1 + + + + + CEIS + Clock error interrupt status + + 5 + 1 + read-write + + + B_0x0 + The RNG clock is correct (fless thansub>RNGCLKless than/sub>> fless thansub>HCLKless than/sub>/32) + 0x0 + + + B_0x1 + The RNG clock before the internal divider is detected too slow (fless thansub>RNGCLKless than/sub>less than fless thansub>HCLKless than/sub>/32) + 0x1 + + + + + SEIS + Seed error interrupt status + + 6 + 1 + read-write + + + B_0x0 + No faulty sequence detected + 0x0 + + + B_0x1 + At least one faulty sequence is detected. + 0x1 + + + + + + + RNG_DR + RNG_DR + RNG data register + 0x008 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RNDATA + Random data + + 0 + 32 + read-only + + + + + RNG_NSCR + RNG_NSCR + RNG noise source control register + 0x00C + 0x20 + read-write + 0x0003FFFF + 0xFFFFFFFF + + + EN_OSC1 + Each bit drives one oscillator enable signal input of instance number 1, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + 0 + 3 + read-write + + + EN_OSC2 + Each bit drives one oscillator enable signal input of instance number 2, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + 3 + 3 + read-write + + + EN_OSC3 + Each bit drives one oscillator enable signal input of instance number 3, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + 6 + 3 + read-write + + + EN_OSC4 + Each bit drives one oscillator enable signal input of instance number 4, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + 9 + 3 + read-write + + + EN_OSC5 + Each bit drives one oscillator enable signal input of instance number 5, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + 12 + 3 + read-write + + + EN_OSC6 + Each bit drives one oscillator enable signal input of instance number 6, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + 15 + 3 + read-write + + + + + RNG_HTCR + RNG_HTCR + RNG health test control register + 0x010 + 0x20 + read-write + 0x000072AC + 0xFFFFFFFF + + + HTCFG + health test configuration + + 0 + 32 + read-write + + + + + + + RNG_S + 0X520C0800 + + + RTC + RTC register block + RTC + 0x44007800 + + 0x0 + 0x400 + registers + + + RTC_S + RTC global secure interrupts + 3 + + + RTC + RTC global non-secure interrupts + 2 + + + + RTC_TR + RTC_TR + RTC time register + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format + 0 + 4 + read-write + + + ST + Second tens in BCD format + 4 + 3 + read-write + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + + + RTC_DR + RTC_DR + RTC date register + 0x04 + 0x20 + read-write + 0x00002101 + 0xFFFFFFFF + + + DU + Date units in BCD format + 0 + 4 + read-write + + + DT + Date tens in BCD format + 4 + 2 + read-write + + + MU + Month units in BCD format + 8 + 4 + read-write + + + MT + Month tens in BCD format + 12 + 1 + read-write + + + WDU + Week day units + + 13 + 3 + read-write + + + B_0x0 + forbidden + 0x0 + + + B_0x1 + Monday + 0x1 + + + B_0x7 + Sunday + 0x7 + + + + + YU + Year units in BCD format + 16 + 4 + read-write + + + YT + Year tens in BCD format + 20 + 4 + read-write + + + + + RTC_SSR + RTC_SSR + RTC subsecond register + 0x08 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous binary counter + + 0 + 32 + read-only + + + + + RTC_ICSR + RTC_ICSR + RTC initialization control and status register + 0x0C + 0x20 + read-write + 0x00000007 + 0xFFFFFFFF + + + WUTWF + Wake-up timer write flag + + 2 + 1 + read-only + + + B_0x0 + Wake-up timer configuration update not allowed except in initialization mode + 0x0 + + + B_0x1 + Wake-up timer configuration update allowed + 0x1 + + + + + SHPF + Shift operation pending + + 3 + 1 + read-only + + + B_0x0 + No shift operation is pending + 0x0 + + + B_0x1 + A shift operation is pending + 0x1 + + + + + INITS + Initialization status flag + + 4 + 1 + read-only + + + B_0x0 + Calendar has not been initialized + 0x0 + + + B_0x1 + Calendar has been initialized + 0x1 + + + + + RSF + Registers synchronization flag + + 5 + 1 + read-write + + + B_0x0 + Calendar shadow registers not yet synchronized + 0x0 + + + B_0x1 + Calendar shadow registers synchronized + 0x1 + + + + + INITF + Initialization flag + + 6 + 1 + read-only + + + B_0x0 + Calendar registers update is not allowed + 0x0 + + + B_0x1 + Calendar registers update is allowed + 0x1 + + + + + INIT + Initialization mode + 7 + 1 + read-write + + + B_0x0 + Free running mode + 0x0 + + + B_0x1 + Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER), plus BIN and BCDU fields. + 0x1 + + + + + BIN + Binary mode + 8 + 2 + read-write + + + B_0x0 + Free running BCD calendar mode (Binary mode disabled). + 0x0 + + + B_0x1 + Free running Binary mode (BCD mode disabled) + 0x1 + + + B_0x2 + Free running BCD calendar and Binary modes + 0x2 + + + B_0x3 + Free running BCD calendar and Binary modes + 0x3 + + + + + BCDU + BCD update (BIN = 10 or 11) + + 10 + 3 + read-write + + + B_0x0 + 1s calendar increment is generated each time SS[7:0] = 0 + 0x0 + + + B_0x1 + 1s calendar increment is generated each time SS[8:0] = 0 + 0x1 + + + B_0x2 + 1s calendar increment is generated each time SS[9:0] = 0 + 0x2 + + + B_0x3 + 1s calendar increment is generated each time SS[10:0] = 0 + 0x3 + + + B_0x4 + 1s calendar increment is generated each time SS[11:0] = 0 + 0x4 + + + B_0x5 + 1s calendar increment is generated each time SS[12:0] = 0 + 0x5 + + + B_0x6 + 1s calendar increment is generated each time SS[13:0] = 0 + 0x6 + + + B_0x7 + 1s calendar increment is generated each time SS[14:0] = 0 + 0x7 + + + + + RECALPF + Recalibration pending Flag + + 16 + 1 + read-only + + + + + RTC_PRER + RTC_PRER + RTC prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + 0xFFFFFFFF + + + PREDIV_S + Synchronous prescaler factor + + 0 + 15 + read-write + + + PREDIV_A + Asynchronous prescaler factor + + 16 + 7 + read-write + + + + + RTC_WUTR + RTC_WUTR + RTC wake-up timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + WUT + Wake-up auto-reload value bits + + 0 + 16 + read-write + + + WUTOCLR + Wake-up auto-reload output clear value + + 16 + 16 + read-write + + + + + RTC_CR + RTC_CR + RTC control register + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + WUCKSEL + ck_wut wake-up clock selection + + 0 + 3 + read-write + + + B_0x0 + RTC/16 clock is selected + 0x0 + + + B_0x1 + RTC/8 clock is selected + 0x1 + + + B_0x2 + RTC/4 clock is selected + 0x2 + + + B_0x3 + RTC/2 clock is selected + 0x3 + + + + + TSEDGE + Timestamp event active edge + + 3 + 1 + read-write + + + B_0x0 + RTC_TS input rising edge generates a timestamp event + 0x0 + + + B_0x1 + RTC_TS input falling edge generates a timestamp event + 0x1 + + + + + REFCKON + RTC_REFIN reference clock detection enable (50 or 60 Hz) + + 4 + 1 + read-write + + + B_0x0 + RTC_REFIN detection disabled + 0x0 + + + B_0x1 + RTC_REFIN detection enabled + 0x1 + + + + + BYPSHAD + Bypass the shadow registers + + 5 + 1 + read-write + + + B_0x0 + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. + 0x0 + + + B_0x1 + Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. + 0x1 + + + + + FMT + Hour format + 6 + 1 + read-write + + + B_0x0 + 24 hour/day format + 0x0 + + + B_0x1 + AM/PM hour format + 0x1 + + + + + SSRUIE + SSR underflow interrupt enable + 7 + 1 + read-write + + + B_0x0 + SSR underflow interrupt disabled + 0x0 + + + B_0x1 + SSR underflow interrupt enabled + 0x1 + + + + + ALRAE + Alarm A enable + 8 + 1 + read-write + + + B_0x0 + Alarm A disabled + 0x0 + + + B_0x1 + Alarm A enabled + 0x1 + + + + + ALRBE + Alarm B enable + 9 + 1 + read-write + + + B_0x0 + Alarm B disabled + 0x0 + + + B_0x1 + Alarm B enabled + 0x1 + + + + + WUTE + Wake-up timer enable + + 10 + 1 + read-write + + + B_0x0 + Wake-up timer disabled + 0x0 + + + B_0x1 + Wake-up timer enabled + 0x1 + + + + + TSE + timestamp enable + 11 + 1 + read-write + + + B_0x0 + timestamp disable + 0x0 + + + B_0x1 + timestamp enable + 0x1 + + + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + read-write + + + B_0x0 + Alarm A interrupt disabled + 0x0 + + + B_0x1 + Alarm A interrupt enabled + 0x1 + + + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + read-write + + + B_0x0 + Alarm B interrupt disable + 0x0 + + + B_0x1 + Alarm B interrupt enable + 0x1 + + + + + WUTIE + Wake-up timer interrupt enable + 14 + 1 + read-write + + + B_0x0 + Wake-up timer interrupt disabled + 0x0 + + + B_0x1 + Wake-up timer interrupt enabled + 0x1 + + + + + TSIE + Timestamp interrupt enable + 15 + 1 + read-write + + + B_0x0 + Timestamp interrupt disable + 0x0 + + + B_0x1 + Timestamp interrupt enable + 0x1 + + + + + ADD1H + Add 1 hour (summer time change) + + 16 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Adds 1 hour to the current time. + 0x1 + + + + + SUB1H + Subtract 1 hour (winter time change) + + 17 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Subtracts 1 hour to the current time. + 0x1 + + + + + BKP + Backup + + 18 + 1 + read-write + + + COSEL + Calibration output selection + + 19 + 1 + read-write + + + B_0x0 + Calibration output is 512 Hz + 0x0 + + + B_0x1 + Calibration output is 1 Hz + 0x1 + + + + + POL + Output polarity + + 20 + 1 + read-write + + + B_0x0 + The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). + 0x0 + + + B_0x1 + The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1). + 0x1 + + + + + OSEL + Output selection + + 21 + 2 + read-write + + + B_0x0 + Output disabled + 0x0 + + + B_0x1 + Alarm A output enabled + 0x1 + + + B_0x2 + Alarm B output enabled + 0x2 + + + B_0x3 + Wake-up output enabled + 0x3 + + + + + COE + Calibration output enable + + 23 + 1 + read-write + + + B_0x0 + Calibration output disabled + 0x0 + + + B_0x1 + Calibration output enabled + 0x1 + + + + + ITSE + timestamp on internal event enable + 24 + 1 + read-write + + + B_0x0 + internal event timestamp disabled + 0x0 + + + B_0x1 + internal event timestamp enabled + 0x1 + + + + + TAMPTS + Activate timestamp on tamper detection event + + 25 + 1 + read-write + + + B_0x0 + Tamper detection event does not cause a RTC timestamp to be saved + 0x0 + + + B_0x1 + Save RTC timestamp on tamper detection event + 0x1 + + + + + TAMPOE + Tamper detection output enable on TAMPALRM + 26 + 1 + read-write + + + B_0x0 + The tamper flag is not routed on TAMPALRM + 0x0 + + + B_0x1 + The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL. + 0x1 + + + + + ALRAFCLR + Alarm A flag automatic clear + 27 + 1 + read-write + + + B_0x0 + Alarm A event generates a trigger event and ALRAF must be cleared by software to allow next alarm event. + 0x0 + + + B_0x1 + Alarm A event generates a trigger event. + 0x1 + + + + + ALRBFCLR + Alarm B flag automatic clear + 28 + 1 + read-write + + + B_0x0 + Alarm B event generates a trigger event and ALRBF must be cleared by software to allow next alarm event. + 0x0 + + + B_0x1 + Alarm B event generates a trigger event. + 0x1 + + + + + TAMPALRM_PU + TAMPALRM pull-up enable + 29 + 1 + read-write + + + B_0x0 + No pull-up is applied on TAMPALRM output + 0x0 + + + B_0x1 + A pull-up is applied on TAMPALRM output + 0x1 + + + + + TAMPALRM_TYPE + TAMPALRM output type + 30 + 1 + read-write + + + B_0x0 + TAMPALRM is push-pull output + 0x0 + + + B_0x1 + TAMPALRM is open-drain output + 0x1 + + + + + OUT2EN + RTC_OUT2 output enable + + 31 + 1 + read-write + + + + + RTC_PRIVCFGR + RTC_PRIVCFGR + RTC privilege mode control register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALRAPRIV + Alarm A and SSR underflow privilege protection + 0 + 1 + read-write + + + B_0x0 + RTC Alarm A and SSR underflow configuration and interrupt clear can be written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + RTC Alarm A and SSR underflow configuration and interrupt clear can be written only when the APB access is privileged. + 0x1 + + + + + ALRBPRIV + Alarm B privilege protection + 1 + 1 + read-write + + + B_0x0 + RTC Alarm B configuration and interrupt clear can be written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + RTC Alarm B configuration and interrupt clear can be written only when the APB access is privileged. + 0x1 + + + + + WUTPRIV + Wake-up timer privilege protection + 2 + 1 + read-write + + + B_0x0 + RTC wake-up timer configuration and interrupt clear can be written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + RTC wake-up timer configuration and interrupt clear can be written only when the APB access is privileged. + 0x1 + + + + + TSPRIV + Timestamp privilege protection + 3 + 1 + read-write + + + B_0x0 + RTC Timestamp configuration and interrupt clear can be written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + RTC Timestamp configuration and interrupt clear can be written only when the APB access is privileged. + 0x1 + + + + + CALPRIV + Shift register, Delight saving, calibration and reference clock privilege protection + 13 + 1 + read-write + + + B_0x0 + Shift register, Delight saving, calibration and reference clock can be written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + Shift register, Delight saving, calibration and reference clock can be written only when the APB access is privileged. + 0x1 + + + + + INITPRIV + Initialization privilege protection + 14 + 1 + read-write + + + B_0x0 + RTC Initialization mode, calendar and prescalers registers can be written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + RTC Initialization mode, calendar and prescalers registers can be written only when the APB access is privileged. + 0x1 + + + + + PRIV + RTC privilege protection + 15 + 1 + read-write + + + B_0x0 + All RTC registers can be written when the APB access is privileged or non-privileged, except the registers protected by other privilege protection bits. + 0x0 + + + B_0x1 + All RTC registers can be written only when the APB access is privileged. + 0x1 + + + + + + + RTC_SECCFGR + RTC_SECCFGR + RTC secure configuration register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALRASEC + Alarm A and SSR underflow protection + 0 + 1 + read-write + + + B_0x0 + RTC alarm A and SSR underflow configuration and interrupt clear can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + RTC alarm A and SSR underflow configuration and interrupt clear can be written only when the APB access is secure. + 0x1 + + + + + ALRBSEC + Alarm B protection + 1 + 1 + read-write + + + B_0x0 + RTC alarm B configuration and interrupt clear can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + RTC alarm B configuration and interrupt clear can be written only when the APB access is secure. + 0x1 + + + + + WUTSEC + Wake-up timer protection + 2 + 1 + read-write + + + B_0x0 + RTC wake-up timer configuration and interrupt clear can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + RTC wake-up timer configuration and interrupt clear can be written only when the APB access is secure. + 0x1 + + + + + TSSEC + Timestamp protection + 3 + 1 + read-write + + + B_0x0 + RTC timestamp configuration and interrupt clear can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + RTC timestamp configuration and interrupt clear can be written only when the APB access is secure. + 0x1 + + + + + CALSEC + Shift register, daylight saving, calibration and reference clock protection + 13 + 1 + read-write + + + B_0x0 + Shift register, daylight saving, calibration and reference clock can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + Shift register, daylight saving, calibration and reference clock can be written only when the APB access is secure. + 0x1 + + + + + INITSEC + Initialization protection + 14 + 1 + read-write + + + B_0x0 + RTC Initialization mode, calendar and prescalers registers can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + RTC Initialization mode, calendar and prescalers registers can be written only when the APB access is secure. + 0x1 + + + + + SEC + RTC global protection + 15 + 1 + read-write + + + B_0x0 + All RTC registers can be written when the APB access is secure or non-secure, except the registers protected by other secure protection bits. + 0x0 + + + B_0x1 + All RTC registers can be written only when the APB access is secure. + 0x1 + + + + + + + RTC_WPR + RTC_WPR + RTC write protection register + 0x24 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Write protection key + + 0 + 8 + write-only + + + + + RTC_CALR + RTC_CALR + RTC calibration register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CALM + Calibration minus + + 0 + 9 + read-write + + + LPCAL + RTC low-power mode + 12 + 1 + read-write + + + B_0x0 + Calibration window is 2less thansup>20less than/sup> RTCCLK, which is a high-consumption mode. + 0x0 + + + B_0x1 + Calibration window is 2less thansup>20less than/sup> ck_apre, which is the required configuration for ultra-low consumption mode. + 0x1 + + + + + CALW16 + Use a 16-second calibration cycle period + + 13 + 1 + read-write + + + CALW8 + Use an 8-second calibration cycle period + + 14 + 1 + read-write + + + CALP + Increase frequency of RTC by 488. + 15 + 1 + read-write + + + B_0x0 + No RTCCLK pulses are added. + 0x0 + + + B_0x1 + One RTCCLK pulse is effectively inserted every 2less thansup>11less than/sup> pulses (frequency increased by 488. + 0x1 + + + + + + + RTC_SHIFTR + RTC_SHIFTR + RTC shift control register + 0x2C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SUBFS + Subtract a fraction of a second + + 0 + 15 + write-only + + + ADD1S + Add one second + + 31 + 1 + write-only + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Add one second to the clock/calendar + 0x1 + + + + + + + RTC_TSTR + RTC_TSTR + RTC timestamp time register + 0x30 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format. + 0 + 4 + read-only + + + ST + Second tens in BCD format. + 4 + 3 + read-only + + + MNU + Minute units in BCD format. + 8 + 4 + read-only + + + MNT + Minute tens in BCD format. + 12 + 3 + read-only + + + HU + Hour units in BCD format. + 16 + 4 + read-only + + + HT + Hour tens in BCD format. + 20 + 2 + read-only + + + PM + AM/PM notation + 22 + 1 + read-only + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + + + RTC_TSDR + RTC_TSDR + RTC timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DU + Date units in BCD format + 0 + 4 + read-only + + + DT + Date tens in BCD format + 4 + 2 + read-only + + + MU + Month units in BCD format + 8 + 4 + read-only + + + MT + Month tens in BCD format + 12 + 1 + read-only + + + WDU + Week day units + 13 + 3 + read-only + + + + + RTC_TSSSR + RTC_TSSSR + RTC timestamp subsecond register + 0x38 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + SS + Subsecond value/synchronous binary counter values + + 0 + 32 + read-only + + + + + RTC_ALRMAR + RTC_ALRMAR + RTC alarm A register + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MSK1 + Alarm A seconds mask + 7 + 1 + read-write + + + B_0x0 + Alarm A set if the seconds match + 0x0 + + + B_0x1 + Seconds don't care in alarm A comparison + 0x1 + + + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + MSK2 + Alarm A minutes mask + 15 + 1 + read-write + + + B_0x0 + Alarm A set if the minutes match + 0x0 + + + B_0x1 + Minutes don't care in alarm A comparison + 0x1 + + + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + MSK3 + Alarm A hours mask + 23 + 1 + read-write + + + B_0x0 + Alarm A set if the hours match + 0x0 + + + B_0x1 + Hours don't care in alarm A comparison + 0x1 + + + + + DU + Date units or day in BCD format + 24 + 4 + read-write + + + DT + Date tens in BCD format + 28 + 2 + read-write + + + WDSEL + Week day selection + 30 + 1 + read-write + + + B_0x0 + DU[3:0] represents the date units + 0x0 + + + B_0x1 + DU[3:0] represents the week day. + 0x1 + + + + + MSK4 + Alarm A date mask + 31 + 1 + read-write + + + B_0x0 + Alarm A set if the date/day match + 0x0 + + + B_0x1 + Date/day don't care in alarm A comparison + 0x1 + + + + + + + RTC_ALRMASSR + RTC_ALRMASSR + RTC alarm A subsecond register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SS + Subseconds value + + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit + + 24 + 6 + read-write + + + B_0x0 + No comparison on subseconds for Alarm A. + 0x0 + + + B_0x1 + SS[31:1] are don't care in Alarm A comparison. + 0x1 + + + + + SSCLR + Clear synchronous counter on alarm (Binary mode only) + + 31 + 1 + read-write + + + B_0x0 + The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. + 0x0 + + + B_0x1 + The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRABINR. + 0x1 + + + + + + + RTC_ALRMBR + RTC_ALRMBR + RTC alarm B register + 0x48 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SU + Second units in BCD format + 0 + 4 + read-write + + + ST + Second tens in BCD format + 4 + 3 + read-write + + + MSK1 + Alarm B seconds mask + 7 + 1 + read-write + + + B_0x0 + Alarm B set if the seconds match + 0x0 + + + B_0x1 + Seconds don't care in alarm B comparison + 0x1 + + + + + MNU + Minute units in BCD format + 8 + 4 + read-write + + + MNT + Minute tens in BCD format + 12 + 3 + read-write + + + MSK2 + Alarm B minutes mask + 15 + 1 + read-write + + + B_0x0 + Alarm B set if the minutes match + 0x0 + + + B_0x1 + Minutes don't care in alarm B comparison + 0x1 + + + + + HU + Hour units in BCD format + 16 + 4 + read-write + + + HT + Hour tens in BCD format + 20 + 2 + read-write + + + PM + AM/PM notation + 22 + 1 + read-write + + + B_0x0 + AM or 24-hour format + 0x0 + + + B_0x1 + PM + 0x1 + + + + + MSK3 + Alarm B hours mask + 23 + 1 + read-write + + + B_0x0 + Alarm B set if the hours match + 0x0 + + + B_0x1 + Hours don't care in alarm B comparison + 0x1 + + + + + DU + Date units or day in BCD format + 24 + 4 + read-write + + + DT + Date tens in BCD format + 28 + 2 + read-write + + + WDSEL + Week day selection + 30 + 1 + read-write + + + B_0x0 + DU[3:0] represents the date units + 0x0 + + + B_0x1 + DU[3:0] represents the week day. + 0x1 + + + + + MSK4 + Alarm B date mask + 31 + 1 + read-write + + + B_0x0 + Alarm B set if the date and day match + 0x0 + + + B_0x1 + Date and day don't care in alarm B comparison + 0x1 + + + + + + + RTC_ALRMBSSR + RTC_ALRMBSSR + RTC alarm B subsecond register + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SS + Subseconds value + + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit + + 24 + 6 + read-write + + + B_0x0 + No comparison on subseconds for Alarm B. + 0x0 + + + B_0x1 + SS[31:1] are don't care in Alarm B comparison. + 0x1 + + + + + SSCLR + Clear synchronous counter on alarm (Binary mode only) + + 31 + 1 + read-write + + + B_0x0 + The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. + 0x0 + + + B_0x1 + The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRBBINR. + 0x1 + + + + + + + RTC_SR + RTC_SR + RTC status register + 0x50 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ALRAF + Alarm A flag + + 0 + 1 + read-only + + + ALRBF + Alarm B flag + + 1 + 1 + read-only + + + WUTF + Wake-up timer flag + + 2 + 1 + read-only + + + TSF + Timestamp flag + + 3 + 1 + read-only + + + TSOVF + Timestamp overflow flag + + 4 + 1 + read-only + + + ITSF + Internal timestamp flag + + 5 + 1 + read-only + + + SSRUF + SSR underflow flag + + 6 + 1 + read-only + + + + + RTC_MISR + RTC_MISR + RTC nonsecure masked interrupt status register + 0x54 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ALRAMF + Alarm A masked flag + + 0 + 1 + read-only + + + ALRBMF + Alarm B nonsecure masked flag + + 1 + 1 + read-only + + + WUTMF + Wake-up timer nonsecure masked flag + + 2 + 1 + read-only + + + TSMF + Timestamp nonsecure masked flag + + 3 + 1 + read-only + + + TSOVMF + Timestamp overflow nonsecure masked flag + + 4 + 1 + read-only + + + ITSMF + Internal timestamp nonsecure masked flag + + 5 + 1 + read-only + + + SSRUMF + SSR underflow nonsecure masked flag + + 6 + 1 + read-only + + + + + RTC_SMISR + RTC_SMISR + RTC secure masked interrupt status register + 0x58 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + ALRAMF + Alarm A interrupt secure masked flag + + 0 + 1 + read-only + + + ALRBMF + Alarm B interrupt secure masked flag + + 1 + 1 + read-only + + + WUTMF + Wake-up timer interrupt secure masked flag + + 2 + 1 + read-only + + + TSMF + Timestamp interrupt secure masked flag + + 3 + 1 + read-only + + + TSOVMF + Timestamp overflow interrupt secure masked flag + + 4 + 1 + read-only + + + ITSMF + Internal timestamp interrupt secure masked flag + + 5 + 1 + read-only + + + SSRUMF + SSR underflow secure masked flag + + 6 + 1 + read-only + + + + + RTC_SCR + RTC_SCR + RTC status clear register + 0x5C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CALRAF + Clear alarm A flag + + 0 + 1 + write-only + + + CALRBF + Clear alarm B flag + + 1 + 1 + write-only + + + CWUTF + Clear wake-up timer flag + + 2 + 1 + write-only + + + CTSF + Clear timestamp flag + + 3 + 1 + write-only + + + CTSOVF + Clear timestamp overflow flag + + 4 + 1 + write-only + + + CITSF + Clear internal timestamp flag + + 5 + 1 + write-only + + + CSSRUF + Clear SSR underflow flag + + 6 + 1 + write-only + + + + + RTC_OR + RTC_OR + RTC option register + 0x60 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OUT2_RMP + RTC_OUT2 mapping + 0 + 1 + read-write + + + B_0x0 + RTC_OUT2 is mapped on PI8 + 0x0 + + + B_0x1 + RTC_OUT2 is mapped on PB2 + 0x1 + + + + + + + RTC_ALRABINR + RTC_ALRABINR + RTC alarm A binary mode register + 0x70 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous counter alarm value in Binary mode + + 0 + 32 + read-write + + + + + RTC_ALRBBINR + RTC_ALRBBINR + RTC alarm B binary mode register + 0x74 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SS + Synchronous counter alarm value in Binary mode + + 0 + 32 + read-write + + + + + + + RTC_S + 0X54007800 + + + SAES + SAES register block + SAES + 0x420c0c00 + + 0x0 + 0x400 + registers + + + SAES + Secure AES + 36 + + + + SAES_CR + SAES_CR + SAES control register + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN + Enable + + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DATATYPE + Data type + + 1 + 2 + read-write + + + B_0x0 + No swapping (32-bit data). + 0x0 + + + B_0x1 + Half-word swapping (16-bit data) + 0x1 + + + B_0x2 + Byte swapping (8-bit data) + 0x2 + + + B_0x3 + Bit-level swapping + 0x3 + + + + + MODE + Operating mode + + 3 + 2 + read-write + + + B_0x0 + Encryption + 0x0 + + + B_0x1 + Key derivation (or key preparation), for ECB/CBC decryption only + 0x1 + + + B_0x2 + Decryption + 0x2 + + + + + CHMOD + CHMOD[1:0]: Chaining mode + + 5 + 2 + read-write + + + B_0x0 + Electronic codebook (ECB) + 0x0 + + + B_0x1 + Cipher-block chaining (CBC) + 0x1 + + + B_0x2 + Counter mode (CTR) + 0x2 + + + B_0x3 + Galois counter mode (GCM) and Galois message authentication code (GMAC) + 0x3 + + + + + DMAINEN + DMA input enable + + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + DMAOUTEN + DMA output enable + + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + GCMPH + GCM or CCM phase selection + + 13 + 2 + read-write + + + B_0x0 + Initialization phase + 0x0 + + + B_0x1 + Header phase + 0x1 + + + B_0x2 + Payload phase + 0x2 + + + B_0x3 + Final phase + 0x3 + + + + + CHMOD_1 + CHMOD[2] + 16 + 1 + read-write + + + KEYSIZE + Key size selection + + 18 + 1 + read-write + + + B_0x0 + 128-bit + 0x0 + + + B_0x1 + 256-bit + 0x1 + + + + + KEYPROT + Key protection + + 19 + 1 + read-write + + + B_0x0 + When KEYVALID is set and KEYSEL[2:0] = 0 application can transfer the ownership of the SAES, with its loaded key, to an application running in another security context (such as non-secure, secure). + 0x0 + + + B_0x1 + When KEYVALID is set, key error flag (KEIF) is set when an access to any registers is detected, this access having a security context (for example, secure, non-secure) that does not match the one of the application that loaded the key. + 0x1 + + + + + NPBLB + Number of padding bytes in last block + + 20 + 4 + read-write + + + B_0x0 + All bytes are valid (no padding) + 0x0 + + + B_0x1 + Padding for the last LSB byte + 0x1 + + + B_0xF + Padding for the 15 LSB bytes of last block. + 0xF + + + + + KMOD + Key mode selection + + 24 + 2 + read-write + + + B_0x0 + Normal key mode. + 0x0 + + + B_0x1 + Wrapped key for SAES mode. + 0x1 + + + B_0x2 + Shared key mode. + 0x2 + + + + + KSHAREID + Key share identification + + 26 + 2 + read-write + + + B_0x0 + AES peripheral + 0x0 + + + + + KEYSEL + Key selection + + 28 + 3 + read-write + + + B_0x0 + Software key, loaded in key registers SAES_KEYx + 0x0 + + + B_0x1 + Derived hardware unique key (DHUK) + 0x1 + + + B_0x2 + Boot hardware key (BHK) + 0x2 + + + B_0x4 + XOR of DHUK and BHK + 0x4 + + + + + IPRST + SAES peripheral software reset + + 31 + 1 + read-write + + + + + SAES_SR + SAES_SR + SAES status register + 0x004 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDERRF + Read error flag + + 1 + 1 + read-only + + + B_0x0 + No error + 0x0 + + + B_0x1 + Unexpected read to SAES_DOUTR register occurred during computation or data input phase. + 0x1 + + + + + WRERRF + Write error flag + + 2 + 1 + read-only + + + B_0x0 + No error + 0x0 + + + B_0x1 + Unexpected write to SAES_DINR register occurred during computation or data output phase. + 0x1 + + + + + BUSY + Busy + + 3 + 1 + read-only + + + B_0x0 + Idle + 0x0 + + + B_0x1 + Busy + 0x1 + + + + + KEYVALID + Key valid flag + + 7 + 1 + read-only + + + B_0x0 + Key not valid + 0x0 + + + B_0x1 + Key valid + 0x1 + + + + + + + SAES_DINR + SAES_DINR + SAES data input register + 0x008 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + DIN + Data input + + 0 + 32 + write-only + + + + + SAES_DOUTR + SAES_DOUTR + SAES data output register + 0x00C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DOUT + Data output + + 0 + 32 + read-only + + + + + SAES_KEYR0 + SAES_KEYR0 + SAES key register 0 + 0x010 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [31:0] + + 0 + 32 + write-only + + + + + SAES_KEYR1 + SAES_KEYR1 + SAES key register 1 + 0x014 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [63:32] + + 0 + 32 + write-only + + + + + SAES_KEYR2 + SAES_KEYR2 + SAES key register 2 + 0x018 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [95:64] + + 0 + 32 + write-only + + + + + SAES_KEYR3 + SAES_KEYR3 + SAES key register 3 + 0x01C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [127:96] + + 0 + 32 + write-only + + + + + SAES_IVR0 + SAES_IVR0 + SAES initialization vector register 0 + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [31:0] + + 0 + 32 + read-write + + + + + SAES_IVR1 + SAES_IVR1 + SAES initialization vector register 1 + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [63:32] + + 0 + 32 + read-write + + + + + SAES_IVR2 + SAES_IVR2 + SAES initialization vector register 2 + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [95:64] + + 0 + 32 + read-write + + + + + SAES_IVR3 + SAES_IVR3 + SAES initialization vector register 3 + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IVI + Initialization vector input, bits [127:96] + + 0 + 32 + read-write + + + + + SAES_KEYR4 + SAES_KEYR4 + SAES key register 4 + 0x030 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [159:128] + + 0 + 32 + write-only + + + + + SAES_KEYR5 + SAES_KEYR5 + SAES key register 5 + 0x034 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [191:160] + + 0 + 32 + write-only + + + + + SAES_KEYR6 + SAES_KEYR6 + SAES key register 6 + 0x038 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [223:192] + + 0 + 32 + write-only + + + + + SAES_KEYR7 + SAES_KEYR7 + SAES key register 7 + 0x03C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + KEY + Cryptographic key, bits [255:224] + + 0 + 32 + write-only + + + + + SAES_SUSPR0 + SAES_SUSPR0 + SAES suspend registers + 0x40 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + SAES_SUSPR1 + SAES_SUSPR1 + SAES suspend registers + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + SAES_SUSPR2 + SAES_SUSPR2 + SAES suspend registers + 0x48 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + SAES_SUSPR3 + SAES_SUSPR3 + SAES suspend registers + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + SAES_SUSPR4 + SAES_SUSPR4 + SAES suspend registers + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + SAES_SUSPR5 + SAES_SUSPR5 + SAES suspend registers + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + SAES_SUSPR6 + SAES_SUSPR6 + SAES suspend registers + 0x58 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + SAES_SUSPR7 + SAES_SUSPR7 + SAES suspend registers + 0x5C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SUSP + Suspend data + + 0 + 32 + read-write + + + + + SAES_IER + SAES_IER + SAES interrupt enable register + 0x300 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCFIE + Computation complete flag interrupt enable + + 0 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + RWEIE + Read or write error interrupt enable + + 1 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + KEIE + Key error interrupt enable + + 2 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + RNGEIE + RNG error interrupt enable + + 3 + 1 + read-write + + + B_0x0 + Disabled (masked) + 0x0 + + + B_0x1 + Enabled (not masked) + 0x1 + + + + + + + SAES_ISR + SAES_ISR + SAES interrupt status register + 0x304 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CCF + Computation complete flag + + 0 + 1 + read-only + + + B_0x0 + Not completed + 0x0 + + + B_0x1 + Completed + 0x1 + + + + + RWEIF + Read or write error interrupt flag + + 1 + 1 + read-only + + + B_0x0 + No read or write error detected + 0x0 + + + B_0x1 + Read or write error detected + 0x1 + + + + + KEIF + Key error interrupt flag + + 2 + 1 + read-only + + + B_0x0 + No key error detected + 0x0 + + + B_0x1 + Key information failed to load into key registers or the key register use is forbidden + 0x1 + + + + + RNGEIF + RNG error interrupt flag + + 3 + 1 + read-only + + + B_0x0 + RNG bus is functional + 0x0 + + + B_0x1 + Error detected on RNG bus interface (random seed fetching error) + 0x1 + + + + + + + SAES_ICR + SAES_ICR + SAES interrupt clear register + 0x308 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CCF + Computation complete flag clear + + 0 + 1 + write-only + + + RWEIF + Read or write error interrupt flag clear + + 1 + 1 + write-only + + + KEIF + Key error interrupt flag clear + + 2 + 1 + write-only + + + RNGEIF + RNG error interrupt flag clear + + 3 + 1 + write-only + + + + + + + SAES_S + 0X520C0C00 + + + SBS + SBS address block description + SBS + 0x44000400 + + 0x0 + 0x150 + registers + + + + SBS_HDPLCR + SBS_HDPLCR + SBS temporal isolation control register + 0x010 + 0x20 + read-write + 0x000000B4 + 0xFFFFFFFF + + + INCR_HDPL + increment HDPL value + + 0 + 8 + read-write + + + B_0xB4 + no increment + 0xB4 + + + B_0x6A + recommended value to increment HDPL level by one + 0x6A + + + + + + + SBS_HDPLSR + SBS_HDPLSR + SBS temporal isolation status register + 0x014 + 0x20 + read-only + 0x00000000 + 0x00000000 + + + HDPL + temporal isolation level + + 0 + 8 + read-only + + + B_0xB4 + HDPL0, RSS + 0xB4 + + + B_0x51 + HDPL1, iRoT + 0x51 + + + B_0x8A + HDPL2, uRoT + 0x8A + + + B_0x6F + HDPL3, application (secure/non-secure) + 0x6F + + + + + + + SBS_NEXTHDPLCR + SBS_NEXTHDPLCR + SBS next HDPL control register + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + NEXTHDPL + index to point to a higher HDPL than the current one + + 0 + 2 + read-write + + + + + SBS_DBGCR + SBS_DBGCR + SBS debug control register + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AP_UNLOCK + access port unlock + + 0 + 8 + read-write + + + DBG_UNLOCK + debug unlock when DBG_AUTH_HDPL is reached + + 8 + 8 + read-write + + + DBG_AUTH_HDPL + authenticated debug temporal isolation level + + 16 + 8 + read-write + + + B_0x51 + HDPL1 + 0x51 + + + B_0x8A + HDPL2 + 0x8A + + + B_0x6F + HDPL3 + 0x6F + + + + + DBG_AUTH_SEC + control debug opening secure/non-secure + + 24 + 8 + read-write + + + + + SBS_DBGLOCKR + SBS_DBGLOCKR + SBS debug lock register + 0x024 + 0x20 + read-write + 0x000000B4 + 0xFFFFFFFF + + + DBGCFG_LOCK + debug configuration lock + + 0 + 8 + read-write + + + B_0xB4 + Writes to SBS_DBGCR allowed (default) + 0xB4 + + + + + + + SBS_RSSCMDR + SBS_RSSCMDR + SBS RSS command register + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RSSCMD + RSS command + + 0 + 16 + read-write + + + + + SBS_EPOCHSELCR + SBS_EPOCHSELCR + SBS EPOCH selection control register + 0x0A0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EPOCH_SEL + select EPOCH value to be sent to the SAES + + 0 + 2 + read-write + + + B_0x0 + NS_EPOCH (non-secure) counter input selected + 0x0 + + + B_0x1 + SEC_EPOCH counter input selected + 0x1 + + + + + + + SBS_SECCFGR + SBS_SECCFGR + SBS security mode configuration control register + 0x0C0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SBSSEC + SBS clock control, memory-erase status register and compensation cell register security enable + 0 + 1 + read-write + + + B_0x0 + SBS_MESR, SBS_CCCSR, SBS_CCVALR, SBS_CCSWCR registers accessible through secure or non-secure transaction + 0x0 + + + B_0x1 + SBS_MESR, SBS_CCCSR, SBS_CCVALR, SBS_CCSWCR registers accessible only through secure transaction + 0x1 + + + + + CLASSBSEC + ClassB security enable + 1 + 1 + read-write + + + B_0x0 + SBS_CFGR2 register accessible through secure or non-secure transaction + 0x0 + + + B_0x1 + SBS_CFGR2 register accessible only through secure transaction + 0x1 + + + + + FPUSEC + FPU security enable + + 3 + 1 + read-write + + + B_0x0 + SBS_FPUIMP register accessible through secure or non-secure transaction + 0x0 + + + B_0x1 + SBS_FPUIMP register accessible only through secure transaction + 0x1 + + + + + + + SBS_PMCR + SBS_PMCR + SBS product mode and configuration register + 0x100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PB6_FMP + Fast-mode Plus driving capability activation on PB6 + + 16 + 1 + read-write + + + B_0x0 + PB6 pin operates in standard mode. + 0x0 + + + B_0x1 + Fm+ mode is enabled on PB6 pin and the speed control is bypassed. + 0x1 + + + + + PB7_FMP + Fast-mode Plus driving capability activation on PB7 + + 17 + 1 + read-write + + + B_0x0 + PB7 pin operates in standard mode. + 0x0 + + + B_0x1 + Fm+ mode is enabled on PB7 pin and the speed control is bypassed. + 0x1 + + + + + PB8_FMP + Fast-mode Plus driving capability activation on PB8 + + 18 + 1 + read-write + + + B_0x0 + PB8 pin operates in standard mode. + 0x0 + + + B_0x1 + Fm+ mode is enabled on PB8 pin and the speed control is bypassed. + 0x1 + + + + + PB9_FMP + Fast-mode Plus driving capability activation on PB9 + + 19 + 1 + read-write + + + B_0x0 + PB9 pin operates in standard mode. + 0x0 + + + B_0x1 + Fm+ mode is enabled on PB9 pin and the speed control is bypassed. + 0x1 + + + + + ETH_SEL_PHY + Ethernet PHY interface selection + + 21 + 3 + read-write + + + B_0x0 + GMII or MII + 0x0 + + + B_0x4 + RMII + 0x4 + + + + + + + SBS_FPUIMR + SBS_FPUIMR + SBS FPU interrupt mask register + 0x104 + 0x20 + read-write + 0x0000001F + 0xFFFFFFFF + + + FPU_IE + FPU interrupt enable + + 0 + 6 + read-write + + + + + SBS_MESR + SBS_MESR + SBS memory erase status register + 0x108 + 0x20 + read-write + 0x00000000 + 0xFFFFFFF0 + + + MCLR + device memories erase status + + 0 + 1 + read-write + + + B_0x0 + memory erase on going if not yet cleared by software + 0x0 + + + B_0x1 + Memory erase done + 0x1 + + + + + IPMEE + ICACHE erase status + + 16 + 1 + read-write + + + B_0x0 + ICACHE and PKA RAM erase on going + 0x0 + + + B_0x1 + ICACHE and PKA SRAM erase done + 0x1 + + + + + + + SBS_CCCSR + SBS_CCCSR + SBS compensation cell for I/Os control and status register + 0x110 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN1 + enable compensation cell for VDDIO power rail + + 0 + 1 + read-write + + + B_0x0 + I/O compensation cell disabled + 0x0 + + + B_0x1 + I/O compensation cell enabled + 0x1 + + + + + CS1 + code selection for VDDIO power rail (reset value set to 1) + + 1 + 1 + read-write + + + B_0x0 + Code from the cell (available in the SBS_CCVR) + 0x0 + + + B_0x1 + Code from SBS_CCCR + 0x1 + + + + + EN2 + enable compensation cell for VDDIO2 power rail + + 2 + 1 + read-write + + + B_0x0 + I/O compensation cell disabled + 0x0 + + + B_0x1 + I/O compensation cell enabled + 0x1 + + + + + CS2 + code selection for VDDIO2 power rail (reset value set to 1) + + 3 + 1 + read-write + + + B_0x0 + Code from the cell (available in SBS_CCVR) + 0x0 + + + B_0x1 + Code from SBS_CCCR + 0x1 + + + + + RDY1 + VDDIO compensation cell ready flag + + 8 + 1 + read-only + + + B_0x0 + VDDIO compensation cell not ready + 0x0 + + + B_0x1 + VDDIO compensation cell ready (code value provided by the cell can be used) + 0x1 + + + + + RDY2 + VDDIO2 compensation cell ready flag + + 9 + 1 + read-only + + + B_0x0 + VDDIO2 compensation cell not ready + 0x0 + + + B_0x1 + VDDIO2 compensation cell ready (code value provided by the cell can be used) + 0x1 + + + + + + + SBS_CCVALR + SBS_CCVALR + SBS compensation cell for I/Os value register + 0x114 + 0x20 + read-only + 0x00000088 + 0xFFFFFFFF + + + ANSRC1 + compensation value for the NMOS transistor + + 0 + 4 + read-only + + + APSRC1 + compensation value for the PMOS transistor + + 4 + 4 + read-only + + + ANSRC2 + Compensation value for the NMOS transistor + + 8 + 4 + read-only + + + APSRC2 + compensation value for the PMOS transistor + + 12 + 4 + read-only + + + + + SBS_CCSWCR + SBS_CCSWCR + SBS compensation cell for I/Os software code register + 0x118 + 0x20 + read-write + 0x00007878 + 0xFFFFFFFF + + + SW_ANSRC1 + NMOS compensation code for VDD power rails + + 0 + 4 + read-write + + + SW_APSRC1 + PMOS compensation code for the VDD power rails + + 4 + 4 + read-write + + + SW_ANSRC2 + NMOS compensation code for VDDIO power rails + + 8 + 4 + read-write + + + SW_APSRC2 + PMOS compensation code for the Vless thansub>DDIOless than/sub> power rails + + 12 + 4 + read-write + + + + + SBS_CFGR2 + SBS_CFGR2 + SBS Class B register + 0x120 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CLL + core lockup lock + + 0 + 1 + read-write + + + B_0x0 + lockup output disconnected from timer break inputs + 0x0 + + + B_0x1 + lockup output connected to timer break inputs + 0x1 + + + + + SEL + SRAM ECC error lock + + 1 + 1 + read-write + + + B_0x0 + SRAM double ECC error flag disconnected from timer break inputs + 0x0 + + + B_0x1 + SRAM double ECC error flag connected to timer break inputs + 0x1 + + + + + PVDL + PVD lock + + 2 + 1 + read-write + + + B_0x0 + PVD interrupt disconnected from timer break inputs. + 0x0 + + + B_0x1 + PVD interrupt is connected to timer break inputs. + 0x1 + + + + + ECCL + ECC lock + + 3 + 1 + read-write + + + B_0x0 + double ECC error flag disconnected to timer break inputs + 0x0 + + + B_0x1 + double ECC error flag connected to timer break inputs + 0x1 + + + + + + + SBS_CNSLCKR + SBS_CNSLCKR + SBS CPU non-secure lock register + 0x144 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LOCKNSVTOR + VTOR_NS register lock + + 0 + 1 + read-write + + + B_0x0 + VTOR_NS register write enabled + 0x0 + + + B_0x1 + VTOR_NS register write disabled + 0x1 + + + + + LOCKNSMPU + non-secure MPU register lock + + 1 + 1 + read-write + + + B_0x0 + non-secure MPU registers write enabled + 0x0 + + + B_0x1 + non-secure MPU registers write disabled + 0x1 + + + + + + + SBS_CSLCKR + SBS_CSLCKR + SBS CPU secure lock register + 0x148 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LOCKSVTAIRCR + VTOR_S and AIRCR register lock + + 0 + 1 + read-write + + + B_0x0 + VTOR_S register PRIS and BFHFNMINS bits in the AIRCR register write enabled + 0x0 + + + B_0x1 + VTOR_S register PRIS and BFHFNMINS bits in the AIRCR register write disabled + 0x1 + + + + + LOCKSMPU + secure MPU registers lock + + 1 + 1 + read-write + + + B_0x0 + Secure MPU registers writes enabled + 0x0 + + + B_0x1 + Secure MPU registers writes disabled + 0x1 + + + + + LOCKSAU + SAU registers lock + + 2 + 1 + read-write + + + B_0x0 + SAU registers write enabled + 0x0 + + + B_0x1 + SAU registers write disabled + 0x1 + + + + + + + SBS_ECCNMIR + SBS_ECCNMIR + SBS flift ECC NMI mask register + 0x14C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ECCNMI_MASK_EN + NMI behavior setup when a double ECC error occurs on flitf data part + 0 + 1 + read-write + + + B_0x0 + NMI generated if a double ECC error in the flitf data part + 0x0 + + + B_0x1 + NMI not generated if a double ECC error in the flitf data part + 0x1 + + + + + + + + + SBS_S + 0X54000400 + + + SDMMC + SDMMC address block description + SDMMC + 0x46008000 + + 0x0 + 0xC0 + registers + + + SDMMC1 + SDMMC1 global interrupt + 79 + + + + SDMMC_POWER + SDMMC_POWER + SDMMC power control register + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PWRCTRL + SDMMC state control bits + + 0 + 2 + read-write + + + B_0x0 + After reset, Reset: the SDMMC is disabled and the clock to the Card is stopped, SDMMC_D[7:0], and SDMMC_CMD are HiZ and SDMMC_CK is driven low. + 0x0 + + + B_0x2 + Power-cycle, the SDMMC is disabled and the clock to the card is stopped, SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low. + 0x2 + + + B_0x3 + Power-on: the card is clocked, The first 74 SDMMC_CK cycles the SDMMC is still disabled. + 0x3 + + + + + VSWITCH + Voltage switch sequence start + + 2 + 1 + read-write + + + B_0x0 + Voltage switch sequence not started and not active. + 0x0 + + + B_0x1 + Voltage switch sequence started or active. + 0x1 + + + + + VSWITCHEN + Voltage switch procedure enable + + 3 + 1 + read-write + + + B_0x0 + SDMMC_CK clock kept unchanged after successfully received command response. + 0x0 + + + B_0x1 + SDMMC_CK clock stopped after successfully received command response. + 0x1 + + + + + DIRPOL + Data and command direction signals polarity selection + + 4 + 1 + read-write + + + B_0x0 + Voltage transceiver IOs driven as output when direction signal is low. + 0x0 + + + B_0x1 + Voltage transceiver IOs driven as output when direction signal is high. + 0x1 + + + + + + + SDMMC_CLKCR + SDMMC_CLKCR + SDMMC clock control register + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CLKDIV + Clock divide factor + + 0 + 10 + read-write + + + B_0x000 + SDMMC_CK frequency = sdmmc_ker_ck / 1 (Does not support DDR) + 0x000 + + + B_0x001 + SDMMC_CK frequency = sdmmc_ker_ck / 2 + 0x001 + + + B_0x002 + SDMMC_CK frequency = sdmmc_ker_ck / 4 + 0x002 + + + B_0x080 + SDMMC_CK frequency = sdmmc_ker_ck / 256 + 0x080 + + + B_0x3FF + SDMMC_CK frequency = sdmmc_ker_ck / 2046 + 0x3FF + + + + + PWRSAV + Power saving configuration bit + + 12 + 1 + read-write + + + B_0x0 + SDMMC_CK clock is always enabled + 0x0 + + + B_0x1 + SDMMC_CK is only enabled when the bus is active + 0x1 + + + + + WIDBUS + Wide bus mode enable bit + + 14 + 2 + read-write + + + B_0x0 + Default 1-bit wide bus mode: SDMMC_D0 used (Does not support DDR) + 0x0 + + + B_0x1 + 4-bit wide bus mode: SDMMC_D[3:0] used + 0x1 + + + B_0x2 + 8-bit wide bus mode: SDMMC_D[7:0] used + 0x2 + + + + + NEGEDGE + SDMMC_CK dephasing selection bit for data and command + + 16 + 1 + read-write + + + B_0x0 + When clock division >1 (CLKDIV > 0) and DDR = 0: + 0x0 + + + B_0x1 + When clock division >1 (CLKDIV > 0) and DDR = 0: + 0x1 + + + + + HWFC_EN + Hardware flow control enable + + 17 + 1 + read-write + + + B_0x0 + Hardware flow control is disabled + 0x0 + + + B_0x1 + Hardware flow control is enabled + 0x1 + + + + + DDR + Data rate signaling selection + + 18 + 1 + read-write + + + B_0x0 + SDR Single data rate signaling + 0x0 + + + B_0x1 + DDR double data rate signaling + 0x1 + + + + + BUSSPEED + Bus speed for selection of SDMMC operating modes + + 19 + 1 + read-write + + + B_0x0 + DS, HS, SDR12, SDR25, Legacy compatible, High speed SDR, High speed DDR bus speed mode selected + 0x0 + + + B_0x1 + SDR50, DDR50, SDR104, HS200 bus speed mode selected. + 0x1 + + + + + SELCLKRX + Receive clock selection + + 20 + 2 + read-write + + + B_0x0 + sdmmc_io_in_ck selected as receive clock + 0x0 + + + B_0x1 + SDMMC_CKIN feedback clock selected as receive clock + 0x1 + + + B_0x2 + sdmmc_fb_ck tuned feedback clock selected as receive clock. + 0x2 + + + + + + + SDMMC_ARGR + SDMMC_ARGR + SDMMC argument register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CMDARG + Command argument + + 0 + 32 + read-write + + + + + SDMMC_CMDR + SDMMC_CMDR + SDMMC command register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CMDINDEX + Command index + + 0 + 6 + read-write + + + CMDTRANS + The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM + + 6 + 1 + read-write + + + CMDSTOP + The CPSM treats the command as a Stop Transmission command and signals abort to the DPSM + + 7 + 1 + read-write + + + WAITRESP + Wait for response bits + + 8 + 2 + read-write + + + B_0x0 + No response, expect CMDSENT flag + 0x0 + + + B_0x1 + Short response, expect CMDREND or CCRCFAIL flag + 0x1 + + + B_0x2 + Short response, expect CMDREND flag (No CRC) + 0x2 + + + B_0x3 + Long response, expect CMDREND or CCRCFAIL flag + 0x3 + + + + + WAITINT + CPSM waits for interrupt request + + 10 + 1 + read-write + + + WAITPEND + CPSM waits for end of data transfer (CmdPend internal signal) from DPSM + + 11 + 1 + read-write + + + CPSMEN + Command path state machine (CPSM) enable bit + + 12 + 1 + read-write + + + DTHOLD + Hold new data block transmission and reception in the DPSM + + 13 + 1 + read-write + + + BOOTMODE + Select the boot mode procedure to be used + + 14 + 1 + read-write + + + B_0x0 + Normal boot mode procedure selected + 0x0 + + + B_0x1 + Alternative boot mode procedure selected. + 0x1 + + + + + BOOTEN + Enable boot mode procedure + 15 + 1 + read-write + + + B_0x0 + Boot mode procedure disabled + 0x0 + + + B_0x1 + Boot mode procedure enabled + 0x1 + + + + + CMDSUSPEND + The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end + + 16 + 1 + read-write + + + + + SDMMC_RESPCMDR + SDMMC_RESPCMDR + SDMMC command response register + 0x010 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RESPCMD + Response command index + + 0 + 6 + read-only + + + + + SDMMC_RESP1R + SDMMC_RESP1R + SDMMC response 1 register + 0x14 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CARDSTATUS + Card status according table below + + 0 + 32 + read-only + + + + + SDMMC_RESP2R + SDMMC_RESP2R + SDMMC response 2 register + 0x18 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CARDSTATUS + Card status according table below + + 0 + 32 + read-only + + + + + SDMMC_RESP3R + SDMMC_RESP3R + SDMMC response 3 register + 0x1C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CARDSTATUS + Card status according table below + + 0 + 32 + read-only + + + + + SDMMC_RESP4R + SDMMC_RESP4R + SDMMC response 4 register + 0x20 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CARDSTATUS + Card status according table below + + 0 + 32 + read-only + + + + + SDMMC_DTIMER + SDMMC_DTIMER + SDMMC data timer register + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DATATIME + Data and R1b busy timeout period + + 0 + 32 + read-write + + + + + SDMMC_DLENR + SDMMC_DLENR + SDMMC data length register + 0x028 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DATALENGTH + Data length value + + 0 + 25 + read-write + + + + + SDMMC_DCTRL + SDMMC_DCTRL + SDMMC data control register + 0x02C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTEN + Data transfer enable bit + + 0 + 1 + read-write + + + B_0x0 + Do not start data transfer without CPSM data transfer command. + 0x0 + + + B_0x1 + Start data transfer without CPSM data transfer command. + 0x1 + + + + + DTDIR + Data transfer direction selection + + 1 + 1 + read-write + + + B_0x0 + From host to card. + 0x0 + + + B_0x1 + From card to host. + 0x1 + + + + + DTMODE + Data transfer mode selection + + 2 + 2 + read-write + + + B_0x0 + Block data transfer ending on block count. + 0x0 + + + B_0x1 + SDIO multibyte data transfer. + 0x1 + + + B_0x2 + e MMC Stream data transfer. + 0x2 + + + B_0x3 + Block data transfer ending with STOP_TRANSMISSION command (not to be used with DTEN initiated data transfers). + 0x3 + + + + + DBLOCKSIZE + Data block size + + 4 + 4 + read-write + + + B_0x0 + Block length = 2less thansup>0less than/sup> = 1 byte + 0x0 + + + B_0x1 + Block length = 2less thansup>1less than/sup> = 2 bytes + 0x1 + + + B_0x2 + Block length = 2less thansup>2 less than/sup>= 4 bytes + 0x2 + + + B_0x3 + Block length = 2less thansup>3less than/sup> = 8 bytes + 0x3 + + + B_0x4 + Block length = 2less thansup>4less than/sup> = 16 bytes + 0x4 + + + B_0x5 + Block length = 2less thansup>5less than/sup> = 32 bytes + 0x5 + + + B_0x6 + Block length = 2less thansup>6less than/sup> = 64 bytes + 0x6 + + + B_0x7 + Block length = 2less thansup>7less than/sup> = 128 bytes + 0x7 + + + B_0x8 + Block length = 2less thansup>8less than/sup> = 256 bytes + 0x8 + + + B_0x9 + Block length = 2less thansup>9less than/sup> = 512 bytes + 0x9 + + + B_0xA + Block length = 2less thansup>10less than/sup> = 1024 bytes + 0xA + + + B_0xB + Block length = 2less thansup>11less than/sup> = 2048 bytes + 0xB + + + B_0xC + Block length = 2less thansup>12less than/sup> = 4096 bytes + 0xC + + + B_0xD + Block length = 2less thansup>13less than/sup> = 8192 bytes + 0xD + + + B_0xE + Block length = 2less thansup>14less than/sup> = 16384 bytes + 0xE + + + + + RWSTART + Read Wait start + + 8 + 1 + read-write + + + RWSTOP + Read Wait stop + + 9 + 1 + read-write + + + B_0x0 + No Read Wait stop. + 0x0 + + + B_0x1 + Enable for Read Wait stop when DPSM is in the R_W state. + 0x1 + + + + + RWMOD + Read Wait mode + + 10 + 1 + read-write + + + B_0x0 + Read Wait control using SDMMC_D2 + 0x0 + + + B_0x1 + Read Wait control stopping SDMMC_CK + 0x1 + + + + + SDIOEN + SD I/O interrupt enable functions + + 11 + 1 + read-write + + + BOOTACKEN + Enable the reception of the boot acknowledgment + + 12 + 1 + read-write + + + B_0x0 + Boot acknowledgment disabled, not expected to be received + 0x0 + + + B_0x1 + Boot acknowledgment enabled, expected to be received + 0x1 + + + + + FIFORST + FIFO reset, flushes any remaining data + + 13 + 1 + read-write + + + B_0x0 + FIFO not affected. + 0x0 + + + B_0x1 + Flush any remaining data and reset the FIFO pointers. + 0x1 + + + + + + + SDMMC_DCNTR + SDMMC_DCNTR + SDMMC data counter register + 0x030 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + DATACOUNT + Data count value + + 0 + 25 + read-only + + + + + SDMMC_STAR + SDMMC_STAR + SDMMC status register + 0x034 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + CCRCFAIL + Command response received (CRC check failed) + + 0 + 1 + read-only + + + DCRCFAIL + Data block sent/received (CRC check failed) + + 1 + 1 + read-only + + + CTIMEOUT + Command response timeout + + 2 + 1 + read-only + + + DTIMEOUT + Data timeout + + 3 + 1 + read-only + + + TXUNDERR + Transmit FIFO underrun error (masked by hardware when IDMA is enabled) + + 4 + 1 + read-only + + + RXOVERR + Received FIFO overrun error (masked by hardware when IDMA is enabled) + + 5 + 1 + read-only + + + CMDREND + Command response received (CRC check passed, or no CRC) + + 6 + 1 + read-only + + + CMDSENT + Command sent (no response required) + + 7 + 1 + read-only + + + DATAEND + Data transfer ended correctly + + 8 + 1 + read-only + + + DHOLD + Data transfer Hold + + 9 + 1 + read-only + + + DBCKEND + Data block sent/received + + 10 + 1 + read-only + + + DABORT + Data transfer aborted by CMD12 + + 11 + 1 + read-only + + + DPSMACT + Data path state machine active, i. + 12 + 1 + read-only + + + CPSMACT + Command path state machine active, i. + 13 + 1 + read-only + + + TXFIFOHE + Transmit FIFO half empty + + 14 + 1 + read-only + + + RXFIFOHF + Receive FIFO half full + + 15 + 1 + read-only + + + TXFIFOF + Transmit FIFO full + + 16 + 1 + read-only + + + RXFIFOF + Receive FIFO full + + 17 + 1 + read-only + + + TXFIFOE + Transmit FIFO empty + + 18 + 1 + read-only + + + RXFIFOE + Receive FIFO empty + + 19 + 1 + read-only + + + BUSYD0 + Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response + + 20 + 1 + read-only + + + B_0x0 + card signals not busy on SDMMC_D0. + 0x0 + + + B_0x1 + card signals busy on SDMMC_D0. + 0x1 + + + + + BUSYD0END + end of SDMMC_D0 Busy following a CMD response detected + + 21 + 1 + read-only + + + B_0x0 + card SDMMC_D0 signal does NOT signal change from busy to not busy. + 0x0 + + + B_0x1 + card SDMMC_D0 signal changed from busy to NOT busy. + 0x1 + + + + + SDIOIT + SDIO interrupt received + + 22 + 1 + read-only + + + ACKFAIL + Boot acknowledgment received (boot acknowledgment check fail) + + 23 + 1 + read-only + + + ACKTIMEOUT + Boot acknowledgment timeout + + 24 + 1 + read-only + + + VSWEND + Voltage switch critical timing section completion + + 25 + 1 + read-only + + + CKSTOP + SDMMC_CK stopped in Voltage switch procedure + + 26 + 1 + read-only + + + IDMATE + IDMA transfer error + + 27 + 1 + read-only + + + IDMABTC + IDMA buffer transfer complete + + 28 + 1 + read-only + + + + + SDMMC_ICR + SDMMC_ICR + SDMMC interrupt clear register + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCRCFAILC + CCRCFAIL flag clear bit + + 0 + 1 + read-write + + + B_0x0 + CCRCFAIL not cleared + 0x0 + + + B_0x1 + CCRCFAIL cleared + 0x1 + + + + + DCRCFAILC + DCRCFAIL flag clear bit + + 1 + 1 + read-write + + + B_0x0 + DCRCFAIL not cleared + 0x0 + + + B_0x1 + DCRCFAIL cleared + 0x1 + + + + + CTIMEOUTC + CTIMEOUT flag clear bit + + 2 + 1 + read-write + + + B_0x0 + CTIMEOUT not cleared + 0x0 + + + B_0x1 + CTIMEOUT cleared + 0x1 + + + + + DTIMEOUTC + DTIMEOUT flag clear bit + + 3 + 1 + read-write + + + B_0x0 + DTIMEOUT not cleared + 0x0 + + + B_0x1 + DTIMEOUT cleared + 0x1 + + + + + TXUNDERRC + TXUNDERR flag clear bit + + 4 + 1 + read-write + + + B_0x0 + TXUNDERR not cleared + 0x0 + + + B_0x1 + TXUNDERR cleared + 0x1 + + + + + RXOVERRC + RXOVERR flag clear bit + + 5 + 1 + read-write + + + B_0x0 + RXOVERR not cleared + 0x0 + + + B_0x1 + RXOVERR cleared + 0x1 + + + + + CMDRENDC + CMDREND flag clear bit + + 6 + 1 + read-write + + + B_0x0 + CMDREND not cleared + 0x0 + + + B_0x1 + CMDREND cleared + 0x1 + + + + + CMDSENTC + CMDSENT flag clear bit + + 7 + 1 + read-write + + + B_0x0 + CMDSENT not cleared + 0x0 + + + B_0x1 + CMDSENT cleared + 0x1 + + + + + DATAENDC + DATAEND flag clear bit + + 8 + 1 + read-write + + + B_0x0 + DATAEND not cleared + 0x0 + + + B_0x1 + DATAEND cleared + 0x1 + + + + + DHOLDC + DHOLD flag clear bit + + 9 + 1 + read-write + + + B_0x0 + DHOLD not cleared + 0x0 + + + B_0x1 + DHOLD cleared + 0x1 + + + + + DBCKENDC + DBCKEND flag clear bit + + 10 + 1 + read-write + + + B_0x0 + DBCKEND not cleared + 0x0 + + + B_0x1 + DBCKEND cleared + 0x1 + + + + + DABORTC + DABORT flag clear bit + + 11 + 1 + read-write + + + B_0x0 + DABORT not cleared + 0x0 + + + B_0x1 + DABORT cleared + 0x1 + + + + + BUSYD0ENDC + BUSYD0END flag clear bit + + 21 + 1 + read-write + + + B_0x0 + BUSYD0END not cleared + 0x0 + + + B_0x1 + BUSYD0END cleared + 0x1 + + + + + SDIOITC + SDIOIT flag clear bit + + 22 + 1 + read-write + + + B_0x0 + SDIOIT not cleared + 0x0 + + + B_0x1 + SDIOIT cleared + 0x1 + + + + + ACKFAILC + ACKFAIL flag clear bit + + 23 + 1 + read-write + + + B_0x0 + ACKFAIL not cleared + 0x0 + + + B_0x1 + ACKFAIL cleared + 0x1 + + + + + ACKTIMEOUTC + ACKTIMEOUT flag clear bit + + 24 + 1 + read-write + + + B_0x0 + ACKTIMEOUT not cleared + 0x0 + + + B_0x1 + ACKTIMEOUT cleared + 0x1 + + + + + VSWENDC + VSWEND flag clear bit + + 25 + 1 + read-write + + + B_0x0 + VSWEND not cleared + 0x0 + + + B_0x1 + VSWEND cleared + 0x1 + + + + + CKSTOPC + CKSTOP flag clear bit + + 26 + 1 + read-write + + + B_0x0 + CKSTOP not cleared + 0x0 + + + B_0x1 + CKSTOP cleared + 0x1 + + + + + IDMATEC + IDMA transfer error clear bit + + 27 + 1 + read-write + + + B_0x0 + IDMATE not cleared + 0x0 + + + B_0x1 + IDMATE cleared + 0x1 + + + + + IDMABTCC + IDMA buffer transfer complete clear bit + + 28 + 1 + read-write + + + B_0x0 + IDMABTC not cleared + 0x0 + + + B_0x1 + IDMABTC cleared + 0x1 + + + + + + + SDMMC_MASKR + SDMMC_MASKR + SDMMC mask register + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCRCFAILIE + Command CRC fail interrupt enable + + 0 + 1 + read-write + + + B_0x0 + Command CRC fail interrupt disabled + 0x0 + + + B_0x1 + Command CRC fail interrupt enabled + 0x1 + + + + + DCRCFAILIE + Data CRC fail interrupt enable + + 1 + 1 + read-write + + + B_0x0 + Data CRC fail interrupt disabled + 0x0 + + + B_0x1 + Data CRC fail interrupt enabled + 0x1 + + + + + CTIMEOUTIE + Command timeout interrupt enable + + 2 + 1 + read-write + + + B_0x0 + Command timeout interrupt disabled + 0x0 + + + B_0x1 + Command timeout interrupt enabled + 0x1 + + + + + DTIMEOUTIE + Data timeout interrupt enable + + 3 + 1 + read-write + + + B_0x0 + Data timeout interrupt disabled + 0x0 + + + B_0x1 + Data timeout interrupt enabled + 0x1 + + + + + TXUNDERRIE + Tx FIFO underrun error interrupt enable + + 4 + 1 + read-write + + + B_0x0 + Tx FIFO underrun error interrupt disabled + 0x0 + + + B_0x1 + Tx FIFO underrun error interrupt enabled + 0x1 + + + + + RXOVERRIE + Rx FIFO overrun error interrupt enable + + 5 + 1 + read-write + + + B_0x0 + Rx FIFO overrun error interrupt disabled + 0x0 + + + B_0x1 + Rx FIFO overrun error interrupt enabled + 0x1 + + + + + CMDRENDIE + Command response received interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Command response received interrupt disabled + 0x0 + + + B_0x1 + command Response received interrupt enabled + 0x1 + + + + + CMDSENTIE + Command sent interrupt enable + + 7 + 1 + read-write + + + B_0x0 + Command sent interrupt disabled + 0x0 + + + B_0x1 + Command sent interrupt enabled + 0x1 + + + + + DATAENDIE + Data end interrupt enable + + 8 + 1 + read-write + + + B_0x0 + Data end interrupt disabled + 0x0 + + + B_0x1 + Data end interrupt enabled + 0x1 + + + + + DHOLDIE + Data hold interrupt enable + + 9 + 1 + read-write + + + B_0x0 + Data hold interrupt disabled + 0x0 + + + B_0x1 + Data hold interrupt enabled + 0x1 + + + + + DBCKENDIE + Data block end interrupt enable + + 10 + 1 + read-write + + + B_0x0 + Data block end interrupt disabled + 0x0 + + + B_0x1 + Data block end interrupt enabled + 0x1 + + + + + DABORTIE + Data transfer aborted interrupt enable + + 11 + 1 + read-write + + + B_0x0 + Data transfer abort interrupt disabled + 0x0 + + + B_0x1 + Data transfer abort interrupt enabled + 0x1 + + + + + TXFIFOHEIE + Tx FIFO half empty interrupt enable + + 14 + 1 + read-write + + + B_0x0 + Tx FIFO half empty interrupt disabled + 0x0 + + + B_0x1 + Tx FIFO half empty interrupt enabled + 0x1 + + + + + RXFIFOHFIE + Rx FIFO half full interrupt enable + + 15 + 1 + read-write + + + B_0x0 + Rx FIFO half full interrupt disabled + 0x0 + + + B_0x1 + Rx FIFO half full interrupt enabled + 0x1 + + + + + RXFIFOFIE + Rx FIFO full interrupt enable + + 17 + 1 + read-write + + + B_0x0 + Rx FIFO full interrupt disabled + 0x0 + + + B_0x1 + Rx FIFO full interrupt enabled + 0x1 + + + + + TXFIFOEIE + Tx FIFO empty interrupt enable + + 18 + 1 + read-write + + + B_0x0 + Tx FIFO empty interrupt disabled + 0x0 + + + B_0x1 + Tx FIFO empty interrupt enabled + 0x1 + + + + + BUSYD0ENDIE + BUSYD0END interrupt enable + + 21 + 1 + read-write + + + B_0x0 + BUSYD0END interrupt disabled + 0x0 + + + B_0x1 + BUSYD0END interrupt enabled + 0x1 + + + + + SDIOITIE + SDIO mode interrupt received interrupt enable + + 22 + 1 + read-write + + + B_0x0 + SDIO Mode interrupt received interrupt disabled + 0x0 + + + B_0x1 + SDIO Mode interrupt received interrupt enabled + 0x1 + + + + + ACKFAILIE + Acknowledgment Fail interrupt enable + + 23 + 1 + read-write + + + B_0x0 + Acknowledgment Fail interrupt disabled + 0x0 + + + B_0x1 + Acknowledgment Fail interrupt enabled + 0x1 + + + + + ACKTIMEOUTIE + Acknowledgment timeout interrupt enable + + 24 + 1 + read-write + + + B_0x0 + Acknowledgment timeout interrupt disabled + 0x0 + + + B_0x1 + Acknowledgment timeout interrupt enabled + 0x1 + + + + + VSWENDIE + Voltage switch critical timing section completion interrupt enable + + 25 + 1 + read-write + + + B_0x0 + Voltage switch critical timing section completion interrupt disabled + 0x0 + + + B_0x1 + Voltage switch critical timing section completion interrupt enabled + 0x1 + + + + + CKSTOPIE + Voltage Switch clock stopped interrupt enable + + 26 + 1 + read-write + + + B_0x0 + Voltage Switch clock stopped interrupt disabled + 0x0 + + + B_0x1 + Voltage Switch clock stopped interrupt enabled + 0x1 + + + + + IDMABTCIE + IDMA buffer transfer complete interrupt enable + + 28 + 1 + read-write + + + B_0x0 + IDMA buffer transfer complete interrupt disabled + 0x0 + + + B_0x1 + IDMA buffer transfer complete interrupt enabled + 0x1 + + + + + + + SDMMC_ACKTIMER + SDMMC_ACKTIMER + SDMMC acknowledgment timer register + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ACKTIME + Boot acknowledgment timeout period + + 0 + 25 + read-write + + + + + SDMMC_IDMACTRLR + SDMMC_IDMACTRLR + SDMMC DMA control register + 0x050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDMAEN + IDMA enable + + 0 + 1 + read-write + + + B_0x0 + IDMA disabled + 0x0 + + + B_0x1 + IDMA enabled + 0x1 + + + + + IDMABMODE + Buffer mode selection + + 1 + 1 + read-write + + + B_0x0 + Single buffer mode. + 0x0 + + + B_0x1 + Linked list mode. + 0x1 + + + + + + + SDMMC_IDMABSIZER + SDMMC_IDMABSIZER + SDMMC IDMA buffer size register + 0x054 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDMABNDT + Number of bytes per buffer + + 5 + 12 + read-write + + + + + SDMMC_IDMABASER + SDMMC_IDMABASER + SDMMC IDMA buffer base address register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDMABASE + Buffer memory base address bits [31:2], must be word aligned (bit [1:0] are always 0 and read only) + + 0 + 32 + read-write + + + + + SDMMC_IDMALAR + SDMMC_IDMALAR + SDMMC IDMA linked list address register + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDMALA + Word aligned linked list item address offset + + 2 + 14 + read-write + + + ABR + Acknowledge linked list buffer ready + + 29 + 1 + read-write + + + B_0x0 + Loaded linked list buffer is not ready (this causes a linked list IDMA transfer error to be generated). + 0x0 + + + B_0x1 + Loaded linked list buffer ready acknowledge. + 0x1 + + + + + ULS + Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR. + 30 + 1 + read-write + + + B_0x0 + SDMMC_IDMABSIZER is not to be updated from next linked list table. + 0x0 + + + B_0x1 + SDMMC_IDMABSIZER is to be updated from next linked list table. + 0x1 + + + + + ULA + Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR. + 31 + 1 + read-write + + + B_0x0 + SDMMC_IDMALAR is not to be updated, last linked list item. + 0x0 + + + B_0x1 + SDMMC_IDMALAR is to be updated from linked list table. + 0x1 + + + + + + + SDMMC_IDMABAR + SDMMC_IDMABAR + SDMMC IDMA linked list memory base register + 0x068 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDMABA + Word aligned Linked list memory base address + + 2 + 30 + read-write + + + + + SDMMC_FIFOR0 + SDMMC_FIFOR0 + SDMMC data FIFO registers 0 + 0x80 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR1 + SDMMC_FIFOR1 + SDMMC data FIFO registers 1 + 0x84 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR2 + SDMMC_FIFOR2 + SDMMC data FIFO registers 2 + 0x88 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR3 + SDMMC_FIFOR3 + SDMMC data FIFO registers 3 + 0x8C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR4 + SDMMC_FIFOR4 + SDMMC data FIFO registers 4 + 0x90 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR5 + SDMMC_FIFOR5 + SDMMC data FIFO registers 5 + 0x94 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR6 + SDMMC_FIFOR6 + SDMMC data FIFO registers 6 + 0x98 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR7 + SDMMC_FIFOR7 + SDMMC data FIFO registers 7 + 0x9C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR8 + SDMMC_FIFOR8 + SDMMC data FIFO registers 8 + 0xA0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR9 + SDMMC_FIFOR9 + SDMMC data FIFO registers 9 + 0xA4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR10 + SDMMC_FIFOR10 + SDMMC data FIFO registers 10 + 0xA8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR11 + SDMMC_FIFOR11 + SDMMC data FIFO registers 11 + 0xAC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR12 + SDMMC_FIFOR12 + SDMMC data FIFO registers 12 + 0xB0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR13 + SDMMC_FIFOR13 + SDMMC data FIFO registers 13 + 0xB4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR14 + SDMMC_FIFOR14 + SDMMC data FIFO registers 14 + 0xB8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + SDMMC_FIFOR15 + SDMMC_FIFOR15 + SDMMC data FIFO registers 15 + 0xBC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + FIFODATA + Receive and transmit FIFO data + + 0 + 32 + read-write + + + + + + + SDMMC_S + 0X56008000 + + + SPI + SPI address block description + SPI + 0x40013000 + + 0x0 + 0x54 + registers + + + SPI1 + SPI1 global interrupt + 55 + + + + SPI_CR1 + SPI_CR1 + SPI/I2S control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPE + serial peripheral enable + + 0 + 1 + read-write + + + B_0x0 + Serial peripheral disabled. + 0x0 + + + B_0x1 + Serial peripheral enabled + 0x1 + + + + + MASRX + master automatic suspension in Receive mode + + 8 + 1 + read-write + + + B_0x0 + SPI flow/clock generation is continuous, regardless of overrun condition. + 0x0 + + + B_0x1 + SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. + 0x1 + + + + + CSTART + master transfer start + + 9 + 1 + read-write + + + B_0x0 + master transfer is at idle + 0x0 + + + B_0x1 + master transfer is ongoing or temporary suspended by automatic suspend + 0x1 + + + + + CSUSP + master suspend request + + 10 + 1 + write-only + + + HDDIR + Rx/Tx direction at half-duplex mode + + 11 + 1 + read-write + + + B_0x0 + SPI is receiver + 0x0 + + + B_0x1 + SPI is transmitter + 0x1 + + + + + SSI + internal SS signal input level + + 12 + 1 + read-write + + + CRC33_17 + 32-bit CRC polynomial configuration + 13 + 1 + read-write + + + B_0x0 + Full size (33-bit or 17-bit) CRC polynomial is not used + 0x0 + + + B_0x1 + Full size (33-bit or 17-bit) CRC polynomial is used + 0x1 + + + + + RCRCINI + CRC calculation initialization pattern control for receiver + 14 + 1 + read-write + + + B_0x0 + All zero pattern is applied + 0x0 + + + B_0x1 + All ones pattern is applied + 0x1 + + + + + TCRCINI + CRC calculation initialization pattern control for transmitter + 15 + 1 + read-write + + + B_0x0 + all zero pattern is applied + 0x0 + + + B_0x1 + all ones pattern is applied + 0x1 + + + + + IOLOCK + locking the AF configuration of associated I/Os + + 16 + 1 + read-write + + + B_0x0 + AF configuration is not locked + 0x0 + + + B_0x1 + AF configuration is locked + 0x1 + + + + + + + SPI_CR2 + SPI_CR2 + SPI/I2S control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSIZE + number of data at current transfer + + 0 + 16 + read-write + + + + + SPI_CFG1 + SPI_CFG1 + SPI/I2S configuration register 1 + 0x08 + 0x20 + read-write + 0x00070007 + 0xFFFFFFFF + + + DSIZE + number of bits in a single SPI data frame + + 0 + 5 + read-write + + + B_0x0 + not used + 0x0 + + + B_0x1 + not used + 0x1 + + + B_0x2 + not used + 0x2 + + + B_0x3 + 4 bits + 0x3 + + + B_0x4 + 5 bits + 0x4 + + + B_0x5 + 6 bits + 0x5 + + + B_0x6 + 7 bits + 0x6 + + + B_0x7 + 8 bits + 0x7 + + + B_0x1D + 30 bits + 0x1D + + + B_0x1E + 31 bits + 0x1E + + + B_0x1F + 32 bits + 0x1F + + + + + FTHLV + FIFO threshold level + + 5 + 4 + read-write + + + B_0x0 + 1-data + 0x0 + + + B_0x1 + 2-data + 0x1 + + + B_0x2 + 3-data + 0x2 + + + B_0x3 + 4-data + 0x3 + + + B_0x4 + 5-data + 0x4 + + + B_0x5 + 6-data + 0x5 + + + B_0x6 + 7-data + 0x6 + + + B_0x7 + 8-data + 0x7 + + + B_0x8 + 9-data + 0x8 + + + B_0x9 + 10-data + 0x9 + + + B_0xA + 11-data + 0xA + + + B_0xB + 12-data + 0xB + + + B_0xC + 13-data + 0xC + + + B_0xD + 14-data + 0xD + + + B_0xE + 15-data + 0xE + + + B_0xF + 16-data + 0xF + + + + + UDRCFG + behavior of slave transmitter at underrun condition + + 9 + 1 + read-write + + + B_0x0 + slave sends a constant pattern defined by the user at the SPI_UDRDR register + 0x0 + + + B_0x1 + Slave repeats lastly received data from master. + 0x1 + + + + + RXDMAEN + Rx DMA stream enable + 14 + 1 + read-write + + + B_0x0 + Rx-DMA disabled + 0x0 + + + B_0x1 + Rx-DMA enabled + 0x1 + + + + + TXDMAEN + Tx DMA stream enable + 15 + 1 + read-write + + + B_0x0 + Tx DMA disabled + 0x0 + + + B_0x1 + Tx DMA enabled + 0x1 + + + + + CRCSIZE + length of CRC frame to be transacted and compared + + 16 + 5 + read-write + + + B_0x3 + 4-bits + 0x3 + + + B_0x4 + 5-bits + 0x4 + + + B_0x5 + 6-bits + 0x5 + + + B_0x6 + 7-bits + 0x6 + + + B_0x7 + 8-bits + 0x7 + + + B_0x1D + 30-bits + 0x1D + + + B_0x1E + 31-bits + 0x1E + + + B_0x1F + 32-bits + 0x1F + + + + + CRCEN + hardware CRC computation enable + 22 + 1 + read-write + + + B_0x0 + CRC calculation disabled + 0x0 + + + B_0x1 + CRC calculation enabled + 0x1 + + + + + MBR + master baud rate prescaler setting + + 28 + 3 + read-write + + + B_0x0 + SPI master clock/2 + 0x0 + + + B_0x1 + SPI master clock/4 + 0x1 + + + B_0x2 + SPI master clock/8 + 0x2 + + + B_0x3 + SPI master clock/16 + 0x3 + + + B_0x4 + SPI master clock/32 + 0x4 + + + B_0x5 + SPI master clock/64 + 0x5 + + + B_0x6 + SPI master clock/128 + 0x6 + + + B_0x7 + SPI master clock/256 + 0x7 + + + + + BPASS + bypass of the prescaler at master baud rate clock generator + 31 + 1 + read-write + + + B_0x0 + bypass is disabled + 0x0 + + + B_0x1 + bypass is enabled + 0x1 + + + + + + + SPI_CFG2 + SPI_CFG2 + SPI/I2S configuration register 2 + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + MSSI + Master SS Idleness + + 0 + 4 + read-write + + + B_0x0 + no extra delay + 0x0 + + + B_0x1 + 1 clock cycle period delay added + 0x1 + + + B_0xF + 15 clock cycle periods delay added + 0xF + + + + + MIDI + master Inter-Data Idleness + + 4 + 4 + read-write + + + B_0x0 + no delay + 0x0 + + + B_0x1 + 1 clock cycle period delay + 0x1 + + + B_0xF + 15 clock cycle periods delay + 0xF + + + + + RDIOM + RDY signal input/output management + + 13 + 1 + read-write + + + B_0x0 + RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) + 0x0 + + + B_0x1 + RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) + 0x1 + + + + + RDIOP + RDY signal input/output polarity + 14 + 1 + read-write + + + B_0x0 + high level of the signal means the slave is ready for communication + 0x0 + + + B_0x1 + low level of the signal means the slave is ready for communication + 0x1 + + + + + IOSWP + swap functionality of MISO and MOSI pins + + 15 + 1 + read-write + + + B_0x0 + no swap + 0x0 + + + B_0x1 + MOSI and MISO are swapped + 0x1 + + + + + COMM + SPI Communication Mode + 17 + 2 + read-write + + + B_0x0 + full-duplex + 0x0 + + + B_0x1 + simplex transmitter + 0x1 + + + B_0x2 + simplex receiver + 0x2 + + + B_0x3 + half-duplex + 0x3 + + + + + SP + serial protocol + + 19 + 3 + read-write + + + B_0x0 + SPI Motorola + 0x0 + + + B_0x1 + SPI TI + 0x1 + + + + + MASTER + SPI master + 22 + 1 + read-write + + + B_0x0 + SPI slave + 0x0 + + + B_0x1 + SPI master + 0x1 + + + + + LSBFRST + data frame format + + 23 + 1 + read-write + + + B_0x0 + MSB transmitted first + 0x0 + + + B_0x1 + LSB transmitted first + 0x1 + + + + + CPHA + clock phase + 24 + 1 + read-write + + + B_0x0 + the first clock transition is the first data capture edge + 0x0 + + + B_0x1 + the second clock transition is the first data capture edge + 0x1 + + + + + CPOL + clock polarity + 25 + 1 + read-write + + + B_0x0 + SCK signal is at 0 when idle + 0x0 + + + B_0x1 + SCK signal is at 1 when idle + 0x1 + + + + + SSM + software management of SS signal input + + 26 + 1 + read-write + + + B_0x0 + SS input value is determined by the SS PAD + 0x0 + + + B_0x1 + SS input value is determined by the SSI bit + 0x1 + + + + + SSIOP + SS input/output polarity + 28 + 1 + read-write + + + B_0x0 + low level is active for SS signal + 0x0 + + + B_0x1 + high level is active for SS signal + 0x1 + + + + + SSOE + SS output enable + + 29 + 1 + read-write + + + B_0x0 + SS output is disabled and the SPI can work in multimaster configuration + 0x0 + + + B_0x1 + SS output is enabled. + 0x1 + + + + + SSOM + SS output management in master mode + + 30 + 1 + read-write + + + B_0x0 + SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag + 0x0 + + + B_0x1 + SPI data frames are interleaved with SS non active pulses when MIDI[3:0]>1 + 0x1 + + + + + AFCNTR + alternate function GPIOs control + + 31 + 1 + read-write + + + B_0x0 + The peripheral takes no control of GPIOs while it is disabled + 0x0 + + + B_0x1 + The peripheral keeps always control of all associated GPIOs + 0x1 + + + + + + + SPI_IER + SPI_IER + SPI/I2S interrupt enable register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RXPIE + RXP interrupt enable + 0 + 1 + read-write + + + B_0x0 + RXP interrupt disabled + 0x0 + + + B_0x1 + RXP interrupt enabled + 0x1 + + + + + TXPIE + TXP interrupt enable + + 1 + 1 + read-write + + + B_0x0 + TXP interrupt disabled + 0x0 + + + B_0x1 + TXP interrupt enabled + 0x1 + + + + + DXPIE + DXP interrupt enabled + + 2 + 1 + read-write + + + B_0x0 + DXP interrupt disabled + 0x0 + + + B_0x1 + DXP interrupt enabled + 0x1 + + + + + EOTIE + EOT, SUSP and TXC interrupt enable + 3 + 1 + read-write + + + B_0x0 + EOT/SUSP/TXC interrupt disabled + 0x0 + + + B_0x1 + EOT/SUSP/TXC interrupt enabled + 0x1 + + + + + TXTFIE + TXTFIE interrupt enable + 4 + 1 + read-write + + + B_0x0 + TXTF interrupt disabled + 0x0 + + + B_0x1 + TXTF interrupt enabled + 0x1 + + + + + UDRIE + UDR interrupt enable + 5 + 1 + read-write + + + B_0x0 + UDR interrupt disabled + 0x0 + + + B_0x1 + UDR interrupt enabled + 0x1 + + + + + OVRIE + OVR interrupt enable + 6 + 1 + read-write + + + B_0x0 + OVR interrupt disabled + 0x0 + + + B_0x1 + OVR interrupt enabled + 0x1 + + + + + CRCEIE + CRC error interrupt enable + 7 + 1 + read-write + + + B_0x0 + CRC interrupt disabled + 0x0 + + + B_0x1 + CRC interrupt enabled + 0x1 + + + + + TIFREIE + TIFRE interrupt enable + 8 + 1 + read-write + + + B_0x0 + TIFRE interrupt disabled + 0x0 + + + B_0x1 + TIFRE interrupt enabled + 0x1 + + + + + MODFIE + mode Fault interrupt enable + 9 + 1 + read-write + + + B_0x0 + MODF interrupt disabled + 0x0 + + + B_0x1 + MODF interrupt enabled + 0x1 + + + + + + + SPI_SR + SPI_SR + SPI/I2S status register + 0x14 + 0x20 + read-only + 0x00001002 + 0xFFFFFFFF + + + RXP + Rx-packet available + + 0 + 1 + read-only + + + B_0x0 + RxFIFO is empty or an incomplete data packet is received + 0x0 + + + B_0x1 + RxFIFO contains at least one data packet + 0x1 + + + + + TXP + Tx-packet space available + + 1 + 1 + read-only + + + B_0x0 + not enough free space at TxFIFO to host next data packet + 0x0 + + + B_0x1 + enough free space at TxFIFO to host at least one data packet + 0x1 + + + + + DXP + duplex packet + + 2 + 1 + read-only + + + B_0x0 + TxFIFO is Full and/or RxFIFO is Empty + 0x0 + + + B_0x1 + both TxFIFO has space for write and RxFIFO contains for read a single packet at least + 0x1 + + + + + EOT + end of transfer + + 3 + 1 + read-only + + + B_0x0 + transfer is ongoing or not started + 0x0 + + + B_0x1 + transfer complete + 0x1 + + + + + TXTF + transmission transfer filled + + 4 + 1 + read-only + + + B_0x0 + upload of TxFIFO is ongoing or not started + 0x0 + + + B_0x1 + TxFIFO upload is finished + 0x1 + + + + + UDR + underrun + + 5 + 1 + read-only + + + B_0x0 + no underrun + 0x0 + + + B_0x1 + underrun detected + 0x1 + + + + + OVR + overrun + + 6 + 1 + read-only + + + B_0x0 + no overrun + 0x0 + + + B_0x1 + overrun detected + 0x1 + + + + + CRCE + CRC error + + 7 + 1 + read-only + + + B_0x0 + no CRC error + 0x0 + + + B_0x1 + CRC error detected + 0x1 + + + + + TIFRE + TI frame format error + + 8 + 1 + read-only + + + B_0x0 + no TI Frame Error + 0x0 + + + B_0x1 + TI frame error detected + 0x1 + + + + + MODF + mode fault + + 9 + 1 + read-only + + + B_0x0 + no mode fault + 0x0 + + + B_0x1 + mode fault detected. + 0x1 + + + + + SUSP + suspension status + + 11 + 1 + read-only + + + B_0x0 + SPI not suspended (master mode active or other mode). + 0x0 + + + B_0x1 + Master mode is suspended (current frame completed). + 0x1 + + + + + TXC + TxFIFO transmission complete + + 12 + 1 + read-only + + + B_0x0 + current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going. + 0x0 + + + B_0x1 + last TxFIFO frame transmission complete + 0x1 + + + + + RXPLVL + RxFIFO packing level + + 13 + 2 + read-only + + + B_0x0 + no next frame is available at RxFIFO + 0x0 + + + B_0x1 + 1 frame is available + 0x1 + + + B_0x2 + 2 frames are available* + 0x2 + + + B_0x3 + 3 frames are available* + 0x3 + + + + + RXWNE + RxFIFO word not empty + + 15 + 1 + read-only + + + B_0x0 + less than four bytes of RxFIFO space is occupied by data + 0x0 + + + B_0x1 + at least four bytes of RxFIFO space is occupied by data + 0x1 + + + + + CTSIZE + number of data frames remaining in current TSIZE session + + 16 + 16 + read-only + + + + + SPI_IFCR + SPI_IFCR + SPI/I2S interrupt/status flags clear register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + EOTC + end of transfer flag clear + + 3 + 1 + write-only + + + TXTFC + transmission transfer filled flag clear + + 4 + 1 + write-only + + + UDRC + underrun flag clear + + 5 + 1 + write-only + + + OVRC + overrun flag clear + + 6 + 1 + write-only + + + CRCEC + CRC error flag clear + + 7 + 1 + write-only + + + TIFREC + TI frame format error flag clear + + 8 + 1 + write-only + + + MODFC + mode fault flag clear + + 9 + 1 + write-only + + + SUSPC + Suspend flag clear + + 11 + 1 + write-only + + + + + SPI_TXDR + SPI_TXDR + /I2SSPI/I2S transmit data register + 0x20 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TXDR + transmit data register + + 0 + 32 + write-only + + + + + SPI_RXDR + SPI_RXDR + SPI/I2S receive data register + 0x30 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXDR + receive data register + + 0 + 32 + read-only + + + + + SPI_CRCPOLY + SPI_CRCPOLY + SPI/I2S polynomial register + 0x40 + 0x20 + read-write + 0x00000107 + 0xFFFFFFFF + + + CRCPOLY + CRC polynomial register + + 0 + 32 + read-write + + + + + SPI_TXCRC + SPI_TXCRC + SPI/I2S transmitter CRC register + 0x44 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TXCRC + CRC register for transmitter + + 0 + 32 + read-only + + + + + SPI_RXCRC + SPI_RXCRC + SPI/I2S receiver CRC register + 0x48 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXCRC + CRC register for receiver + + 0 + 32 + read-only + + + + + SPI_UDRDR + SPI_UDRDR + SPI underrun data register + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UDRDR + data at slave underrun condition + + 0 + 32 + read-write + + + + + SPI_I2SCFGR + SPI_I2SCFGR + SPI/I2S configuration register + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + I2SMOD + I2S mode selection + 0 + 1 + read-write + + + B_0x0 + SPI mode is selected + 0x0 + + + B_0x1 + I2S/PCM mode is selected + 0x1 + + + + + I2SCFG + I2S configuration mode + + 1 + 3 + read-write + + + B_0x0 + slave - transmit + 0x0 + + + B_0x1 + slave - receive + 0x1 + + + B_0x2 + master - transmit + 0x2 + + + B_0x3 + master - receive + 0x3 + + + B_0x4 + slave - Full Duplex + 0x4 + + + B_0x5 + master - Full Duplex + 0x5 + + + + + I2SSTD + Iless thansup>2less than/sup>S standard selection + + 4 + 2 + read-write + + + B_0x0 + Iless thansup>2less than/sup>S Philips standard. + 0x0 + + + B_0x1 + MSB justified standard (left justified) + 0x1 + + + B_0x2 + LSB justified standard (right justified) + 0x2 + + + B_0x3 + PCM standard + 0x3 + + + + + PCMSYNC + PCM frame synchronization + 7 + 1 + read-write + + + B_0x0 + short frame synchronization + 0x0 + + + B_0x1 + long frame synchronization + 0x1 + + + + + DATLEN + data length to be transferred. + 8 + 2 + read-write + + + B_0x0 + 16-bit data length + 0x0 + + + B_0x1 + 24-bit data length + 0x1 + + + B_0x2 + 32-bit data length + 0x2 + + + B_0x3 + Not allowed + 0x3 + + + + + CHLEN + channel length (number of bits per audio channel) + 10 + 1 + read-write + + + B_0x0 + 16-bit wide + 0x0 + + + B_0x1 + 32-bit wide + 0x1 + + + + + CKPOL + serial audio clock polarity + 11 + 1 + read-write + + + B_0x0 + the signals generated by the SPI/I2S (i. + 0x0 + + + B_0x1 + the signals generated by the SPI/I2S (i. + 0x1 + + + + + FIXCH + fixed channel length in slave + 12 + 1 + read-write + + + B_0x0 + the channel length in slave mode is different from 16 or 32 bits (CHLEN must be set) + 0x0 + + + B_0x1 + the channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN) + 0x1 + + + + + WSINV + word select inversion + + 13 + 1 + read-write + + + B_0x0 + In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge. + 0x0 + + + B_0x1 + In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge. + 0x1 + + + + + DATFMT + data format + 14 + 1 + read-write + + + B_0x0 + The data inside the SPI_RXDR or SPI_TXDR are right aligned + 0x0 + + + B_0x1 + The data inside the SPI_RXDR or SPI_TXDR are left aligned. + 0x1 + + + + + I2SDIV + Iless thansup>2less than/sup>S linear prescaler + + 16 + 8 + read-write + + + ODD + odd factor for the prescaler + + 24 + 1 + read-write + + + B_0x0 + Real divider value is = I2SDIV *2 + 0x0 + + + B_0x1 + Real divider value is = (I2SDIV * 2) + 1 + 0x1 + + + + + MCKOE + master clock output enable + 25 + 1 + read-write + + + B_0x0 + Master clock output is disabled + 0x0 + + + B_0x1 + Master clock output is enabled + 0x1 + + + + + + + + + SPI_S + 0X50013000 + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 56 + + + + SPI2_S + 0x50003800 + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 57 + + + + SPI3_S + 0x50003C00 + + + SPI4 + 0x40014C00 + + SPI4 + SPI4 global interrupt + 82 + + + + SPI4_S + 0x50014C00 + + + TAMP + TAMP register block + TAMP + 0x44007c00 + + 0x0 + 0x400 + registers + + + TAMP + Tamper global interrupts + 4 + + + + TAMP_CR1 + TAMP_CR1 + TAMP control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TAMP1E + Tamper detection on TAMP_IN1 enable + 0 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN1 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN1 is enabled. + 0x1 + + + + + TAMP2E + Tamper detection on TAMP_IN2 enableless thansup>(1)less than/sup> + 1 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN2 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN2 is enabled. + 0x1 + + + + + TAMP3E + Tamper detection on TAMP_IN3 enableless thansup>(1)less than/sup> + 2 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN3 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN3 is enabled. + 0x1 + + + + + TAMP4E + Tamper detection on TAMP_IN4 enableless thansup>(1)less than/sup> + 3 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN4 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN4 is enabled. + 0x1 + + + + + TAMP5E + Tamper detection on TAMP_IN5 enableless thansup>(1)less than/sup> + 4 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN5 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN5 is enabled. + 0x1 + + + + + TAMP6E + Tamper detection on TAMP_IN6 enableless thansup>(1)less than/sup> + 5 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN6 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN6 is enabled. + 0x1 + + + + + TAMP7E + Tamper detection on TAMP_IN7 enableless thansup>(1)less than/sup> + 6 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN7 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN7 is enabled. + 0x1 + + + + + TAMP8E + Tamper detection on TAMP_IN8 enableless thansup>(1)less than/sup> + 7 + 1 + read-write + + + B_0x0 + Tamper detection on TAMP_IN8 is disabled. + 0x0 + + + B_0x1 + Tamper detection on TAMP_IN8 is enabled. + 0x1 + + + + + ITAMP1E + Internal tamper 1 enable + 16 + 1 + read-write + + + B_0x0 + Internal tamper 1 disabled. + 0x0 + + + B_0x1 + Internal tamper 1 enabled. + 0x1 + + + + + ITAMP2E + Internal tamper 2 enable + 17 + 1 + read-write + + + B_0x0 + Internal tamper 2 disabled. + 0x0 + + + B_0x1 + Internal tamper 2 enabled. + 0x1 + + + + + ITAMP3E + Internal tamper 3 enable + 18 + 1 + read-write + + + B_0x0 + Internal tamper 3 disabled. + 0x0 + + + B_0x1 + Internal tamper 3 enabled. + 0x1 + + + + + ITAMP4E + Internal tamper 4 enable + 19 + 1 + read-write + + + B_0x0 + Internal tamper 4 disabled. + 0x0 + + + B_0x1 + Internal tamper 4 enabled. + 0x1 + + + + + ITAMP5E + Internal tamper 5 enable + 20 + 1 + read-write + + + B_0x0 + Internal tamper 5 disabled. + 0x0 + + + B_0x1 + Internal tamper 5 enabled. + 0x1 + + + + + ITAMP6E + Internal tamper 6 enable + 21 + 1 + read-write + + + B_0x0 + Internal tamper 6 disabled. + 0x0 + + + B_0x1 + Internal tamper 6 enabled. + 0x1 + + + + + ITAMP7E + Internal tamper 7 enable + 22 + 1 + read-write + + + B_0x0 + Internal tamper 7 disabled. + 0x0 + + + B_0x1 + Internal tamper 7 enabled + 0x1 + + + + + ITAMP8E + Internal tamper 8 enable + 23 + 1 + read-write + + + B_0x0 + Internal tamper 8 disabled. + 0x0 + + + B_0x1 + Internal tamper 8 enabled. + 0x1 + + + + + ITAMP9E + Internal tamper 9 enable + 24 + 1 + read-write + + + B_0x0 + Internal tamper 9 disabled. + 0x0 + + + B_0x1 + Internal tamper 9 enabled. + 0x1 + + + + + ITAMP11E + Internal tamper 11 enable + 26 + 1 + read-write + + + B_0x0 + Internal tamper 11 disabled. + 0x0 + + + B_0x1 + Internal tamper 11 enabled. + 0x1 + + + + + ITAMP12E + Internal tamper 12 enable + 27 + 1 + read-write + + + B_0x0 + Internal tamper 12 disabled. + 0x0 + + + B_0x1 + Internal tamper 12 enabled. + 0x1 + + + + + ITAMP13E + Internal tamper 13 enable + 28 + 1 + read-write + + + B_0x0 + Internal tamper 13 disabled. + 0x0 + + + B_0x1 + Internal tamper 13 enabled. + 0x1 + + + + + ITAMP15E + Internal tamper 15 enable + 30 + 1 + read-write + + + B_0x0 + Internal tamper 15 disabled. + 0x0 + + + B_0x1 + Internal tamper 15 enabled. + 0x1 + + + + + + + TAMP_CR2 + TAMP_CR2 + TAMP control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TAMP1POM + Tamper 1 potential mode + 0 + 1 + read-write + + + B_0x0 + Tamper 1 event detection is in confirmed mode. + 0x0 + + + B_0x1 + Tamper 1 event detection is in potential mode. + 0x1 + + + + + TAMP2POM + Tamper 2 potential mode + 1 + 1 + read-write + + + B_0x0 + Tamper 2 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 2 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP3POM + Tamper 3 potential mode + 2 + 1 + read-write + + + B_0x0 + Tamper 3 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 3 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP4POM + Tamper 4 potential mode + 3 + 1 + read-write + + + B_0x0 + Tamper 4 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 4 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP5POM + Tamper 5 potential mode + 4 + 1 + read-write + + + B_0x0 + Tamper 5 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 5 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP6POM + Tamper 6 potential mode + 5 + 1 + read-write + + + B_0x0 + Tamper 6 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 6 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP7POM + Tamper 7 potential mode + 6 + 1 + read-write + + + B_0x0 + Tamper 7 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 7 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP8POM + Tamper 8 potential mode + 7 + 1 + read-write + + + B_0x0 + Tamper 8 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Tamper 8 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + TAMP1MSK + Tamper 1 mask + + 16 + 1 + read-write + + + B_0x0 + Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 1 event generates a trigger event. + 0x1 + + + + + TAMP2MSK + Tamper 2 mask + + 17 + 1 + read-write + + + B_0x0 + Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 2 event generates a trigger event. + 0x1 + + + + + TAMP3MSK + Tamper 3 mask + + 18 + 1 + read-write + + + B_0x0 + Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection. + 0x0 + + + B_0x1 + Tamper 3 event generates a trigger event. + 0x1 + + + + + BKBLOCK + Backup registers and device secretsless thansup>(1)less than/sup> access blocked + 22 + 1 + read-write + + + B_0x0 + backup registers and device secretsless thansup>(1)less than/sup> can be accessed if no tamper flag is set + 0x0 + + + B_0x1 + backup registers and device secretsless thansup>(1)less than/sup> cannot be accessed + 0x1 + + + + + BKERASE + Backup registers and device secretsless thansup>(1)less than/sup> erase + + 23 + 1 + write-only + + + TAMP1TRG + Active level for tamper 1 input + + 24 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 1 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 1 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP2TRG + Active level for tamper 2 input + + 25 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 2 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 2 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP3TRG + Active level for tamper 3 input + + 26 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 3 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 3 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP4TRG + Active level for tamper 4 input (active mode disabled) + + 27 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 4 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 4 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP5TRG + Active level for tamper 5 input (active mode disabled) + + 28 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 5 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 5 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP6TRG + Active level for tamper 6 input (active mode disabled) + + 29 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 6 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 6 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP7TRG + Active level for tamper 7 input (active mode disabled) + + 30 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 7 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 7 input staying high triggers a tamper detection event. + 0x1 + + + + + TAMP8TRG + Active level for tamper 8 input (active mode disabled) + + 31 + 1 + read-write + + + B_0x0 + If TAMPFLT different to 00 tamper 8 input staying low triggers a tamper detection event. + 0x0 + + + B_0x1 + If TAMPFLT different to 00 tamper 8 input staying high triggers a tamper detection event. + 0x1 + + + + + + + TAMP_CR3 + TAMP_CR3 + TAMP control register 3 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ITAMP1POM + Internal tamper 1 potential mode + 0 + 1 + read-write + + + B_0x0 + Internal tamper 1 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 1 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP2POM + Internal tamper 2 potential mode + 1 + 1 + read-write + + + B_0x0 + Internal tamper 2 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 2 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP3POM + Internal tamper 3 potential mode + 2 + 1 + read-write + + + B_0x0 + Internal tamper 3 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 3 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP4POM + Internal tamper 4 potential mode + 3 + 1 + read-write + + + B_0x0 + Internal tamper 4 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 4 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP5POM + Internal tamper 5 potential mode + 4 + 1 + read-write + + + B_0x0 + Internal tamper 5 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 5 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP6POM + Internal tamper 6 potential mode + 5 + 1 + read-write + + + B_0x0 + Internal tamper 6 event detection is in confirmed mode. + 0x0 + + + B_0x1 + Internal tamper 6 event detection is in potential mode. + 0x1 + + + + + ITAMP7POM + Internal tamper 7 potential mode + 6 + 1 + read-write + + + B_0x0 + Internal tamper 7 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 7 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP8POM + Internal tamper 8 potential mode + 7 + 1 + read-write + + + B_0x0 + Internal tamper 8 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 8 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP9POM + Internal tamper 9 potential mode + 8 + 1 + read-write + + + B_0x0 + Internal tamper 9 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 9 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP11POM + Internal tamper 11 potential mode + 10 + 1 + read-write + + + B_0x0 + Internal tamper 11 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 11 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP12POM + Internal tamper 12 potential mode + 11 + 1 + read-write + + + B_0x0 + Internal tamper 12 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 12 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP13POM + Internal tamper 13 potential mode + 12 + 1 + read-write + + + B_0x0 + Internal tamper 13 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 13 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + ITAMP15POM + Internal tamper 15 potential mode + 14 + 1 + read-write + + + B_0x0 + Internal tamper 15 event detection is in confirmed modeless thansup>(1)less than/sup>. + 0x0 + + + B_0x1 + Internal tamper 15 event detection is in potential modeless thansup>(2)less than/sup>. + 0x1 + + + + + + + TAMP_FLTCR + TAMP_FLTCR + TAMP filter control register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TAMPFREQ + Tamper sampling frequency + + 0 + 3 + read-write + + + B_0x0 + RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + 0x0 + + + B_0x1 + RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + 0x1 + + + B_0x2 + RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + 0x2 + + + B_0x3 + RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + 0x3 + + + B_0x4 + RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + 0x4 + + + B_0x5 + RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + 0x5 + + + B_0x6 + RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + 0x6 + + + B_0x7 + RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + 0x7 + + + + + TAMPFLT + TAMP_INx filter count + + 3 + 2 + read-write + + + B_0x0 + Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input). + 0x0 + + + B_0x1 + Tamper event is activated after 2 consecutive samples at the active level. + 0x1 + + + B_0x2 + Tamper event is activated after 4 consecutive samples at the active level. + 0x2 + + + B_0x3 + Tamper event is activated after 8 consecutive samples at the active level. + 0x3 + + + + + TAMPPRCH + TAMP_INx precharge duration + + 5 + 2 + read-write + + + B_0x0 + 1 RTCCLK cycle + 0x0 + + + B_0x1 + 2 RTCCLK cycles + 0x1 + + + B_0x2 + 4 RTCCLK cycles + 0x2 + + + B_0x3 + 8 RTCCLK cycles + 0x3 + + + + + TAMPPUDIS + TAMP_INx pull-up disable + + 7 + 1 + read-write + + + B_0x0 + Precharge TAMP_INx pins before sampling (enable internal pull-up) + 0x0 + + + B_0x1 + Disable precharge of TAMP_INx pins. + 0x1 + + + + + + + TAMP_ATCR1 + TAMP_ATCR1 + TAMP active tamper control register 1 + 0x10 + 0x20 + read-write + 0x00070000 + 0xFFFFFFFF + + + TAMP1AM + Tamper 1 active mode + 0 + 1 + read-write + + + B_0x0 + Tamper 1 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 1 detection mode is active. + 0x1 + + + + + TAMP2AM + Tamper 2 active mode + 1 + 1 + read-write + + + B_0x0 + Tamper 2 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 2 detection mode is active. + 0x1 + + + + + TAMP3AM + Tamper 3 active mode + 2 + 1 + read-write + + + B_0x0 + Tamper 3 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 3 detection mode is active. + 0x1 + + + + + TAMP4AM + Tamper 4 active mode + 3 + 1 + read-write + + + B_0x0 + Tamper 4 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 4 detection mode is active. + 0x1 + + + + + TAMP5AM + Tamper 5 active mode + 4 + 1 + read-write + + + B_0x0 + Tamper 5 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 5 detection mode is active. + 0x1 + + + + + TAMP6AM + Tamper 6 active mode + 5 + 1 + read-write + + + B_0x0 + Tamper 6 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 6 detection mode is active. + 0x1 + + + + + TAMP7AM + Tamper 7 active mode + 6 + 1 + read-write + + + B_0x0 + Tamper 7 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 7 detection mode is active. + 0x1 + + + + + TAMP8AM + Tamper 8 active mode + 7 + 1 + read-write + + + B_0x0 + Tamper 8 detection mode is passive. + 0x0 + + + B_0x1 + Tamper 8 detection mode is active. + 0x1 + + + + + ATOSEL1 + Active tamper shared output 1 selection + + 8 + 2 + read-write + + + B_0x0 + TAMPOUTSEL1 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL1 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL1 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL1 = TAMP_OUT4 + 0x3 + + + + + ATOSEL2 + Active tamper shared output 2 selection + + 10 + 2 + read-write + + + B_0x0 + TAMPOUTSEL2 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL2 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL2 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL2 = TAMP_OUT4 + 0x3 + + + + + ATOSEL3 + Active tamper shared output 3 selection + + 12 + 2 + read-write + + + B_0x0 + TAMPOUTSEL3 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL3 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL3 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL3 = TAMP_OUT4 + 0x3 + + + + + ATOSEL4 + Active tamper shared output 4 selection + + 14 + 2 + read-write + + + B_0x0 + TAMPOUTSEL4 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL4 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL4 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL4 = TAMP_OUT4 + 0x3 + + + + + ATCKSEL + Active tamper RTC asynchronous prescaler clock selection + + 16 + 4 + read-write + + + B_0x0 + RTCCLK is selected + 0x0 + + + B_0x1 + RTCCLK/2 is selected + 0x1 + + + B_0x2 + RTCCLK/4 is selected + 0x2 + + + B_0x3 + RTCCLK/8 is selected + 0x3 + + + B_0x4 + RTCCLK/16 is selected + 0x4 + + + B_0x5 + RTCCLK/32 is selected + 0x5 + + + B_0x6 + RTCCLK/64 is selected + 0x6 + + + B_0x7 + RTCCLK/128 is selected + 0x7 + + + B_0xB + RTCCLK/2048 is selected when (PREDIV_A+1) = 128 and (PREDIV_S+1) is a multiple of 16. + 0xB + + + + + ATPER + Active tamper output change period + + 24 + 3 + read-write + + + ATOSHARE + Active tamper output sharing + 30 + 1 + read-write + + + B_0x0 + Each active tamper input TAMP_INi is compared with its dedicated output TAMP_OUTi + 0x0 + + + B_0x1 + Each active tamper input TAMP_INi is compared with TAMPOUTSELi defined by ATOSELi bits. + 0x1 + + + + + FLTEN + Active tamper filter enable + 31 + 1 + read-write + + + B_0x0 + Active tamper filtering disable + 0x0 + + + B_0x1 + Active tamper filtering enable: a tamper event is detected when 2 comparison mismatches occur out of 4 consecutive samples. + 0x1 + + + + + + + TAMP_ATSEEDR + TAMP_ATSEEDR + TAMP active tamper seed register + 0x14 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + SEED + Pseudo-random generator seed value + + 0 + 32 + write-only + + + + + TAMP_ATOR + TAMP_ATOR + TAMP active tamper output register + 0x18 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + PRNG + Pseudo-random generator value + + 0 + 8 + read-only + + + SEEDF + Seed running flag + + 14 + 1 + read-only + + + INITS + Active tamper initialization status + + 15 + 1 + read-only + + + + + TAMP_ATCR2 + TAMP_ATCR2 + TAMP active tamper control register 2 + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ATOSEL1 + Active tamper shared output 1 selection + + 8 + 3 + read-write + + + B_0x0 + TAMPOUTSEL1 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL1 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL1 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL1 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL1 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL1 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL1 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL1 = TAMP_OUT8 + 0x7 + + + + + ATOSEL2 + Active tamper shared output 2 selection + + 11 + 3 + read-write + + + B_0x0 + TAMPOUTSEL2 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL2 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL2 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL2 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL2 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL2 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL2 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL2 = TAMP_OUT8 + 0x7 + + + + + ATOSEL3 + Active tamper shared output 3 selection + + 14 + 3 + read-write + + + B_0x0 + TAMPOUTSEL3 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL3 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL3 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL3 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL3 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL3 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL3 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL3 = TAMP_OUT8 + 0x7 + + + + + ATOSEL4 + Active tamper shared output 4 selection + + 17 + 3 + read-write + + + B_0x0 + TAMPOUTSEL4 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL4 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL4 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL4 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL4 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL4 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL4 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL4 = TAMP_OUT8 + 0x7 + + + + + ATOSEL5 + Active tamper shared output 5 selection + + 20 + 3 + read-write + + + B_0x0 + TAMPOUTSEL5 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL5 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL5 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL5 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL5 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL5 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL5 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL5 = TAMP_OUT8 + 0x7 + + + + + ATOSEL6 + Active tamper shared output 6 selection + + 23 + 3 + read-write + + + B_0x0 + TAMPOUTSEL6 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL6 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL6 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL6 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL6 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL6 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL6 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL6 = TAMP_OUT8 + 0x7 + + + + + ATOSEL7 + Active tamper shared output 7 selection + + 26 + 3 + read-write + + + B_0x0 + TAMPOUTSEL7 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL7 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL7 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL7 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL7 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL7 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL7 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL7 = TAMP_OUT8 + 0x7 + + + + + ATOSEL8 + Active tamper shared output 8 selection + + 29 + 3 + read-write + + + B_0x0 + TAMPOUTSEL8 = TAMP_OUT1 + 0x0 + + + B_0x1 + TAMPOUTSEL8 = TAMP_OUT2 + 0x1 + + + B_0x2 + TAMPOUTSEL8 = TAMP_OUT3 + 0x2 + + + B_0x3 + TAMPOUTSEL8 = TAMP_OUT4 + 0x3 + + + B_0x4 + TAMPOUTSEL8 = TAMP_OUT5 + 0x4 + + + B_0x5 + TAMPOUTSEL8 = TAMP_OUT6 + 0x5 + + + B_0x6 + TAMPOUTSEL8 = TAMP_OUT7 + 0x6 + + + B_0x7 + TAMPOUTSEL8 = TAMP_OUT8 + 0x7 + + + + + + + TAMP_SECCFGR + TAMP_SECCFGR + TAMP secure configuration register + 0x20 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKPRWSEC + Backup registers read/write protection offset + + 0 + 8 + read-write + + + CNT1SEC + Monotonic counter 1 secure protection + 15 + 1 + read-write + + + B_0x0 + Monotonic counter 1 (TAMP_COUNT1R) can be read and written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + Monotonic counter 1 (TAMP_COUNT1R) can be read and written only when the APB access is secure. + 0x1 + + + + + BKPWSEC + Backup registers write protection offset + + 16 + 8 + read-write + + + BHKLOCK + Boot hardware key lock + + 30 + 1 + read-write + + + B_0x0 + The Backup registers from TAMP_BKP0R to TAMP_BKP7R can be accessed according to the Protection zone they belong to. + 0x0 + + + B_0x1 + The backup registers from TAMP_BKP0R to TAMP_BKP7R cannot be accessed neither in read nor in write (they are read as 0 and write ignore). + 0x1 + + + + + TAMPSEC + Tamper protection (excluding monotonic counters and backup registers) + + 31 + 1 + read-write + + + B_0x0 + Tamper configuration and interrupt can be written when the APB access is secure or nonsecure. + 0x0 + + + B_0x1 + Tamper configuration and interrupt can be written only when the APB access is secure. + 0x1 + + + + + + + TAMP_PRIVCFGR + TAMP_PRIVCFGR + TAMP privilege configuration register + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT1PRIV + Monotonic counter 1 privilege protection + 15 + 1 + read-write + + + B_0x0 + Monotonic counter 1 (TAMP_COUNT1R) can be read and written when the APB access is privileged or non-privileged. + 0x0 + + + B_0x1 + Monotonic counter 1 (TAMP_COUNT1R) can be read and written only when the APB access is privileged. + 0x1 + + + + + BKPRWPRIV + Backup registers zone 1 privilege protection + 29 + 1 + read-write + + + B_0x0 + Backup registers zone 1 can be read and written with privileged or unprivileged access. + 0x0 + + + B_0x1 + Backup registers zone 1 can be read and written only with privileged access + 0x1 + + + + + BKPWPRIV + Backup registers zone 2 privilege protection + 30 + 1 + read-write + + + B_0x0 + Backup registers zone 2 can be written with privileged or unprivileged access. + 0x0 + + + B_0x1 + Backup registers zone 2 can be written only with privileged access. + 0x1 + + + + + TAMPPRIV + Tamper privilege protection (excluding backup registers) + + 31 + 1 + read-write + + + B_0x0 + Tamper configuration and interrupt can be written with privileged or unprivileged access. + 0x0 + + + B_0x1 + Tamper configuration and interrupt can be written only with privileged access. + 0x1 + + + + + + + TAMP_IER + TAMP_IER + TAMP interrupt enable register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TAMP1IE + Tamper 1 interrupt enable + 0 + 1 + read-write + + + B_0x0 + Tamper 1 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 1 interrupt enabled. + 0x1 + + + + + TAMP2IE + Tamper 2 interrupt enable + 1 + 1 + read-write + + + B_0x0 + Tamper 2 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 2 interrupt enabled. + 0x1 + + + + + TAMP3IE + Tamper 3 interrupt enable + 2 + 1 + read-write + + + B_0x0 + Tamper 3 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 3 interrupt enabled. + 0x1 + + + + + TAMP4IE + Tamper 4 interrupt enable + 3 + 1 + read-write + + + B_0x0 + Tamper 4 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 4 interrupt enabled. + 0x1 + + + + + TAMP5IE + Tamper 5 interrupt enable + 4 + 1 + read-write + + + B_0x0 + Tamper 5 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 5 interrupt enabled. + 0x1 + + + + + TAMP6IE + Tamper 6 interrupt enable + 5 + 1 + read-write + + + B_0x0 + Tamper 6 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 6 interrupt enabled. + 0x1 + + + + + TAMP7IE + Tamper 7interrupt enable + 6 + 1 + read-write + + + B_0x0 + Tamper 7 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 7interrupt enabled. + 0x1 + + + + + TAMP8IE + Tamper 8 interrupt enable + 7 + 1 + read-write + + + B_0x0 + Tamper 8 interrupt disabled. + 0x0 + + + B_0x1 + Tamper 8 interrupt enabled. + 0x1 + + + + + ITAMP1IE + Internal tamper 1 interrupt enable + 16 + 1 + read-write + + + B_0x0 + Internal tamper 1 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 1 interrupt enabled + 0x1 + + + + + ITAMP2IE + Internal tamper 2 interrupt enable + 17 + 1 + read-write + + + B_0x0 + Internal tamper 2 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 2 interrupt enabled. + 0x1 + + + + + ITAMP3IE + Internal tamper 3 interrupt enable + 18 + 1 + read-write + + + B_0x0 + Internal tamper 3 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 3 interrupt enabled. + 0x1 + + + + + ITAMP4IE + Internal tamper 4 interrupt enable + 19 + 1 + read-write + + + B_0x0 + Internal tamper 4 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 4 interrupt enabled. + 0x1 + + + + + ITAMP5IE + Internal tamper 5 interrupt enable + 20 + 1 + read-write + + + B_0x0 + Internal tamper 5 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 5 interrupt enabled. + 0x1 + + + + + ITAMP6IE + Internal tamper 6 interrupt enable + 21 + 1 + read-write + + + B_0x0 + Internal tamper 6 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 6 interrupt enabled. + 0x1 + + + + + ITAMP7IE + Internal tamper 7 interrupt enable + 22 + 1 + read-write + + + B_0x0 + Internal tamper 7 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 7 interrupt enabled. + 0x1 + + + + + ITAMP8IE + Internal tamper 8 interrupt enable + 23 + 1 + read-write + + + B_0x0 + Internal tamper 8 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 8 interrupt enabled. + 0x1 + + + + + ITAMP9IE + Internal tamper 9 interrupt enable + 24 + 1 + read-write + + + B_0x0 + Internal tamper 9 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 9 interrupt enabled. + 0x1 + + + + + ITAMP11IE + Internal tamper 11 interrupt enable + 26 + 1 + read-write + + + B_0x0 + Internal tamper 11 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 11 interrupt enabled. + 0x1 + + + + + ITAMP12IE + Internal tamper 12 interrupt enable + 27 + 1 + read-write + + + B_0x0 + Internal tamper 12 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 12 interrupt enabled. + 0x1 + + + + + ITAMP13IE + Internal tamper 13 interrupt enable + 28 + 1 + read-write + + + B_0x0 + Internal tamper 13 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 13 interrupt enabled. + 0x1 + + + + + ITAMP15IE + Internal tamper 15 interrupt enable + 30 + 1 + read-write + + + B_0x0 + Internal tamper 15 interrupt disabled. + 0x0 + + + B_0x1 + Internal tamper 15 interrupt enabled. + 0x1 + + + + + + + TAMP_SR + TAMP_SR + TAMP status register + 0x30 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TAMP1F + TAMP1 detection flag + + 0 + 1 + read-only + + + TAMP2F + TAMP2 detection flag + + 1 + 1 + read-only + + + TAMP3F + TAMP3 detection flag + + 2 + 1 + read-only + + + TAMP4F + TAMP4 detection flag + + 3 + 1 + read-only + + + TAMP5F + TAMP5 detection flag + + 4 + 1 + read-only + + + TAMP6F + TAMP6 detection flag + + 5 + 1 + read-only + + + TAMP7F + TAMP7 detection flag + + 6 + 1 + read-only + + + TAMP8F + TAMP8 detection flag + + 7 + 1 + read-only + + + ITAMP1F + Internal tamper 1 flag + + 16 + 1 + read-only + + + ITAMP2F + Internal tamper 2 flag + + 17 + 1 + read-only + + + ITAMP3F + Internal tamper 3 flag + + 18 + 1 + read-only + + + ITAMP4F + Internal tamper 4 flag + + 19 + 1 + read-only + + + ITAMP5F + Internal tamper 5 flag + + 20 + 1 + read-only + + + ITAMP6F + Internal tamper 6 flag + + 21 + 1 + read-only + + + ITAMP7F + Internal tamper 7 flag + + 22 + 1 + read-only + + + ITAMP8F + Internal tamper 8 flag + + 23 + 1 + read-only + + + ITAMP9F + Internal tamper 9 flag + + 24 + 1 + read-only + + + ITAMP11F + Internal tamper 11 flag + + 26 + 1 + read-only + + + ITAMP12F + Internal tamper 12 flag + + 27 + 1 + read-only + + + ITAMP13F + Internal tamper 13 flag + + 28 + 1 + read-only + + + ITAMP15F + Internal tamper 15 flag + + 30 + 1 + read-write + + + + + TAMP_MISR + TAMP_MISR + TAMP nonsecure masked interrupt status register + 0x34 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TAMP1MF + TAMP1 nonsecure interrupt masked flag + + 0 + 1 + read-only + + + TAMP2MF + TAMP2 nonsecure interrupt masked flag + + 1 + 1 + read-only + + + TAMP3MF + TAMP3 nonsecure interrupt masked flag + + 2 + 1 + read-only + + + TAMP4MF + TAMP4 nonsecure interrupt masked flag + + 3 + 1 + read-only + + + TAMP5MF + TAMP5 nonsecure interrupt masked flag + + 4 + 1 + read-only + + + TAMP6MF + TAMP6 nonsecure interrupt masked flag + + 5 + 1 + read-only + + + TAMP7MF + TAMP7 nonsecure interrupt masked flag + + 6 + 1 + read-only + + + TAMP8MF + TAMP8 nonsecure interrupt masked flag + + 7 + 1 + read-only + + + ITAMP1MF + Internal tamper 1 nonsecure interrupt masked flag + + 16 + 1 + read-only + + + ITAMP2MF + Internal tamper 2 nonsecure interrupt masked flag + + 17 + 1 + read-only + + + ITAMP3MF + Internal tamper 3 nonsecure interrupt masked flag + + 18 + 1 + read-only + + + ITAMP4MF + Internal tamper 4 nonsecure interrupt masked flag + + 19 + 1 + read-only + + + ITAMP5MF + Internal tamper 5 nonsecure interrupt masked flag + + 20 + 1 + read-only + + + ITAMP6MF + Internal tamper 6 nonsecure interrupt masked flag + + 21 + 1 + read-only + + + ITAMP7MF + Internal tamper 7 tamper nonsecure interrupt masked flag + + 22 + 1 + read-only + + + ITAMP8MF + Internal tamper 8 nonsecure interrupt masked flag + + 23 + 1 + read-only + + + ITAMP9MF + internal tamper 9 nonsecure interrupt masked flag + + 24 + 1 + read-only + + + ITAMP11MF + internal tamper 11 nonsecure interrupt masked flag + + 26 + 1 + read-only + + + ITAMP12MF + internal tamper 12 nonsecure interrupt masked flag + + 27 + 1 + read-only + + + ITAMP13MF + internal tamper 13 nonsecure interrupt masked flag + + 28 + 1 + read-only + + + ITAMP15MF + internal tamper 15 nonsecure interrupt masked flag + + 30 + 1 + read-only + + + + + TAMP_SMISR + TAMP_SMISR + TAMP secure masked interrupt status register + 0x38 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TAMP1MF + TAMP1 secure interrupt masked flag + + 0 + 1 + read-only + + + TAMP2MF + TAMP2 secure interrupt masked flag + + 1 + 1 + read-only + + + TAMP3MF + TAMP3 secure interrupt masked flag + + 2 + 1 + read-only + + + TAMP4MF + TAMP4 secure interrupt masked flag + + 3 + 1 + read-only + + + TAMP5MF + TAMP5 secure interrupt masked flag + + 4 + 1 + read-only + + + TAMP6MF + TAMP6 secure interrupt masked flag + + 5 + 1 + read-only + + + TAMP7MF + TAMP7 secure interrupt masked flag + + 6 + 1 + read-only + + + TAMP8MF + TAMP8 secure interrupt masked flag + + 7 + 1 + read-only + + + ITAMP1MF + Internal tamper 1 secure interrupt masked flag + + 16 + 1 + read-only + + + ITAMP2MF + Internal tamper 2 secure interrupt masked flag + + 17 + 1 + read-only + + + ITAMP3MF + Internal tamper 3 secure interrupt masked flag + + 18 + 1 + read-only + + + ITAMP4MF + Internal tamper 4 secure interrupt masked flag + + 19 + 1 + read-only + + + ITAMP5MF + Internal tamper 5 secure interrupt masked flag + + 20 + 1 + read-only + + + ITAMP6MF + Internal tamper 6 secure interrupt masked flag + + 21 + 1 + read-only + + + ITAMP7MF + Internal tamper 7 secure interrupt masked flag + + 22 + 1 + read-only + + + ITAMP8MF + Internal tamper 8 secure interrupt masked flag + + 23 + 1 + read-only + + + ITAMP9MF + internal tamper 9 secure interrupt masked flag + + 24 + 1 + read-only + + + ITAMP11MF + internal tamper 11 secure interrupt masked flag + + 26 + 1 + read-only + + + ITAMP12MF + internal tamper 12 secure interrupt masked flag + + 27 + 1 + read-only + + + ITAMP13MF + internal tamper 13 secure interrupt masked flag + + 28 + 1 + read-only + + + ITAMP15MF + internal tamper 15 secure interrupt masked flag + + 30 + 1 + read-only + + + + + TAMP_SCR + TAMP_SCR + TAMP status clear register + 0x3C + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + CTAMP1F + Clear TAMP1 detection flag + + 0 + 1 + write-only + + + CTAMP2F + Clear TAMP2 detection flag + + 1 + 1 + write-only + + + CTAMP3F + Clear TAMP3 detection flag + + 2 + 1 + write-only + + + CTAMP4F + Clear TAMP4 detection flag + + 3 + 1 + write-only + + + CTAMP5F + Clear TAMP5 detection flag + + 4 + 1 + write-only + + + CTAMP6F + Clear TAMP6 detection flag + + 5 + 1 + write-only + + + CTAMP7F + Clear TAMP7 detection flag + + 6 + 1 + write-only + + + CTAMP8F + Clear TAMP8 detection flag + + 7 + 1 + write-only + + + CITAMP1F + Clear ITAMP1 detection flag + + 16 + 1 + write-only + + + CITAMP2F + Clear ITAMP2 detection flag + + 17 + 1 + write-only + + + CITAMP3F + Clear ITAMP3 detection flag + + 18 + 1 + write-only + + + CITAMP4F + Clear ITAMP4 detection flag + + 19 + 1 + write-only + + + CITAMP5F + Clear ITAMP5 detection flag + + 20 + 1 + write-only + + + CITAMP6F + Clear ITAMP6 detection flag + + 21 + 1 + write-only + + + CITAMP7F + Clear ITAMP7 detection flag + + 22 + 1 + write-only + + + CITAMP8F + Clear ITAMP8 detection flag + + 23 + 1 + write-only + + + CITAMP9F + Clear ITAMP9 detection flag + + 24 + 1 + write-only + + + CITAMP11F + Clear ITAMP11 detection flag + + 26 + 1 + write-only + + + CITAMP12F + Clear ITAMP12 detection flag + + 27 + 1 + write-only + + + CITAMP13F + Clear ITAMP13 detection flag + + 28 + 1 + write-only + + + CITAMP15F + Clear ITAMP15 detection flag + + 30 + 1 + write-only + + + + + TAMP_COUNT1R + TAMP_COUNT1R + TAMP monotonic counter 1 register + 0x040 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + COUNT + This register is read-only only and is incremented by one when a write access is done to this register. + 0 + 32 + read-only + + + + + TAMP_OR + TAMP_OR + TAMP option register + 0x50 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OUT3_RMP + TAMP_OUT3 mapping + 1 + 2 + read-write + + + B_0x0 + TAMP_OUT3 is on PC13 + 0x0 + + + B_0x1 + TAMP_OUT3 is on PI8 + 0x1 + + + B_0x2 + TAMP_OUT3 is on PE3 + 0x2 + + + B_0x3 + TAMP_OUT3 is on PA2 + 0x3 + + + + + OUT5_RMP + TAMP_OUT5 mapping + 3 + 1 + read-write + + + B_0x0 + TAMP_OUT5 is on PI11 + 0x0 + + + B_0x1 + TAMP_OUT5 is on PC1 + 0x1 + + + + + IN2_RMP + TAMP_IN2 mapping + 8 + 1 + read-write + + + B_0x0 + TAMP_IN2 is on PA0 + 0x0 + + + B_0x1 + TAMP_IN2 is on PI8 + 0x1 + + + + + IN3_RMP + TAMP_IN3 mapping + 9 + 1 + read-write + + + B_0x0 + TAMP_IN3 is on PC1 + 0x0 + + + B_0x1 + TAMP_IN3 is on PE6 + 0x1 + + + + + IN4_RMP + TAMP_IN4 mapping + 10 + 1 + read-write + + + B_0x0 + TAMP_IN4 is on PA2 + 0x0 + + + B_0x1 + TAMP_IN4 is on PI11 + 0x1 + + + + + + + TAMP_RPCFGR + TAMP_RPCFGR + TAMP resources protection configuration register + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RPCFG0 + Configurable resource 0 protection + 0 + 1 + read-write + + + B_0x0 + Resource 0 is not included in the device secrets protected by TAMP peripheral + 0x0 + + + B_0x1 + Resource 0 is included in the device secrets protected by TAMP peripheral + 0x1 + + + + + + + TAMP_BKP0R + TAMP_BKP0R + TAMP backup 0 register + 0x100 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP1R + TAMP_BKP1R + TAMP backup 1 register + 0x104 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP2R + TAMP_BKP2R + TAMP backup 2 register + 0x108 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP3R + TAMP_BKP3R + TAMP backup 3 register + 0x10C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP4R + TAMP_BKP4R + TAMP backup 4 register + 0x110 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP5R + TAMP_BKP5R + TAMP backup 5 register + 0x114 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP6R + TAMP_BKP6R + TAMP backup 6 register + 0x118 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP7R + TAMP_BKP7R + TAMP backup 7 register + 0x11C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP8R + TAMP_BKP8R + TAMP backup 8 register + 0x120 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP9R + TAMP_BKP9R + TAMP backup 9 register + 0x124 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP10R + TAMP_BKP10R + TAMP backup 10 register + 0x128 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP11R + TAMP_BKP11R + TAMP backup 11 register + 0x12C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP12R + TAMP_BKP12R + TAMP backup 12 register + 0x130 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP13R + TAMP_BKP13R + TAMP backup 13 register + 0x134 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP14R + TAMP_BKP14R + TAMP backup 14 register + 0x138 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP15R + TAMP_BKP15R + TAMP backup 15 register + 0x13C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP16R + TAMP_BKP16R + TAMP backup 16 register + 0x140 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP17R + TAMP_BKP17R + TAMP backup 17 register + 0x144 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP18R + TAMP_BKP18R + TAMP backup 18 register + 0x148 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP19R + TAMP_BKP19R + TAMP backup 19 register + 0x14C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP20R + TAMP_BKP20R + TAMP backup 20 register + 0x150 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP21R + TAMP_BKP21R + TAMP backup 21 register + 0x154 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP22R + TAMP_BKP22R + TAMP backup 22 register + 0x158 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP23R + TAMP_BKP23R + TAMP backup 23 register + 0x15C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP24R + TAMP_BKP24R + TAMP backup 24 register + 0x160 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP25R + TAMP_BKP25R + TAMP backup 25 register + 0x164 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP26R + TAMP_BKP26R + TAMP backup 26 register + 0x168 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP27R + TAMP_BKP27R + TAMP backup 27 register + 0x16C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP28R + TAMP_BKP28R + TAMP backup 28 register + 0x170 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP29R + TAMP_BKP29R + TAMP backup 29 register + 0x174 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP30R + TAMP_BKP30R + TAMP backup 30 register + 0x178 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + TAMP_BKP31R + TAMP_BKP31R + TAMP backup 31 register + 0x17C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BKP + The application can write or read data to and from these registers. + 0 + 32 + read-write + + + + + + + TAMP_S + 0X54007C00 + + + TIM1 + TIM1 address block description + TIM1 + 0x40012c00 + + 0x0 + 0x3E4 + registers + + + TIM1_CC + TIM1 capture compare interrupt + 44 + + + TIM1_TRGI_COM_DIR_IDX + TIM1 trigger and commutation/TIM1 Direction Change interrupt/TIM1 Index + 43 + + + TIM1_UPD + TIM1 Update + 42 + + + TIM1_BRK_TERR_IERR + TIM1 Break/TIM1 Transition error/TIM1 Index error + 41 + + + + TIM1_CR1 + TIM1_CR1 + TIM1 control register 1 + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub>=tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub>=2*tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub>=4*tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM1_CR2 + TIM1_CR2 + TIM1 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCPC + Capture/compare preloaded control + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[2:0]: Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input + 0x0 + + + B_0x1 + tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input + 0x1 + + + + + OIS1 + Output idle state 1 (tim_oc1 output) + + 8 + 1 + read-write + + + B_0x0 + tim_oc1=0 (after a dead-time) when MOE=0 + 0x0 + + + B_0x1 + tim_oc1=1 (after a dead-time) when MOE=0 + 0x1 + + + + + OIS1N + Output idle state 1 (tim_oc1n output) + + 9 + 1 + read-write + + + B_0x0 + tim_oc1n=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + tim_oc1n=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output idle state 2 (tim_oc2 output) + + 10 + 1 + read-write + + + OIS2N + Output idle state 2 (tim_oc2n output) + + 11 + 1 + read-write + + + OIS3 + Output idle state 3 (tim_oc3n output) + + 12 + 1 + read-write + + + OIS3N + Output idle state 3 (tim_oc3n output) + + 13 + 1 + read-write + + + OIS4 + Output idle state 4 (tim_oc4 output) + + 14 + 1 + read-write + + + OIS4N + Output idle state 4 (tim_oc4n output) + + 15 + 1 + read-write + + + OIS5 + Output idle state 5 (tim_oc5 output) + + 16 + 1 + read-write + + + OIS6 + Output idle state 6 (tim_oc6 output) + + 18 + 1 + read-write + + + MMS2 + Master mode selection 2 + + 20 + 4 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo2). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo2). + 0x1 + + + B_0x2 + Update - the update event is selected as trigger output (tim_trgo2). + 0x2 + + + B_0x3 + Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (tim_trgo2). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo2) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo2) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo2) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo2) + 0x7 + + + B_0x8 + Compare - tim_oc5refc signal is used as trigger output (tim_trgo2) + 0x8 + + + B_0x9 + Compare - tim_oc6refc signal is used as trigger output (tim_trgo2) + 0x9 + + + B_0xA + Compare Pulse - tim_oc4refc rising or falling edges generate pulses on tim_trgo2 + 0xA + + + B_0xB + Compare pulse - tim_oc6refc rising or falling edges generate pulses on tim_trgo2 + 0xB + + + B_0xC + Compare pulse - tim_oc4refc or tim_oc6refc rising edges generate pulses on tim_trgo2 + 0xC + + + B_0xD + Compare pulse - tim_oc4refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2 + 0xD + + + B_0xE + Compare pulse - tim_oc5refc or tim_oc6refc rising edges generate pulses on tim_trgo2 + 0xE + + + B_0xF + Compare pulse - tim_oc5refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2 + 0xF + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM1_SMCR + TIM1_SMCR + TIM1 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Quadrature encoder mode 1, x2 mode- Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Quadrature encoder mode 2, x2 mode - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Quadrature encoder mode 3, x4 mode - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal Trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal Trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal Trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 Edge Detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External Trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etr_in frequency divided by 2 + 0x1 + + + B_0x2 + tim_etr_in frequency divided by 4 + 0x2 + + + B_0x3 + tim_etr_in frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge. + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge. + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM1_DIER + TIM1_DIER + TIM1 DMA/interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled + 0x0 + + + B_0x1 + CC3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled + 0x0 + + + B_0x1 + CC4 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index Change interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction Change interrupt disabled + 0x0 + + + B_0x1 + Direction Change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM1_SR + TIM1_SR + TIM1 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/compare 4 interrupt flag + + 4 + 1 + read-write + + + COMIF + COM interrupt flag + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred. + 0x0 + + + B_0x1 + COM interrupt pending. + 0x1 + + + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + BIF + Break interrupt flag + + 7 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break input. + 0x1 + + + + + B2IF + Break 2 interrupt flag + + 8 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break 2 input. + 0x1 + + + + + CC1OF + Capture/compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/compare 4 overcapture flag + + 12 + 1 + read-write + + + SBIF + System break interrupt flag + + 13 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the system break input. + 0x1 + + + + + CC5IF + Compare 5 interrupt flag + + 16 + 1 + read-write + + + CC6IF + Compare 6 interrupt flag + + 17 + 1 + read-write + + + IDXF + Index interrupt flag + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM1_EGR + TIM1_EGR + TIM1 event generation register + 0x014 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + COMG + Capture/compare control update generation + + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits update (providing CCPC bit is set) + 0x1 + + + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + BG + Break generation + + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + B2G + Break 2 generation + + 8 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break 2 event is generated. + 0x1 + + + + + + + TIM1_CCMR1 + TIM1_CCMR1 + TIM1 capture/compare mode register 1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/compare 1 Selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM1_CCMR1_ALTERNATE1 + TIM1_CCMR1_ALTERNATE1 + TIM1 capture/compare mode register 1 + TIM1_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int signal + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int signal (tim_ocref_clr input or tim_etrf input) + 0x1 + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM1_CCMR2 + TIM1_CCMR2 + TIM1 capture/compare mode register 2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM1_CCMR2_ALTERNATE1 + TIM1_CCMR2_ALTERNATE1 + TIM1 capture/compare mode register 2 + TIM1_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR3 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 3 to active level on match. + 0x1 + + + B_0x2 + Set channel 3 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc3ref toggles when TIMx_CNT=TIMx_CCR3. + 0x3 + + + B_0x4 + Force inactive level - tim_oc3ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc3ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNTless thanTIMx_CCR3 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 3 is inactive as long as TIMx_CNTless thanTIMx_CCR3 else active. + 0x7 + + + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM1_CCER + TIM1_CCER + TIM1 capture/compare enable register + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1E + Capture/compare 1 output enable + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/compare 1 output polarity + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/compare 1 complementary output enable + + 2 + 1 + read-write + + + B_0x0 + Off - tim_oc1n is not active. + 0x0 + + + B_0x1 + On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/compare 1 complementary output polarity + + 3 + 1 + read-write + + + B_0x0 + tim_oc1n active high. + 0x0 + + + B_0x1 + tim_oc1n active low. + 0x1 + + + + + CC2E + Capture/compare 2 output enable + + 4 + 1 + read-write + + + CC2P + Capture/compare 2 output polarity + + 5 + 1 + read-write + + + CC2NE + Capture/compare 2 complementary output enable + + 6 + 1 + read-write + + + CC2NP + Capture/compare 2 complementary output polarity + + 7 + 1 + read-write + + + CC3E + Capture/compare 3 output enable + + 8 + 1 + read-write + + + CC3P + Capture/compare 3 output polarity + + 9 + 1 + read-write + + + CC3NE + Capture/compare 3 complementary output enable + + 10 + 1 + read-write + + + CC3NP + Capture/compare 3 complementary output polarity + + 11 + 1 + read-write + + + CC4E + Capture/compare 4 output enable + + 12 + 1 + read-write + + + CC4P + Capture/compare 4 output polarity + + 13 + 1 + read-write + + + CC4NE + Capture/compare 4 complementary output enable + + 14 + 1 + read-write + + + CC4NP + Capture/compare 4 complementary output polarity + + 15 + 1 + read-write + + + CC5E + Capture/compare 5 output enable + + 16 + 1 + read-write + + + CC5P + Capture/compare 5 output polarity + + 17 + 1 + read-write + + + CC6E + Capture/compare 6 output enable + + 20 + 1 + read-write + + + CC6P + Capture/compare 6 output polarity + + 21 + 1 + read-write + + + + + TIM1_CNT + TIM1_CNT + TIM1 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + UIF copy + + 31 + 1 + read-only + + + + + TIM1_PSC + TIM1_PSC + TIM1 prescaler + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM1_ARR + TIM1_ARR + TIM1 auto-reload register + 0x02C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 20 + read-write + + + + + TIM1_RCR + TIM1_RCR + TIM1 repetition counter register + 0x030 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter reload value + + 0 + 16 + read-write + + + + + TIM1_CCR1 + TIM1_CCR1 + TIM1 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM1_CCR2 + TIM1_CCR2 + TIM1 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 20 + read-write + + + + + TIM1_CCR3 + TIM1_CCR3 + TIM1 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare value + + 0 + 20 + read-write + + + + + TIM1_CCR4 + TIM1_CCR4 + TIM1 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare value + + 0 + 20 + read-write + + + + + TIM1_BDTR + TIM1_BDTR + TIM1 break and dead-time register + 0x044 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + 0 + 8 + read-write + + + LOCK + Lock configuration + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected. + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BK2BID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for idle mode + + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + 12 + 1 + read-write + + + B_0x0 + Break function disabled + 0x0 + + + B_0x1 + Break function enabled + 0x1 + + + + + BKP + Break polarity + + 13 + 1 + read-write + + + B_0x0 + Break input tim_brk is active low + 0x0 + + + B_0x1 + Break input tim_brk is active high + 0x1 + + + + + AOE + Automatic output enable + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if none of the break inputs tim_brk and tim_brk2 is active) + 0x1 + + + + + MOE + Main output enable + + 15 + 1 + read-write + + + B_0x0 + In response to a break 2 event. + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). + 0x1 + + + + + BKF + Break filter + + 16 + 4 + read-write + + + B_0x0 + No filter, tim_brk acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BK2F + Break 2 filter + + 20 + 4 + read-write + + + B_0x0 + No filter, tim_brk2 acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BK2E + Break 2 enable + + 24 + 1 + read-write + + + B_0x0 + Break2 function disabled + 0x0 + + + B_0x1 + Break2 function enabled + 0x1 + + + + + BK2P + Break 2 polarity + + 25 + 1 + read-write + + + B_0x0 + Break input tim_brk2 is active low + 0x0 + + + B_0x1 + Break input tim_brk2 is active high + 0x1 + + + + + BKDSRM + Break disarm + + 26 + 1 + read-write + + + B_0x0 + Break input tim_brk is armed + 0x0 + + + B_0x1 + Break input tim_brk is disarmed + 0x1 + + + + + BK2DSRM + Break2 disarm + + 27 + 1 + read-write + + + BKBID + Break bidirectional + + 28 + 1 + read-write + + + B_0x0 + Break input tim_brk in input mode + 0x0 + + + B_0x1 + Break input tim_brk in bidirectional mode + 0x1 + + + + + BK2BID + Break2 bidirectional + + 29 + 1 + read-write + + + + + TIM1_CCR5 + TIM1_CCR5 + TIM1 capture/compare register 5 + 0x048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR5 + Capture/compare 5 value + + 0 + 20 + read-write + + + GC5C1 + Group channel 5 and channel 1 + + 29 + 1 + read-write + + + B_0x0 + No effect of oc5ref on oc1refc + 0x0 + + + B_0x1 + oc1refc is the logical AND of oc1ref and oc5ref + 0x1 + + + + + GC5C2 + Group channel 5 and channel 2 + + 30 + 1 + read-write + + + B_0x0 + No effect of tim_oc5ref on tim_oc2refc + 0x0 + + + B_0x1 + tim_oc2refc is the logical AND of tim_oc2ref and tim_oc5ref + 0x1 + + + + + GC5C3 + Group channel 5 and channel 3 + + 31 + 1 + read-write + + + B_0x0 + No effect of tim_oc5ref on tim_oc3refc + 0x0 + + + B_0x1 + tim_oc3refc is the logical AND of tim_oc3ref and tim_oc5ref + 0x1 + + + + + + + TIM1_CCR6 + TIM1_CCR6 + TIM1 capture/compare register 6 + 0x04C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR6 + Capture/compare 6 value + + 0 + 20 + read-write + + + + + TIM1_CCMR3 + TIM1_CCMR3 + TIM1 capture/compare mode register 3 + 0x050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OC5FE + Output compare 5 fast enable + 2 + 1 + read-write + + + OC5PE + Output compare 5 preload enable + 3 + 1 + read-write + + + OC5M + OC5M[2:0]: Output compare 5 mode + 4 + 3 + read-write + + + OC5CE + Output compare 5 clear enable + 7 + 1 + read-write + + + OC6FE + Output compare 6 fast enable + 10 + 1 + read-write + + + OC6PE + Output compare 6 preload enable + 11 + 1 + read-write + + + OC6M + OC6M[2:0]: Output compare 6 mode + 12 + 3 + read-write + + + OC6CE + Output compare 6 clear enable + 15 + 1 + read-write + + + OC5M_1 + OC5M[3] + 16 + 1 + read-write + + + OC6M_1 + OC6M[3] + 24 + 1 + read-write + + + + + TIM1_DTR2 + TIM1_DTR2 + TIM1 timer deadtime register 2 + 0x054 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTGF + Dead-time falling edge generator setup + + 0 + 8 + read-write + + + DTAE + Deadtime asymmetric enable + + 16 + 1 + read-write + + + B_0x0 + Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + 0x0 + + + B_0x1 + Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + 0x1 + + + + + DTPE + Deadtime preload enable + + 17 + 1 + read-write + + + B_0x0 + Deadtime value is not preloaded + 0x0 + + + B_0x1 + Deadtime value preload is enabled + 0x1 + + + + + + + TIM1_ECR + TIM1_ECR + TIM1 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + IBLK + Index blanking + + 3 + 2 + read-write + + + B_0x0 + Index always active + 0x0 + + + B_0x1 + Index disabled when tim_ti3 input is active, as per CC3P bitfield + 0x1 + + + B_0x2 + Index disabled when tim_ti4 input is active, as per CC4P bitfield + 0x2 + + + + + FIDX + First index + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + 24 + 3 + read-write + + + + + TIM1_TISEL + TIM1_TISEL + TIM1 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM1_AF1 + TIM1_AF1 + TIM1 alternate function option register 1 + 0x060 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + TIMx_BKIN input enable + + 0 + 1 + read-write + + + B_0x0 + TIMx_BKIN input disabled + 0x0 + + + B_0x1 + TIMx_BKIN input enabled + 0x1 + + + + + BKCMP1E + tim_brk_cmp1 enable + + 1 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp1 input enabled + 0x1 + + + + + BKCMP2E + tim_brk_cmp2 enable + + 2 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp2 input enabled + 0x1 + + + + + BKCMP3E + tim_brk_cmp3 enable + + 3 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp3 input enabled + 0x1 + + + + + BKCMP4E + tim_brk_cmp4 enable + + 4 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp4 input enabled + 0x1 + + + + + BKCMP5E + tim_brk_cmp5 enable + + 5 + 1 + read-write + + + B_0x0 + tim_brk_cmp5 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp5 input enabled + 0x1 + + + + + BKCMP6E + tim_brk_cmp6 enable + + 6 + 1 + read-write + + + B_0x0 + tim_brk_cmp6 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp6 input enabled + 0x1 + + + + + BKCMP7E + tim_brk_cmp7 enable + + 7 + 1 + read-write + + + B_0x0 + tim_brk_cmp7 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp7 input enabled + 0x1 + + + + + BKCMP8E + tim_brk_cmp8 enable + + 8 + 1 + read-write + + + B_0x0 + tim_brk_cmp8 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp8 input enabled + 0x1 + + + + + BKINP + TIMx_BKIN input polarity + + 9 + 1 + read-write + + + B_0x0 + TIMx_BKIN input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + TIMx_BKIN input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP1P + tim_brk_cmp1 input polarity + + 10 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp1 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP2P + tim_brk_cmp2 input polarity + + 11 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp2 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP3P + tim_brk_cmp3 input polarity + + 12 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp3 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP4P + tim_brk_cmp4 input polarity + + 13 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp4 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + ETRSEL + etr_in source selection + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM1_AF2 + TIM1_AF2 + TIM1 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BK2INE + TIMx_BKIN2 input enable + + 0 + 1 + read-write + + + B_0x0 + TIMx_BKIN2 input disabled + 0x0 + + + B_0x1 + TIMx_BKIN2 input enabled + 0x1 + + + + + BK2CMP1E + tim_brk2_cmp1 enable + + 1 + 1 + read-write + + + B_0x0 + tim_brk2_cmp1 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp1 input enabled + 0x1 + + + + + BK2CMP2E + tim_brk2_cmp2 enable + + 2 + 1 + read-write + + + B_0x0 + tim_brk2_cmp2 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp2 input enabled + 0x1 + + + + + BK2CMP3E + tim_brk2_cmp3 enable + + 3 + 1 + read-write + + + B_0x0 + tim_brk2_cmp3 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp3 input enabled + 0x1 + + + + + BK2CMP4E + tim_brk2_cmp4 enable + + 4 + 1 + read-write + + + B_0x0 + tim_brk2_cmp4 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp4 input enabled + 0x1 + + + + + BK2CMP5E + tim_brk2_cmp5 enable + + 5 + 1 + read-write + + + B_0x0 + tim_brk2_cmp5 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp5 input enabled + 0x1 + + + + + BK2CMP6E + tim_brk2_cmp6 enable + + 6 + 1 + read-write + + + B_0x0 + tim_brk2_cmp6 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp6 input enabled + 0x1 + + + + + BK2CMP7E + tim_brk2_cmp7 enable + + 7 + 1 + read-write + + + B_0x0 + tim_brk2_cmp7 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp7 input enabled + 0x1 + + + + + BK2CMP8E + tim_brk2_cmp8 enable + + 8 + 1 + read-write + + + B_0x0 + tim_brk2_cmp8 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp8 input enabled + 0x1 + + + + + BK2INP + TIMx_BKIN2 input polarity + + 9 + 1 + read-write + + + B_0x0 + TIMx_BKIN2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + TIMx_BKIN2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP1P + tim_brk2_cmp1 input polarity + + 10 + 1 + read-write + + + B_0x0 + tim_brk2_cmp1 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp1 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP2P + tim_brk2_cmp2 input polarity + + 11 + 1 + read-write + + + B_0x0 + tim_brk2_cmp2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP3P + tim_brk2_cmp3 input polarity + + 12 + 1 + read-write + + + B_0x0 + tim_brk2_cmp3 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp3 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP4P + tim_brk2_cmp4 input polarity + + 13 + 1 + read-write + + + B_0x0 + tim_brk2_cmp4 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp4 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM1_DCR + TIM1_DCR + TIM1 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1 + 0x0 + + + B_0x1 + TIMx_CR2 + 0x1 + + + B_0x2 + TIMx_SMCR + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x3 + CC2 + 0x3 + + + B_0x4 + CC3 + 0x4 + + + B_0x5 + CC4 + 0x5 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM1_DMAR + TIM1_DMAR + TIM1 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM1_S + 0X50012C00 + + + TIM2 + TIM2 address block description + TIM2 + 0x40000000 + + 0x0 + 0x3E4 + registers + + + TIM2 + TIM2 global interrupt + 45 + + + + TIM2_CR1 + TIM2_CR1 + TIM2 control register 1 + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering Enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM2_CR2 + TIM2_CR2 + TIM2 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[2:0]: Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. + 0x1 + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM2_SMCR + TIM2_SMCR + TIM2 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 edge detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered timer input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered timer input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etrp frequency divided by 2 + 0x1 + + + B_0x2 + tim_etrp frequency divided by 4 + 0x2 + + + B_0x3 + tim_etrp frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM2_DIER + TIM2_DIER + TIM2 DMA/Interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction change interrupt disabled + 0x0 + + + B_0x1 + Direction change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM2_SR + TIM2_SR + TIM2 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + IDXF + Index interrupt flag + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM2_EGR + TIM2_EGR + TIM2 event generation register + 0x014 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM2_CCMR1 + TIM2_CCMR1 + TIM2 capture/compare mode register 1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM2_CCMR1_ALTERNATE1 + TIM2_CCMR1_ALTERNATE1 + TIM2 capture/compare mode register 1 + TIM2_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int input + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM2_CCMR2 + TIM2_CCMR2 + TIM2 capture/compare mode register 2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM2_CCMR2_ALTERNATE1 + TIM2_CCMR2_ALTERNATE1 + TIM2 capture/compare mode register 2 + TIM2_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM2_CCER + TIM2_CCER + TIM2 capture/compare enable register + 0x020 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM2_CNT + TIM2_CNT + TIM2 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + + 0 + 31 + read-write + + + UIFCPY_CNT + Value depends on IUFREMAP in TIMx_CR1. + 31 + 1 + read-write + + + + + TIM2_PSC + TIM2_PSC + TIM2 prescaler + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM2_ARR + TIM2_ARR + TIM2 auto-reload register + 0x02C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 32 + read-write + + + + + TIM2_CCR1 + TIM2_CCR1 + TIM2 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 32 + read-write + + + + + TIM2_CCR2 + TIM2_CCR2 + TIM2 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 32 + read-write + + + + + TIM2_CCR3 + TIM2_CCR3 + TIM2 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value + + 0 + 32 + read-write + + + + + TIM2_CCR4 + TIM2_CCR4 + TIM2 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value + + 0 + 32 + read-write + + + + + TIM2_ECR + TIM2_ECR + TIM2 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + IBLK + Index blanking + + 3 + 2 + read-write + + + B_0x0 + Index always active + 0x0 + + + B_0x1 + Index disabled hen tim_ti3 input is active, as per CC3P bitfield + 0x1 + + + B_0x2 + Index disabled when tim_ti4 input is active, as per CC4P bitfield + 0x2 + + + + + FIDX + First index + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + 24 + 3 + read-write + + + + + TIM2_TISEL + TIM2_TISEL + TIM2 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH3 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM2_AF1 + TIM2_AF1 + TIM2 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + etr_in source selection + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM2_AF2 + TIM2_AF2 + TIM2 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM2_DCR + TIM2_DCR + TIM2 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x3 + CC2 + 0x3 + + + B_0x4 + CC3 + 0x4 + + + B_0x5 + CC4 + 0x5 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM2_DMAR + TIM2_DMAR + TIM2 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM2_S + 0X50000000 + + + TIM3 + TIM3 address block description + TIM3 + 0x40000400 + + 0x0 + 0x3E4 + registers + + + TIM3 + TIM3 global interrupt + 46 + + + + TIM3_CR1 + TIM3_CR1 + TIM3 control register 1 + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering Enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM3_CR2 + TIM3_CR2 + TIM3 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[2:0]: Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. + 0x1 + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM3_SMCR + TIM3_SMCR + TIM3 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 edge detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered timer input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered timer input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etrp frequency divided by 2 + 0x1 + + + B_0x2 + tim_etrp frequency divided by 4 + 0x2 + + + B_0x3 + tim_etrp frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM3_DIER + TIM3_DIER + TIM3 DMA/Interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction change interrupt disabled + 0x0 + + + B_0x1 + Direction change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM3_SR + TIM3_SR + TIM3 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + IDXF + Index interrupt flag + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM3_EGR + TIM3_EGR + TIM3 event generation register + 0x014 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM3_CCMR1 + TIM3_CCMR1 + TIM3 capture/compare mode register 1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM3_CCMR1_ALTERNATE1 + TIM3_CCMR1_ALTERNATE1 + TIM3 capture/compare mode register 1 + TIM3_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int input + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM3_CCMR2 + TIM3_CCMR2 + TIM3 capture/compare mode register 2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM3_CCMR2_ALTERNATE1 + TIM3_CCMR2_ALTERNATE1 + TIM3 capture/compare mode register 2 + TIM3_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM3_CCER + TIM3_CCER + TIM3 capture/compare enable register + 0x020 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM3_CNT + TIM3_CNT + TIM3 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + Value depends on IUFREMAP in TIMx_CR1. + 31 + 1 + read-write + + + + + TIM3_PSC + TIM3_PSC + TIM3 prescaler + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM3_ARR + TIM3_ARR + TIM3 auto-reload register + 0x02C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Low Auto-reload value + + 0 + 20 + read-write + + + + + TIM3_CCR1 + TIM3_CCR1 + TIM3 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM3_CCR2 + TIM3_CCR2 + TIM3 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM3_CCR3 + TIM3_CCR3 + TIM3 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value + + 0 + 20 + read-write + + + + + TIM3_CCR4 + TIM3_CCR4 + TIM3 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value + + 0 + 20 + read-write + + + + + TIM3_ECR + TIM3_ECR + TIM3 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + IBLK + Index blanking + + 3 + 2 + read-write + + + B_0x0 + Index always active + 0x0 + + + B_0x1 + Index disabled hen tim_ti3 input is active, as per CC3P bitfield + 0x1 + + + B_0x2 + Index disabled when tim_ti4 input is active, as per CC4P bitfield + 0x2 + + + + + FIDX + First index + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + 24 + 3 + read-write + + + + + TIM3_TISEL + TIM3_TISEL + TIM3 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH3 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM3_AF1 + TIM3_AF1 + TIM3 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + etr_in source selection + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM3_AF2 + TIM3_AF2 + TIM3 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM3_DCR + TIM3_DCR + TIM3 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x3 + CC2 + 0x3 + + + B_0x4 + CC3 + 0x4 + + + B_0x5 + CC4 + 0x5 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM3_DMAR + TIM3_DMAR + TIM3 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM3_S + 0X50000400 + + + TIM4 + TIM4 address block description + TIM4 + 0x40000800 + + 0x0 + 0x3E4 + registers + + + TIM4 + TIM4 global interrupt + 47 + + + + TIM4_CR1 + TIM4_CR1 + TIM4 control register 1 + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering Enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM4_CR2 + TIM4_CR2 + TIM4 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[2:0]: Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. + 0x1 + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM4_SMCR + TIM4_SMCR + TIM4 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 edge detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered timer input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered timer input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etrp frequency divided by 2 + 0x1 + + + B_0x2 + tim_etrp frequency divided by 4 + 0x2 + + + B_0x3 + tim_etrp frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM4_DIER + TIM4_DIER + TIM4 DMA/Interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction change interrupt disabled + 0x0 + + + B_0x1 + Direction change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM4_SR + TIM4_SR + TIM4 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + IDXF + Index interrupt flag + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM4_EGR + TIM4_EGR + TIM4 event generation register + 0x014 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM4_CCMR1 + TIM4_CCMR1 + TIM4 capture/compare mode register 1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM4_CCMR1_ALTERNATE1 + TIM4_CCMR1_ALTERNATE1 + TIM4 capture/compare mode register 1 + TIM4_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int input + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM4_CCMR2 + TIM4_CCMR2 + TIM4 capture/compare mode register 2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM4_CCMR2_ALTERNATE1 + TIM4_CCMR2_ALTERNATE1 + TIM4 capture/compare mode register 2 + TIM4_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM4_CCER + TIM4_CCER + TIM4 capture/compare enable register + 0x020 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM4_CNT + TIM4_CNT + TIM4 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + Value depends on IUFREMAP in TIMx_CR1. + 31 + 1 + read-write + + + + + TIM4_PSC + TIM4_PSC + TIM4 prescaler + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM4_ARR + TIM4_ARR + TIM4 auto-reload register + 0x02C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Low Auto-reload value + + 0 + 20 + read-write + + + + + TIM4_CCR1 + TIM4_CCR1 + TIM4 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM4_CCR2 + TIM4_CCR2 + TIM4 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM4_CCR3 + TIM4_CCR3 + TIM4 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value + + 0 + 20 + read-write + + + + + TIM4_CCR4 + TIM4_CCR4 + TIM4 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value + + 0 + 20 + read-write + + + + + TIM4_ECR + TIM4_ECR + TIM4 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + IBLK + Index blanking + + 3 + 2 + read-write + + + B_0x0 + Index always active + 0x0 + + + B_0x1 + Index disabled hen tim_ti3 input is active, as per CC3P bitfield + 0x1 + + + B_0x2 + Index disabled when tim_ti4 input is active, as per CC4P bitfield + 0x2 + + + + + FIDX + First index + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + 24 + 3 + read-write + + + + + TIM4_TISEL + TIM4_TISEL + TIM4 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH3 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM4_AF1 + TIM4_AF1 + TIM4 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + etr_in source selection + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM4_AF2 + TIM4_AF2 + TIM4 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM4_DCR + TIM4_DCR + TIM4 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x3 + CC2 + 0x3 + + + B_0x4 + CC3 + 0x4 + + + B_0x5 + CC4 + 0x5 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM4_DMAR + TIM4_DMAR + TIM4 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM4_S + 0X50000800 + + + TIM5 + TIM5 address block description + TIM5 + 0x40000c00 + + 0x0 + 0x3E4 + registers + + + TIM5 + TIM5 global interrupt + 48 + + + + TIM5_CR1 + TIM5_CR1 + TIM5 control register 1 + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering Enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM5_CR2 + TIM5_CR2 + TIM5 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[2:0]: Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input. + 0x1 + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM5_SMCR + TIM5_SMCR + TIM5 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 edge detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered timer input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered timer input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etrp frequency divided by 2 + 0x1 + + + B_0x2 + tim_etrp frequency divided by 4 + 0x2 + + + B_0x3 + tim_etrp frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM5_DIER + TIM5_DIER + TIM5 DMA/Interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled. + 0x0 + + + B_0x1 + CC3 interrupt enabled. + 0x1 + + + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled. + 0x0 + + + B_0x1 + CC4 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled. + 0x0 + + + B_0x1 + CC1 DMA request enabled. + 0x1 + + + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled. + 0x0 + + + B_0x1 + CC2 DMA request enabled. + 0x1 + + + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled. + 0x0 + + + B_0x1 + CC3 DMA request enabled. + 0x1 + + + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled. + 0x0 + + + B_0x1 + CC4 DMA request enabled. + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled. + 0x0 + + + B_0x1 + Trigger DMA request enabled. + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction change interrupt disabled + 0x0 + + + B_0x1 + Direction change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM5_SR + TIM5_SR + TIM5 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/Compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/Compare 4 interrupt flag + + 4 + 1 + read-write + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/Compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/Compare 4 overcapture flag + + 12 + 1 + read-write + + + IDXF + Index interrupt flag + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM5_EGR + TIM5_EGR + TIM5 event generation register + 0x014 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + + + TIM5_CCMR1 + TIM5_CCMR1 + TIM5 capture/compare mode register 1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM5_CCMR1_ALTERNATE1 + TIM5_CCMR1_ALTERNATE1 + TIM5 capture/compare mode register 1 + TIM5_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int input + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM5_CCMR2 + TIM5_CCMR2 + TIM5 capture/compare mode register 2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM5_CCMR2_ALTERNATE1 + TIM5_CCMR2_ALTERNATE1 + TIM5 capture/compare mode register 2 + TIM5_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/Compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/Compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM5_CCER + TIM5_CCER + TIM5 capture/compare enable register + 0x020 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + CC3E + Capture/Compare 3 output enable. + 8 + 1 + read-write + + + CC3P + Capture/Compare 3 output Polarity. + 9 + 1 + read-write + + + CC3NP + Capture/Compare 3 output Polarity. + 11 + 1 + read-write + + + CC4E + Capture/Compare 4 output enable. + 12 + 1 + read-write + + + CC4P + Capture/Compare 4 output Polarity. + 13 + 1 + read-write + + + CC4NP + Capture/Compare 4 output Polarity. + 15 + 1 + read-write + + + + + TIM5_CNT + TIM5_CNT + TIM5 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Least significant part of counter value + + 0 + 31 + read-write + + + UIFCPY_CNT + Value depends on IUFREMAP in TIMx_CR1. + 31 + 1 + read-write + + + + + TIM5_PSC + TIM5_PSC + TIM5 prescaler + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM5_ARR + TIM5_ARR + TIM5 auto-reload register + 0x02C + 0x20 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 32 + read-write + + + + + TIM5_CCR1 + TIM5_CCR1 + TIM5 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 32 + read-write + + + + + TIM5_CCR2 + TIM5_CCR2 + TIM5 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 32 + read-write + + + + + TIM5_CCR3 + TIM5_CCR3 + TIM5 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare 3 value + + 0 + 32 + read-write + + + + + TIM5_CCR4 + TIM5_CCR4 + TIM5 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare 4 value + + 0 + 32 + read-write + + + + + TIM5_ECR + TIM5_ECR + TIM5 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + IBLK + Index blanking + + 3 + 2 + read-write + + + B_0x0 + Index always active + 0x0 + + + B_0x1 + Index disabled hen tim_ti3 input is active, as per CC3P bitfield + 0x1 + + + B_0x2 + Index disabled when tim_ti4 input is active, as per CC4P bitfield + 0x2 + + + + + FIDX + First index + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + 24 + 3 + read-write + + + + + TIM5_TISEL + TIM5_TISEL + TIM5 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH3 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM5_AF1 + TIM5_AF1 + TIM5 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ETRSEL + etr_in source selection + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM5_AF2 + TIM5_AF2 + TIM5 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM5_DCR + TIM5_DCR + TIM5 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1, + 0x0 + + + B_0x1 + TIMx_CR2, + 0x1 + + + B_0x2 + TIMx_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x3 + CC2 + 0x3 + + + B_0x4 + CC3 + 0x4 + + + B_0x5 + CC4 + 0x5 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM5_DMAR + TIM5_DMAR + TIM5 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM5_S + 0X50000C00 + + + TIM6 + TIM6 address block description + TIM6 + 0x40001000 + + 0x0 + 0x30 + registers + + + TIM6 + TIM6 global interrupt + 49 + + + + TIM6_CR1 + TIM6_CR1 + TIM6 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generates an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered. + 0x0 + + + B_0x1 + TIMx_ARR register is buffered. + 0x1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM6_CR2 + TIM6_CR2 + TIM6 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as a trigger output (tim_trgo). + 0x2 + + + + + + + TIM6_DIER + TIM6_DIER + TIM6 DMA/Interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + + + TIM6_SR + TIM6_SR + TIM6 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + + + TIM6_EGR + TIM6_EGR + TIM6 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Re-initializes the timer counter and generates an update of the registers. + 0x1 + + + + + + + TIM6_CNT + TIM6_CNT + TIM6 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + UIF copy + + 31 + 1 + read-only + + + + + TIM6_PSC + TIM6_PSC + TIM6 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM6_ARR + TIM6_ARR + TIM6 auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 20 + read-write + + + + + + + TIM6_S + 0X50001000 + + + TIM7 + TIM7 address block description + TIM7 + 0x40001400 + + 0x0 + 0x30 + registers + + + TIM7 + TIM7 global interrupt + 50 + + + + TIM7_CR1 + TIM7_CR1 + TIM7 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generates an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the CEN bit). + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered. + 0x0 + + + B_0x1 + TIMx_ARR register is buffered. + 0x1 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM7_CR2 + TIM7_CR2 + TIM7 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as a trigger output (tim_trgo). + 0x2 + + + + + + + TIM7_DIER + TIM7_DIER + TIM7 DMA/Interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled. + 0x0 + + + B_0x1 + Update DMA request enabled. + 0x1 + + + + + + + TIM7_SR + TIM7_SR + TIM7 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + + + TIM7_EGR + TIM7_EGR + TIM7 event generation register + 0x14 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action. + 0x0 + + + B_0x1 + Re-initializes the timer counter and generates an update of the registers. + 0x1 + + + + + + + TIM7_CNT + TIM7_CNT + TIM7 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + UIF copy + + 31 + 1 + read-only + + + + + TIM7_PSC + TIM7_PSC + TIM7 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM7_ARR + TIM7_ARR + TIM7 auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 20 + read-write + + + + + + + TIM7_S + 0X50001400 + + + TIM8 + TIM8 address block description + TIM8 + 0x40013400 + + 0x0 + 0x3E4 + registers + + + TIM8_CC + TIM8 capture compare interrupt + 68 + + + TIM8_TRGI_DIR_IDX + TIM8 trigger and commutation interrupt/TIM8 Direction Change interrupt/TIM8 Index + 67 + + + TIM8_UPD + TIM8 Update interrupt + 66 + + + TIM8_BRK_TERR_IERR + TIM8 Break interrupt/TIM8 Transition error/TIM8 Index error + 65 + + + + TIM8_CR1 + TIM8_CR1 + TIM8 control register 1 + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + DIR + Direction + + 4 + 1 + read-write + + + B_0x0 + Counter used as upcounter + 0x0 + + + B_0x1 + Counter used as downcounter + 0x1 + + + + + CMS + Center-aligned mode selection + + 5 + 2 + read-write + + + B_0x0 + Edge-aligned mode. + 0x0 + + + B_0x1 + Center-aligned mode 1. + 0x1 + + + B_0x2 + Center-aligned mode 2. + 0x2 + + + B_0x3 + Center-aligned mode 3. + 0x3 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTSless than/sub>=tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub>=2*tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub>=4*tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM8_CR2 + TIM8_CR2 + TIM8 control register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCPC + Capture/compare preloaded control + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + MMS[2:0]: Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input + 0x0 + + + B_0x1 + tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input + 0x1 + + + + + OIS1 + Output idle state 1 (tim_oc1 output) + + 8 + 1 + read-write + + + B_0x0 + tim_oc1=0 (after a dead-time) when MOE=0 + 0x0 + + + B_0x1 + tim_oc1=1 (after a dead-time) when MOE=0 + 0x1 + + + + + OIS1N + Output idle state 1 (tim_oc1n output) + + 9 + 1 + read-write + + + B_0x0 + tim_oc1n=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + tim_oc1n=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output idle state 2 (tim_oc2 output) + + 10 + 1 + read-write + + + OIS2N + Output idle state 2 (tim_oc2n output) + + 11 + 1 + read-write + + + OIS3 + Output idle state 3 (tim_oc3n output) + + 12 + 1 + read-write + + + OIS3N + Output idle state 3 (tim_oc3n output) + + 13 + 1 + read-write + + + OIS4 + Output idle state 4 (tim_oc4 output) + + 14 + 1 + read-write + + + OIS4N + Output idle state 4 (tim_oc4n output) + + 15 + 1 + read-write + + + OIS5 + Output idle state 5 (tim_oc5 output) + + 16 + 1 + read-write + + + OIS6 + Output idle state 6 (tim_oc6 output) + + 18 + 1 + read-write + + + MMS2 + Master mode selection 2 + + 20 + 4 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo2). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo2). + 0x1 + + + B_0x2 + Update - the update event is selected as trigger output (tim_trgo2). + 0x2 + + + B_0x3 + Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (tim_trgo2). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo2) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo2) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo2) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo2) + 0x7 + + + B_0x8 + Compare - tim_oc5refc signal is used as trigger output (tim_trgo2) + 0x8 + + + B_0x9 + Compare - tim_oc6refc signal is used as trigger output (tim_trgo2) + 0x9 + + + B_0xA + Compare Pulse - tim_oc4refc rising or falling edges generate pulses on tim_trgo2 + 0xA + + + B_0xB + Compare pulse - tim_oc6refc rising or falling edges generate pulses on tim_trgo2 + 0xB + + + B_0xC + Compare pulse - tim_oc4refc or tim_oc6refc rising edges generate pulses on tim_trgo2 + 0xC + + + B_0xD + Compare pulse - tim_oc4refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2 + 0xD + + + B_0xE + Compare pulse - tim_oc5refc or tim_oc6refc rising edges generate pulses on tim_trgo2 + 0xE + + + B_0xF + Compare pulse - tim_oc5refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2 + 0xF + + + + + MMS_1 + MMS[3] + 25 + 1 + read-write + + + + + TIM8_SMCR + TIM8_SMCR + TIM8 slave mode control register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Quadrature encoder mode 1, x2 mode- Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Quadrature encoder mode 2, x2 mode - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Quadrature encoder mode 3, x4 mode - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + OCCS + OCREF clear selection + + 3 + 1 + read-write + + + B_0x0 + tim_ocref_clr_int is connected to the tim_ocref_clr input + 0x0 + + + B_0x1 + tim_ocref_clr_int is connected to tim_etrf + 0x1 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal Trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal Trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal Trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 Edge Detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External Trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + ETF + External trigger filter + + 8 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + ETPS + External trigger prescaler + + 12 + 2 + read-write + + + B_0x0 + Prescaler OFF + 0x0 + + + B_0x1 + tim_etr_in frequency divided by 2 + 0x1 + + + B_0x2 + tim_etr_in frequency divided by 4 + 0x2 + + + B_0x3 + tim_etr_in frequency divided by 8 + 0x3 + + + + + ECE + External clock enable + + 14 + 1 + read-write + + + B_0x0 + External clock mode 2 disabled + 0x0 + + + B_0x1 + External clock mode 2 enabled. + 0x1 + + + + + ETP + External trigger polarity + + 15 + 1 + read-write + + + B_0x0 + tim_etr_in is non-inverted, active at high level or rising edge. + 0x0 + + + B_0x1 + tim_etr_in is inverted, active at low level or falling edge. + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + SMSPS + SMS preload source + + 25 + 1 + read-write + + + B_0x0 + The transfer is triggered by the Timer's Update event + 0x0 + + + B_0x1 + The transfer is triggered by the Index event + 0x1 + + + + + + + TIM8_DIER + TIM8_DIER + TIM8 DMA/interrupt enable register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + CC3IE + Capture/compare 3 interrupt enable + 3 + 1 + read-write + + + B_0x0 + CC3 interrupt disabled + 0x0 + + + B_0x1 + CC3 interrupt enabled + 0x1 + + + + + CC4IE + Capture/compare 4 interrupt enable + 4 + 1 + read-write + + + B_0x0 + CC4 interrupt disabled + 0x0 + + + B_0x1 + CC4 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + CC2DE + Capture/compare 2 DMA request enable + 10 + 1 + read-write + + + B_0x0 + CC2 DMA request disabled + 0x0 + + + B_0x1 + CC2 DMA request enabled + 0x1 + + + + + CC3DE + Capture/compare 3 DMA request enable + 11 + 1 + read-write + + + B_0x0 + CC3 DMA request disabled + 0x0 + + + B_0x1 + CC3 DMA request enabled + 0x1 + + + + + CC4DE + Capture/compare 4 DMA request enable + 12 + 1 + read-write + + + B_0x0 + CC4 DMA request disabled + 0x0 + + + B_0x1 + CC4 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + IDXIE + Index interrupt enable + 20 + 1 + read-write + + + B_0x0 + Index interrupt disabled + 0x0 + + + B_0x1 + Index Change interrupt enabled + 0x1 + + + + + DIRIE + Direction change interrupt enable + 21 + 1 + read-write + + + B_0x0 + Direction Change interrupt disabled + 0x0 + + + B_0x1 + Direction Change interrupt enabled + 0x1 + + + + + IERRIE + Index error interrupt enable + 22 + 1 + read-write + + + B_0x0 + Index error interrupt disabled + 0x0 + + + B_0x1 + Index error interrupt enabled + 0x1 + + + + + TERRIE + Transition error interrupt enable + 23 + 1 + read-write + + + B_0x0 + Transition error interrupt disabled + 0x0 + + + B_0x1 + Transition error interrupt enabled + 0x1 + + + + + + + TIM8_SR + TIM8_SR + TIM8 status register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/compare 2 interrupt flag + + 2 + 1 + read-write + + + CC3IF + Capture/compare 3 interrupt flag + + 3 + 1 + read-write + + + CC4IF + Capture/compare 4 interrupt flag + + 4 + 1 + read-write + + + COMIF + COM interrupt flag + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred. + 0x0 + + + B_0x1 + COM interrupt pending. + 0x1 + + + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + BIF + Break interrupt flag + + 7 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break input. + 0x1 + + + + + B2IF + Break 2 interrupt flag + + 8 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the break 2 input. + 0x1 + + + + + CC1OF + Capture/compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + + 10 + 1 + read-write + + + CC3OF + Capture/compare 3 overcapture flag + + 11 + 1 + read-write + + + CC4OF + Capture/compare 4 overcapture flag + + 12 + 1 + read-write + + + SBIF + System break interrupt flag + + 13 + 1 + read-write + + + B_0x0 + No break event occurred. + 0x0 + + + B_0x1 + An active level has been detected on the system break input. + 0x1 + + + + + CC5IF + Compare 5 interrupt flag + + 16 + 1 + read-write + + + CC6IF + Compare 6 interrupt flag + + 17 + 1 + read-write + + + IDXF + Index interrupt flag + + 20 + 1 + read-write + + + B_0x0 + No index event occurred. + 0x0 + + + B_0x1 + An index event has occurred + 0x1 + + + + + DIRF + Direction change interrupt flag + + 21 + 1 + read-write + + + B_0x0 + No direction change + 0x0 + + + B_0x1 + Direction change + 0x1 + + + + + IERRF + Index error interrupt flag + + 22 + 1 + read-write + + + B_0x0 + No index error has been detected. + 0x0 + + + B_0x1 + An index error has been detected + 0x1 + + + + + TERRF + Transition error interrupt flag + + 23 + 1 + read-write + + + B_0x0 + No encoder transition error has been detected. + 0x0 + + + B_0x1 + An encoder transition error has been detected + 0x1 + + + + + + + TIM8_EGR + TIM8_EGR + TIM8 event generation register + 0x014 + 16 + write-only + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + + 2 + 1 + write-only + + + CC3G + Capture/compare 3 generation + + 3 + 1 + write-only + + + CC4G + Capture/compare 4 generation + + 4 + 1 + write-only + + + COMG + Capture/compare control update generation + + 5 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits update (providing CCPC bit is set) + 0x1 + + + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. + 0x1 + + + + + BG + Break generation + + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + B2G + Break 2 generation + + 8 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break 2 event is generated. + 0x1 + + + + + + + TIM8_CCMR1 + TIM8_CCMR1 + TIM8 capture/compare mode register 1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/compare 1 Selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM8_CCMR1_ALTERNATE1 + TIM8_CCMR1_ALTERNATE1 + TIM8 capture/compare mode register 1 + TIM8_CCMR1 + 0x018 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int signal + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int signal (tim_ocref_clr input or tim_etrf input) + 0x1 + + + + + CC2S + Capture/compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM8_CCMR2 + TIM8_CCMR2 + TIM8 capture/compare mode register 2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + Input capture 3 filter + 4 + 4 + read-write + + + CC4S + Capture/compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + Input capture 4 filter + 12 + 4 + read-write + + + + + TIM8_CCMR2_ALTERNATE1 + TIM8_CCMR2_ALTERNATE1 + TIM8 capture/compare mode register 2 + TIM8_CCMR2 + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC3S + Capture/compare 3 selection + + 0 + 2 + read-write + + + B_0x0 + CC3 channel is configured as output + 0x0 + + + B_0x1 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 + 0x1 + + + B_0x2 + CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 + 0x2 + + + B_0x3 + CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. + 0x3 + + + + + OC3FE + Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M + OC3M[2:0]: Output compare 3 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR3 and the counter TIMx_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 3 to active level on match. + 0x1 + + + B_0x2 + Set channel 3 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc3ref toggles when TIMx_CNT=TIMx_CCR3. + 0x3 + + + B_0x4 + Force inactive level - tim_oc3ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc3ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNTless thanTIMx_CCR3 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 3 is inactive as long as TIMx_CNTless thanTIMx_CCR3 else active. + 0x7 + + + + + OC3CE + Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + Capture/compare 4 selection + + 8 + 2 + read-write + + + B_0x0 + CC4 channel is configured as output + 0x0 + + + B_0x1 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 + 0x1 + + + B_0x2 + CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 + 0x2 + + + B_0x3 + CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. + 0x3 + + + + + OC4FE + Output compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + Output compare 4 preload enable + 11 + 1 + read-write + + + OC4M + OC4M[2:0]: Output compare 4 mode + + 12 + 3 + read-write + + + OC4CE + Output compare 4 clear enable + 15 + 1 + read-write + + + OC3M_1 + OC3M[3] + 16 + 1 + read-write + + + OC4M_1 + OC4M[3] + 24 + 1 + read-write + + + + + TIM8_CCER + TIM8_CCER + TIM8 capture/compare enable register + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1E + Capture/compare 1 output enable + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/compare 1 output polarity + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/compare 1 complementary output enable + + 2 + 1 + read-write + + + B_0x0 + Off - tim_oc1n is not active. + 0x0 + + + B_0x1 + On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/compare 1 complementary output polarity + + 3 + 1 + read-write + + + B_0x0 + tim_oc1n active high. + 0x0 + + + B_0x1 + tim_oc1n active low. + 0x1 + + + + + CC2E + Capture/compare 2 output enable + + 4 + 1 + read-write + + + CC2P + Capture/compare 2 output polarity + + 5 + 1 + read-write + + + CC2NE + Capture/compare 2 complementary output enable + + 6 + 1 + read-write + + + CC2NP + Capture/compare 2 complementary output polarity + + 7 + 1 + read-write + + + CC3E + Capture/compare 3 output enable + + 8 + 1 + read-write + + + CC3P + Capture/compare 3 output polarity + + 9 + 1 + read-write + + + CC3NE + Capture/compare 3 complementary output enable + + 10 + 1 + read-write + + + CC3NP + Capture/compare 3 complementary output polarity + + 11 + 1 + read-write + + + CC4E + Capture/compare 4 output enable + + 12 + 1 + read-write + + + CC4P + Capture/compare 4 output polarity + + 13 + 1 + read-write + + + CC4NE + Capture/compare 4 complementary output enable + + 14 + 1 + read-write + + + CC4NP + Capture/compare 4 complementary output polarity + + 15 + 1 + read-write + + + CC5E + Capture/compare 5 output enable + + 16 + 1 + read-write + + + CC5P + Capture/compare 5 output polarity + + 17 + 1 + read-write + + + CC6E + Capture/compare 6 output enable + + 20 + 1 + read-write + + + CC6P + Capture/compare 6 output polarity + + 21 + 1 + read-write + + + + + TIM8_CNT + TIM8_CNT + TIM8 counter + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + UIF copy + + 31 + 1 + read-only + + + + + TIM8_PSC + TIM8_PSC + TIM8 prescaler + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM8_ARR + TIM8_ARR + TIM8 auto-reload register + 0x02C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 20 + read-write + + + + + TIM8_RCR + TIM8_RCR + TIM8 repetition counter register + 0x030 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter reload value + + 0 + 16 + read-write + + + + + TIM8_CCR1 + TIM8_CCR1 + TIM8 capture/compare register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM8_CCR2 + TIM8_CCR2 + TIM8 capture/compare register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 20 + read-write + + + + + TIM8_CCR3 + TIM8_CCR3 + TIM8 capture/compare register 3 + 0x03C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR3 + Capture/compare value + + 0 + 20 + read-write + + + + + TIM8_CCR4 + TIM8_CCR4 + TIM8 capture/compare register 4 + 0x040 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR4 + Capture/compare value + + 0 + 20 + read-write + + + + + TIM8_BDTR + TIM8_BDTR + TIM8 break and dead-time register + 0x044 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + 0 + 8 + read-write + + + LOCK + Lock configuration + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected. + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BK2BID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for idle mode + + 10 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + 11 + 1 + read-write + + + B_0x0 + When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). + 0x0 + + + B_0x1 + When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + 12 + 1 + read-write + + + B_0x0 + Break function disabled + 0x0 + + + B_0x1 + Break function enabled + 0x1 + + + + + BKP + Break polarity + + 13 + 1 + read-write + + + B_0x0 + Break input tim_brk is active low + 0x0 + + + B_0x1 + Break input tim_brk is active high + 0x1 + + + + + AOE + Automatic output enable + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if none of the break inputs tim_brk and tim_brk2 is active) + 0x1 + + + + + MOE + Main output enable + + 15 + 1 + read-write + + + B_0x0 + In response to a break 2 event. + 0x0 + + + B_0x1 + OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). + 0x1 + + + + + BKF + Break filter + + 16 + 4 + read-write + + + B_0x0 + No filter, tim_brk acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BK2F + Break 2 filter + + 20 + 4 + read-write + + + B_0x0 + No filter, tim_brk2 acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BK2E + Break 2 enable + + 24 + 1 + read-write + + + B_0x0 + Break2 function disabled + 0x0 + + + B_0x1 + Break2 function enabled + 0x1 + + + + + BK2P + Break 2 polarity + + 25 + 1 + read-write + + + B_0x0 + Break input tim_brk2 is active low + 0x0 + + + B_0x1 + Break input tim_brk2 is active high + 0x1 + + + + + BKDSRM + Break disarm + + 26 + 1 + read-write + + + B_0x0 + Break input tim_brk is armed + 0x0 + + + B_0x1 + Break input tim_brk is disarmed + 0x1 + + + + + BK2DSRM + Break2 disarm + + 27 + 1 + read-write + + + BKBID + Break bidirectional + + 28 + 1 + read-write + + + B_0x0 + Break input tim_brk in input mode + 0x0 + + + B_0x1 + Break input tim_brk in bidirectional mode + 0x1 + + + + + BK2BID + Break2 bidirectional + + 29 + 1 + read-write + + + + + TIM8_CCR5 + TIM8_CCR5 + TIM8 capture/compare register 5 + 0x048 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR5 + Capture/compare 5 value + + 0 + 20 + read-write + + + GC5C1 + Group channel 5 and channel 1 + + 29 + 1 + read-write + + + B_0x0 + No effect of oc5ref on oc1refc + 0x0 + + + B_0x1 + oc1refc is the logical AND of oc1ref and oc5ref + 0x1 + + + + + GC5C2 + Group channel 5 and channel 2 + + 30 + 1 + read-write + + + B_0x0 + No effect of tim_oc5ref on tim_oc2refc + 0x0 + + + B_0x1 + tim_oc2refc is the logical AND of tim_oc2ref and tim_oc5ref + 0x1 + + + + + GC5C3 + Group channel 5 and channel 3 + + 31 + 1 + read-write + + + B_0x0 + No effect of tim_oc5ref on tim_oc3refc + 0x0 + + + B_0x1 + tim_oc3refc is the logical AND of tim_oc3ref and tim_oc5ref + 0x1 + + + + + + + TIM8_CCR6 + TIM8_CCR6 + TIM8 capture/compare register 6 + 0x04C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR6 + Capture/compare 6 value + + 0 + 20 + read-write + + + + + TIM8_CCMR3 + TIM8_CCMR3 + TIM8 capture/compare mode register 3 + 0x050 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OC5FE + Output compare 5 fast enable + 2 + 1 + read-write + + + OC5PE + Output compare 5 preload enable + 3 + 1 + read-write + + + OC5M + OC5M[2:0]: Output compare 5 mode + 4 + 3 + read-write + + + OC5CE + Output compare 5 clear enable + 7 + 1 + read-write + + + OC6FE + Output compare 6 fast enable + 10 + 1 + read-write + + + OC6PE + Output compare 6 preload enable + 11 + 1 + read-write + + + OC6M + OC6M[2:0]: Output compare 6 mode + 12 + 3 + read-write + + + OC6CE + Output compare 6 clear enable + 15 + 1 + read-write + + + OC5M_1 + OC5M[3] + 16 + 1 + read-write + + + OC6M_1 + OC6M[3] + 24 + 1 + read-write + + + + + TIM8_DTR2 + TIM8_DTR2 + TIM8 timer deadtime register 2 + 0x054 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTGF + Dead-time falling edge generator setup + + 0 + 8 + read-write + + + DTAE + Deadtime asymmetric enable + + 16 + 1 + read-write + + + B_0x0 + Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + 0x0 + + + B_0x1 + Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + 0x1 + + + + + DTPE + Deadtime preload enable + + 17 + 1 + read-write + + + B_0x0 + Deadtime value is not preloaded + 0x0 + + + B_0x1 + Deadtime value preload is enabled + 0x1 + + + + + + + TIM8_ECR + TIM8_ECR + TIM8 timer encoder control register + 0x058 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IE + Index enable + + 0 + 1 + read-write + + + B_0x0 + Index disabled + 0x0 + + + B_0x1 + Index enabled + 0x1 + + + + + IDIR + Index direction + + 1 + 2 + read-write + + + B_0x0 + Index resets the counter whatever the direction + 0x0 + + + B_0x1 + Index resets the counter when up-counting only + 0x1 + + + B_0x2 + Index resets the counter when down-counting only + 0x2 + + + + + IBLK + Index blanking + + 3 + 2 + read-write + + + B_0x0 + Index always active + 0x0 + + + B_0x1 + Index disabled when tim_ti3 input is active, as per CC3P bitfield + 0x1 + + + B_0x2 + Index disabled when tim_ti4 input is active, as per CC4P bitfield + 0x2 + + + + + FIDX + First index + + 5 + 1 + read-write + + + B_0x0 + Index is always active + 0x0 + + + B_0x1 + the first Index only resets the counter + 0x1 + + + + + IPOS + Index positioning + + 6 + 2 + read-write + + + B_0x0 + Index resets the counter when AB = 00 + 0x0 + + + B_0x1 + Index resets the counter when AB = 01 + 0x1 + + + B_0x2 + Index resets the counter when AB = 10 + 0x2 + + + B_0x3 + Index resets the counter when AB = 11 + 0x3 + + + + + PW + Pulse width + + 16 + 8 + read-write + + + PWPRSC + Pulse width prescaler + + 24 + 3 + read-write + + + + + TIM8_TISEL + TIM8_TISEL + TIM8 timer input selection register + 0x05C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[15:0] input + + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[15:0] input + + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + TI3SEL + Selects tim_ti3[15:0] input + + 16 + 4 + read-write + + + B_0x0 + tim_ti3_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti3_in1 + 0x1 + + + B_0xF + tim_ti3_in15 + 0xF + + + + + TI4SEL + Selects tim_ti4[15:0] input + + 24 + 4 + read-write + + + B_0x0 + tim_ti4_in0: TIMx_CH4 + 0x0 + + + B_0x1 + tim_ti4_in1 + 0x1 + + + B_0xF + tim_ti4_in15 + 0xF + + + + + + + TIM8_AF1 + TIM8_AF1 + TIM8 alternate function option register 1 + 0x060 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + TIMx_BKIN input enable + + 0 + 1 + read-write + + + B_0x0 + TIMx_BKIN input disabled + 0x0 + + + B_0x1 + TIMx_BKIN input enabled + 0x1 + + + + + BKCMP1E + tim_brk_cmp1 enable + + 1 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp1 input enabled + 0x1 + + + + + BKCMP2E + tim_brk_cmp2 enable + + 2 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp2 input enabled + 0x1 + + + + + BKCMP3E + tim_brk_cmp3 enable + + 3 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp3 input enabled + 0x1 + + + + + BKCMP4E + tim_brk_cmp4 enable + + 4 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp4 input enabled + 0x1 + + + + + BKCMP5E + tim_brk_cmp5 enable + + 5 + 1 + read-write + + + B_0x0 + tim_brk_cmp5 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp5 input enabled + 0x1 + + + + + BKCMP6E + tim_brk_cmp6 enable + + 6 + 1 + read-write + + + B_0x0 + tim_brk_cmp6 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp6 input enabled + 0x1 + + + + + BKCMP7E + tim_brk_cmp7 enable + + 7 + 1 + read-write + + + B_0x0 + tim_brk_cmp7 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp7 input enabled + 0x1 + + + + + BKCMP8E + tim_brk_cmp8 enable + + 8 + 1 + read-write + + + B_0x0 + tim_brk_cmp8 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp8 input enabled + 0x1 + + + + + BKINP + TIMx_BKIN input polarity + + 9 + 1 + read-write + + + B_0x0 + TIMx_BKIN input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + TIMx_BKIN input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP1P + tim_brk_cmp1 input polarity + + 10 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp1 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP2P + tim_brk_cmp2 input polarity + + 11 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp2 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP3P + tim_brk_cmp3 input polarity + + 12 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp3 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + BKCMP4P + tim_brk_cmp4 input polarity + + 13 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) + 0x0 + + + B_0x1 + tim_brk_cmp4 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) + 0x1 + + + + + ETRSEL + etr_in source selection + + 14 + 4 + read-write + + + B_0x0 + tim_etr0: TIMx_ETR input + 0x0 + + + B_0x1 + tim_etr1 + 0x1 + + + B_0xF + tim_etr15 + 0xF + + + + + + + TIM8_AF2 + TIM8_AF2 + TIM8 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BK2INE + TIMx_BKIN2 input enable + + 0 + 1 + read-write + + + B_0x0 + TIMx_BKIN2 input disabled + 0x0 + + + B_0x1 + TIMx_BKIN2 input enabled + 0x1 + + + + + BK2CMP1E + tim_brk2_cmp1 enable + + 1 + 1 + read-write + + + B_0x0 + tim_brk2_cmp1 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp1 input enabled + 0x1 + + + + + BK2CMP2E + tim_brk2_cmp2 enable + + 2 + 1 + read-write + + + B_0x0 + tim_brk2_cmp2 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp2 input enabled + 0x1 + + + + + BK2CMP3E + tim_brk2_cmp3 enable + + 3 + 1 + read-write + + + B_0x0 + tim_brk2_cmp3 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp3 input enabled + 0x1 + + + + + BK2CMP4E + tim_brk2_cmp4 enable + + 4 + 1 + read-write + + + B_0x0 + tim_brk2_cmp4 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp4 input enabled + 0x1 + + + + + BK2CMP5E + tim_brk2_cmp5 enable + + 5 + 1 + read-write + + + B_0x0 + tim_brk2_cmp5 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp5 input enabled + 0x1 + + + + + BK2CMP6E + tim_brk2_cmp6 enable + + 6 + 1 + read-write + + + B_0x0 + tim_brk2_cmp6 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp6 input enabled + 0x1 + + + + + BK2CMP7E + tim_brk2_cmp7 enable + + 7 + 1 + read-write + + + B_0x0 + tim_brk2_cmp7 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp7 input enabled + 0x1 + + + + + BK2CMP8E + tim_brk2_cmp8 enable + + 8 + 1 + read-write + + + B_0x0 + tim_brk2_cmp8 input disabled + 0x0 + + + B_0x1 + tim_brk2_cmp8 input enabled + 0x1 + + + + + BK2INP + TIMx_BKIN2 input polarity + + 9 + 1 + read-write + + + B_0x0 + TIMx_BKIN2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + TIMx_BKIN2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP1P + tim_brk2_cmp1 input polarity + + 10 + 1 + read-write + + + B_0x0 + tim_brk2_cmp1 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp1 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP2P + tim_brk2_cmp2 input polarity + + 11 + 1 + read-write + + + B_0x0 + tim_brk2_cmp2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP3P + tim_brk2_cmp3 input polarity + + 12 + 1 + read-write + + + B_0x0 + tim_brk2_cmp3 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp3 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + BK2CMP4P + tim_brk2_cmp4 input polarity + + 13 + 1 + read-write + + + B_0x0 + tim_brk2_cmp4 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1) + 0x0 + + + B_0x1 + tim_brk2_cmp4 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1) + 0x1 + + + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM8_DCR + TIM8_DCR + TIM8 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIMx_CR1 + 0x0 + + + B_0x1 + TIMx_CR2 + 0x1 + + + B_0x2 + TIMx_SMCR + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer + 0x0 + + + B_0x1 + 2 transfers + 0x1 + + + B_0x2 + 3 transfers + 0x2 + + + B_0x1A + 26 transfers + 0x1A + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x3 + CC2 + 0x3 + + + B_0x4 + CC3 + 0x4 + + + B_0x5 + CC4 + 0x5 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM8_DMAR + TIM8_DMAR + TIM8 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM8_S + 0X50013400 + + + TIM12 + General-purpose timers + TIM + 0x40001800 + + 0x0 + 0x400 + registers + + + TIM12 + TIM12 global interrupt + 120 + + + + TIM12_CR1 + TIM12_CR1 + TIM12 control register 1 + 0x0 + 16 + 0x00000000 + 0x0000FFFF + + + CEN + Counter enable + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + 1 + 1 + read-write + + + B_0x0 + UEV enabled. The Update (UEV) event is generated by one of the following events: + 0x0 + + + B_0x1 + UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. + 0x1 + + + + + URS + Update request source + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt or DMA request if enabled. These events can be: + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt or DMA request if enabled. + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIMx_ARR register is not buffered + 0x0 + + + B_0x1 + TIMx_ARR register is buffered + 0x1 + + + + + CKD + Clock division + 8 + 2 + read-write + + + B_0x0 + tDTS = ttim_ker_ck + 0x0 + + + B_0x1 + tDTS = 2 ttim_ker_ck + 0x1 + + + B_0x2 + tDTS = 4 ttim_ker_ck + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + 0x0 + + + B_0x1 + Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 0x1 + + + + + DITHEN + Dithering Enable + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM12_CR2 + TIM12_CR2 + TIM12 control register 2 + 0x4 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + MMS1 + Master mode selection + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset. + 0x0 + + + B_0x1 + Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode.When the Counter Enable signal is controlled by the trigger input, there is a delay on + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer. + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo) + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo) + 0x5 + + + B_0x6 + Compare - tim_oc3refc signal is used as trigger output (tim_trgo) + 0x6 + + + B_0x7 + Compare - tim_oc4refc signal is used as trigger output (tim_trgo) + 0x7 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15..0] multiplexer output is to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15..0], tim_ti2_in[15..0] and tim_ti3_in[15..0] multiplexers outputs are XORed and connected to the tim_ti1 input. See also sensors on page 1494. + 0x1 + + + + + + + TIM12_SMCR + TIM12_SMCR + TIM12 slave mode control register + 0x8 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + SMS + Slave mode selection + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + B_0x2 + Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. + 0x2 + + + B_0x3 + Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. + 0x3 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled. + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + TS + Trigger selection (see bits 21:20 for TS[4:3]) + 4 + 3 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 edge detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered timer input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered timer input 2 (tim_ti2fp2) + 0x6 + + + B_0x7 + External trigger input (tim_etrf) + 0x7 + + + + + MSM + Master/Slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event. + 0x1 + + + + + SMS_2 + Slave mode selection + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_2 + Trigger selection (see bits 21:20 for TS[4:3]) + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + + + TIM12_DIER + TIM12_DIER + TIM12 DMA/Interrupt enable register + 0xc + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled. + 0x0 + + + B_0x1 + Update interrupt enabled. + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled. + 0x0 + + + B_0x1 + CC1 interrupt enabled. + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled. + 0x0 + + + B_0x1 + CC2 interrupt enabled. + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled. + 0x0 + + + B_0x1 + Trigger interrupt enabled. + 0x1 + + + + + + + TIM12_SR + TIM12_SR + TIM12 status register + 0x10 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + UIF + Update interrupt flag + 0 + 1 + read-write + + + B_0x0 + No update occurred + 0x0 + + + B_0x1 + Update interrupt pending. This bit is set by hardware when the registers are updated: + 0x1 + + + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + read-write + + + TIF + Trigger interrupt flag + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred. + 0x0 + + + B_0x1 + Trigger interrupt pending. + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected. + 0x0 + + + B_0x1 + The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + read-write + + + + + TIM12_EGR + TIM12_EGR + TIM12 event generation register + 0x14 + 16 + 0x00000000 + 0x0000FFFF + + + UG + Update generation + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). + 0x1 + + + + + CC1G + Capture/compare 1 generation + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A capture/compare event is generated on channel 1: + 0x1 + + + + + CC2G + Capture/compare 2 generation + 2 + 1 + write-only + + + TG + Trigger generation + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 0x1 + + + + + + + TIM12_CCMR1_Input + TIM12_CCMR1_Input + TIM12 capture/compare mode register 1 [alternate] + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fDTS + 0x0 + + + B_0x1 + fSAMPLING=ftim_ker_ck, N=2 + 0x1 + + + B_0x2 + fSAMPLING=ftim_ker_ck, N=4 + 0x2 + + + B_0x3 + fSAMPLING=ftim_ker_ck, N=8 + 0x3 + + + B_0x4 + fSAMPLING=fDTS/2, N=6 + 0x4 + + + B_0x5 + fSAMPLING=fDTS/2, N=8 + 0x5 + + + B_0x6 + fSAMPLING=fDTS/4, N=6 + 0x6 + + + B_0x7 + fSAMPLING=fDTS/4, N=8 + 0x7 + + + B_0x8 + fSAMPLING=fDTS/8, N=6 + 0x8 + + + B_0x9 + fSAMPLING=fDTS/8, N=8 + 0x9 + + + B_0xA + fSAMPLING=fDTS/16, N=5 + 0xA + + + B_0xB + fSAMPLING=fDTS/16, N=6 + 0xB + + + B_0xC + fSAMPLING=fDTS/16, N=8 + 0xC + + + B_0xD + fSAMPLING=fDTS/32, N=5 + 0xD + + + B_0xE + fSAMPLING=fDTS/32, N=6 + 0xE + + + B_0xF + fSAMPLING=fDTS/32, N=8 + 0xF + + + + + CC2S + Capture/compare 2 selection + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM12_CCMR1_Output + TIM12_CCMR1_Output + TIM12 capture/compare mode register 1 [alternate] + TIM12_CCMR1_Input + 0x18 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) + 0x3 + + + + + OC1FE + Output compare 1 fast enable + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 0x1 + + + + + OC1PE + Output compare 1 preload enable + 3 + 1 + read-write + + + B_0x0 + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. + 0x0 + + + B_0x1 + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 0x1 + + + + + OC1M1 + Output compare 1 mode + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). + 0x0 + + + B_0x1 + Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0) as long as TIMx_CNT>TIMx_CCR1 else active (tim_oc1ref=1). + 0x6 + + + B_0x7 + PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. + 0x7 + + + + + CC2S + Capture/Compare 2 selection + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M1 + Output compare 2 mode + 12 + 3 + read-write + + + OC1M2 + Output compare 1 mode + 16 + 1 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). + 0x0 + + + B_0x1 + Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + 0x1 + + + + + OC2M2 + Output compare 2 mode + 24 + 1 + read-write + + + + + TIM12_CCER + TIM12_CCER + TIM12 capture/compare enable register + 0x20 + 16 + 0x00000000 + 0x0000FFFF + + + CC1E + Capture/Compare 1 output enable. + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output Polarity. + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NP + Capture/Compare 1 output Polarity. + 3 + 1 + read-write + + + CC2E + Capture/Compare 2 output enable. + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output Polarity. + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 output Polarity. + 7 + 1 + read-write + + + + + TIM12_CNT + TIM12_CNT + TIM12 counter + 0x24 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CNT + or UIFCPY: Value depends on IUFREMAP in TIMx_CR1. + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-write + + + + + TIM12_PSC + TIM12_PSC + TIM12 prescaler + 0x28 + 16 + 0x00000000 + 0x0000FFFF + + + PSC + Prescaler value + 0 + 16 + read-write + + + + + TIM12_ARR + TIM12_ARR + TIM12 auto-reload register + 0x2c + 0x20 + 0xFFFFFFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + 0 + 20 + read-write + + + + + TIM12_CCR1 + TIM12_CCR1 + TIM12 capture/compare register 1 + 0x34 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + 0 + 20 + read-write + + + + + TIM12_CCR2 + TIM12_CCR2 + TIM12 capture/compare register 2 + 0x38 + 0x20 + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + 0 + 20 + read-write + + + + + TIM12_TISEL + TIM12_TISEL + TIM12 timer input selection register + 0x5c + 0x20 + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + Selects tim_ti1[0..15] input + 0 + 4 + read-write + + + B_0x0 + tim_ti1_in0: TIMx_CH1 + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + Selects tim_ti2[0..15] input + 8 + 4 + read-write + + + B_0x0 + tim_ti2_in0: TIMx_CH2 + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + + + + + SEC_TIM12 + 0x50001800 + + + TIM15 + TIM15 address block description + TIM15 + 0x40014000 + + 0x0 + 0x3E4 + registers + + + TIM15 + TIM15 global interrupt + 71 + + + + TIM15_CR1 + TIM15_CR1 + TIM15 control register 1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + CEN + Counter enable + + 0 + 1 + read-write + + + B_0x0 + Counter disabled + 0x0 + + + B_0x1 + Counter enabled + 0x1 + + + + + UDIS + Update disable + + 1 + 1 + read-write + + + B_0x0 + UEV enabled. + 0x0 + + + B_0x1 + UEV disabled. + 0x1 + + + + + URS + Update request source + + 2 + 1 + read-write + + + B_0x0 + Any of the following events generate an update interrupt if enabled. + 0x0 + + + B_0x1 + Only counter overflow/underflow generates an update interrupt if enabled + 0x1 + + + + + OPM + One-pulse mode + 3 + 1 + read-write + + + B_0x0 + Counter is not stopped at update event + 0x0 + + + B_0x1 + Counter stops counting at the next update event (clearing the bit CEN) + 0x1 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + read-write + + + B_0x0 + TIM15_ARR register is not buffered + 0x0 + + + B_0x1 + TIM15_ARR register is buffered + 0x1 + + + + + CKD + Clock division + + 8 + 2 + read-write + + + B_0x0 + tless thansub>DTS less than/sub>= tless thansub>tim_ker_ckless than/sub> + 0x0 + + + B_0x1 + tless thansub>DTSless than/sub> = 2*tless thansub>tim_ker_ckless than/sub> + 0x1 + + + B_0x2 + tless thansub>DTSless than/sub> = 4*tless thansub>tim_ker_ckless than/sub> + 0x2 + + + + + UIFREMAP + UIF status bit remapping + 11 + 1 + read-write + + + B_0x0 + No remapping. + 0x0 + + + B_0x1 + Remapping enabled. + 0x1 + + + + + DITHEN + Dithering enable + + 12 + 1 + read-write + + + B_0x0 + Dithering disabled + 0x0 + + + B_0x1 + Dithering enabled + 0x1 + + + + + + + TIM15_CR2 + TIM15_CR2 + TIM15 control register 2 + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + CCPC + Capture/compare preloaded control + + 0 + 1 + read-write + + + B_0x0 + CCxE, CCxNE and OCxM bits are not preloaded + 0x0 + + + B_0x1 + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit). + 0x1 + + + + + CCUS + Capture/compare control update selection + + 2 + 1 + read-write + + + B_0x0 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. + 0x0 + + + B_0x1 + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi. + 0x1 + + + + + CCDS + Capture/compare DMA selection + 3 + 1 + read-write + + + B_0x0 + CCx DMA request sent when CCx event occurs + 0x0 + + + B_0x1 + CCx DMA requests sent when update event occurs + 0x1 + + + + + MMS + Master mode selection + + 4 + 3 + read-write + + + B_0x0 + Reset - the UG bit from the TIM15_EGR register is used as trigger output (tim_trgo). + 0x0 + + + B_0x1 + Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). + 0x1 + + + B_0x2 + Update - The update event is selected as trigger output (tim_trgo). + 0x2 + + + B_0x3 + Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). + 0x3 + + + B_0x4 + Compare - tim_oc1refc signal is used as trigger output (tim_trgo). + 0x4 + + + B_0x5 + Compare - tim_oc2refc signal is used as trigger output (tim_trgo). + 0x5 + + + + + TI1S + tim_ti1 selection + 7 + 1 + read-write + + + B_0x0 + The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input + 0x0 + + + B_0x1 + The tim_ti1_in[15:0] and tim_ti2_in[15:0] multiplexers output are connected to the tim_ti1 input (XOR combination) + 0x1 + + + + + OIS1 + Output Idle state 1 (tim_oc1 output) + + 8 + 1 + read-write + + + B_0x0 + tim_oc1=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + tim_oc1=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS1N + Output Idle state 1 (tim_oc1n output) + + 9 + 1 + read-write + + + B_0x0 + tim_oc1n=0 after a dead-time when MOE=0 + 0x0 + + + B_0x1 + tim_oc1n=1 after a dead-time when MOE=0 + 0x1 + + + + + OIS2 + Output idle state 2 (tim_oc2 output) + + 10 + 1 + read-write + + + B_0x0 + tim_oc2=0 when MOE=0 + 0x0 + + + B_0x1 + tim_oc2=1 when MOE=0 + 0x1 + + + + + + + TIM15_SMCR + TIM15_SMCR + TIM15 slave mode control register + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SMS + SMS[2:0]: Slave mode selection + + 0 + 3 + read-write + + + B_0x0 + Slave mode disabled - if CEN = 1' then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x4 + Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. + 0x4 + + + B_0x5 + Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. + 0x5 + + + B_0x6 + Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). + 0x6 + + + B_0x7 + External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. + 0x7 + + + + + TS + TS[2:0]: Trigger selection + + 4 + 3 + read-write + + + B_0x0 + Internal Trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal Trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal Trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal Trigger 3 (tim_itr3) + 0x3 + + + B_0x4 + tim_ti1 Edge Detector (tim_ti1f_ed) + 0x4 + + + B_0x5 + Filtered Timer Input 1 (tim_ti1fp1) + 0x5 + + + B_0x6 + Filtered Timer Input 2 (tim_ti2fp2) + 0x6 + + + + + MSM + Master/slave mode + 7 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). + 0x1 + + + + + SMS_1 + Slave mode selection +When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. +Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. +Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. + 16 + 1 + read-write + + + B_0x0 + Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. + 0x0 + + + B_0x1 + Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. + 0x1 + + + + + TS_1 + Trigger selection +This bit-field selects the trigger input to be used to synchronize the counter. +Others: Reserved +See for product specific implementation details. +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. + 20 + 2 + read-write + + + B_0x0 + Internal trigger 0 (tim_itr0) + 0x0 + + + B_0x1 + Internal trigger 1 (tim_itr1) + 0x1 + + + B_0x2 + Internal trigger 2 (tim_itr2) + 0x2 + + + B_0x3 + Internal trigger 3 (tim_itr3) + 0x3 + + + + + SMSPE + SMS preload enable + + 24 + 1 + read-write + + + B_0x0 + SMS[3:0] bitfield is not preloaded + 0x0 + + + B_0x1 + SMS[3:0] preload is enabled + 0x1 + + + + + + + TIM15_DIER + TIM15_DIER + TIM15 DMA/interrupt enable register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + UIE + Update interrupt enable + 0 + 1 + read-write + + + B_0x0 + Update interrupt disabled + 0x0 + + + B_0x1 + Update interrupt enabled + 0x1 + + + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + read-write + + + B_0x0 + CC1 interrupt disabled + 0x0 + + + B_0x1 + CC1 interrupt enabled + 0x1 + + + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + read-write + + + B_0x0 + CC2 interrupt disabled + 0x0 + + + B_0x1 + CC2 interrupt enabled + 0x1 + + + + + COMIE + COM interrupt enable + 5 + 1 + read-write + + + B_0x0 + COM interrupt disabled + 0x0 + + + B_0x1 + COM interrupt enabled + 0x1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + read-write + + + B_0x0 + Trigger interrupt disabled + 0x0 + + + B_0x1 + Trigger interrupt enabled + 0x1 + + + + + BIE + Break interrupt enable + 7 + 1 + read-write + + + B_0x0 + Break interrupt disabled + 0x0 + + + B_0x1 + Break interrupt enabled + 0x1 + + + + + UDE + Update DMA request enable + 8 + 1 + read-write + + + B_0x0 + Update DMA request disabled + 0x0 + + + B_0x1 + Update DMA request enabled + 0x1 + + + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + read-write + + + B_0x0 + CC1 DMA request disabled + 0x0 + + + B_0x1 + CC1 DMA request enabled + 0x1 + + + + + COMDE + COM DMA request enable + 13 + 1 + read-write + + + B_0x0 + COM DMA request disabled + 0x0 + + + B_0x1 + COM DMA request enabled + 0x1 + + + + + TDE + Trigger DMA request enable + 14 + 1 + read-write + + + B_0x0 + Trigger DMA request disabled + 0x0 + + + B_0x1 + Trigger DMA request enabled + 0x1 + + + + + + + TIM15_SR + TIM15_SR + TIM15 status register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + UIF + Update interrupt flag + + 0 + 1 + read-write + + + B_0x0 + No update occurred. + 0x0 + + + B_0x1 + Update interrupt pending. + 0x1 + + + + + CC1IF + Capture/Compare 1 interrupt flag + + 1 + 1 + read-write + + + B_0x0 + No compare match / No input capture occurred + 0x0 + + + B_0x1 + A compare match or an input capture occurred + 0x1 + + + + + CC2IF + Capture/Compare 2 interrupt flag + + 2 + 1 + read-write + + + COMIF + COM interrupt flag + + 5 + 1 + read-write + + + B_0x0 + No COM event occurred + 0x0 + + + B_0x1 + COM interrupt pending + 0x1 + + + + + TIF + Trigger interrupt flag + + 6 + 1 + read-write + + + B_0x0 + No trigger event occurred + 0x0 + + + B_0x1 + Trigger interrupt pending + 0x1 + + + + + BIF + Break interrupt flag + + 7 + 1 + read-write + + + B_0x0 + No break event occurred + 0x0 + + + B_0x1 + An active level has been detected on the break input + 0x1 + + + + + CC1OF + Capture/Compare 1 overcapture flag + + 9 + 1 + read-write + + + B_0x0 + No overcapture has been detected + 0x0 + + + B_0x1 + The counter value has been captured in TIM15_CCR1 register while CC1IF flag was already set + 0x1 + + + + + CC2OF + Capture/Compare 2 overcapture flag + + 10 + 1 + read-write + + + + + TIM15_EGR + TIM15_EGR + TIM15 event generation register + 0x14 + 16 + read-write + 0x0000 + 0xFFFF + + + UG + Update generation + + 0 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + Reinitialize the counter and generates an update of the registers. + 0x1 + + + + + CC1G + Capture/Compare 1 generation + + 1 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + + + CC2G + Capture/Compare 2 generation + + 2 + 1 + write-only + + + COMG + Capture/Compare control update generation + + 5 + 1 + read-write + + + B_0x0 + No action + 0x0 + + + B_0x1 + When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + 0x1 + + + + + TG + Trigger generation + + 6 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + The TIF flag is set in TIM15_SR register. + 0x1 + + + + + BG + Break generation + + 7 + 1 + write-only + + + B_0x0 + No action + 0x0 + + + B_0x1 + A break event is generated. + 0x1 + + + + + + + TIM15_CCMR1 + TIM15_CCMR1 + TIM15 capture/compare mode register 1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1 + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2 + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + IC1PSC + Input capture 1 prescaler + + 2 + 2 + read-write + + + B_0x0 + no prescaler, capture is done each time an edge is detected on the capture input + 0x0 + + + B_0x1 + capture is done once every 2 events + 0x1 + + + B_0x2 + capture is done once every 4 events + 0x2 + + + B_0x3 + capture is done once every 8 events + 0x3 + + + + + IC1F + Input capture 1 filter + + 4 + 4 + read-write + + + B_0x0 + No filter, sampling is done at fless thansub>DTSless than/sub> + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2 + 0x1 + + + B_0x2 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1 + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + Input capture 2 filter + 12 + 4 + read-write + + + + + TIM15_CCMR1_ALTERNATE1 + TIM15_CCMR1_ALTERNATE1 + TIM15 capture/compare mode register 1 + TIM15_CCMR1 + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CC1S + Capture/Compare 1 selection + + 0 + 2 + read-write + + + B_0x0 + CC1 channel is configured as output. + 0x0 + + + B_0x1 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. + 0x1 + + + B_0x2 + CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2. + 0x2 + + + B_0x3 + CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. + 0x3 + + + + + OC1FE + Output Compare 1 fast enable + + 2 + 1 + read-write + + + B_0x0 + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. + 0x0 + + + B_0x1 + An active edge on the trigger input acts like a compare match on CC1 output. + 0x1 + + + + + OC1PE + Output Compare 1 preload enable + + 3 + 1 + read-write + + + B_0x0 + Preload register on TIM15_CCR1 disabled. + 0x0 + + + B_0x1 + Preload register on TIM15_CCR1 enabled. + 0x1 + + + + + OC1M + OC1M[2:0]: Output compare 1 mode + + 4 + 3 + read-write + + + B_0x0 + Frozen - The comparison between the output compare register TIM15_CCR1 and the counter TIM15_CNT has no effect on the outputs. + 0x0 + + + B_0x1 + Set channel 1 to active level on match. + 0x1 + + + B_0x2 + Set channel 1 to inactive level on match. + 0x2 + + + B_0x3 + Toggle - tim_oc1ref toggles when TIM15_CNT=TIM15_CCR1. + 0x3 + + + B_0x4 + Force inactive level - tim_oc1ref is forced low. + 0x4 + + + B_0x5 + Force active level - tim_oc1ref is forced high. + 0x5 + + + B_0x6 + PWM mode 1 - Channel 1 is active as long as TIM15_CNTless thanTIM15_CCR1 else inactive. + 0x6 + + + B_0x7 + PWM mode 2 - Channel 1 is inactive as long as TIM15_CNTless thanTIM15_CCR1 else active. + 0x7 + + + + + OC1CE + Output compare 1 clear enable + 7 + 1 + read-write + + + B_0x0 + tim_oc1ref is not affected by the tim_ocref_clr_int input. + 0x0 + + + B_0x1 + tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input. + 0x1 + + + + + CC2S + Capture/Compare 2 selection + + 8 + 2 + read-write + + + B_0x0 + CC2 channel is configured as output. + 0x0 + + + B_0x1 + CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2. + 0x1 + + + B_0x2 + C2 channel is configured as input, tim_ic2 is mapped on tim_ti1. + 0x2 + + + B_0x3 + CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. + 0x3 + + + + + OC2FE + Output compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + Output compare 2 preload enable + 11 + 1 + read-write + + + OC2M + OC2M[2:0]: Output compare 2 mode + 12 + 3 + read-write + + + OC2CE + Output compare 2 clear enable + 15 + 1 + read-write + + + OC1M_1 + OC1M[3] + 16 + 1 + read-write + + + OC2M_1 + OC2M[3] + 24 + 1 + read-write + + + + + TIM15_CCER + TIM15_CCER + TIM15 capture/compare enable register + 0x20 + 16 + read-write + 0x0000 + 0xFFFF + + + CC1E + Capture/Compare 1 output enable + + 0 + 1 + read-write + + + B_0x0 + Capture mode disabled / OC1 is not active (see below) + 0x0 + + + B_0x1 + Capture mode enabled / OC1 signal is output on the corresponding output pin + 0x1 + + + + + CC1P + Capture/Compare 1 output polarity + + 1 + 1 + read-write + + + B_0x0 + OC1 active high (output mode) / Edge sensitivity selection (input mode, see below) + 0x0 + + + B_0x1 + OC1 active low (output mode) / Edge sensitivity selection (input mode, see below) + 0x1 + + + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + read-write + + + B_0x0 + Off - tim_oc1n is not active. + 0x0 + + + B_0x1 + On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. + 0x1 + + + + + CC1NP + Capture/Compare 1 complementary output polarity + + 3 + 1 + read-write + + + B_0x0 + tim_oc1n active high + 0x0 + + + B_0x1 + tim_oc1n active low + 0x1 + + + + + CC2E + Capture/Compare 2 output enable + + 4 + 1 + read-write + + + CC2P + Capture/Compare 2 output polarity + + 5 + 1 + read-write + + + CC2NP + Capture/Compare 2 complementary output polarity + + 7 + 1 + read-write + + + + + TIM15_CNT + TIM15_CNT + TIM15 counter + 0x24 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNT + Counter value + + 0 + 16 + read-write + + + UIFCPY + UIF Copy + + 31 + 1 + read-only + + + + + TIM15_PSC + TIM15_PSC + TIM15 prescaler + 0x28 + 16 + read-write + 0x0000 + 0xFFFF + + + PSC + Prescaler value + + 0 + 16 + read-write + + + + + TIM15_ARR + TIM15_ARR + TIM15 auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + 0xFFFFFFFF + + + ARR + Auto-reload value + + 0 + 20 + read-write + + + + + TIM15_RCR + TIM15_RCR + TIM15 repetition counter register + 0x30 + 16 + read-write + 0x0000 + 0xFFFF + + + REP + Repetition counter reload value + + 0 + 8 + read-write + + + + + TIM15_CCR1 + TIM15_CCR1 + TIM15 capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR1 + Capture/compare 1 value + + 0 + 20 + read-write + + + + + TIM15_CCR2 + TIM15_CCR2 + TIM15 capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCR2 + Capture/compare 2 value + + 0 + 20 + read-write + + + + + TIM15_BDTR + TIM15_BDTR + TIM15 break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTG + Dead-time generator setup + + 0 + 8 + read-write + + + LOCK + Lock configuration + + 8 + 2 + read-write + + + B_0x0 + LOCK OFF - No bit is write protected + 0x0 + + + B_0x1 + LOCK Level 1 = DTG bits in TIM15_BDTR register, OISx and OISxN bits in TIM15_CR2 register and BKBID/BKE/BKP/AOE bits in TIM15_BDTR register can no longer be written + 0x1 + + + B_0x2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIM15_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 0x2 + + + B_0x3 + OCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIM15_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 0x3 + + + + + OSSI + Off-state selection for Idle mode + + 10 + 1 + read-write + + + B_0x0 + When inactive, tim_ocx/tim_ocxn outputs are disabled (tim_ocx/tim_ocxn enable output signal=0) + 0x0 + + + B_0x1 + When inactive, tim_ocx/tim_ocxn outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. + 0x1 + + + + + OSSR + Off-state selection for Run mode + + 11 + 1 + read-write + + + B_0x0 + When inactive, tim_ocx/tim_ocxn outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state) + 0x0 + + + B_0x1 + When inactive, tim_ocx/tim_ocxn outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). + 0x1 + + + + + BKE + Break enable + + 12 + 1 + read-write + + + B_0x0 + Break inputs (tim_brk and tim_sys_brk clock failure event) disabled + 0x0 + + + + + BKP + Break polarity + + 13 + 1 + read-write + + + B_0x0 + Break input tim_brk is active low + 0x0 + + + B_0x1 + Break input tim_brk is active high + 0x1 + + + + + AOE + Automatic output enable + + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is not be active) + 0x1 + + + + + MOE + Main output enable + + 15 + 1 + read-write + + + B_0x0 + tim_ocx and tim_ocxn outputs are disabled or forced to idle state depending on the OSSI bit. + 0x0 + + + B_0x1 + tim_ocx and tim_ocxn outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIM15_CCER register) + 0x1 + + + + + BKF + Break filter + + 16 + 4 + read-write + + + B_0x0 + No filter, tim_brk acts asynchronously + 0x0 + + + B_0x1 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 + 0x1 + + + B_0x2 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 + 0x2 + + + B_0x3 + fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 + 0x3 + + + B_0x4 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 + 0x4 + + + B_0x5 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 + 0x5 + + + B_0x6 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 + 0x6 + + + B_0x7 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 + 0x7 + + + B_0x8 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 + 0x8 + + + B_0x9 + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 + 0x9 + + + B_0xA + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 + 0xA + + + B_0xB + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 + 0xB + + + B_0xC + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 + 0xC + + + B_0xD + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 + 0xD + + + B_0xE + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 + 0xE + + + B_0xF + fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 + 0xF + + + + + BKDSRM + Break disarm + + 26 + 1 + read-write + + + B_0x0 + Break input tim_brk is armed + 0x0 + + + B_0x1 + Break input tim_brk is disarmed + 0x1 + + + + + BKBID + Break bidirectional + + 28 + 1 + read-write + + + B_0x0 + Break input tim_brk in input mode + 0x0 + + + B_0x1 + Break input tim_brk in bidirectional mode + 0x1 + + + + + + + TIM15_DTR2 + TIM15_DTR2 + TIM15 timer deadtime register 2 + 0x054 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTGF + Dead-time falling edge generator setup + + 0 + 8 + read-write + + + DTAE + Deadtime asymmetric enable + + 16 + 1 + read-write + + + B_0x0 + Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + 0x0 + + + B_0x1 + Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + 0x1 + + + + + DTPE + Deadtime preload enable + + 17 + 1 + read-write + + + B_0x0 + Deadtime value is not preloaded + 0x0 + + + B_0x1 + Deadtime value preload is enabled + 0x1 + + + + + + + TIM15_TISEL + TIM15_TISEL + TIM15 input selection register + 0x5C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TI1SEL + selects tim_ti1_in[15:0] input + + 0 + 4 + read-write + + + B_0x0 + TIM15_CH1 input (tim_ti1_in0) + 0x0 + + + B_0x1 + tim_ti1_in1 + 0x1 + + + B_0xF + tim_ti1_in15 + 0xF + + + + + TI2SEL + selects tim_ti2_in[15:0] input + + 8 + 4 + read-write + + + B_0x0 + TIM15_CH2 input (tim_ti2_in0) + 0x0 + + + B_0x1 + tim_ti2_in1 + 0x1 + + + B_0xF + tim_ti2_in15 + 0xF + + + + + + + TIM15_AF1 + TIM15_AF1 + TIM15 alternate function register 1 + 0x060 + 0x20 + read-write + 0x00000001 + 0xFFFFFFFF + + + BKINE + TIMx_BKIN input enable + + 0 + 1 + read-write + + + B_0x0 + TIMx_BKIN input disabled + 0x0 + + + B_0x1 + TIMx_BKIN input enabled + 0x1 + + + + + BKCMP1E + tim_brk_cmp1 enable + + 1 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp1 input enabled + 0x1 + + + + + BKCMP2E + tim_brk_cmp2 enable + + 2 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp2 input enabled + 0x1 + + + + + BKCMP3E + tim_brk_cmp3 enable + + 3 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp3 input enabled + 0x1 + + + + + BKCMP4E + tim_brk_cmp4 enable + + 4 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp4 input enabled + 0x1 + + + + + BKCMP5E + tim_brk_cmp5 enable + + 5 + 1 + read-write + + + B_0x0 + tim_brk_cmp5 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp5 input enabled + 0x1 + + + + + BKCMP6E + tim_brk_cmp6 enable + + 6 + 1 + read-write + + + B_0x0 + tim_brk_cmp6 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp6 input enabled + 0x1 + + + + + BKCMP7E + tim_brk_cmp7 enable + + 7 + 1 + read-write + + + B_0x0 + tim_brk_cmp7 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp7 input enabled + 0x1 + + + + + BKCMP8E + tim_brk_cmp8 enable + + 8 + 1 + read-write + + + B_0x0 + tim_brk_cmp8 input disabled + 0x0 + + + B_0x1 + tim_brk_cmp8 input enabled + 0x1 + + + + + BKINP + TIMx_BKIN input polarity + + 9 + 1 + read-write + + + B_0x0 + TIMx_BKIN input is active high + 0x0 + + + B_0x1 + TIMx_BKIN input is active low + 0x1 + + + + + BKCMP1P + tim_brk_cmp1 input polarity + + 10 + 1 + read-write + + + B_0x0 + tim_brk_cmp1 input is active high + 0x0 + + + B_0x1 + tim_brk_cmp1 input is active low + 0x1 + + + + + BKCMP2P + tim_brk_cmp2 input polarity + + 11 + 1 + read-write + + + B_0x0 + tim_brk_cmp2 input is active high + 0x0 + + + B_0x1 + tim_brk_cmp2 input is active low + 0x1 + + + + + BKCMP3P + tim_brk_cmp3 input polarity + + 12 + 1 + read-write + + + B_0x0 + tim_brk_cmp3 input is active high + 0x0 + + + B_0x1 + tim_brk_cmp3 input is active low + 0x1 + + + + + BKCMP4P + tim_brk_cmp4 input polarity + + 13 + 1 + read-write + + + B_0x0 + tim_brk_cmp4 input is active high + 0x0 + + + B_0x1 + tim_brk_cmp4 input is active low + 0x1 + + + + + + + TIM15_AF2 + TIM15_AF2 + TIM15 alternate function register 2 + 0x064 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + OCRSEL + ocref_clr source selection + + 16 + 3 + read-write + + + B_0x0 + tim_ocref_clr0 + 0x0 + + + B_0x1 + tim_ocref_clr1 + 0x1 + + + B_0x2 + tim_ocref_clr2 + 0x2 + + + B_0x3 + tim_ocref_clr3 + 0x3 + + + B_0x4 + tim_ocref_clr4 + 0x4 + + + B_0x5 + tim_ocref_clr5 + 0x5 + + + B_0x6 + tim_ocref_clr6 + 0x6 + + + B_0x7 + tim_ocref_clr7 + 0x7 + + + + + + + TIM15_DCR + TIM15_DCR + TIM15 DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DBA + DMA base address + + 0 + 5 + read-write + + + B_0x0 + TIM15_CR1, + 0x0 + + + B_0x1 + TIM15_CR2, + 0x1 + + + B_0x2 + TIM15_SMCR, + 0x2 + + + + + DBL + DMA burst length + + 8 + 5 + read-write + + + B_0x0 + 1 transfer, + 0x0 + + + B_0x1 + 2 transfers, + 0x1 + + + B_0x2 + 3 transfers, + 0x2 + + + B_0x11 + 18 transfers. + 0x11 + + + + + DBSS + DMA burst source selection + + 16 + 4 + read-write + + + B_0x1 + Update + 0x1 + + + B_0x2 + CC1 + 0x2 + + + B_0x6 + COM + 0x6 + + + B_0x7 + Trigger + 0x7 + + + + + + + TIM15_DMAR + TIM15_DMAR + TIM15 DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMAB + DMA register for burst accesses + + 0 + 32 + read-write + + + + + + + TIM15_S + 0X50014000 + + + UCPD + UCPD register block + UCPD + 0x4000dc00 + + 0x0 + 0x400 + registers + + + UCPD1 + UCPD1 global interrupt + 76 + + + + UCPD_CFGR1 + UCPD_CFGR1 + UCPD configuration register 1 + 0x000 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + HBITCLKDIV + Division ratio for producing half-bit clock + + 0 + 6 + read-write + + + B_0x00 + 1 (bypass) + 0x00 + + + B_0x1A + 27 + 0x1A + + + B_0x3F + 64 + 0x3F + + + + + IFRGAP + Division ratio for producing inter-frame gap timer clock + + 6 + 5 + read-write + + + B_0x00 + Not supported + 0x00 + + + B_0x01 + 2 + 0x01 + + + B_0x0D + 14 + 0x0D + + + B_0x0E + 15 + 0x0E + + + B_0x0F + 16 + 0x0F + + + B_0x1F + 32 + 0x1F + + + + + TRANSWIN + Transition window duration + + 11 + 5 + read-write + + + B_0x00 + Not supported + 0x00 + + + B_0x01 + 2 + 0x01 + + + B_0x09 + 10 (recommended) + 0x09 + + + B_0x1F + 32 + 0x1F + + + + + PSC_USBPDCLK + Pre-scaler division ratio for generating ucpd_clk + + 17 + 3 + read-write + + + B_0x0 + 1 (bypass) + 0x0 + + + B_0x1 + 2 + 0x1 + + + B_0x2 + 4 + 0x2 + + + B_0x3 + 8 + 0x3 + + + B_0x4 + 16 + 0x4 + + + + + RXORDSETEN + Receiver ordered set enable + + 20 + 9 + read-write + + + TXDMAEN + Transmission DMA mode enable + + 29 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXDMAEN + Reception DMA mode enable + + 30 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + UCPDEN + UCPD peripheral enable + + 31 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + UCPD_CFGR2 + UCPD_CFGR2 + UCPD configuration register 2 + 0x004 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RXFILTDIS + BMC decoder Rx pre-filter enable + + 0 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + RXFILT2N3 + BMC decoder Rx pre-filter sampling method + + 1 + 1 + read-write + + + B_0x0 + 3 samples + 0x0 + + + B_0x1 + 2 samples + 0x1 + + + + + FORCECLK + Force ClkReq clock request + 2 + 1 + read-write + + + B_0x0 + Do not force clock request + 0x0 + + + B_0x1 + Force clock request + 0x1 + + + + + WUPEN + Wake-up from Stop mode enable + + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXAFILTEN + Rx analog filter enable + + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + UCPD_CFGR3 + UCPD_CFGR3 + UCPD configuration register 3 + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TRIM_CC1_RD + SW trim value for Rd resistor on the CC1 line + 0 + 4 + read-write + + + TRIM_CC1_RP + SW trim value for Rp current sources on the CC1 line + 9 + 4 + read-write + + + TRIM_CC2_RD + SW trim value for Rd resistor on the CC2 line + 16 + 4 + read-write + + + TRIM_CC2_RP + SW trim value for Rp current sources on the CC2 line + 25 + 4 + read-write + + + + + UCPD_CR + UCPD_CR + UCPD control register + 0x00C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXMODE + Type of Tx packet + + 0 + 2 + read-write + + + B_0x0 + Transmission of Tx packet previously defined in other registers + 0x0 + + + B_0x1 + Cable Reset sequence + 0x1 + + + B_0x2 + BIST test sequence (BIST Carrier Mode 2) + 0x2 + + + + + TXSEND + Command to send a Tx packet + + 2 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Start Tx packet transmission + 0x1 + + + + + TXHRST + Command to send a Tx Hard Reset + + 3 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Start Tx Hard Reset message + 0x1 + + + + + RXMODE + Receiver mode + + 4 + 1 + read-write + + + B_0x0 + Normal receive mode + 0x0 + + + B_0x1 + BIST receive mode (BIST test data mode) + 0x1 + + + + + PHYRXEN + USB Power Delivery receiver enable + + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + PHYCCSEL + CC1/CC2 line selector for USB Power Delivery signaling + + 6 + 1 + read-write + + + B_0x0 + Use CC1 IO for Power Delivery communication + 0x0 + + + B_0x1 + Use CC2 IO for Power Delivery communication + 0x1 + + + + + ANASUBMODE + Analog PHY sub-mode + + 7 + 2 + read-write + + + ANAMODE + Analog PHY operating mode + + 9 + 1 + read-write + + + B_0x0 + Source + 0x0 + + + B_0x1 + Sink + 0x1 + + + + + CCENABLE + CC line enable + + 10 + 2 + read-write + + + B_0x0 + Disable both PHYs + 0x0 + + + B_0x1 + Enable CC1 PHY + 0x1 + + + B_0x2 + Enable CC2 PHY + 0x2 + + + B_0x3 + Enable CC1 and CC2 PHY + 0x3 + + + + + FRSRXEN + FRS event detection enable + + 16 + 1 + read-write + + + B_0x1 + Enable + 0x1 + + + + + FRSTX + FRS Tx signaling enable. + 17 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RDCH + Rdch condition drive + + 18 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Rdch condition drive + 0x1 + + + + + CC1TCDIS + CC1 Type-C detector disable + + 20 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + CC2TCDIS + CC2 Type-C detector disable + + 21 + 1 + read-write + + + B_0x0 + Enable + 0x0 + + + B_0x1 + Disable + 0x1 + + + + + + + UCPD_IMR + UCPD_IMR + UCPD interrupt mask register + 0x010 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXISIE + TXIS interrupt enable + 0 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TXMSGDISCIE + TXMSGDISC interrupt enable + 1 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TXMSGSENTIE + TXMSGSENT interrupt enable + 2 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TXMSGABTIE + TXMSGABT interrupt enable + 3 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HRSTDISCIE + HRSTDISC interrupt enable + 4 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + HRSTSENTIE + HRSTSENT interrupt enable + 5 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TXUNDIE + TXUND interrupt enable + 6 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXNEIE + RXNE interrupt enable + 8 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXORDDETIE + RXORDDET interrupt enable + 9 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXHRSTDETIE + RXHRSTDET interrupt enable + 10 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXOVRIE + RXOVR interrupt enable + 11 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + RXMSGENDIE + RXMSGEND interrupt enable + 12 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + TYPECEVT1IE + TYPECEVT1 interrupt enable + 14 + 1 + read-write + + + TYPECEVT2IE + TYPECEVT2 interrupt enable + 15 + 1 + read-write + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + FRSEVTIE + FRSEVT interrupt enable + 20 + 1 + read-only + + + B_0x0 + Disable + 0x0 + + + B_0x1 + Enable + 0x1 + + + + + + + UCPD_SR + UCPD_SR + UCPD status register + 0x014 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + TXIS + Transmit interrupt status + + 0 + 1 + read-only + + + B_0x0 + New Tx data write not required + 0x0 + + + B_0x1 + New Tx data write required + 0x1 + + + + + TXMSGDISC + Message transmission discarded + + 1 + 1 + read-only + + + B_0x0 + No Tx message discarded + 0x0 + + + B_0x1 + Tx message discarded + 0x1 + + + + + TXMSGSENT + Message transmission completed + + 2 + 1 + read-only + + + B_0x0 + No Tx message completed + 0x0 + + + B_0x1 + Tx message completed + 0x1 + + + + + TXMSGABT + Transmit message abort + + 3 + 1 + read-only + + + B_0x0 + No transmit message abort + 0x0 + + + B_0x1 + Transmit message abort + 0x1 + + + + + HRSTDISC + Hard Reset discarded + + 4 + 1 + read-only + + + B_0x0 + No Hard Reset discarded + 0x0 + + + B_0x1 + Hard Reset discarded + 0x1 + + + + + HRSTSENT + Hard Reset message sent + + 5 + 1 + read-only + + + B_0x0 + No Hard Reset message sent + 0x0 + + + B_0x1 + Hard Reset message sent + 0x1 + + + + + TXUND + Tx data underrun detection + + 6 + 1 + read-only + + + B_0x0 + No Tx data underrun detected + 0x0 + + + B_0x1 + Tx data underrun detected + 0x1 + + + + + RXNE + Receive data register not empty detection + + 8 + 1 + read-only + + + B_0x0 + Rx data register empty + 0x0 + + + B_0x1 + Rx data register not empty + 0x1 + + + + + RXORDDET + Rx ordered set (4 K-codes) detection + + 9 + 1 + read-only + + + B_0x0 + No ordered set detected + 0x0 + + + B_0x1 + A new ordered set detected + 0x1 + + + + + RXHRSTDET + Rx Hard Reset receipt detection + + 10 + 1 + read-only + + + B_0x0 + Hard Reset not received + 0x0 + + + B_0x1 + Hard Reset received + 0x1 + + + + + RXOVR + Rx data overflow detection + + 11 + 1 + read-only + + + B_0x0 + No overflow + 0x0 + + + B_0x1 + Overflow + 0x1 + + + + + RXMSGEND + Rx message received + + 12 + 1 + read-only + + + B_0x0 + No new Rx message received + 0x0 + + + B_0x1 + A new Rx message received + 0x1 + + + + + RXERR + Receive message error + + 13 + 1 + read-only + + + B_0x0 + No error detected + 0x0 + + + B_0x1 + Error(s) detected + 0x1 + + + + + TYPECEVT1 + Type-C voltage level event on CC1 line + + 14 + 1 + read-only + + + B_0x0 + No new event + 0x0 + + + B_0x1 + A new Type-C event + 0x1 + + + + + TYPECEVT2 + Type-C voltage level event on CC2 line + + 15 + 1 + read-only + + + B_0x0 + No new event + 0x0 + + + B_0x1 + A new Type-C event + 0x1 + + + + + TYPEC_VSTATE_CC1 + The status bitfield indicates the voltage level on the CC1 line in its steady state. + 16 + 2 + read-only + + + B_0x0 + Lowest + 0x0 + + + B_0x1 + Low + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Highest + 0x3 + + + + + TYPEC_VSTATE_CC2 + CC2 line voltage level + + 18 + 2 + read-only + + + B_0x0 + Lowest + 0x0 + + + B_0x1 + Low + 0x1 + + + B_0x2 + High + 0x2 + + + B_0x3 + Highest + 0x3 + + + + + FRSEVT + FRS detection event + + 20 + 1 + read-only + + + B_0x0 + No new event + 0x0 + + + B_0x1 + New FRS receive event occurred + 0x1 + + + + + + + UCPD_ICR + UCPD_ICR + UCPD interrupt clear register + 0x018 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + TXMSGDISCCF + Tx message discard flag (TXMSGDISC) clear + + 1 + 1 + write-only + + + TXMSGSENTCF + Tx message send flag (TXMSGSENT) clear + + 2 + 1 + write-only + + + TXMSGABTCF + Tx message abort flag (TXMSGABT) clear + + 3 + 1 + write-only + + + HRSTDISCCF + Hard reset discard flag (HRSTDISC) clear + + 4 + 1 + write-only + + + HRSTSENTCF + Hard reset send flag (HRSTSENT) clear + + 5 + 1 + write-only + + + TXUNDCF + Tx underflow flag (TXUND) clear + + 6 + 1 + write-only + + + RXORDDETCF + Rx ordered set detect flag (RXORDDET) clear + + 9 + 1 + write-only + + + RXHRSTDETCF + Rx Hard Reset detect flag (RXHRSTDET) clear + + 10 + 1 + write-only + + + RXOVRCF + Rx overflow flag (RXOVR) clear + + 11 + 1 + write-only + + + RXMSGENDCF + Rx message received flag (RXMSGEND) clear + + 12 + 1 + write-only + + + TYPECEVT1CF + Type-C CC1 event flag (TYPECEVT1) clear + + 14 + 1 + write-only + + + TYPECEVT2CF + Type-C CC2 line event flag (TYPECEVT2) clear + + 15 + 1 + write-only + + + FRSEVTCF + FRS event flag (FRSEVT) clear + + 20 + 1 + write-only + + + + + UCPD_TX_ORDSETR + UCPD_TX_ORDSETR + UCPD Tx ordered set type register + 0x01C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXORDSET + Ordered set to transmit + + 0 + 20 + read-write + + + + + UCPD_TX_PAYSZR + UCPD_TX_PAYSZR + UCPD Tx payload size register + 0x020 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXPAYSZ + Payload size yet to transmit + + 0 + 10 + read-write + + + B_0x2 + 2 bytes - the size of Control message from the protocol layer + 0x2 + + + B_0x6 + 6 bytes - the shortest Data message allowed from the protocol layer) + 0x6 + + + B_0x1E + 30 bytes - the longest non-extended Data message allowed from the protocol layer + 0x1E + + + B_0x106 + 262 bytes - the longest possible extended message + 0x106 + + + B_0x3FF + 1024 bytes - the longest possible payload (for future expansion) + 0x3FF + + + + + + + UCPD_TXDR + UCPD_TXDR + UCPD Tx data register + 0x024 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TXDATA + Data byte to transmit + 0 + 8 + read-write + + + + + UCPD_RX_ORDSETR + UCPD_RX_ORDSETR + UCPD Rx ordered set register + 0x028 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXORDSET + Rx ordered set code detected + 0 + 3 + read-only + + + B_0x0 + SOP code detected in receiver + 0x0 + + + B_0x1 + SOP' code detected in receiver + 0x1 + + + B_0x2 + SOP'' code detected in receiver + 0x2 + + + B_0x3 + SOP'_Debug detected in receiver + 0x3 + + + B_0x4 + SOP''_Debug detected in receiver + 0x4 + + + B_0x5 + Cable Reset detected in receiver + 0x5 + + + B_0x6 + SOP extension#1 detected in receiver + 0x6 + + + B_0x7 + SOP extension#2 detected in receiver + 0x7 + + + + + RXSOP3OF4 + The bit indicates the number of correct K-codes. + 3 + 1 + read-only + + + B_0x0 + 4 correct K-codes out of 4 + 0x0 + + + B_0x1 + 3 correct K-codes out of 4 + 0x1 + + + + + RXSOPKINVALID + The bitfield is for debug purposes only. + 4 + 3 + read-only + + + B_0x0 + No K-code corrupted + 0x0 + + + B_0x1 + First K-code corrupted + 0x1 + + + B_0x2 + Second K-code corrupted + 0x2 + + + B_0x3 + Third K-code corrupted + 0x3 + + + B_0x4 + Fourth K-code corrupted + 0x4 + + + + + + + UCPD_RX_PAYSZR + UCPD_RX_PAYSZR + UCPD Rx payload size register + 0x02C + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXPAYSZ + Rx payload size received + + 0 + 10 + read-only + + + B_0x2 + 2 bytes - the size of Control message from the protocol layer + 0x2 + + + B_0x6 + 6 bytes - the shortest Data message allowed from the protocol layer) + 0x6 + + + B_0x1E + 30 bytes - the longest non-extended Data message allowed from the protocol layer + 0x1E + + + B_0x106 + 262 bytes - the longest possible extended message + 0x106 + + + B_0x3FF + 1024 bytes - the longest possible payload (for future expansion) + 0x3FF + + + + + + + UCPD_RXDR + UCPD_RXDR + UCPD receive data register + 0x030 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RXDATA + Data byte received + 0 + 8 + read-only + + + + + UCPD_RX_ORDEXTR1 + UCPD_RX_ORDEXTR1 + UCPD Rx ordered set extension register 1 + 0x034 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RXSOPX1 + Ordered set 1 received + + 0 + 20 + read-write + + + + + UCPD_RX_ORDEXTR2 + UCPD_RX_ORDEXTR2 + UCPD Rx ordered set extension register 2 + 0x038 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RXSOPX2 + Ordered set 2 received + + 0 + 20 + read-write + + + + + + + UCPD_S + 0X5000DC00 + + + USART + USART address block description + USART + 0x40013800 + + 0x0 + 0x30 + registers + + + USART1 + USART1 global interrupt + 58 + + + + USART_CR1 + USART_CR1 + USART control register 1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable + + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode + + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable + + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable + + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable + + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE = 1 in the USART_ISR register + 0x1 + + + + + RXFNEIE + RXFIFO not empty interrupt enable + + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXFNFIE + TXFIFO not full interrupt enable + + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXFNF =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable + + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection + + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable + + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method + + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length + + 12 + 1 + read-write + + + MME + Mute mode enable + + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable + + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode + + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time + + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time + + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable + + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of block interrupt enable + + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length + + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable + + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + TXFEIE + TXFIFO empty interrupt enable + + 30 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFE=1 in the USART_ISR register + 0x1 + + + + + RXFFIE + RXFIFO Full interrupt enable + + 31 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when RXFF=1 in the USART_ISR register + 0x1 + + + + + + + USART_CR1_ALTERNATE1 + USART_CR1_ALTERNATE1 + USART control register 1 + USART_CR1 + 0x00 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + UE + USART enable + + 0 + 1 + read-write + + + B_0x0 + USART prescaler and outputs disabled, low-power mode + 0x0 + + + B_0x1 + USART enabled + 0x1 + + + + + UESM + USART enable in low-power mode + + 1 + 1 + read-write + + + B_0x0 + USART not able to wake up the MCU from low-power mode. + 0x0 + + + B_0x1 + USART able to wake up the MCU from low-power mode. + 0x1 + + + + + RE + Receiver enable + + 2 + 1 + read-write + + + B_0x0 + Receiver is disabled + 0x0 + + + B_0x1 + Receiver is enabled and begins searching for a start bit + 0x1 + + + + + TE + Transmitter enable + + 3 + 1 + read-write + + + B_0x0 + Transmitter is disabled + 0x0 + + + B_0x1 + Transmitter is enabled + 0x1 + + + + + IDLEIE + IDLE interrupt enable + + 4 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever IDLE = 1 in the USART_ISR register + 0x1 + + + + + RXNEIE + Receive data register not empty + + 5 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever ORE=1 or RXNE=1 in the USART_ISR register + 0x1 + + + + + TCIE + Transmission complete interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TC=1 in the USART_ISR register + 0x1 + + + + + TXEIE + Transmit data register empty + + 7 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TXE =1 in the USART_ISR register + 0x1 + + + + + PEIE + PE interrupt enable + + 8 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever PE=1 in the USART_ISR register + 0x1 + + + + + PS + Parity selection + + 9 + 1 + read-write + + + B_0x0 + Even parity + 0x0 + + + B_0x1 + Odd parity + 0x1 + + + + + PCE + Parity control enable + + 10 + 1 + read-write + + + B_0x0 + Parity control disabled + 0x0 + + + B_0x1 + Parity control enabled + 0x1 + + + + + WAKE + Receiver wake-up method + + 11 + 1 + read-write + + + B_0x0 + Idle line + 0x0 + + + B_0x1 + Address mark + 0x1 + + + + + M0 + Word length + + 12 + 1 + read-write + + + MME + Mute mode enable + + 13 + 1 + read-write + + + B_0x0 + Receiver in active mode permanently + 0x0 + + + B_0x1 + Receiver can switch between mute mode and active mode. + 0x1 + + + + + CMIE + Character match interrupt enable + + 14 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the CMF bit is set in the USART_ISR register. + 0x1 + + + + + OVER8 + Oversampling mode + + 15 + 1 + read-write + + + B_0x0 + Oversampling by 16 + 0x0 + + + B_0x1 + Oversampling by 8 + 0x1 + + + + + DEDT + Driver Enable deassertion time + + 16 + 5 + read-write + + + DEAT + Driver Enable assertion time + + 21 + 5 + read-write + + + RTOIE + Receiver timeout interrupt enable + + 26 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the RTOF bit is set in the USART_ISR register. + 0x1 + + + + + EOBIE + End of block interrupt enable + + 27 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M1 + Word length + + 28 + 1 + read-write + + + FIFOEN + FIFO mode enable + + 29 + 1 + read-write + + + B_0x0 + FIFO mode is disabled. + 0x0 + + + B_0x1 + FIFO mode is enabled. + 0x1 + + + + + + + USART_CR2 + USART_CR2 + USART control register 2 + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SLVEN + Synchronous slave mode enable + + 0 + 1 + read-write + + + B_0x0 + Slave mode disabled. + 0x0 + + + B_0x1 + Slave mode enabled. + 0x1 + + + + + DIS_NSS + When the DIS_NSS bit is set, the NSS pin input is ignored. + 3 + 1 + read-write + + + B_0x0 + SPI slave selection depends on NSS input pin. + 0x0 + + + B_0x1 + SPI slave is always selected and NSS input pin is ignored. + 0x1 + + + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + + 4 + 1 + read-write + + + B_0x0 + 4-bit address detection + 0x0 + + + B_0x1 + 7-bit address detection (in 8-bit data mode) + 0x1 + + + + + LBDL + LIN break detection length + + 5 + 1 + read-write + + + B_0x0 + 10-bit break detection + 0x0 + + + B_0x1 + 11-bit break detection + 0x1 + + + + + LBDIE + LIN break detection interrupt enable + + 6 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever LBDF=1 in the USART_ISR register + 0x1 + + + + + LBCL + Last bit clock pulse + + 8 + 1 + read-write + + + B_0x0 + The clock pulse of the last data bit is not output to the CK pin + 0x0 + + + B_0x1 + The clock pulse of the last data bit is output to the CK pin + 0x1 + + + + + CPHA + Clock phase + + 9 + 1 + read-write + + + B_0x0 + The first clock transition is the first data capture edge + 0x0 + + + B_0x1 + The second clock transition is the first data capture edge + 0x1 + + + + + CPOL + Clock polarity + + 10 + 1 + read-write + + + B_0x0 + Steady low value on CK pin outside transmission window + 0x0 + + + B_0x1 + Steady high value on CK pin outside transmission window + 0x1 + + + + + CLKEN + Clock enable + + 11 + 1 + read-write + + + B_0x0 + CK pin disabled + 0x0 + + + B_0x1 + CK pin enabled + 0x1 + + + + + STOP + stop bits + + 12 + 2 + read-write + + + B_0x0 + 1 stop bit + 0x0 + + + B_0x1 + 0. + 0x1 + + + B_0x2 + 2 stop bits + 0x2 + + + B_0x3 + 1. + 0x3 + + + + + LINEN + LIN mode enable + + 14 + 1 + read-write + + + B_0x0 + LIN mode disabled + 0x0 + + + B_0x1 + LIN mode enabled + 0x1 + + + + + SWAP + Swap TX/RX pins + + 15 + 1 + read-write + + + B_0x0 + TX/RX pins are used as defined in standard pinout + 0x0 + + + B_0x1 + The TX and RX pins functions are swapped. + 0x1 + + + + + RXINV + RX pin active level inversion + + 16 + 1 + read-write + + + B_0x0 + RX pin signal works using the standard logic levels (Vless thansub>DDless than/sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + RX pin signal values are inverted. + 0x1 + + + + + TXINV + TX pin active level inversion + + 17 + 1 + read-write + + + B_0x0 + TX pin signal works using the standard logic levels (Vless thansub>DDless than/sub> =1/idle, Gnd=0/mark) + 0x0 + + + B_0x1 + TX pin signal values are inverted. + 0x1 + + + + + DATAINV + Binary data inversion + + 18 + 1 + read-write + + + B_0x0 + Logical data from the data register are send/received in positive/direct logic. + 0x0 + + + B_0x1 + Logical data from the data register are send/received in negative/inverse logic. + 0x1 + + + + + MSBFIRST + Most significant bit first + + 19 + 1 + read-write + + + B_0x0 + data is transmitted/received with data bit 0 first, following the start bit. + 0x0 + + + B_0x1 + data is transmitted/received with the MSB (bit 7/8) first, following the start bit. + 0x1 + + + + + ABREN + Auto baud rate enable + + 20 + 1 + read-write + + + B_0x0 + Auto baud rate detection is disabled. + 0x0 + + + B_0x1 + Auto baud rate detection is enabled. + 0x1 + + + + + ABRMOD + Auto baud rate mode + + 21 + 2 + read-write + + + B_0x0 + Measurement of the start bit is used to detect the baud rate. + 0x0 + + + B_0x1 + Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -> Frame = Start10xxxxxx) + 0x1 + + + B_0x2 + 0x7F frame detection. + 0x2 + + + B_0x3 + 0x55 frame detection + 0x3 + + + + + RTOEN + Receiver timeout enable + + 23 + 1 + read-write + + + B_0x0 + Receiver timeout feature disabled. + 0x0 + + + B_0x1 + Receiver timeout feature enabled. + 0x1 + + + + + ADD + Address of the USART node + + 24 + 8 + read-write + + + + + USART_CR3 + USART_CR3 + USART control register 3 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable + + 0 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. + 0x1 + + + + + IREN + IrDA mode enable + + 1 + 1 + read-write + + + B_0x0 + IrDA disabled + 0x0 + + + B_0x1 + IrDA enabled + 0x1 + + + + + IRLP + IrDA low-power + + 2 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Low-power mode + 0x1 + + + + + HDSEL + Half-duplex selection + + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + NACK + Smartcard NACK enable + + 4 + 1 + read-write + + + B_0x0 + NACK transmission in case of parity error is disabled + 0x0 + + + B_0x1 + NACK transmission during parity error is enabled + 0x1 + + + + + SCEN + Smartcard mode enable + + 5 + 1 + read-write + + + B_0x0 + Smartcard mode disabled + 0x0 + + + B_0x1 + Smartcard mode enabled + 0x1 + + + + + DMAR + DMA enable receiver + + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter + + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable + + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. + 0x1 + + + + + CTSE + CTS enable + + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). + 0x1 + + + + + CTSIE + CTS interrupt enable + + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 0x1 + + + + + ONEBIT + One sample bit method enable + + 11 + 1 + read-write + + + B_0x0 + Three sample bit method + 0x0 + + + B_0x1 + One sample bit method + 0x1 + + + + + OVRDIS + Overrun Disable + + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE, is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. + 0x1 + + + + + DDRE + DMA Disable on reception Error + + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. + 0x0 + + + B_0x1 + DMA is disabled following a reception error. + 0x1 + + + + + DEM + Driver enable mode + + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. + 0x1 + + + + + DEP + Driver enable polarity selection + + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + SCARCNT + Smartcard auto-retry count + + 17 + 3 + read-write + + + B_0x0 + retransmission disabled - No automatic retransmission in transmission mode. + 0x0 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection + + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection + + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUFIE + Wake-up from low-power mode interrupt enable + + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the USART_ISR register + 0x1 + + + + + TXFTIE + TXFIFO threshold interrupt enable + + 23 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG. + 0x1 + + + + + TCBGTIE + Transmission Complete before guard time, interrupt enable + + 24 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TCBGT=1 in the USART_ISR register + 0x1 + + + + + RXFTCFG + Receive FIFO threshold configuration + + 25 + 3 + read-write + + + B_0x0 + Receive FIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + Receive FIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + Receive FIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + Receive FIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + Receive FIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + Receive FIFO becomes full + 0x5 + + + + + RXFTIE + RXFIFO threshold interrupt enable + + 28 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG. + 0x1 + + + + + TXFTCFG + TXFIFO threshold configuration + + 29 + 3 + read-write + + + B_0x0 + TXFIFO reaches 1/8 of its depth + 0x0 + + + B_0x1 + TXFIFO reaches 1/4 of its depth + 0x1 + + + B_0x2 + TXFIFO reaches 1/2 of its depth + 0x2 + + + B_0x3 + TXFIFO reaches 3/4 of its depth + 0x3 + + + B_0x4 + TXFIFO reaches 7/8 of its depth + 0x4 + + + B_0x5 + TXFIFO becomes empty + 0x5 + + + + + + + USART_CR3_ALTERNATE1 + USART_CR3_ALTERNATE1 + USART control register 3 + USART_CR3 + 0x08 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EIE + Error interrupt enable + + 0 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. + 0x1 + + + + + IREN + IrDA mode enable + + 1 + 1 + read-write + + + B_0x0 + IrDA disabled + 0x0 + + + B_0x1 + IrDA enabled + 0x1 + + + + + IRLP + IrDA low-power + + 2 + 1 + read-write + + + B_0x0 + Normal mode + 0x0 + + + B_0x1 + Low-power mode + 0x1 + + + + + HDSEL + Half-duplex selection + + 3 + 1 + read-write + + + B_0x0 + Half-duplex mode is not selected + 0x0 + + + B_0x1 + Half-duplex mode is selected + 0x1 + + + + + NACK + Smartcard NACK enable + + 4 + 1 + read-write + + + B_0x0 + NACK transmission in case of parity error is disabled + 0x0 + + + B_0x1 + NACK transmission during parity error is enabled + 0x1 + + + + + SCEN + Smartcard mode enable + + 5 + 1 + read-write + + + B_0x0 + Smartcard mode disabled + 0x0 + + + B_0x1 + Smartcard mode enabled + 0x1 + + + + + DMAR + DMA enable receiver + + 6 + 1 + read-write + + + B_0x1 + DMA mode is enabled for reception + 0x1 + + + B_0x0 + DMA mode is disabled for reception + 0x0 + + + + + DMAT + DMA enable transmitter + + 7 + 1 + read-write + + + B_0x1 + DMA mode is enabled for transmission + 0x1 + + + B_0x0 + DMA mode is disabled for transmission + 0x0 + + + + + RTSE + RTS enable + + 8 + 1 + read-write + + + B_0x0 + RTS hardware flow control disabled + 0x0 + + + B_0x1 + RTS output enabled, data is only requested when there is space in the receive buffer. + 0x1 + + + + + CTSE + CTS enable + + 9 + 1 + read-write + + + B_0x0 + CTS hardware flow control disabled + 0x0 + + + B_0x1 + CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). + 0x1 + + + + + CTSIE + CTS interrupt enable + + 10 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + 0x0 + + + B_0x1 + An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 0x1 + + + + + ONEBIT + One sample bit method enable + + 11 + 1 + read-write + + + B_0x0 + Three sample bit method + 0x0 + + + B_0x1 + One sample bit method + 0x1 + + + + + OVRDIS + Overrun Disable + + 12 + 1 + read-write + + + B_0x0 + Overrun Error Flag, ORE, is set when received data is not read before receiving new data. + 0x0 + + + B_0x1 + Overrun functionality is disabled. + 0x1 + + + + + DDRE + DMA Disable on reception Error + + 13 + 1 + read-write + + + B_0x0 + DMA is not disabled in case of reception error. + 0x0 + + + B_0x1 + DMA is disabled following a reception error. + 0x1 + + + + + DEM + Driver enable mode + + 14 + 1 + read-write + + + B_0x0 + DE function is disabled. + 0x0 + + + B_0x1 + DE function is enabled. + 0x1 + + + + + DEP + Driver enable polarity selection + + 15 + 1 + read-write + + + B_0x0 + DE signal is active high. + 0x0 + + + B_0x1 + DE signal is active low. + 0x1 + + + + + SCARCNT + Smartcard auto-retry count + + 17 + 3 + read-write + + + B_0x0 + retransmission disabled - No automatic retransmission in transmission mode. + 0x0 + + + + + WUS0 + Wake-up from low-power mode interrupt flag selection + + 20 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUS1 + Wake-up from low-power mode interrupt flag selection + + 21 + 1 + read-write + + + B_0x0 + WUF active on address match (as defined by ADD[7:0] and ADDM7) + 0x0 + + + + + WUFIE + Wake-up from low-power mode interrupt enable + + 22 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever WUF=1 in the USART_ISR register + 0x1 + + + + + TCBGTIE + Transmission Complete before guard time, interrupt enable + + 24 + 1 + read-write + + + B_0x0 + Interrupt inhibited + 0x0 + + + B_0x1 + USART interrupt generated whenever TCBGT=1 in the USART_ISR register + 0x1 + + + + + + + USART_BRR + USART_BRR + USART baud rate register + 0x0C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRR + USART baud rate + + 0 + 16 + read-write + + + + + USART_GTPR + USART_GTPR + USART guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PSC + Prescaler value + + 0 + 8 + read-write + + + B_0x1_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE + divides the source clock by 1 + 0x1 + + + B_0x2_IRDA_LOW_POWER_AND_NORMAL_IRDA_MODE + divides the source clock by 2 + 0x2 + + + B_0x3_SMARTCARD_MODE + divides the source clock by 6 + 0x3 + + + + + GT + Guard time value + + 8 + 8 + read-write + + + + + USART_RTOR + USART_RTOR + USART receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RTO + Receiver timeout value + + 0 + 24 + read-write + + + BLEN + Block Length + + 24 + 8 + read-write + + + + + USART_RQR + USART_RQR + USART request register + 0x18 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + ABRRQ + Auto baud rate request + + 0 + 1 + write-only + + + SBKRQ + Send break request + + 1 + 1 + write-only + + + MMRQ + Mute mode request + + 2 + 1 + write-only + + + RXFRQ + Receive data flush request + + 3 + 1 + write-only + + + TXFRQ + Transmit data flush request + + 4 + 1 + write-only + + + + + USART_ISR + USART_ISR + USART interrupt and status register + 0x1C + 0x20 + read-only + 0x000000C0 + 0xF00FFFFF + + + PE + Parity error + + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error + + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag + + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error + + 3 + 1 + read-only + + + B_0x0 + No overrun error + 0x0 + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected + + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXFNE + RXFIFO not empty + + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete + + 6 + 1 + read-only + + + TXFNF + TXFIFO not full + + 7 + 1 + read-only + + + B_0x0 + Transmit FIFO is full + 0x0 + + + B_0x1 + Transmit FIFO is not full + 0x1 + + + + + LBDF + LIN break detection flag + + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag + + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout + + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag + + 12 + 1 + read-only + + + B_0x0 + End of block not reached + 0x0 + + + B_0x1 + End of block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag + + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error + + 14 + 1 + read-only + + + ABRF + Auto baud rate flag + + 15 + 1 + read-only + + + BUSY + Busy flag + + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception ongoing + 0x1 + + + + + CMF + Character match flag + + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag + + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from mute mode + + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag + + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag + + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag + + 22 + 1 + read-only + + + TXFE + TXFIFO Empty + + 23 + 1 + read-only + + + B_0x0 + TXFIFO not empty. + 0x0 + + + B_0x1 + TXFIFO empty. + 0x1 + + + + + RXFF + RXFIFO Full + + 24 + 1 + read-only + + + B_0x0 + RXFIFO not full. + 0x0 + + + B_0x1 + RXFIFO Full. + 0x1 + + + + + TCBGT + Transmission complete before guard time flag + + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i. + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + RXFT + RXFIFO threshold flag + + 26 + 1 + read-only + + + B_0x0 + Receive FIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + Receive FIFO reached the programmed threshold. + 0x1 + + + + + TXFT + TXFIFO threshold flag + + 27 + 1 + read-only + + + B_0x0 + TXFIFO does not reach the programmed threshold. + 0x0 + + + B_0x1 + TXFIFO reached the programmed threshold. + 0x1 + + + + + + + USART_ISR_ALTERNATE1 + USART_ISR_ALTERNATE1 + USART interrupt and status register + USART_ISR + 0x1C + 0x20 + read-only + 0x000000C0 + 0xF00FFFFF + + + PE + Parity error + + 0 + 1 + read-only + + + B_0x0 + No parity error + 0x0 + + + B_0x1 + Parity error + 0x1 + + + + + FE + Framing error + + 1 + 1 + read-only + + + B_0x0 + No Framing error is detected + 0x0 + + + B_0x1 + Framing error or break character is detected + 0x1 + + + + + NE + Noise detection flag + + 2 + 1 + read-only + + + B_0x0 + No noise is detected + 0x0 + + + B_0x1 + Noise is detected + 0x1 + + + + + ORE + Overrun error + + 3 + 1 + read-only + + + B_0x1 + Overrun error is detected + 0x1 + + + + + IDLE + Idle line detected + + 4 + 1 + read-only + + + B_0x0 + No Idle line is detected + 0x0 + + + B_0x1 + Idle line is detected + 0x1 + + + + + RXNE + Read data register not empty + + 5 + 1 + read-only + + + B_0x0 + Data is not received + 0x0 + + + B_0x1 + Received data is ready to be read. + 0x1 + + + + + TC + Transmission complete + + 6 + 1 + read-only + + + TXE + Transmit data register empty + + 7 + 1 + read-only + + + B_0x0 + Data register full + 0x0 + + + B_0x1 + Data register empty + 0x1 + + + + + LBDF + LIN break detection flag + + 8 + 1 + read-only + + + B_0x0 + LIN Break not detected + 0x0 + + + B_0x1 + LIN break detected + 0x1 + + + + + CTSIF + CTS interrupt flag + + 9 + 1 + read-only + + + B_0x0 + No change occurred on the CTS status line + 0x0 + + + B_0x1 + A change occurred on the CTS status line + 0x1 + + + + + CTS + CTS flag + + 10 + 1 + read-only + + + B_0x0 + CTS line set + 0x0 + + + B_0x1 + CTS line reset + 0x1 + + + + + RTOF + Receiver timeout + + 11 + 1 + read-only + + + B_0x0 + Timeout value not reached + 0x0 + + + B_0x1 + Timeout value reached without any data reception + 0x1 + + + + + EOBF + End of block flag + + 12 + 1 + read-only + + + B_0x0 + End of block not reached + 0x0 + + + B_0x1 + End of block (number of characters) reached + 0x1 + + + + + UDR + SPI slave underrun error flag + + 13 + 1 + read-only + + + B_0x0 + No underrun error + 0x0 + + + B_0x1 + underrun error + 0x1 + + + + + ABRE + Auto baud rate error + + 14 + 1 + read-only + + + ABRF + Auto baud rate flag + + 15 + 1 + read-only + + + BUSY + Busy flag + + 16 + 1 + read-only + + + B_0x0 + USART is idle (no reception) + 0x0 + + + B_0x1 + Reception ongoing + 0x1 + + + + + CMF + Character match flag + + 17 + 1 + read-only + + + B_0x0 + No Character match detected + 0x0 + + + B_0x1 + Character match detected + 0x1 + + + + + SBKF + Send break flag + + 18 + 1 + read-only + + + B_0x0 + No break character transmitted + 0x0 + + + B_0x1 + Break character transmitted + 0x1 + + + + + RWU + Receiver wake-up from mute mode + + 19 + 1 + read-only + + + B_0x0 + Receiver in active mode + 0x0 + + + B_0x1 + Receiver in mute mode + 0x1 + + + + + WUF + Wake-up from low-power mode flag + + 20 + 1 + read-only + + + TEACK + Transmit enable acknowledge flag + + 21 + 1 + read-only + + + REACK + Receive enable acknowledge flag + + 22 + 1 + read-only + + + TCBGT + Transmission complete before guard time flag + + 25 + 1 + read-only + + + B_0x0 + Transmission is not complete or transmission is complete unsuccessfully (i. + 0x0 + + + B_0x1 + Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). + 0x1 + + + + + + + USART_ICR + USART_ICR + USART interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + 0xFFFFFFFF + + + PECF + Parity error clear flag + + 0 + 1 + write-only + + + FECF + Framing error clear flag + + 1 + 1 + write-only + + + NECF + Noise detected clear flag + + 2 + 1 + write-only + + + ORECF + Overrun error clear flag + + 3 + 1 + write-only + + + IDLECF + Idle line detected clear flag + + 4 + 1 + write-only + + + TXFECF + TXFIFO empty clear flag + + 5 + 1 + write-only + + + TCCF + Transmission complete clear flag + + 6 + 1 + write-only + + + TCBGTCF + Transmission complete before Guard time clear flag + + 7 + 1 + write-only + + + LBDCF + LIN break detection clear flag + + 8 + 1 + write-only + + + CTSCF + CTS clear flag + + 9 + 1 + write-only + + + RTOCF + Receiver timeout clear flag + + 11 + 1 + write-only + + + EOBCF + End of block clear flag + + 12 + 1 + write-only + + + UDRCF + SPI slave underrun clear flag + + 13 + 1 + write-only + + + CMCF + Character match clear flag + + 17 + 1 + write-only + + + WUCF + Wake-up from low-power mode clear flag + + 20 + 1 + write-only + + + + + USART_RDR + USART_RDR + USART receive data register + 0x24 + 0x20 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDR + Receive data value + + 0 + 9 + read-only + + + + + USART_TDR + USART_TDR + USART transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDR + Transmit data value + + 0 + 9 + read-write + + + + + USART_PRESC + USART_PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRESCALER + Clock prescaler + + 0 + 4 + read-write + + + B_0x0 + input clock not divided + 0x0 + + + B_0x1 + input clock divided by 2 + 0x1 + + + B_0x2 + input clock divided by 4 + 0x2 + + + B_0x3 + input clock divided by 6 + 0x3 + + + B_0x4 + input clock divided by 8 + 0x4 + + + B_0x5 + input clock divided by 10 + 0x5 + + + B_0x6 + input clock divided by 12 + 0x6 + + + B_0x7 + input clock divided by 16 + 0x7 + + + B_0x8 + input clock divided by 32 + 0x8 + + + B_0x9 + input clock divided by 64 + 0x9 + + + B_0xA + input clock divided by 128 + 0xA + + + B_0xB + input clock divided by 256 + 0xB + + + + + + + + + USART_S + 0X50013800 + + + USART2 + 0X40004400 + + USART2 + USART2 global interrupt + 59 + + + + USART2_S + 0X50004400 + + + USART3 + 0X40004800 + + USART3 + USART3 global interrupt + 60 + + + + USART3_S + 0X50004800 + + + UART4 + 0X40004c00 + + UART4 + UART4 global interrupt + 61 + + + + UART4_S + 0X50004c00 + + + UART5 + 0X40005000 + + UART5 + UART5 global interrupt + 62 + + + + UART5_S + 0X50005000 + + + USART6 + 0X40006400 + + USART6 + USART6 global interrupt + 85 + + + + USART6_S + 0X50006400 + + + USB + USB address block description + USB + 0x40016000 + + 0x0 + 0x5C + registers + + + USB_FS + USB OTG FS global interrupt + 74 + + + + USB_CHEP0R + USB_CHEP0R + USB endpoint/channel 0 register + 0x0 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP1R + USB_CHEP1R + USB endpoint/channel 1 register + 0x4 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP2R + USB_CHEP2R + USB endpoint/channel 2 register + 0x8 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP3R + USB_CHEP3R + USB endpoint/channel 3 register + 0xC + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP4R + USB_CHEP4R + USB endpoint/channel 4 register + 0x10 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP5R + USB_CHEP5R + USB endpoint/channel 5 register + 0x14 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP6R + USB_CHEP6R + USB endpoint/channel 6 register + 0x18 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CHEP7R + USB_CHEP7R + USB endpoint/channel 7 register + 0x1C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EA + endpoint/channel address + + 0 + 4 + read-write + + + STATTX + Status bits, for transmission transfers + + 4 + 2 + write-only + + + DTOGTX + Data toggle, for transmission transfers + + 6 + 1 + write-only + + + VTTX + Valid USB transaction transmitted + + 7 + 1 + read-write + + + EPKIND + endpoint/channel kind + + 8 + 1 + read-write + + + UTYPE + USB type of transaction + + 9 + 2 + read-write + + + SETUP + Setup transaction completed + + 11 + 1 + read-only + + + STATRX + Status bits, for reception transfers + + 12 + 2 + write-only + + + DTOGRX + Data Toggle, for reception transfers + + 14 + 1 + write-only + + + VTRX + USB valid transaction received + + 15 + 1 + read-write + + + DEVADDR + Host mode + + 16 + 7 + read-write + + + NAK + Host mode + + 23 + 1 + read-write + + + LS_EP + Low speed endpoint host with HUB only + + 24 + 1 + read-write + + + B_0x0 + Full speed endpoint + 0x0 + + + B_0x1 + Low speed endpoint + 0x1 + + + + + ERR_TX + Received error for an OUT/SETUP transaction + + 25 + 1 + read-write + + + ERR_RX + Received error for an IN transaction + + 26 + 1 + read-write + + + THREE_ERR_TX + Three errors for an OUT or SETUP transaction + + 27 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + THREE_ERR_RX + Three errors for an IN transaction + + 29 + 2 + read-write + + + B_0x0 + Less than 3 errors received. + 0x0 + + + B_0x1 + More than 3 errors received, last error is timeout error. + 0x1 + + + B_0x2 + More than 3 errors received, last error is data error (CRC error). + 0x2 + + + B_0x3 + More than 3 errors received, last error is protocol error (invalid PID, false EOP, bitstuffing error, SYNC error). + 0x3 + + + + + + + USB_CNTR + USB_CNTR + USB control register + 0x40 + 0x20 + read-write + 0x00000003 + 0xFFFFFFFF + + + USBRST + USB Reset + + 0 + 1 + read-write + + + B_0x0_DEVICE_MODE + No effect + 0x0 + + + B_0x1_DEVICE_MODE + USB core is under reset + 0x1 + + + + + PDWN + Power down + + 1 + 1 + read-write + + + B_0x0 + Exit power down + 0x0 + + + B_0x1 + Enter power down mode + 0x1 + + + + + SUSPRDY + Suspend state effective + + 2 + 1 + read-only + + + B_0x0 + Normal operation + 0x0 + + + B_0x1 + Suspend state + 0x1 + + + + + SUSPEN + Suspend state enable + + 3 + 1 + read-write + + + B_0x0_DEVICE_MODE + No effect + 0x0 + + + B_0x1_DEVICE_MODE + Enter L1/L2 suspend + 0x1 + + + + + L2RES + L2 remote wake-up / resume driver + + 4 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Send L2 resume signaling to device + 0x1 + + + + + L1RES + L1 remote wake-up / resume driver + + 5 + 1 + read-write + + + B_0x0 + No effect + 0x0 + + + B_0x1 + Send 50us remote-wake-up signaling to host + 0x1 + + + + + L1REQM + LPM L1 state request interrupt mask + 7 + 1 + read-write + + + B_0x0 + LPM L1 state request (L1REQ) interrupt disabled. + 0x0 + + + B_0x1 + L1REQ interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + ESOFM + Expected start of frame interrupt mask + 8 + 1 + read-write + + + B_0x0 + Expected start of frame (ESOF) interrupt disabled. + 0x0 + + + B_0x1 + ESOF interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + SOFM + Start of frame interrupt mask + 9 + 1 + read-write + + + B_0x0 + SOF interrupt disabled. + 0x0 + + + B_0x1 + SOF interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + RST_DCONM + USB reset request (Device mode) or device connect/disconnect (Host mode) interrupt mask + 10 + 1 + read-write + + + B_0x0 + RESET interrupt disabled. + 0x0 + + + B_0x1 + RESET interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + SUSPM + Suspend mode interrupt mask + 11 + 1 + read-write + + + B_0x0 + Suspend mode request (SUSP) interrupt disabled. + 0x0 + + + B_0x1 + SUSP interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + WKUPM + Wake-up interrupt mask + 12 + 1 + read-write + + + B_0x0 + WKUP interrupt disabled. + 0x0 + + + B_0x1 + WKUP interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + ERRM + Error interrupt mask + 13 + 1 + read-write + + + B_0x0 + ERR interrupt disabled. + 0x0 + + + B_0x1 + ERR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + PMAOVRM + Packet memory area over / underrun interrupt mask + 14 + 1 + read-write + + + B_0x0 + PMAOVR interrupt disabled. + 0x0 + + + B_0x1 + PMAOVR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + CTRM + Correct transfer interrupt mask + 15 + 1 + read-write + + + B_0x0 + Correct transfer (CTR) interrupt disabled. + 0x0 + + + B_0x1 + CTR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. + 0x1 + + + + + THR512M + 512 byte threshold interrupt mask + 16 + 1 + read-write + + + B_0x0 + 512 byte threshold interrupt disabled + 0x0 + + + B_0x1 + 512 byte threshold interrupt enabled + 0x1 + + + + + DDISCM + Device disconnection mask + + 17 + 1 + read-write + + + B_0x0 + Device disconnection interrupt disabled + 0x0 + + + B_0x1 + Device disconnection interrupt enabled + 0x1 + + + + + HOST + HOST mode + + 31 + 1 + read-write + + + B_0x0 + USB Device function + 0x0 + + + B_0x1 + USB host function + 0x1 + + + + + + + USB_ISTR + USB_ISTR + USB interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + IDN + Device Endpoint / host channel identification number + + 0 + 4 + read-only + + + DIR + Direction of transaction + + 4 + 1 + read-only + + + L1REQ + LPM L1 state request + + 7 + 1 + read-write + + + ESOF + Expected start of frame + + 8 + 1 + read-write + + + SOF + Start of frame + + 9 + 1 + read-write + + + RST_DCON + USB reset request (Device mode) or device connect/disconnect (Host mode) + + 10 + 1 + read-write + + + SUSP + Suspend mode request + + 11 + 1 + read-write + + + WKUP + Wake-up + + 12 + 1 + read-write + + + ERR + Error + + 13 + 1 + read-write + + + PMAOVR + Packet memory area over / underrun + + 14 + 1 + read-write + + + CTR + Completed transfer in host mode + + 15 + 1 + read-only + + + THR512 + 512 byte threshold interrupt + + 16 + 1 + read-write + + + DDISC + Device connection + + 17 + 1 + read-write + + + DCON_STAT + Device connection status + + 29 + 1 + read-only + + + B_0x0 + No device connected + 0x0 + + + B_0x1 + FS or LS device connected to the host + 0x1 + + + + + LS_DCON + Low speed device connected + + 30 + 1 + read-only + + + + + USB_FNR + USB_FNR + USB frame number register + 0x48 + 0x20 + read-only + 0x00000000 + 0xFFFFF000 + + + FN + Frame number + + 0 + 11 + read-only + + + LSOF + Lost SOF + + 11 + 2 + read-only + + + LCK + Locked + + 13 + 1 + read-only + + + RXDM + Receive data - line status + + 14 + 1 + read-only + + + RXDP + Receive data + line status + + 15 + 1 + read-only + + + + + USB_DADDR + USB_DADDR + USB Device address + 0x4C + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADD + Device address + + 0 + 7 + read-write + + + EF + Enable function + + 7 + 1 + read-write + + + + + USB_LPMCSR + USB_LPMCSR + LPM control and status register + 0x54 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + LPMEN + LPM support enable + + 0 + 1 + read-write + + + LPMACK + LPM token acknowledge enable + + 1 + 1 + read-write + + + B_0x0 + the valid LPM token is NYET. + 0x0 + + + B_0x1 + the valid LPM token is ACK. + 0x1 + + + + + REMWAKE + bRemoteWake value + + 3 + 1 + read-only + + + BESL + BESL value + + 4 + 4 + read-only + + + + + USB_BCDR + USB_BCDR + Battery charging detector + 0x58 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BCDEN + Battery charging detector (BCD) enable + + 0 + 1 + read-write + + + DCDEN + Data contact detection (DCD) mode enable + + 1 + 1 + read-write + + + PDEN + Primary detection (PD) mode enable + + 2 + 1 + read-write + + + SDEN + Secondary detection (SD) mode enable + + 3 + 1 + read-write + + + DCDET + Data contact detection (DCD) status + + 4 + 1 + read-only + + + B_0x0 + data lines contact not detected. + 0x0 + + + B_0x1 + data lines contact detected. + 0x1 + + + + + PDET + Primary detection (PD) status + + 5 + 1 + read-only + + + B_0x0 + no BCD support detected (connected to SDP or proprietary device). + 0x0 + + + B_0x1 + BCD support detected (connected to ACA, CDP or DCP). + 0x1 + + + + + SDET + Secondary detection (SD) status + + 6 + 1 + read-only + + + B_0x0 + CDP detected. + 0x0 + + + B_0x1 + DCP detected. + 0x1 + + + + + PS2DET + DM pull-up detection status + + 7 + 1 + read-only + + + B_0x0 + Normal port detected (connected to SDP, ACA, CDP or DCP). + 0x0 + + + B_0x1 + PS2 port or proprietary charger detected. + 0x1 + + + + + DPPU_DPD + DP pull-up / DPDM pull-down + + 15 + 1 + read-write + + + + + + + USB_S + 0X50016000 + + + USBSRAM + USBSRAM address block description + USBSRAM + 0x40016400 + + 0x0 + 0x40 + registers + + + + USBSRAM_CHEP_TXRXBD_0 + USBSRAM_CHEP_TXRXBD_0 + Channel/endpoint transmit buffer descriptor 0 + 0x0 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_0_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_0_ALTERNATE1 + Channel/endpoint receive buffer descriptor 0 + USBSRAM_CHEP_TXRXBD_0 + 0x0 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_0 + USBSRAM_CHEP_RXTXBD_0 + Channel/endpoint receive buffer descriptor 0 + 0x4 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_0_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_0_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 0 + USBSRAM_CHEP_RXTXBD_0 + 0x4 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_1 + USBSRAM_CHEP_TXRXBD_1 + Channel/endpoint transmit buffer descriptor 1 + 0x8 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_1_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_1_ALTERNATE1 + Channel/endpoint receive buffer descriptor 1 + USBSRAM_CHEP_TXRXBD_1 + 0x8 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_1 + USBSRAM_CHEP_RXTXBD_1 + Channel/endpoint receive buffer descriptor 1 + 0xC + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_1_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_1_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 1 + USBSRAM_CHEP_RXTXBD_1 + 0xC + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_2 + USBSRAM_CHEP_TXRXBD_2 + Channel/endpoint transmit buffer descriptor 2 + 0x10 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_2_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_2_ALTERNATE1 + Channel/endpoint receive buffer descriptor 2 + USBSRAM_CHEP_TXRXBD_2 + 0x10 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_2 + USBSRAM_CHEP_RXTXBD_2 + Channel/endpoint receive buffer descriptor 2 + 0x14 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_2_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_2_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 2 + USBSRAM_CHEP_RXTXBD_2 + 0x14 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_3 + USBSRAM_CHEP_TXRXBD_3 + Channel/endpoint transmit buffer descriptor 3 + 0x18 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_3_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_3_ALTERNATE1 + Channel/endpoint receive buffer descriptor 3 + USBSRAM_CHEP_TXRXBD_3 + 0x18 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_3 + USBSRAM_CHEP_RXTXBD_3 + Channel/endpoint receive buffer descriptor 3 + 0x1C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_3_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_3_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 3 + USBSRAM_CHEP_RXTXBD_3 + 0x1C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_4 + USBSRAM_CHEP_TXRXBD_4 + Channel/endpoint transmit buffer descriptor 4 + 0x20 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_4_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_4_ALTERNATE1 + Channel/endpoint receive buffer descriptor 4 + USBSRAM_CHEP_TXRXBD_4 + 0x20 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_4 + USBSRAM_CHEP_RXTXBD_4 + Channel/endpoint receive buffer descriptor 4 + 0x24 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_4_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_4_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 4 + USBSRAM_CHEP_RXTXBD_4 + 0x24 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_5 + USBSRAM_CHEP_TXRXBD_5 + Channel/endpoint transmit buffer descriptor 5 + 0x28 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_5_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_5_ALTERNATE1 + Channel/endpoint receive buffer descriptor 5 + USBSRAM_CHEP_TXRXBD_5 + 0x28 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_5 + USBSRAM_CHEP_RXTXBD_5 + Channel/endpoint receive buffer descriptor 5 + 0x2C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_5_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_5_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 5 + USBSRAM_CHEP_RXTXBD_5 + 0x2C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_6 + USBSRAM_CHEP_TXRXBD_6 + Channel/endpoint transmit buffer descriptor 6 + 0x30 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_6_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_6_ALTERNATE1 + Channel/endpoint receive buffer descriptor 6 + USBSRAM_CHEP_TXRXBD_6 + 0x30 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_6 + USBSRAM_CHEP_RXTXBD_6 + Channel/endpoint receive buffer descriptor 6 + 0x34 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_6_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_6_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 6 + USBSRAM_CHEP_RXTXBD_6 + 0x34 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_7 + USBSRAM_CHEP_TXRXBD_7 + Channel/endpoint transmit buffer descriptor 7 + 0x38 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + USBSRAM_CHEP_TXRXBD_7_ALTERNATE1 + USBSRAM_CHEP_TXRXBD_7_ALTERNATE1 + Channel/endpoint receive buffer descriptor 7 + USBSRAM_CHEP_TXRXBD_7 + 0x38 + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_7 + USBSRAM_CHEP_RXTXBD_7 + Channel/endpoint receive buffer descriptor 7 + 0x3C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_RX + Reception buffer address + + 0 + 16 + read-write + + + COUNT_RX + Reception byte count + + 16 + 10 + read-only + + + NUM_BLOCK + Number of blocks + + 26 + 5 + read-write + + + BLSIZE + Block size + + 31 + 1 + read-write + + + + + USBSRAM_CHEP_RXTXBD_7_ALTERNATE1 + USBSRAM_CHEP_RXTXBD_7_ALTERNATE1 + Channel/endpoint transmit buffer descriptor 7 + USBSRAM_CHEP_RXTXBD_7 + 0x3C + 0x20 + read-write + 0x00000000 + 0x00000000 + + + ADDR_TX + Transmission buffer address + + 0 + 16 + read-write + + + COUNT_TX + Transmission byte count + + 16 + 10 + read-write + + + + + + + USBSRAM_S + 0x50016400 + + + VREFBUF + VREFBUF address block description + VREFBUF + 0x44007400 + + 0x0 + 0x8 + registers + + + + VREFBUF_CSR + VREFBUF_CSR + VREFBUF control and status register + 0x00 + 0x20 + read-write + 0x00000002 + 0xFFFFFFFF + + + ENVR + Voltage reference buffer mode enable + + 0 + 1 + read-write + + + B_0x0 + Internal voltage reference mode disable (external voltage reference mode). + 0x0 + + + B_0x1 + Internal voltage reference mode (reference buffer enable or hold mode) enable. + 0x1 + + + + + HIZ + High impedance mode + + 1 + 1 + read-write + + + B_0x0 + Vless thansub>REF+less than/sub> pin is internally connected to the voltage reference buffer output. + 0x0 + + + B_0x1 + Vless thansub>REF+less than/sub> pin is high impedance. + 0x1 + + + + + VRR + Voltage reference buffer ready + 3 + 1 + read-only + + + B_0x0 + the voltage reference buffer output is not ready. + 0x0 + + + B_0x1 + the voltage reference buffer output reached the requested level. + 0x1 + + + + + VRS + Voltage reference scale + + 4 + 3 + read-write + + + + + VREFBUF_CCR + VREFBUF_CCR + VREFBUF calibration control register + 0x04 + 0x20 + read-write + 0x00000000 + 0xFFFFFF00 + + + TRIM + Trimming code + + 0 + 6 + read-write + + + + + + + VREFBUF_S + 0X54007400 + + + WWDG + WWDG address block description + WWDG + 0x40002c00 + + 0x0 + 0xC + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + WWDG_CR + WWDG_CR + WWDG control register + 0x000 + 0x20 + read-write + 0x0000007F + 0xFFFFFFFF + + + T + 7-bit counter (MSB to LSB) + + 0 + 7 + read-write + + + WDGA + Activation bit + + 7 + 1 + read-write + + + B_0x0 + Watchdog disabled + 0x0 + + + B_0x1 + Watchdog enabled + 0x1 + + + + + + + WWDG_CFR + WWDG_CFR + WWDG configuration register + 0x004 + 0x20 + read-write + 0x0000007F + 0xFFFFFFFF + + + W + 7-bit window value + + 0 + 7 + read-write + + + EWI + Early wake-up interrupt enable + + 9 + 1 + read-write + + + WDGTB + Timer base + + 11 + 3 + read-write + + + B_0x0 + CK counter clock (PCLK div 4096) div 1 + 0x0 + + + B_0x1 + CK counter clock (PCLK div 4096) div 2 + 0x1 + + + B_0x2 + CK counter clock (PCLK div 4096) div 4 + 0x2 + + + B_0x3 + CK counter clock (PCLK div 4096) div 8 + 0x3 + + + B_0x4 + CK counter clock (PCLK div 4096) div 16 + 0x4 + + + B_0x5 + CK counter clock (PCLK div 4096) div 32 + 0x5 + + + B_0x6 + CK counter clock (PCLK div 4096) div 64 + 0x6 + + + B_0x7 + CK counter clock (PCLK div 4096) div 128 + 0x7 + + + + + + + WWDG_SR + WWDG_SR + WWDG status register + 0x008 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + EWIF + Early wake-up interrupt flag + + 0 + 1 + read-write + + + + + + + WWDG_S + 0X50002C00 + + + diff --git a/embedded-software/firmware/gimbal_test_stand/startup_stm32h533xx.s b/embedded-software/firmware/gimbal_test_stand/startup_stm32h533xx.s new file mode 100644 index 00000000..641170b6 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/startup_stm32h533xx.s @@ -0,0 +1,647 @@ +/** + ****************************************************************************** + * @file startup_stm32h533xx.s + * @author MCD Application Team + * @brief STM32h533xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M33 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None + */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + ldr r0, =_sstack + msr MSPLIM, r0 /* set stack pointer limit */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32h533xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_AVD_IRQHandler + .word RTC_IRQHandler + .word RTC_S_IRQHandler + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word FLASH_S_IRQHandler + .word GTZC_IRQHandler + .word RCC_IRQHandler + .word RCC_S_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word IWDG_IRQHandler + .word SAES_IRQHandler + .word ADC1_IRQHandler + .word DAC1_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word TIM5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word SPI3_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC2_IRQHandler + .word LPTIM2_IRQHandler + .word TIM15_IRQHandler + .word 0 + .word 0 + .word USB_DRD_FS_IRQHandler + .word CRS_IRQHandler + .word UCPD1_IRQHandler + .word FMC_IRQHandler + .word OCTOSPI1_IRQHandler + .word SDMMC1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SPI4_IRQHandler + .word 0 + .word 0 + .word USART6_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word GPDMA2_Channel0_IRQHandler + .word GPDMA2_Channel1_IRQHandler + .word GPDMA2_Channel2_IRQHandler + .word GPDMA2_Channel3_IRQHandler + .word GPDMA2_Channel4_IRQHandler + .word GPDMA2_Channel5_IRQHandler + .word GPDMA2_Channel6_IRQHandler + .word GPDMA2_Channel7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word FPU_IRQHandler + .word ICACHE_IRQHandler + .word DCACHE1_IRQHandler + .word 0 + .word 0 + .word DCMI_PSSI_IRQHandler + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word 0 + .word 0 + .word DTS_IRQHandler + .word RNG_IRQHandler + .word OTFDEC1_IRQHandler + .word AES_IRQHandler + .word HASH_IRQHandler + .word PKA_IRQHandler + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word 0 + .word 0 + .word I3C1_EV_IRQHandler + .word I3C1_ER_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word I3C2_EV_IRQHandler + .word I3C2_ER_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak FLASH_S_IRQHandler + .thumb_set FLASH_S_IRQHandler,Default_Handler + + .weak GTZC_IRQHandler + .thumb_set GTZC_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak DAC1_IRQHandler + .thumb_set DAC1_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak USB_DRD_FS_IRQHandler + .thumb_set USB_DRD_FS_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak GPDMA2_Channel0_IRQHandler + .thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler + + .weak GPDMA2_Channel1_IRQHandler + .thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler + + .weak GPDMA2_Channel2_IRQHandler + .thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler + + .weak GPDMA2_Channel3_IRQHandler + .thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler + + .weak GPDMA2_Channel4_IRQHandler + .thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler + + .weak GPDMA2_Channel5_IRQHandler + .thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler + + .weak GPDMA2_Channel6_IRQHandler + .thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler + + .weak GPDMA2_Channel7_IRQHandler + .thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak DCACHE1_IRQHandler + .thumb_set DCACHE1_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak OTFDEC1_IRQHandler + .thumb_set OTFDEC1_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak I3C2_EV_IRQHandler + .thumb_set I3C2_EV_IRQHandler,Default_Handler + + .weak I3C2_ER_IRQHandler + .thumb_set I3C2_ER_IRQHandler,Default_Handler diff --git a/embedded-software/firmware/ulysses-flight-controller/Core/Src/main.c b/embedded-software/firmware/ulysses-flight-controller/Core/Src/main.c index 188dae48..f2d0a558 100644 --- a/embedded-software/firmware/ulysses-flight-controller/Core/Src/main.c +++ b/embedded-software/firmware/ulysses-flight-controller/Core/Src/main.c @@ -242,7 +242,8 @@ int main(void) MX_FREERTOS_Init(); /* Start scheduler */ - osKernelStart(); + +/home/j1m1 osKernelStart(); /* We should never get here as control is now taken by the scheduler */ From 18064a8da9d9083d7eff63aa05ba79345bce74cd Mon Sep 17 00:00:00 2001 From: Jimmy Pan Date: Sun, 5 Apr 2026 15:58:05 -0700 Subject: [PATCH 2/2] fixed syntax error in FC main.c --- embedded-software/firmware/README.md | 4 + .../firmware/gimbal_test_stand/.mxproject | 16 +- .../Core/Inc/i2c_drivers/as5600.h | 172 + .../Core/Inc/stm32h5xx_hal_conf.h | 2 +- .../Core/Src/i2c_drivers/as5600_encoder.c | 326 + .../Src/i2c_drivers/as5600_encoder_device.c | 61 + .../gimbal_test_stand/Core/Src/main.c | 68 +- .../Core/Src/stm32h5xx_hal_msp.c | 78 + .../Inc/stm32h5xx_hal_i2c.h | 842 ++ .../Inc/stm32h5xx_hal_i2c_ex.h | 156 + .../Inc/stm32h5xx_ll_i2c.h | 2380 +++++ .../Src/stm32h5xx_hal_i2c.c | 7824 +++++++++++++++++ .../Src/stm32h5xx_hal_i2c_ex.c | 359 + .../cmake/stm32cubemx/CMakeLists.txt | 8 +- .../gimbal_test_stand/gimbal_test_stand.ioc | 23 +- .../ulysses-flight-controller/Core/Src/main.c | 2 +- .../ground-station/CMakeLists.txt | 51 +- 17 files changed, 12340 insertions(+), 32 deletions(-) create mode 100644 embedded-software/firmware/gimbal_test_stand/Core/Inc/i2c_drivers/as5600.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Core/Src/i2c_drivers/as5600_encoder.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Core/Src/i2c_drivers/as5600_encoder_device.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c_ex.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c create mode 100644 embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c diff --git a/embedded-software/firmware/README.md b/embedded-software/firmware/README.md index 1af3083c..b9e4d47c 100644 --- a/embedded-software/firmware/README.md +++ b/embedded-software/firmware/README.md @@ -27,6 +27,10 @@ cmake --preset debug && cmake --build --preset debug # GNSS radio cd ulysses-gnss-radio cmake --preset Debug && cmake --build --preset Debug + +# Gimbal test stand +cd gimbal_test_stand +cmake --preset debug && cmake --build --preset debug ``` ## Testing diff --git a/embedded-software/firmware/gimbal_test_stand/.mxproject b/embedded-software/firmware/gimbal_test_stand/.mxproject index f15a7cda..94894f48 100644 --- a/embedded-software/firmware/gimbal_test_stand/.mxproject +++ b/embedded-software/firmware/gimbal_test_stand/.mxproject @@ -1,3 +1,11 @@ +[PreviousLibFiles] +LibFiles=Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dmamux.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo_errno.h;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dmamux.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo_errno.h;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/pac_armv81.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/cachel1_armv7.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm85.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_starmc1.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/pmu_armv8.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm55.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm3.h; + +[PreviousUsedCMakes] +SourceFiles=Core/Src/main.c;Core/Src/stm32h5xx_it.c;Core/Src/stm32h5xx_hal_msp.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Core/Src/system_stm32h5xx.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Core/Src/system_stm32h5xx.c;;; +HeaderPath=Drivers/STM32H5xx_HAL_Driver/Inc;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy;Drivers/BSP/STM32H5xx_Nucleo;Drivers/CMSIS/Device/ST/STM32H5xx/Include;Drivers/CMSIS/Include;Core/Inc; +CDefines=USE_NUCLEO_64;USE_HAL_DRIVER;STM32H533xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + [PreviousGenFiles] AdvancedFolderStructure=true HeaderFileListSize=4 @@ -16,11 +24,3 @@ SourceFolderListSize=1 SourcePath#0=../Core/Src SourceFiles=; -[PreviousLibFiles] -LibFiles=Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dmamux.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo_errno.h;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dmamux.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo_errno.h;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_usart_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/pac_armv81.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/cachel1_armv7.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm85.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_starmc1.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/pmu_armv8.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm55.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm3.h; - -[PreviousUsedCMakes] -SourceFiles=Core/Src/main.c;Core/Src/stm32h5xx_it.c;Core/Src/stm32h5xx_hal_msp.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Core/Src/system_stm32h5xx.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/BSP/STM32H5xx_Nucleo/stm32h5xx_nucleo.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Core/Src/system_stm32h5xx.c;;; -HeaderPath=Drivers/STM32H5xx_HAL_Driver/Inc;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy;Drivers/BSP/STM32H5xx_Nucleo;Drivers/CMSIS/Device/ST/STM32H5xx/Include;Drivers/CMSIS/Include;Core/Inc; -CDefines=USE_NUCLEO_64;USE_HAL_DRIVER;STM32H533xx;USE_HAL_DRIVER;USE_HAL_DRIVER; - diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Inc/i2c_drivers/as5600.h b/embedded-software/firmware/gimbal_test_stand/Core/Inc/i2c_drivers/as5600.h new file mode 100644 index 00000000..09e77eb9 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Core/Inc/i2c_drivers/as5600.h @@ -0,0 +1,172 @@ +#pragma once + +#include +#include + +/* + * AS5600 magnetic encoder driver + * + * Notes: + * - I2C 7-bit address is fixed at 0x36. + * - ANGLE and RAW ANGLE are 12-bit values in the range [0, 4095]. + * - DIR is a hardware pin, not an I2C register setting. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define AS5600_I2C_ADDR_7BIT (0x36u) +#define AS5600_I2C_ADDR_8BIT (AS5600_I2C_ADDR_7BIT << 1) + +#define AS5600_FULL_SCALE_COUNTS (4096u) +#define AS5600_MAX_COUNT (4095u) +#define AS5600_DEGREES_PER_COUNT (360.0f / 4096.0f) + +/* Register map */ +#define AS5600_REG_ZMCO (0x00u) +#define AS5600_REG_ZPOS_H (0x01u) +#define AS5600_REG_ZPOS_L (0x02u) +#define AS5600_REG_MPOS_H (0x03u) +#define AS5600_REG_MPOS_L (0x04u) +#define AS5600_REG_MANG_H (0x05u) +#define AS5600_REG_MANG_L (0x06u) +#define AS5600_REG_CONF_H (0x07u) +#define AS5600_REG_CONF_L (0x08u) +#define AS5600_REG_STATUS (0x0Bu) +#define AS5600_REG_RAW_ANGLE_H (0x0Cu) +#define AS5600_REG_RAW_ANGLE_L (0x0Du) +#define AS5600_REG_ANGLE_H (0x0Eu) +#define AS5600_REG_ANGLE_L (0x0Fu) +#define AS5600_REG_AGC (0x1Au) +#define AS5600_REG_MAGNITUDE_H (0x1Bu) +#define AS5600_REG_MAGNITUDE_L (0x1Cu) +#define AS5600_REG_BURN (0xFFu) + +#define AS5600_BURN_ANGLE_CMD (0x80u) +#define AS5600_BURN_SETTING_CMD (0x40u) + +/* STATUS bits */ +#define AS5600_STATUS_MH (1u << 3) /* magnet too strong */ +#define AS5600_STATUS_ML (1u << 4) /* magnet too weak */ +#define AS5600_STATUS_MD (1u << 5) /* magnet detected */ + +/* CONF fields */ +typedef enum { + AS5600_PM_NOM = 0u, + AS5600_PM_LPM1 = 1u, + AS5600_PM_LPM2 = 2u, + AS5600_PM_LPM3 = 3u, +} as5600_power_mode_t; + +typedef enum { + AS5600_HYST_OFF = 0u, + AS5600_HYST_1LSB = 1u, + AS5600_HYST_2LSB = 2u, + AS5600_HYST_3LSB = 3u, +} as5600_hysteresis_t; + +typedef enum { + AS5600_OUT_ANALOG_FULL = 0u, + AS5600_OUT_ANALOG_REDUCED = 1u, + AS5600_OUT_PWM = 2u, +} as5600_output_stage_t; + +typedef enum { + AS5600_PWM_115HZ = 0u, + AS5600_PWM_230HZ = 1u, + AS5600_PWM_460HZ = 2u, + AS5600_PWM_920HZ = 3u, +} as5600_pwm_freq_t; + +typedef enum { + AS5600_SF_16X = 0u, + AS5600_SF_8X = 1u, + AS5600_SF_4X = 2u, + AS5600_SF_2X = 3u, +} as5600_slow_filter_t; + +typedef enum { + AS5600_FTH_SLOW_ONLY = 0u, + AS5600_FTH_6_LSB = 1u, + AS5600_FTH_7_LSB = 2u, + AS5600_FTH_9_LSB = 3u, + AS5600_FTH_18_LSB = 4u, + AS5600_FTH_21_LSB = 5u, + AS5600_FTH_24_LSB = 6u, + AS5600_FTH_10_LSB = 7u, +} as5600_fast_filter_threshold_t; + +typedef struct { + as5600_power_mode_t power_mode; + as5600_hysteresis_t hysteresis; + as5600_output_stage_t output_stage; + as5600_pwm_freq_t pwm_freq; + as5600_slow_filter_t slow_filter; + as5600_fast_filter_threshold_t fast_filter_threshold; + bool watchdog_enable; +} as5600_conf_t; + +typedef struct { + bool magnet_detected; + bool magnet_too_weak; + bool magnet_too_strong; + uint8_t raw_status; +} as5600_status_t; + +typedef struct { + void *hi2c; + uint16_t i2c_addr_8bit; + uint32_t timeout_ms; + + /* Optional software zero offset for application-level calibration. + * This does not burn OTP and does not change sensor registers. */ + uint16_t zero_offset_counts; +} as5600_t; + +void as5600_init(as5600_t *dev, void *hi2c, uint32_t timeout_ms); +void as5600_set_zero_offset_counts(as5600_t *dev, uint16_t zero_offset_counts); +void as5600_zero_here_from_raw_angle(as5600_t *dev); + +bool as5600_ping(const as5600_t *dev); + +bool as5600_read_u8(const as5600_t *dev, uint8_t reg, uint8_t *value); +bool as5600_write_u8(const as5600_t *dev, uint8_t reg, uint8_t value); +bool as5600_read_u16(const as5600_t *dev, uint8_t reg_msb, uint16_t *value_12bit); +bool as5600_write_u16(const as5600_t *dev, uint8_t reg_msb, uint16_t value_12bit); + +bool as5600_read_status(const as5600_t *dev, as5600_status_t *status); +bool as5600_is_magnet_detected(const as5600_t *dev, bool *detected); +bool as5600_read_agc(const as5600_t *dev, uint8_t *agc); +bool as5600_read_magnitude(const as5600_t *dev, uint16_t *magnitude); + +bool as5600_read_raw_angle_counts(const as5600_t *dev, uint16_t *counts); +bool as5600_read_angle_counts(const as5600_t *dev, uint16_t *counts); +bool as5600_read_raw_angle_degrees(const as5600_t *dev, float *degrees); +bool as5600_read_angle_degrees(const as5600_t *dev, float *degrees); + +bool as5600_read_raw_angle_counts_zeroed(const as5600_t *dev, uint16_t *counts); +bool as5600_read_raw_angle_degrees_zeroed(const as5600_t *dev, float *degrees); + +bool as5600_read_conf(const as5600_t *dev, as5600_conf_t *conf); +bool as5600_write_conf(const as5600_t *dev, const as5600_conf_t *conf); + +bool as5600_write_zpos(const as5600_t *dev, uint16_t zpos); +bool as5600_write_mpos(const as5600_t *dev, uint16_t mpos); +bool as5600_write_mang(const as5600_t *dev, uint16_t mang); + +bool as5600_program_range_volatile(const as5600_t *dev, uint16_t zpos, uint16_t mpos); +bool as5600_burn_angle(const as5600_t *dev); +bool as5600_burn_settings(const as5600_t *dev); + +uint16_t as5600_counts_to_degrees_x100(uint16_t counts); +float as5600_counts_to_degrees_f(uint16_t counts); +uint16_t as5600_degrees_to_counts_f(float degrees); +uint16_t as5600_wrap_counts(uint16_t counts); +float as5600_wrap_degrees_360(float degrees); +int16_t as5600_shortest_delta_counts(uint16_t from_counts, uint16_t to_counts); +float as5600_shortest_delta_degrees(float from_deg, float to_deg); + +#ifdef __cplusplus +} +#endif diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_hal_conf.h b/embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_hal_conf.h index e147edda..16d330c2 100644 --- a/embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_hal_conf.h +++ b/embedded-software/firmware/gimbal_test_stand/Core/Inc/stm32h5xx_hal_conf.h @@ -53,7 +53,7 @@ /*#define HAL_GTZC_MODULE_ENABLED */ /*#define HAL_HASH_MODULE_ENABLED */ /*#define HAL_IWDG_MODULE_ENABLED */ -/*#define HAL_I2C_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED /*#define HAL_I3C_MODULE_ENABLED */ /*#define HAL_I2S_MODULE_ENABLED */ /*#define HAL_LPTIM_MODULE_ENABLED */ diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Src/i2c_drivers/as5600_encoder.c b/embedded-software/firmware/gimbal_test_stand/Core/Src/i2c_drivers/as5600_encoder.c new file mode 100644 index 00000000..5a81029e --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Core/Src/i2c_drivers/as5600_encoder.c @@ -0,0 +1,326 @@ +#include "as5600.h" + +#include + +/* Device-layer hooks implemented in as5600_device_stm32_hal.c */ +bool as5600_device_is_ready(void *hi2c, uint16_t addr_8bit, uint32_t timeout_ms); +bool as5600_device_mem_read(void *hi2c, uint16_t addr_8bit, uint8_t reg, uint8_t *data, uint16_t len, uint32_t timeout_ms); +bool as5600_device_mem_write(void *hi2c, uint16_t addr_8bit, uint8_t reg, const uint8_t *data, uint16_t len, uint32_t timeout_ms); + +// Clamp a 16-bit value to the valid 12-bit range (0 to 4095). This does not perform any I2C communication. +static uint16_t clamp12(uint16_t x) { + return (uint16_t)(x & 0x0FFFu); +} + +// Combine two bytes read from the AS5600 registers into a single 12-bit value. The first byte is the MSB and the second byte is the LSB. This does not perform any I2C communication. +static uint16_t combine_u12(uint8_t msb, uint8_t lsb) { + return (uint16_t)((((uint16_t)msb << 8) | (uint16_t)lsb) & 0x0FFFu); +} + +// Split a 12-bit value into two bytes for writing to the AS5600 registers. The MSB will be in the first byte and the LSB in the second byte. This does not perform any I2C communication. +static void split_u12(uint16_t value, uint8_t *msb, uint8_t *lsb) { + value = clamp12(value); + *msb = (uint8_t)((value >> 8) & 0x0Fu); + *lsb = (uint8_t)(value & 0xFFu); +} + +// Pack the as5600_conf_t structure fields into a 16-bit value suitable for writing to the CONF register. This does not perform any I2C communication. +static uint16_t conf_pack(const as5600_conf_t *conf) { + uint16_t reg = 0u; + if (conf == NULL) { + return 0u; + } + + reg |= ((uint16_t)(conf->power_mode & 0x03u) << 0); + reg |= ((uint16_t)(conf->hysteresis & 0x03u) << 2); + reg |= ((uint16_t)(conf->output_stage & 0x03u) << 4); + reg |= ((uint16_t)(conf->pwm_freq & 0x03u) << 6); + reg |= ((uint16_t)(conf->slow_filter & 0x03u) << 8); + reg |= ((uint16_t)(conf->fast_filter_threshold & 0x07u) << 10); + reg |= ((uint16_t)(conf->watchdog_enable ? 1u : 0u) << 13); + + return reg; +} + +// Unpack the 16-bit CONF register value into the as5600_conf_t structure fields. This does not perform any I2C communication. +static void conf_unpack(uint16_t reg, as5600_conf_t *conf) { + if (conf == NULL) { + return; + } + + conf->power_mode = (as5600_power_mode_t)((reg >> 0) & 0x03u); + conf->hysteresis = (as5600_hysteresis_t)((reg >> 2) & 0x03u); + conf->output_stage = (as5600_output_stage_t)((reg >> 4) & 0x03u); + conf->pwm_freq = (as5600_pwm_freq_t)((reg >> 6) & 0x03u); + conf->slow_filter = (as5600_slow_filter_t)((reg >> 8) & 0x03u); + conf->fast_filter_threshold = (as5600_fast_filter_threshold_t)((reg >> 10) & 0x07u); + conf->watchdog_enable = (((reg >> 13) & 0x01u) != 0u); +} + +// Initialize the AS5600 device structure with the given I2C handle and timeout. This does not perform any I2C communication or sensor configuration. +void as5600_init(as5600_t *dev, void *hi2c, uint32_t timeout_ms) { + if (dev == NULL) { + return; + } + + dev->hi2c = hi2c; + dev->i2c_addr_8bit = AS5600_I2C_ADDR_8BIT; + dev->timeout_ms = timeout_ms; + dev->zero_offset_counts = 0u; +} + +// Set a software zero offset in counts for application-level calibration. This does not burn OTP or change sensor registers. +void as5600_set_zero_offset_counts(as5600_t *dev, uint16_t zero_offset_counts) { + if (dev == NULL) { + return; + } + dev->zero_offset_counts = as5600_wrap_counts(zero_offset_counts); +} + +// Set the current raw angle as the zero reference point for future zeroed readings. This does not burn OTP or change sensor registers. +void as5600_zero_here_from_raw_angle(as5600_t *dev) { + uint16_t raw = 0u; + if (dev == NULL) { + return; + } + if (as5600_read_raw_angle_counts(dev, &raw)) { + dev->zero_offset_counts = raw; + } +} + + +// Check if the device is present and responding to I2C commands. +bool as5600_ping(const as5600_t *dev) { + if (dev == NULL || dev->hi2c == NULL) { + return false; + } + return as5600_device_is_ready(dev->hi2c, dev->i2c_addr_8bit, dev->timeout_ms); +} + +bool as5600_read_u8(const as5600_t *dev, uint8_t reg, uint8_t *value) { + if (dev == NULL || dev->hi2c == NULL || value == NULL) { + return false; + } + return as5600_device_mem_read(dev->hi2c, dev->i2c_addr_8bit, reg, value, 1u, dev->timeout_ms); +} + +bool as5600_write_u8(const as5600_t *dev, uint8_t reg, uint8_t value) { + if (dev == NULL || dev->hi2c == NULL) { + return false; + } + return as5600_device_mem_write(dev->hi2c, dev->i2c_addr_8bit, reg, &value, 1u, dev->timeout_ms); +} + +bool as5600_read_u16(const as5600_t *dev, uint8_t reg_msb, uint16_t *value_12bit) { + uint8_t buf[2]; + + if (dev == NULL || dev->hi2c == NULL || value_12bit == NULL) { + return false; + } + + if (!as5600_device_mem_read(dev->hi2c, dev->i2c_addr_8bit, reg_msb, buf, 2u, dev->timeout_ms)) { + return false; + } + + *value_12bit = combine_u12(buf[0], buf[1]); + return true; +} + +bool as5600_write_u16(const as5600_t *dev, uint8_t reg_msb, uint16_t value_12bit) { + uint8_t buf[2]; + + if (dev == NULL || dev->hi2c == NULL) { + return false; + } + + split_u12(value_12bit, &buf[0], &buf[1]); + return as5600_device_mem_write(dev->hi2c, dev->i2c_addr_8bit, reg_msb, buf, 2u, dev->timeout_ms); +} + +bool as5600_read_status(const as5600_t *dev, as5600_status_t *status) { + uint8_t raw = 0u; + + if (status == NULL) { + return false; + } + if (!as5600_read_u8(dev, AS5600_REG_STATUS, &raw)) { + return false; + } + + status->raw_status = raw; + status->magnet_detected = ((raw & AS5600_STATUS_MD) != 0u); + status->magnet_too_weak = ((raw & AS5600_STATUS_ML) != 0u); + status->magnet_too_strong = ((raw & AS5600_STATUS_MH) != 0u); + return true; +} + +bool as5600_is_magnet_detected(const as5600_t *dev, bool *detected) { + as5600_status_t status; + if (detected == NULL) { + return false; + } + if (!as5600_read_status(dev, &status)) { + return false; + } + *detected = status.magnet_detected; + return true; +} + +bool as5600_read_agc(const as5600_t *dev, uint8_t *agc) { + return as5600_read_u8(dev, AS5600_REG_AGC, agc); +} + +bool as5600_read_magnitude(const as5600_t *dev, uint16_t *magnitude) { + return as5600_read_u16(dev, AS5600_REG_MAGNITUDE_H, magnitude); +} + +bool as5600_read_raw_angle_counts(const as5600_t *dev, uint16_t *counts) { + return as5600_read_u16(dev, AS5600_REG_RAW_ANGLE_H, counts); +} + +bool as5600_read_angle_counts(const as5600_t *dev, uint16_t *counts) { + return as5600_read_u16(dev, AS5600_REG_ANGLE_H, counts); +} + +bool as5600_read_raw_angle_degrees(const as5600_t *dev, float *degrees) { + uint16_t counts = 0u; + if (degrees == NULL) { + return false; + } + if (!as5600_read_raw_angle_counts(dev, &counts)) { + return false; + } + *degrees = as5600_counts_to_degrees_f(counts); + return true; +} + +bool as5600_read_angle_degrees(const as5600_t *dev, float *degrees) { + uint16_t counts = 0u; + if (degrees == NULL) { + return false; + } + if (!as5600_read_angle_counts(dev, &counts)) { + return false; + } + *degrees = as5600_counts_to_degrees_f(counts); + return true; +} + +bool as5600_read_raw_angle_counts_zeroed(const as5600_t *dev, uint16_t *counts) { + uint16_t raw = 0u; + if (dev == NULL || counts == NULL) { + return false; + } + if (!as5600_read_raw_angle_counts(dev, &raw)) { + return false; + } + *counts = as5600_wrap_counts((uint16_t)(raw - dev->zero_offset_counts)); + return true; +} + +bool as5600_read_raw_angle_degrees_zeroed(const as5600_t *dev, float *degrees) { + uint16_t counts = 0u; + if (degrees == NULL) { + return false; + } + if (!as5600_read_raw_angle_counts_zeroed(dev, &counts)) { + return false; + } + *degrees = as5600_counts_to_degrees_f(counts); + return true; +} + +bool as5600_read_conf(const as5600_t *dev, as5600_conf_t *conf) { + uint16_t reg = 0u; + if (conf == NULL) { + return false; + } + if (!as5600_read_u16(dev, AS5600_REG_CONF_H, ®)) { + return false; + } + conf_unpack(reg, conf); + return true; +} + +bool as5600_write_conf(const as5600_t *dev, const as5600_conf_t *conf) { + return as5600_write_u16(dev, AS5600_REG_CONF_H, conf_pack(conf)); +} + +bool as5600_write_zpos(const as5600_t *dev, uint16_t zpos) { + return as5600_write_u16(dev, AS5600_REG_ZPOS_H, zpos); +} + +bool as5600_write_mpos(const as5600_t *dev, uint16_t mpos) { + return as5600_write_u16(dev, AS5600_REG_MPOS_H, mpos); +} + +bool as5600_write_mang(const as5600_t *dev, uint16_t mang) { + return as5600_write_u16(dev, AS5600_REG_MANG_H, mang); +} + +bool as5600_program_range_volatile(const as5600_t *dev, uint16_t zpos, uint16_t mpos) { + if (!as5600_write_zpos(dev, zpos)) { + return false; + } + if (!as5600_write_mpos(dev, mpos)) { + return false; + } + return true; +} + +bool as5600_burn_angle(const as5600_t *dev) { + return as5600_write_u8(dev, AS5600_REG_BURN, AS5600_BURN_ANGLE_CMD); +} + +bool as5600_burn_settings(const as5600_t *dev) { + return as5600_write_u8(dev, AS5600_REG_BURN, AS5600_BURN_SETTING_CMD); +} + +uint16_t as5600_counts_to_degrees_x100(uint16_t counts) { + uint32_t x100 = ((uint32_t)as5600_wrap_counts(counts) * 36000u) / 4096u; + return (uint16_t)x100; +} + +float as5600_counts_to_degrees_f(uint16_t counts) { + return (float)as5600_wrap_counts(counts) * AS5600_DEGREES_PER_COUNT; +} + +uint16_t as5600_degrees_to_counts_f(float degrees) { + float wrapped = as5600_wrap_degrees_360(degrees); + uint32_t counts = (uint32_t)((wrapped * 4096.0f / 360.0f) + 0.5f); + return as5600_wrap_counts((uint16_t)counts); +} + +uint16_t as5600_wrap_counts(uint16_t counts) { + return (uint16_t)(counts & 0x0FFFu); +} + +float as5600_wrap_degrees_360(float degrees) { + while (degrees >= 360.0f) { + degrees -= 360.0f; + } + while (degrees < 0.0f) { + degrees += 360.0f; + } + return degrees; +} + +int16_t as5600_shortest_delta_counts(uint16_t from_counts, uint16_t to_counts) { + int16_t delta = (int16_t)(as5600_wrap_counts(to_counts) - as5600_wrap_counts(from_counts)); + if (delta > 2048) { + delta -= 4096; + } else if (delta < -2048) { + delta += 4096; + } + return delta; +} + +float as5600_shortest_delta_degrees(float from_deg, float to_deg) { + float delta = as5600_wrap_degrees_360(to_deg) - as5600_wrap_degrees_360(from_deg); + if (delta > 180.0f) { + delta -= 360.0f; + } else if (delta < -180.0f) { + delta += 360.0f; + } + return delta; +} diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Src/i2c_drivers/as5600_encoder_device.c b/embedded-software/firmware/gimbal_test_stand/Core/Src/i2c_drivers/as5600_encoder_device.c new file mode 100644 index 00000000..a77f9add --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Core/Src/i2c_drivers/as5600_encoder_device.c @@ -0,0 +1,61 @@ +#include "main.h" +#include "as5600.h" + +#include +#include + +/* + * STM32 HAL glue layer. + * + * Keep the portable driver in as5600.c free from direct HAL dependencies. + * Only this file knows about HAL_I2C_* symbols and TIMING details. + */ + +bool as5600_device_is_ready(void *hi2c, uint16_t addr_8bit, uint32_t timeout_ms) { + if (hi2c == NULL) { + return false; + } + + I2C_HandleTypeDef *h = (I2C_HandleTypeDef *)hi2c; + return (HAL_I2C_IsDeviceReady(h, addr_8bit, 2u, timeout_ms) == HAL_OK); +} + +bool as5600_device_mem_read(void *hi2c, + uint16_t addr_8bit, + uint8_t reg, + uint8_t *data, + uint16_t len, + uint32_t timeout_ms) { + if (hi2c == NULL || data == NULL || len == 0u) { + return false; + } + + I2C_HandleTypeDef *h = (I2C_HandleTypeDef *)hi2c; + return (HAL_I2C_Mem_Read(h, + addr_8bit, + reg, + I2C_MEMADD_SIZE_8BIT, + data, + len, + timeout_ms) == HAL_OK); +} + +bool as5600_device_mem_write(void *hi2c, + uint16_t addr_8bit, + uint8_t reg, + const uint8_t *data, + uint16_t len, + uint32_t timeout_ms) { + if (hi2c == NULL || data == NULL || len == 0u) { + return false; + } + + I2C_HandleTypeDef *h = (I2C_HandleTypeDef *)hi2c; + return (HAL_I2C_Mem_Write(h, + addr_8bit, + reg, + I2C_MEMADD_SIZE_8BIT, + (uint8_t *)data, + len, + timeout_ms) == HAL_OK); +} diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Src/main.c b/embedded-software/firmware/gimbal_test_stand/Core/Src/main.c index cb81e8b6..82516671 100644 --- a/embedded-software/firmware/gimbal_test_stand/Core/Src/main.c +++ b/embedded-software/firmware/gimbal_test_stand/Core/Src/main.c @@ -21,6 +21,7 @@ /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ +#include "as5600.h" /* USER CODE END Includes */ @@ -43,8 +44,10 @@ COM_InitTypeDef BspCOMInit; -/* USER CODE BEGIN PV */ +I2C_HandleTypeDef hi2c1; +/* USER CODE BEGIN PV */ +static as5600_t g_as5600; /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ @@ -52,6 +55,7 @@ void SystemClock_Config(void); static void MPU_Config(void); static void MX_GPIO_Init(void); static void MX_ICACHE_Init(void); +static void MX_I2C1_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -94,8 +98,14 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_ICACHE_Init(); + MX_I2C1_Init(); /* USER CODE BEGIN 2 */ +if (as5600_init(&g_as5600, &hi2c1, 10u) != AS5600_OK) +{ + Error_Handler(); +} + /* USER CODE END 2 */ /* Initialize leds */ @@ -176,6 +186,54 @@ void SystemClock_Config(void) __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_0); } +/** + * @brief I2C1 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C1_Init(void) +{ + + /* USER CODE BEGIN I2C1_Init 0 */ + + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + hi2c1.Init.Timing = 0x00707CBB; + hi2c1.Init.OwnAddress1 = 0; + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c1.Init.OwnAddress2 = 0; + hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + /** * @brief ICACHE Initialization Function * @param None @@ -253,14 +311,6 @@ static void MX_GPIO_Init(void) GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - /*Configure GPIO pins : PB6 PB7 */ - GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ diff --git a/embedded-software/firmware/gimbal_test_stand/Core/Src/stm32h5xx_hal_msp.c b/embedded-software/firmware/gimbal_test_stand/Core/Src/stm32h5xx_hal_msp.c index 17b49a9d..3e67e60d 100644 --- a/embedded-software/firmware/gimbal_test_stand/Core/Src/stm32h5xx_hal_msp.c +++ b/embedded-software/firmware/gimbal_test_stand/Core/Src/stm32h5xx_hal_msp.c @@ -73,6 +73,84 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } +/** + * @brief I2C MSP Initialization + * This function configures the hardware resources used in this example + * @param hi2c: I2C handle pointer + * @retval None + */ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(hi2c->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1; + PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + + } + +} + +/** + * @brief I2C MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hi2c: I2C handle pointer + * @retval None + */ +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) +{ + if(hi2c->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspDeInit 0 */ + + /* USER CODE END I2C1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C1_CLK_DISABLE(); + + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7); + + /* USER CODE BEGIN I2C1_MspDeInit 1 */ + + /* USER CODE END I2C1_MspDeInit 1 */ + } + +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h new file mode 100644 index 00000000..49d262e5 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h @@ -0,0 +1,842 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_I2C_H +#define STM32H5xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization section + in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (peripheral in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + +#endif /*HAL_DMA_MODULE_ENABLED*/ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define I2C_FLAG_MASK (0x0001FFFFU) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32h5xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +#if defined(HAL_DMA_MODULE_ENABLED) +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +#endif /*HAL_DMA_MODULE_ENABLED*/ +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START) | \ + (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32h5xx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H5xx_HAL_I2C_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c_ex.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c_ex.h new file mode 100644 index 00000000..31e0f381 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c_ex.h @@ -0,0 +1,156 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_I2C_EX_H +#define STM32H5xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */ +#define I2C_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_I2C_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (I2C_FASTMODEPLUS_ENABLE)) || \ + ((__CONFIG__) == (I2C_FASTMODEPLUS_DISABLE))) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32h5xx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_I2C_EX_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h new file mode 100644 index 00000000..230fd48d --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h @@ -0,0 +1,2380 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_i2c.h + * @author MCD Application Team + * @brief Header file of I2C LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_LL_I2C_H +#define STM32H5xx_LL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_LL_Private_Constants I2C Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_Private_Macros I2C Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeripheralMode; /*!< Specifies the peripheral mode. + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetMode(). */ + + uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. + This parameter must be set by referring to the STM32CubeMX Tool and + the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetTiming(). */ + + uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. + + This feature can be modified afterwards using unitary functions + @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ + + uint32_t DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetDigitalFilter(). */ + + uint32_t OwnAddress1; /*!< Specifies the device own address 1. + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive + match code or next received byte. + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_AcknowledgeNextData(). */ + + uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ +} LL_I2C_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_I2C_WriteReg function + * @{ + */ +#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ +#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ +#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ +#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ +#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ +#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ +#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ +#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ +#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2C_ReadReg function + * @{ + */ +#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */ +#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */ +#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */ +#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */ +#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */ +#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */ +#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */ +#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */ +#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */ +#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */ +#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ +#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ +#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ +#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions + * @{ + */ +#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */ +#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */ +#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ +#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ +#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ +#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ +#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + * @{ + */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode + (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection + * @{ + */ +#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ +#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode + * @{ + */ +#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ +#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length + * @{ + */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks + * @{ + */ +#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. + All Address2 are acknowledged. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ +#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length + * @{ + */ +#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ +#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction + * @{ + */ +#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ +#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_MODE Transfer End Mode + * @{ + */ +#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ +#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Software end mode with HW PEC comparison. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation + * @{ + */ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U +/*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +/*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ + I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) +/*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 10Bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, + slave enters receiver mode. */ +#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, + slave enters transmitter mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for + transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for + reception */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect + SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect + both SCL and SDA high level timeout.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) + enable bit */ +#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \ + I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB +(extended clock) enable bits */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings + * @{ + */ +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tscldel = (SCLDEL+1)xtpresc) + * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tsdadel = SDADELxtpresc) + * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tsclh = (SCLH+1)xtpresc) + * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tscll = (SCLL+1)xtpresc) + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I2C peripheral (PE = 1). + * @rmtoll CR1 PE LL_I2C_Enable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Disable I2C peripheral (PE = 0). + * @note When PE = 0, the I2C SCL and SDA lines are released. + * Internal state machines and status bits are put back to their reset value. + * When cleared, PE must be kept low for at least 3 APB clock cycles. + * @rmtoll CR1 PE LL_I2C_Disable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Check if the I2C peripheral is enabled or disabled. + * @rmtoll CR1 PE LL_I2C_IsEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); +} + +/** + * @brief Configure Noise Filters (Analog and Digital). + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * The filters can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n + * CR1 DNF LL_I2C_ConfigFilters + * @param I2Cx I2C Instance. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref LL_I2C_ANALOGFILTER_ENABLE + * @arg @ref LL_I2C_ANALOGFILTER_DISABLE + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); +} + +/** + * @brief Configure Digital Noise Filter. + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter + * @param I2Cx I2C Instance. + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); +} + +/** + * @brief Get the current Digital Noise Filter configuration. + * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); +} + +/** + * @brief Enable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Disable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Check if Analog Noise Filter is enabled or disabled. + * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n + * RXDR RXDATA LL_I2C_DMA_GetRegAddr + * @param I2Cx I2C Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) + { + /* return address of TXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->TXDR); + } + else + { + /* return address of RXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->RXDR); + } + + return data_reg_addr; +} + +/** + * @brief Enable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); +} + +/** + * @brief Enable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Disable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Check if hardware byte control in slave mode is enabled or disabled. + * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); +} + +/** + * @brief Enable Wakeup from STOP. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when Digital Filter is disabled. + * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Disable Wakeup from STOP. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Check if Wakeup from STOP is enabled or disabled. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable General Call. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Disable General Call. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable I2C Fast Mode Plus (FMP = 1). + * @note 20mA I/O drive enable + * @rmtoll CR1 FMP LL_I2C_EnableFastModePlus + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_FMP); +} + +/** + * @brief Disable I2C Fast Mode Plus (FMP = 0). + * @note 20mA I/O drive disable + * @rmtoll CR1 FMP LL_I2C_DisableFastModePlus + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP); +} + +/** + * @brief Check if the I2C Fast Mode Plus is enabled or disabled. + * @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL); +} + +/** + * @brief Enable automatic clear of ADDR flag. + * @rmtoll CR1 ADDRACLR LL_I2C_EnableAutoClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR); +} + +/** + * @brief Disable automatic clear of ADDR flag. + * @rmtoll CR1 ADDRACLR LL_I2C_DisableAutoClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR); +} + +/** + * @brief Check if the automatic clear of ADDR flag is enabled or disabled. + * @rmtoll CR1 ADDRACLR LL_I2C_IsEnabledAutoClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR) == (I2C_CR1_ADDRACLR)) ? 1UL : 0UL); +} + +/** + * @brief Enable automatic clear of STOP flag. + * @rmtoll CR1 STOPFACLR LL_I2C_EnableAutoClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR); +} + +/** + * @brief Disable automatic clear of STOP flag. + * @rmtoll CR1 STOPFACLR LL_I2C_DisableAutoClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR); +} + +/** + * @brief Check if the automatic clear of STOP flag is enabled or disabled. + * @rmtoll CR1 STOPFACLR LL_I2C_IsEnabledAutoClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR) == (I2C_CR1_STOPFACLR)) ? 1UL : 0UL); +} + +/** + * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. + * @note Changing this bit is not allowed, when the START bit is set. + * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode + * @param I2Cx I2C Instance. + * @param AddressingMode This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode); +} + +/** + * @brief Get the Master addressing mode. + * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + */ +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); +} + +/** + * @brief Set the Own Address1. + * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n + * OAR1 OA1MODE LL_I2C_SetOwnAddress1 + * @param I2Cx I2C Instance. + * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param OwnAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS1_7BIT + * @arg @ref LL_I2C_OWNADDRESS1_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) +{ + MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); +} + +/** + * @brief Enable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Disable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); +} + +/** + * @brief Set the 7bits Own Address2. + * @note This action has no effect if own address2 is enabled. + * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n + * OAR2 OA2MSK LL_I2C_SetOwnAddress2 + * @param I2Cx I2C Instance. + * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. + * @param OwnAddrMask This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS2_NOMASK + * @arg @ref LL_I2C_OWNADDRESS2_MASK01 + * @arg @ref LL_I2C_OWNADDRESS2_MASK02 + * @arg @ref LL_I2C_OWNADDRESS2_MASK03 + * @arg @ref LL_I2C_OWNADDRESS2_MASK04 + * @arg @ref LL_I2C_OWNADDRESS2_MASK05 + * @arg @ref LL_I2C_OWNADDRESS2_MASK06 + * @arg @ref LL_I2C_OWNADDRESS2_MASK07 + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask) +{ + MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); +} + +/** + * @brief Enable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Disable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming + * @param I2Cx I2C Instance. + * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + * @note This parameter is computed with the STM32CubeMX Tool. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) +{ + WRITE_REG(I2Cx->TIMINGR, Timing); +} + +/** + * @brief Get the Timing Prescaler setting. + * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); +} + +/** + * @brief Get the SCL low period setting. + * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); +} + +/** + * @brief Get the SCL high period setting. + * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); +} + +/** + * @brief Get the SDA hold time. + * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); +} + +/** + * @brief Get the SDA setup time. + * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); +} + +/** + * @brief Configure peripheral mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n + * CR1 SMBDEN LL_I2C_SetMode + * @param I2Cx I2C Instance. + * @param PeripheralMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); +} + +/** + * @brief Get peripheral mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n + * CR1 SMBDEN LL_I2C_GetMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + */ +__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode) + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is drived low and + * Alert Response Address Header acknowledge is enabled. + * SMBus Host mode: + * - SMBus Alert pin management is supported. + * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Disable SMBus alert (Host or Device mode) + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is not drived (can be used as a standard GPIO) and + * Alert Response Address Header acknowledge is disabled. + * SMBus Host mode: + * - SMBus Alert pin management is not supported. + * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @param TimeoutB + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, + uint32_t TimeoutB) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, + TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); +} + +/** + * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); +} + +/** + * @brief Get the SMBus Clock TimeoutA setting. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); +} + +/** + * @brief Set the SMBus Clock TimeoutA mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); +} + +/** + * @brief Get the SMBus Clock TimeoutA mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); +} + +/** + * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutB is disabled. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Enable the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + SET_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Disable the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Check if the SMBus Clock Timeout is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ + (ClockTimeout)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Disable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Check if the TXIS Interrupt is enabled or disabled. + * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Disable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Check if Address match interrupt is enabled or disabled. + * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Disable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Check if Not acknowledge received interrupt is enabled or disabled. + * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Disable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Check if STOP detection interrupt is enabled or disabled. + * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Disable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Check if Transfer Complete interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Error interrupts. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Disable Error interrupts. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transmit interrupt flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Address matched flag (slave mode). + * @note RESET: Clear default value. + * SET: When the received slave address matched with one of the enabled slave address. + * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Not Acknowledge received flag. + * @note RESET: Clear default value. + * SET: When a NACK is received after a byte transmission. + * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Stop detection flag. + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. + * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=1 and NBYTES date have been transferred. + * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus error flag. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag (slave mode). + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When the received PEC does not match with the PEC register content. + * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus Timeout detection flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When a timeout or extended clock timeout occurs. + * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus alert flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When SMBus host configuration, SMBus alert enabled and + * a falling edge event occurs on SMBA pin. + * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Clear Address Matched flag. + * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF); +} + +/** + * @brief Clear Not Acknowledge flag. + * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF); +} + +/** + * @brief Clear Stop detection flag. + * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF); +} + +/** + * @brief Clear Transmit data register empty flag (TXE). + * @note This bit can be clear by software in order to flush the transmit data register (TXDR). + * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx) +{ + WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF); +} + +/** + * @brief Clear SMBus PEC error flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_PECCF); +} + +/** + * @brief Clear SMBus Timeout detection flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF); +} + +/** + * @brief Clear SMBus Alert flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable automatic STOP condition generation (master mode). + * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. + * This bit has no effect in slave mode or when RELOAD bit is set. + * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Disable automatic STOP condition generation (master mode). + * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. + * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Check if automatic STOP condition is enabled or disabled. + * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); +} + +/** + * @brief Enable reload mode (master mode). + * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set. + * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Disable reload mode (master mode). + * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). + * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Check if reload mode is enabled or disabled. + * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); +} + +/** + * @brief Configure the number of bytes for transfer. + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize + * @param I2Cx I2C Instance. + * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Get the number of bytes configured for transfer. + * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code + or next received byte. + * @note Usage in Slave mode only. + * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData + * @param I2Cx I2C Instance. + * @param TypeAcknowledge This parameter can be one of the following values: + * @arg @ref LL_I2C_ACK + * @arg @ref LL_I2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); +} + +/** + * @brief Generate a START or RESTART condition + * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll CR2 START LL_I2C_GenerateStartCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_STOP); +} + +/** + * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master sends the complete 10bit slave address read sequence : + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address + in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master only sends the first 7 bits of 10bit address in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. + * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); +} + +/** + * @brief Configure the transfer direction (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest + * @param I2Cx I2C Instance. + * @param TransferRequest This parameter can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest); +} + +/** + * @brief Get the transfer direction requested (master mode). + * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); +} + +/** + * @brief Configure the slave address for transfer (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr + * @param I2Cx I2C Instance. + * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr); +} + +/** + * @brief Get the slave address programmed for transfer. + * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n + * CR2 ADD10 LL_I2C_HandleTransfer\n + * CR2 RD_WRN LL_I2C_HandleTransfer\n + * CR2 START LL_I2C_HandleTransfer\n + * CR2 STOP LL_I2C_HandleTransfer\n + * CR2 RELOAD LL_I2C_HandleTransfer\n + * CR2 NBYTES LL_I2C_HandleTransfer\n + * CR2 AUTOEND LL_I2C_HandleTransfer\n + * CR2 HEAD10R LL_I2C_HandleTransfer + * @param I2Cx I2C Instance. + * @param SlaveAddr Specifies the slave address to be programmed. + * @param SlaveAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRSLAVE_7BIT + * @arg @ref LL_I2C_ADDRSLAVE_10BIT + * @param TransferSize Specifies the number of bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=255. + * @param EndMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_RELOAD + * @arg @ref LL_I2C_MODE_AUTOEND + * @arg @ref LL_I2C_MODE_SOFTEND + * @arg @ref LL_I2C_MODE_SMBUS_RELOAD + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC + * @param Request This parameter can be one of the following values: + * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP + * @arg @ref LL_I2C_GENERATE_STOP + * @arg @ref LL_I2C_GENERATE_START_READ + * @arg @ref LL_I2C_GENERATE_START_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE + * @retval None + */ +__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, + tmp); +} + +/** + * @brief Indicate the value of transfer direction (slave mode). + * @note RESET: Write transfer, Slave enters in receiver mode. + * SET: Read transfer, Slave enters in transmitter mode. + * @rmtoll ISR DIR LL_I2C_GetTransferDirection + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DIRECTION_WRITE + * @arg @ref LL_I2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); +} + +/** + * @brief Return the slave matched address. + * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); +} + +/** + * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition + or an Address Matched is received. + * This bit has no effect when RELOAD bit is set. + * This bit has no effect in device mode when SBC bit is not set. + * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE); +} + +/** + * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); +} + +/** + * @brief Get the SMBus Packet Error byte calculated. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll PECR PEC LL_I2C_GetSMBusPEC + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); +} + +/** + * @brief Read Receive Data register. + * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8 + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx) +{ + return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); +} + +/** + * @brief Write in Transmit Data Register . + * @rmtoll TXDR TXDATA LL_I2C_TransmitData8 + * @param I2Cx I2C Instance. + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) +{ + WRITE_REG(I2Cx->TXDR, Data); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx); +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 || I2C3 || I2C4 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_LL_I2C_H */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c new file mode 100644 index 00000000..6884a936 --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c @@ -0,0 +1,7824 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive channel + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx channel + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. + + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). + [..] + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macro + * @{ + */ +#if defined(HAL_DMA_MODULE_ENABLED) +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__)) +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +#if defined(HAL_DMA_MODULE_ENABLED) +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +#if defined(HAL_DMA_MODULE_ENABLED) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +#endif /* HAL_DMA_MODULE_ENABLED */ + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + +/* Private function to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until AF flag is set */ + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + if (hi2c->XferCount != 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->XferSize = 0U; + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t I2C_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + } + else + { + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) == HAL_OK) + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + } + + /* Increment Trials */ + I2C_Trials++; + } while (I2C_Trials < Trials); + + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + +#if defined(HAL_DMA_MODULE_ENABLED) + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmperror); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + if (hi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + /* Do nothing */ + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if (hi2c->XferSize > 0U) + { + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if (hi2c->XferSize > 0U) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + +#if defined(HAL_DMA_MODULE_ENABLED) + uint32_t tmppreviousstate; +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + } + hi2c->XferISR = NULL; + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort DMA TX transfer if any */ + tmppreviousstate = hi2c->PreviousState; + + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef dmaxferstatus = HAL_OK; + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + + if (dmaxferstatus != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef dmaxferstatus = HAL_OK; + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize); + } + + if (dmaxferstatus != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +} + + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Reset AbortCpltCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + I2C_TreatErrorCallback(hi2c); +} + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief This function handles I2C Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The actual Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + status = HAL_OK; + } + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + } + + /* Check for the Timeout */ + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + } + } + return status; +} + +/** + * @brief This function handles errors detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hi2c->Instance->ISR; + uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP Flag is set or timeout occurred */ + /* AutoEnd should be initiate after AF */ + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + tmp2 = hi2c->Mode; + + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + (tmp1 != I2C_CR2_STOP) && \ + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + { + error_code |= HAL_I2C_ERROR_TIMEOUT; + + status = HAL_ERROR; + + break; + } + } + } + } + } + + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + error_code |= HAL_I2C_ERROR_AF; + + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + { + error_code |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + { + error_code |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + { + error_code |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode |= error_code; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return status; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, \ + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), tmp); +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + +#if defined(HAL_DMA_MODULE_ENABLED) + if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + (hi2c->XferISR != I2C_Mem_ISR_DMA)) +#endif /* HAL_DMA_MODULE_ENABLED */ + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + +#if defined(HAL_DMA_MODULE_ENABLED) + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c new file mode 100644 index 00000000..7538ab3a --- /dev/null +++ b/embedded-software/firmware/gimbal_test_stand/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c @@ -0,0 +1,359 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Filter Mode Functions + * + WakeUp Mode Functions + * + FastModePlus Functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32H5xx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter and Wake Up Feature + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + (++) HAL_I2CEx_EnableWakeUp() + (++) HAL_I2CEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_ConfigFastModePlus() + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions + * +@verbatim + =============================================================================== + ##### Filter Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Fast Mode Plus. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param FastModePlus New state of the Fast Mode Plus. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_FASTMODEPLUS(FastModePlus)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + if (FastModePlus == I2C_FASTMODEPLUS_ENABLE) + { + /* Set I2Cx FMP bit */ + hi2c->Instance->CR1 |= (I2C_CR1_FMP); + } + else + { + /* Reset I2Cx FMP bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_FMP); + } + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/embedded-software/firmware/gimbal_test_stand/cmake/stm32cubemx/CMakeLists.txt b/embedded-software/firmware/gimbal_test_stand/cmake/stm32cubemx/CMakeLists.txt index ce0b6c6c..e65be547 100644 --- a/embedded-software/firmware/gimbal_test_stand/cmake/stm32cubemx/CMakeLists.txt +++ b/embedded-software/firmware/gimbal_test_stand/cmake/stm32cubemx/CMakeLists.txt @@ -33,18 +33,20 @@ set(MX_Application_Src set(STM32_Drivers_Src ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/system_stm32h5xx.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c - ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c - ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c - ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c + ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c diff --git a/embedded-software/firmware/gimbal_test_stand/gimbal_test_stand.ioc b/embedded-software/firmware/gimbal_test_stand/gimbal_test_stand.ioc index 8203742a..4c49fa3a 100644 --- a/embedded-software/firmware/gimbal_test_stand/gimbal_test_stand.ioc +++ b/embedded-software/firmware/gimbal_test_stand/gimbal_test_stand.ioc @@ -12,6 +12,8 @@ CORTEX_M33_NS.default_mode_Activation=1 CORTEX_M33_NS.userName=CORTEX_M33 File.Version=6 GPIO.groupedBy=Group By Peripherals +I2C1.IPParameters=Timing +I2C1.Timing=0x00707CBB KeepUserPlacement=false MMTAppRegionsCount=0 MMTConfigApplied=false @@ -21,14 +23,15 @@ Mcu.ContextProject=TrustZoneDisabled Mcu.Family=STM32H5 Mcu.IP0=BOOTPATH Mcu.IP1=CORTEX_M33_NS -Mcu.IP2=ICACHE -Mcu.IP3=MEMORYMAP -Mcu.IP4=NUCLEO-H533RE -Mcu.IP5=NVIC -Mcu.IP6=PWR -Mcu.IP7=RCC -Mcu.IP8=SYS -Mcu.IPNb=10 +Mcu.IP2=I2C1 +Mcu.IP3=ICACHE +Mcu.IP4=MEMORYMAP +Mcu.IP5=NUCLEO-H533RE +Mcu.IP6=NVIC +Mcu.IP7=PWR +Mcu.IP8=RCC +Mcu.IP9=SYS +Mcu.IPNb=11 Mcu.Name=STM32H533RETx Mcu.Package=LQFP64 Mcu.Pin0=PC13 @@ -102,8 +105,10 @@ PB3(JTDO/TRACESWO).GPIO_Label=SWO PB3(JTDO/TRACESWO).Locked=true PB3(JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO PB6.Locked=true +PB6.Mode=I2C PB6.Signal=I2C1_SCL PB7.Locked=true +PB7.Mode=I2C PB7.Signal=I2C1_SDA PC13.Locked=true PC6.Locked=true @@ -153,7 +158,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ICACHE_Init-ICACHE-false-HAL-true,false-0--NUCLEO-H533RE-true-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ICACHE_Init-ICACHE-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true,false-0--NUCLEO-H533RE-true-HAL-true RCC.ADCFreq_Value=32000000 RCC.AHBFreq_Value=32000000 RCC.APB1Freq_Value=32000000 diff --git a/embedded-software/firmware/ulysses-flight-controller/Core/Src/main.c b/embedded-software/firmware/ulysses-flight-controller/Core/Src/main.c index f2d0a558..fddf462e 100644 --- a/embedded-software/firmware/ulysses-flight-controller/Core/Src/main.c +++ b/embedded-software/firmware/ulysses-flight-controller/Core/Src/main.c @@ -243,7 +243,7 @@ int main(void) /* Start scheduler */ -/home/j1m1 osKernelStart(); + osKernelStart(); /* We should never get here as control is now taken by the scheduler */ diff --git a/embedded-software/ground-station/CMakeLists.txt b/embedded-software/ground-station/CMakeLists.txt index 585eed23..4c7aae41 100644 --- a/embedded-software/ground-station/CMakeLists.txt +++ b/embedded-software/ground-station/CMakeLists.txt @@ -5,6 +5,10 @@ project(ulysses_ground_control LANGUAGES CXX C ) +# ---------------------------------------------------------------------- 1 +include(GNUInstallDirs) +# ---------------------------------------------------------------------- + set(CMAKE_AUTOMOC ON) set(CMAKE_AUTORCC ON) set(CMAKE_AUTOUIC ON) @@ -70,9 +74,40 @@ qt_add_executable(ulysses_ground_control ) if(UNIX AND NOT APPLE) - set_target_properties(ulysses_ground_control PROPERTIES OUTPUT_NAME ulysses_gcs) + set_target_properties(ulysses_ground_control PROPERTIES + OUTPUT_NAME ulysses_gcs + BUILD_WITH_INSTALL_RPATH TRUE + INSTALL_RPATH "$ORIGIN/../lib" + ) endif() +# ---------------------------------------------------------------------- 2 +install(TARGETS ulysses_ground_control + BUNDLE DESTINATION . + RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} +) + +qt_generate_deploy_qml_app_script( + TARGET ulysses_ground_control + OUTPUT_SCRIPT deploy_script +) + +install(SCRIPT ${deploy_script}) + +get_target_property(QT6_SERIALPORT_LOCATION Qt6::SerialPort LOCATION) +get_filename_component(QT6_LIB_DIR "${QT6_SERIALPORT_LOCATION}" DIRECTORY) + +file(GLOB QT6_SERIALPORT_LIBS + "${QT6_LIB_DIR}/libQt6SerialPort.so*" +) + +install(FILES + ${QT6_SERIALPORT_LIBS} + DESTINATION ${CMAKE_INSTALL_LIBDIR} +) +# ---------------------------------------------------------------------- + + # ---------------------------------------------------------------------- # QML module # ---------------------------------------------------------------------- @@ -126,3 +161,17 @@ target_link_libraries(ulysses_ground_control qt_import_qml_plugins(ulysses_ground_control) qt_finalize_executable(ulysses_ground_control) + + +# ---------------------------------------------------------------------- +set(CPACK_PACKAGE_NAME "ulysses-gcs") +set(CPACK_PACKAGE_VERSION "0.1.1") +set(CPACK_PACKAGE_DESCRIPTION_SUMMARY "Ulysses Ground Control") +set(CPACK_PACKAGE_VENDOR "UBC Rocket") +set(CPACK_PACKAGE_INSTALL_DIRECTORY ${CPACK_PACKAGE_NAME}) +set(CPACK_VERBATIM_VARIABLES ON) +set(CPACK_PACKAGING_INSTALL_PREFIX "/opt/ulysses-gcs") +set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Jimmy Pan") +set(CPACK_DEBIAN_PACKAGE_DEPENDS "libc6, libstdc++6, libgcc-s1, libxcb-cursor0, libxkbcommon-x11-0, qt6-wayland") + +include(CPack)