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This document provides an introduction for using the Xilinx® Vivado®
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Design Suite flow for a VMK180/VCK190 evaluation board. The tools used
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Design Suite flow for a Versal™VMK180/VCK190 evaluation board. The tools used
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are Vivado Design Suite and the Vitis™ unified software platform,
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version 2020.2. To install the Vitis unified software platform, see *Vitis Unified Software Platform Documentation: Embedded Software Development* ([UG1400](https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest%3Bd%3Dug1400-vitis-embedded.pdf)).
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>***Note*:** In this tutorial, the instructions for booting Linux on
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>**Note:***In this tutorial, the instructions for booting Linux on
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the hardware is specific to the PetaLinux tools released for 2020.2,
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which must be installed on a Linux host machine for exercising the
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Linux portions of this document.
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Linux portions of this document.*
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>**IMPORTANT!***The VCK190/VMK180 Evaluation kit has a Silicon Labs
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CP210x VCP USB-UART Bridge. Ensure that these drivers are installed.
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See the Silicon Labs CP210x USB-to-UART Installation Guide
The examples in this document are created using the Xilinx tools
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running on a Windows 10, 64-bit operating system, Vitis software
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platform and PetaLinux on a Linux 64-bit operating system. Other
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processes:
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***System and Solution Planning**: Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine.
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*[Configuring the NoC IP Core in an Existing Project](/Versal-EDT/docs/2-cips-noc-ip-config.md#configuring-the-noc-ip-core-in-an-existing-project)
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*[System Design Example using Scalar Engine and Adaptable Engine](..Versal-EDT/docs/5-system-design-example.md)
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*[Running a Bare-Metal Hello World Application on DDR Memory](../Versal-EDT/docs/2-cips-noc-ip-config.md#running-a-bare-metal-hello-world-application-on-ddr-memory)
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***Hardware, IP, and Platform Development**: Creating the PL IP blocks for the hardware platform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado® timing, resource use, and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include:
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*[CIPS IP Core Configuration](../Versal-EDT/docs/2-cips-noc-ip-config.md#cips-ip-core-configuration)
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*[NoC (and DDR) IP Core Configuration](../Versal-EDT/docs/2-cips-noc-ip-config.md#noc-and-ddr-ip-core-configuration)
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*[Design Example: Using AXI GPIO](../Versal-EDT/docs/5-system-design-example.md#design-example-using-axi-gpio)
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***System Integration and Validation**: Integrating and validating the system functional performance, including timing, resource use, and power closure. Topics in this document that apply to this design process include:
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*[Boot and Configuration](../Versal-EDT/docs/4-boot-and-config.md)
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*[Example Project: FreeRTOS GPIO Application Project With RPU](../Versal-EDT/docs/5-system-design-example.md#example-project-freertos-gpio-application-project-with-rpu)
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*[Example Project: Creating Linux Images Using PetaLinux](../Versal-EDT/docs/5-system-design-example.md#example-project-creating-linux-images-using-petalinux)
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