QDMA mastering from FPGA

[quetric]

To support FPGA kernels operating on host-side buffers (and GPU buffers down the line) we need to enable mastering the QDMA from the host side. Modify QDMA config to enable mastering, and implement any required host-side and FPGA-side infrastructure.

[lockezhan]

Hi @quetric Based on the note "enable mastering the QDMA from the host side", I’d like to confirm whether QDMA is already integrated and actively used, or if this is a planned addition? Thanks

[quetric]

Hi @lockezhan yes QDMA (in CPM5) is how we access the device over PCIe. Same as AVED.

[lockezhan]

Thanks @quetric , that clarifies it！

As a follow-up:
In the README, I saw this note:

"In the current version of the linker, a maximum number of 15 kernels can be instantiated. This will be fixed in future [versions."]

Is this limitation due to SLASH's automatic routing capability (e.g., number of AXI/MM slots or internal kernel table limits)?
That is, within this 15-kernel boundary, does SLASH fully handle the wiring (AXI, clocks, interrupts), and beyond that, the failure occurs because the linker currently can't scale automatic connection logic further?

Understanding this would help determine whether I need to prepare a manual block design or stay within the auto-linked flow. Appreciate your insight!

[quetric]

At 15 we're running into the maximum number of master ports on an interconnect that Vivado accepts. This can be solved through better BD construction (and also distributing kernels to multiple NOC NMUs) in the linker but we're prioritizing functional testing at the moment and expect to get to these scalability issues soon.

[lockezhan]

Appreciate the insight, @quetric — that helps clarify the underlying limitation. Totally understand prioritizing functional testing first, and I'm looking forward to seeing how the linker evolves to address scalability in future releases.