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esp: spi: Fix connect_pins (#896)
1 parent ec5cf62 commit 1ce2b38

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Lines changed: 5 additions & 2 deletions

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port/espressif/esp/src/hal/spi.zig

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,6 @@ pub const SPI = enum(u2) {
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self.set_bit_order(config.bit_order);
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}
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163-
// TODO: not sure if this is the best way to do this
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pub inline fn connect_pins(_: SPI, pins: struct {
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data: union(enum) {
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single_one_wire: ?gpio.Pin,
@@ -188,7 +187,7 @@ pub const SPI = enum(u2) {
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},
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.single_two_wires => |maybe_pins| {
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if (maybe_pins.mosi) |mosi| {
191-
mosi.connect_input_to_peripheral(.{ .signal = .fspid });
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mosi.connect_peripheral_to_output(.{ .signal = .fspid });
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}
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if (maybe_pins.miso) |miso| {
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miso.connect_input_to_peripheral(.{ .signal = .fspiq });
@@ -223,6 +222,10 @@ pub const SPI = enum(u2) {
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}
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},
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}
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if (pins.clk) |clk_pin| {
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clk_pin.connect_peripheral_to_output(.{ .signal = .spiclk });
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}
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}
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pub fn writev_blocking(

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