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karthisrinivasankarthisrinivasan
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delay line library
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‎std/Makefile‎

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# limitations under the License.
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#
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#-------------------------------------------------------------------------
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TARGETACT=_all_.act channel.act data.act func.act cells.act arb.act mem.act
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TARGETACT=_all_.act channel.act data.act func.act cells.act arb.act mem.act delay_lines.act
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SUBDIRS=io gates
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TARGETACTSUBDIR=std
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‎std/_all_.act‎

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@@ -34,3 +34,4 @@ import std::data;
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import std::channel;
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import "std/arb.act";
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import "std/mem.act";
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import "std/delay_lines.act";

‎std/delay_lines.act‎

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/*************************************************************************
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*
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* This file is part of ACT standard library
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*
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* Copyright (c) 2025 Karthi Srinivasan
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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**************************************************************************
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*/
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import std::cells;
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import std::gates;
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namespace std {
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export namespace delay_elements {
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// Symmetric Delay Elements -----------------------
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export defproc delay_buffer (bool? in; bool! out)
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{
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std::cells::INVX1 invs[2];
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invs[0].A = in;
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invs[0].Y = invs[1].A;
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invs[1].Y = out;
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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export template <pint L>
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defproc weak_delay_buffer (bool? in; bool! out) {
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bool x;
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prs {
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in<1,L> => x-
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x<1,L> => out-
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}
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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// Symmetric Delay Elements -----------------------
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// Asymmetric Delay Elements ----------------------
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export template <pint REC, L> defproc fast0_slow1_rec (bool? in; bool! out);
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export template <pint REC, L> defproc fast1_slow0_rec (bool? in; bool! out);
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export template <pint REC, L>
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defproc fast0_slow1_rec (bool? in; bool! out) {
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{ REC>=0 : "what" };
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bool x; bool f0s1out, f1s0out;
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[ REC=0 -> f0s1out = in;
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f1s0out = x;
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[]REC>0 -> fast0_slow1_rec<REC-1,L> f0s1r(in); f0s1out = f0s1r.out;
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fast1_slow0_rec<REC-1,L> f1s0r(x); f1s0out = f1s0r.out;
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]
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prs {
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[keeper=0] f0s1out<1,L> & in<1,1> -> x-
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[keeper=0] ~in<1,1> -> x+
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[keeper=0] x<1,1> -> out-
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[keeper=0] ~f1s0out<1,L> & ~x<1,1> -> out+
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}
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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export template <pint REC, L>
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defproc fast1_slow0_rec (bool? in; bool! out) {
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{ REC>=0 : "what" };
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bool x; bool f0s1out, f1s0out;
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[ REC=0 -> f1s0out = in;
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f0s1out = x;
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[]REC>0 -> fast1_slow0_rec<REC-1,L> f1s0r(in); f1s0out = f1s0r.out;
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fast0_slow1_rec<REC-1,L> f0s1r(x); f0s1out = f0s1r.out;
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]
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prs {
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[keeper=0] in<1,1> -> x-
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[keeper=0] ~f1s0out<1,L> & ~in<1,1> -> x+
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[keeper=0] f0s1out<1,L> & x<1,1> -> out-
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[keeper=0] ~x<1,1> -> out+
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}
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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export defproc reuse_1 (bool? in; bool! out; bool! dl_in; bool? dl_out) {
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std::cells::XOR2X1 xor;
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bool a, b, _i;
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_i = xor.A;
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a = xor.B;
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xor.Y = dl_in;
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b = dl_out;
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prs {
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b & in #> a-
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a -> out-
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~a & ~b -> out+
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in => _i-
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}
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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export defcell PCELEM2 (bool? A, B; bool! Y) {
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bool _Y;
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prs {
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A & B -> _Y-
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~A & ~B -> _Y+
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_Y => Y-
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}
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}
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export defcell UACELEM2 (bool? A, B; bool! Y) {
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prs {
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A & B -> Y-
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~A -> Y+
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}
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}
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export defcell DACELEM2 (bool? A, B; bool! Y) {
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prs {
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~A & ~B -> Y+
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A -> Y-
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}
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}
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export defproc reuse_2 (bool? in; bool! out; bool! dl_in; bool? dl_out) {
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bool x, _x, do;
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std::gates::ctree<2,true> C0;
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UACELEM2 UAC0;
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DACELEM2 DAC0;
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std::cells::INVX1 INV0;
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std::cells::INVX1 INV1;
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std::cells::NOR2X1 NOR0;
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C0.in[0] = in;
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C0.in[1] = dl_out;
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C0.out = x;
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UAC0.A = NOR0.Y;
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UAC0.B = in;
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UAC0.Y = do;
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DAC0.A = x;
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DAC0.B = dl_out;
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DAC0.Y = out;
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INV1.A = x;
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INV1.Y = _x;
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NOR0.A = _x;
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NOR0.B = Reset;
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INV0.A = do;
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INV0.Y = dl_in;
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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// Asymmetric Delay Elements ----------------------
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}
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export namespace delay_lines {
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// Symmetric Delay Lines -----------------------
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export template <pint N>
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defproc chain_delay_buffer (bool? in; bool! out) {
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std::delay_elements::delay_buffer d[N];
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in = d[0].in;
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( i : N-1 : d[i].out = d[i+1].in; )
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d[N-1].out = out;
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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export template <pint N, L>
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defproc chain_weak_delay_buffer (bool? in; bool! out) {
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std::delay_elements::weak_delay_buffer<L> d[N];
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in = d[0].in;
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( i : N-1 : d[i].out = d[i+1].in; )
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d[N-1].out = out;
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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// Symmetric Delay Lines -----------------------
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// Asymmetric Delay Lines ----------------------
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export template <pint N, REC, L>
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defproc chain_recursive_fast0_slow1 (bool? in; bool! out) {
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std::delay_elements::fast0_slow1_rec<REC, L> d[N];
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in = d[0].in;
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( i : N-1 : d[i].out = d[i+1].in; )
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d[N-1].out = out;
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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export template <pint N, REC, L>
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defproc chain_recursive_fast1_slow0 (bool? in; bool! out) {
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std::delay_elements::fast1_slow0_rec<REC, L> d[N];
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in = d[0].in;
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( i : N-1 : d[i].out = d[i+1].in; )
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d[N-1].out = out;
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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export template <pint N, L>
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defproc chain_reuse_1_delay_buffer (bool? in; bool! out) {
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std::delay_elements::reuse_1 r(in, out);
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chain_delay_buffer<N> d(r.dl_in, r.dl_out);
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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export template <pint N, L>
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defproc chain_reuse_2_delay_buffer (bool? in; bool! out) {
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std::delay_elements::reuse_2 r(in, out);
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chain_delay_buffer<N> d(r.dl_in, r.dl_out);
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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export template <pint N, L>
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defproc chain_reuse_1_weak_delay_buffer (bool? in; bool! out) {
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std::delay_elements::reuse_1 r(in, out);
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chain_weak_delay_buffer<N,L> d(r.dl_in, r.dl_out);
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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export template <pint N, L>
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defproc chain_reuse_2_weak_delay_buffer (bool? in; bool! out) {
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std::delay_elements::reuse_2 r(in, out);
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chain_weak_delay_buffer<N,L> d(r.dl_in, r.dl_out);
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spec {
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timing in+ : out+ < in-
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timing in- : out- < in+
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}
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}
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// Asymmetric Delay Lines ----------------------
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}
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}

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