Useful formats would be: - [ ] VHDL text file - [ ] Verilog text file - [ ] MIF (memory initialization file, Verilog) For the export, the data format (float / int / uint / sfixed ... ) should be selectable See e.g. https://www.javatpoint.com/verilog-file-operations or https://fpgacoding.com/test-bench-data-files-in-verilog/
Useful formats would be:
For the export, the data format (float / int / uint / sfixed ... ) should be selectable
See e.g. https://www.javatpoint.com/verilog-file-operations or https://fpgacoding.com/test-bench-data-files-in-verilog/