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Fixed vector size in algorithms compiled to variable vector size in implementation #1

@balasanjay

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@balasanjay

Let's say I wanted to write an algorithm specifically using simd.Uint32x8 (for cryptographic reasons, or hash-table sizing reasons (e.g. I'm storing 8 uint32 hash codes in a single vector)).

I would want that to compile to archsimd.Uint32x8 natively for platforms supporting 256-bit operations, but I would want it to also generate an implementation using a pair of archsimd.Uint32x4 values representing lo and hi elements in my logical 8-vector.

(Actually, for that matter, I may even want it to compile it into a variant that is implemented using 8 uint32s that work without any support for simd at all).

Is the intention for midway to support use-cases like that (fixed lane size but generic over underlying lane size), or is the use-case limited to code that is "generic" over the number of lanes.
I believe highway supports this via FixedTag<T, kCount> (and what is currently implemented is equivalent to ScalableTag<T>).

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