PFB Clock Recovery Block

[kurtulmehtap]

Could you add the PFB Clock Recovery Block from GNU RADIO. It contains a lot of filters which can be paralellized.

[kurtulmehtap]

https://wiki.gnuradio.org/index.php/Guided_Tutorial_PSK_Demodulation#7.6.1._Details_of_the_PFB_Clock_Recovery_Block

[awalls-cx18]

A clock recovery block is essentially a PLL which has feedback. It must execute all the functions in its main loop once (interpolating resampler filter, interpolating differentiator resampler filter, timing error detector, P-I loop filter, symbol clock phase advance) before it can start to do them again.

It really cannot be parallelized much at all.

The two resampling filters are implemented as polyphase filter banks. Although they may have many filter arms; only one filter arm of each of the 2 banks is used in any one cycle. There's probably not much to be gained by running 2 FIR filters serially vs. in parallel.

[ghostop14]

I ran into the same issue trying to convert the Costas loop. I did convert it but it runs really poorly on the GPU core (it can only use 1 to maintain the integrity of the calculations). The way the PLL loops work in the code, points need to be calculated sequentially. So SIMD parallel OpenCL processing really doesn't work. I did glance at the PFB block and it looks to use a similar feedback approach. I agree with awalls-cx18. Unfortunately I don't think we'll get the performance boost by moving it to OpenCL. I suspect it'll run about an order of magnitude slower.

One thing to try and I don't have access to the hardware is I wonder how an OpenCL-capable FPGA would time the routines. I purposely made the OpenCL code flexible enough to run on any hardware that supports OpenCL (FPGA's would show up under the Accelerator type most likely). I just don't have access to a $10K Altera card to see if the Costas Loop runs faster than the CPU on that hardware with a single OpenCL thread. Otherwise I think we're looking to FPGA's to get the acceleration on PLL's.