From d5b91d577a828c4f15575820bab34662b9f171c6 Mon Sep 17 00:00:00 2001
From: DaKnig <37626476+DaKnig@users.noreply.github.com>
Date: Sat, 20 Dec 2025 13:07:08 +0200
Subject: [PATCH 1/4] [SDAG] SetCC: remove spurious extensions

(setcc (zext a), (zext b), setu??) -> (setcc a, b, setu??)

From 13bb7beaa9468fdbe18fce2c5d9b2aafd568b6f4 Mon Sep 17 00:00:00 2001
From: DaKnig <37626476+DaKnig@users.noreply.github.com>
Date: Sat, 20 Dec 2025 12:36:13 +0200
Subject: [PATCH 2/4] lit test

---
 llvm/test/CodeGen/AArch64/arm64-vcmp.ll | 64 +++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/llvm/test/CodeGen/AArch64/arm64-vcmp.ll b/llvm/test/CodeGen/AArch64/arm64-vcmp.ll
index 1e05b452de300..aacb1f7d20e07 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vcmp.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vcmp.ll
@@ -234,3 +234,67 @@ define <1 x i64> @cmnez_d(<1 x i64> %A) nounwind {
   %mask = sext <1 x i1> %tst to <1 x i64>
   ret <1 x i64> %mask
 }
+
+; Check for the elimination of spurious type extensions
+define <16 x i1> @abdu_cmp(<16 x i8> %a, <16 x i8> %b, <16 x i8> %g) {
+; CHECK-LABEL: abdu_cmp:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uabd.16b v0, v0, v1
+; CHECK-NEXT:    ushll.8h v1, v2, #0
+; CHECK-NEXT:    ushll2.8h v2, v2, #0
+; CHECK-NEXT:    ushll2.8h v3, v0, #0
+; CHECK-NEXT:    ushll.8h v0, v0, #0
+; CHECK-NEXT:    ushll.4s v4, v1, #0
+; CHECK-NEXT:    ushll2.4s v1, v1, #0
+; CHECK-NEXT:    ushll.4s v5, v2, #0
+; CHECK-NEXT:    ushll2.4s v2, v2, #0
+; CHECK-NEXT:    ushll2.4s v6, v3, #0
+; CHECK-NEXT:    ushll.4s v7, v0, #0
+; CHECK-NEXT:    ushll2.4s v0, v0, #0
+; CHECK-NEXT:    ushll.4s v3, v3, #0
+; CHECK-NEXT:    cmhi.4s v2, v2, v6
+; CHECK-NEXT:    cmhi.4s v0, v1, v0
+; CHECK-NEXT:    cmhi.4s v1, v4, v7
+; CHECK-NEXT:    cmhi.4s v3, v5, v3
+; CHECK-NEXT:    uzp1.8h v0, v1, v0
+; CHECK-NEXT:    uzp1.8h v2, v3, v2
+; CHECK-NEXT:    uzp1.16b v0, v0, v2
+; CHECK-NEXT:    ret
+  %za = zext <16 x i8> %a to <16 x i32>
+  %zb = zext <16 x i8> %b to <16 x i32>
+  %zg = zext <16 x i8> %g to <16 x i32>
+  %mx = call <16 x i32> @llvm.umax.v16i32(<16 x i32> %za, <16 x i32> %zb)
+  %mn = call <16 x i32> @llvm.umin.v16i32(<16 x i32> %za, <16 x i32> %zb)
+  %abdu = sub <16 x i32> %mx, %mn
+  %cond = icmp ult <16 x i32> %abdu, %zg
+  ret <16 x i1> %cond
+}
+
+define <16 x i1> @sext_cmp(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: sext_cmp:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshll.8h v2, v0, #0
+; CHECK-NEXT:    sshll2.8h v0, v0, #0
+; CHECK-NEXT:    sshll2.8h v3, v1, #0
+; CHECK-NEXT:    sshll.8h v1, v1, #0
+; CHECK-NEXT:    sshll.4s v4, v2, #0
+; CHECK-NEXT:    sshll2.4s v2, v2, #0
+; CHECK-NEXT:    sshll.4s v5, v0, #0
+; CHECK-NEXT:    sshll2.4s v0, v0, #0
+; CHECK-NEXT:    sshll2.4s v6, v3, #0
+; CHECK-NEXT:    sshll.4s v7, v1, #0
+; CHECK-NEXT:    sshll2.4s v1, v1, #0
+; CHECK-NEXT:    sshll.4s v3, v3, #0
+; CHECK-NEXT:    cmgt.4s v0, v6, v0
+; CHECK-NEXT:    cmgt.4s v3, v3, v5
+; CHECK-NEXT:    cmgt.4s v1, v1, v2
+; CHECK-NEXT:    cmgt.4s v2, v7, v4
+; CHECK-NEXT:    uzp1.8h v0, v3, v0
+; CHECK-NEXT:    uzp1.8h v1, v2, v1
+; CHECK-NEXT:    uzp1.16b v0, v1, v0
+; CHECK-NEXT:    ret
+  %za = sext <16 x i8> %a to <16 x i32>
+  %zb = sext <16 x i8> %b to <16 x i32>
+  %cond = icmp slt <16 x i32> %za, %zb
+  ret <16 x i1> %cond
+}

From db7cca0ad6b38467ce5e6c69b1a35dfa4cdaa9df Mon Sep 17 00:00:00 2001
From: DaKnig <37626476+DaKnig@users.noreply.github.com>
Date: Sat, 20 Dec 2025 12:39:34 +0200
Subject: [PATCH 3/4] code

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5384713d04b33..efd5ea51b7e47 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13924,6 +13924,34 @@ SDValue DAGCombiner::visitSETCC(SDNode *N) {
       }
     }
   }
+
+  // (setcc (zext a), (zext b), setu??) -> (setcc a, b, setu??)
+  // (setcc (sext a), (sext b), sets??) -> (setcc a, b, sets??)
+  if ((ISD::isUnsignedIntSetCC(Cond) && N0.getOpcode() == ISD::ZERO_EXTEND &&
+       N1.getOpcode() == ISD::ZERO_EXTEND) ||
+      (ISD::isSignedIntSetCC(Cond) && N0.getOpcode() == ISD::SIGN_EXTEND &&
+       N1.getOpcode() == ISD::SIGN_EXTEND)) {
+    SDValue LHS = N0.getOperand(0), RHS = N1.getOperand(0);
+    EVT SmallVT =
+        LHS.getScalarValueSizeInBits() > RHS.getScalarValueSizeInBits()
+            ? LHS.getValueType()
+            : RHS.getValueType();
+    if (!LegalOperations ||
+        (SmallVT.isSimple() &&
+         TLI.isCondCodeLegal(Cond, SmallVT.getSimpleVT()))) {
+      LHS = DAG.getExtOrTrunc(ISD::isSignedIntSetCC(Cond), LHS, SDLoc(LHS),
+                              SmallVT);
+      RHS = DAG.getExtOrTrunc(ISD::isSignedIntSetCC(Cond), RHS, SDLoc(RHS),
+                              SmallVT);
+      SDValue NewSetCC =
+          DAG.getSetCC(DL, getSetCCResultType(SmallVT), LHS, RHS, Cond);
+      // Promote to a legal type for setcc, then adjust back to VT (if before
+      // LegalOperations)
+      return DAG.getZExtOrTrunc(
+          TLI.promoteTargetBoolean(DAG, NewSetCC, N0.getValueType()), DL, VT);
+    }
+  }
+
   return SDValue();
 }
 

From bb40490fb7ef1f3848655fc45c25a24e4569f119 Mon Sep 17 00:00:00 2001
From: DaKnig <37626476+DaKnig@users.noreply.github.com>
Date: Sat, 20 Dec 2025 13:45:23 +0200
Subject: [PATCH 4/4] changed  lits

---
 llvm/test/CodeGen/AArch64/arm64-vcmp.ll | 40 ++-----------------------
 1 file changed, 2 insertions(+), 38 deletions(-)

diff --git a/llvm/test/CodeGen/AArch64/arm64-vcmp.ll b/llvm/test/CodeGen/AArch64/arm64-vcmp.ll
index aacb1f7d20e07..b88df3028fc3c 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vcmp.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vcmp.ll
@@ -240,25 +240,7 @@ define <16 x i1> @abdu_cmp(<16 x i8> %a, <16 x i8> %b, <16 x i8> %g) {
 ; CHECK-LABEL: abdu_cmp:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uabd.16b v0, v0, v1
-; CHECK-NEXT:    ushll.8h v1, v2, #0
-; CHECK-NEXT:    ushll2.8h v2, v2, #0
-; CHECK-NEXT:    ushll2.8h v3, v0, #0
-; CHECK-NEXT:    ushll.8h v0, v0, #0
-; CHECK-NEXT:    ushll.4s v4, v1, #0
-; CHECK-NEXT:    ushll2.4s v1, v1, #0
-; CHECK-NEXT:    ushll.4s v5, v2, #0
-; CHECK-NEXT:    ushll2.4s v2, v2, #0
-; CHECK-NEXT:    ushll2.4s v6, v3, #0
-; CHECK-NEXT:    ushll.4s v7, v0, #0
-; CHECK-NEXT:    ushll2.4s v0, v0, #0
-; CHECK-NEXT:    ushll.4s v3, v3, #0
-; CHECK-NEXT:    cmhi.4s v2, v2, v6
-; CHECK-NEXT:    cmhi.4s v0, v1, v0
-; CHECK-NEXT:    cmhi.4s v1, v4, v7
-; CHECK-NEXT:    cmhi.4s v3, v5, v3
-; CHECK-NEXT:    uzp1.8h v0, v1, v0
-; CHECK-NEXT:    uzp1.8h v2, v3, v2
-; CHECK-NEXT:    uzp1.16b v0, v0, v2
+; CHECK-NEXT:    cmhi.16b v0, v2, v0
 ; CHECK-NEXT:    ret
   %za = zext <16 x i8> %a to <16 x i32>
   %zb = zext <16 x i8> %b to <16 x i32>
@@ -273,25 +255,7 @@ define <16 x i1> @abdu_cmp(<16 x i8> %a, <16 x i8> %b, <16 x i8> %g) {
 define <16 x i1> @sext_cmp(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: sext_cmp:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sshll.8h v2, v0, #0
-; CHECK-NEXT:    sshll2.8h v0, v0, #0
-; CHECK-NEXT:    sshll2.8h v3, v1, #0
-; CHECK-NEXT:    sshll.8h v1, v1, #0
-; CHECK-NEXT:    sshll.4s v4, v2, #0
-; CHECK-NEXT:    sshll2.4s v2, v2, #0
-; CHECK-NEXT:    sshll.4s v5, v0, #0
-; CHECK-NEXT:    sshll2.4s v0, v0, #0
-; CHECK-NEXT:    sshll2.4s v6, v3, #0
-; CHECK-NEXT:    sshll.4s v7, v1, #0
-; CHECK-NEXT:    sshll2.4s v1, v1, #0
-; CHECK-NEXT:    sshll.4s v3, v3, #0
-; CHECK-NEXT:    cmgt.4s v0, v6, v0
-; CHECK-NEXT:    cmgt.4s v3, v3, v5
-; CHECK-NEXT:    cmgt.4s v1, v1, v2
-; CHECK-NEXT:    cmgt.4s v2, v7, v4
-; CHECK-NEXT:    uzp1.8h v0, v3, v0
-; CHECK-NEXT:    uzp1.8h v1, v2, v1
-; CHECK-NEXT:    uzp1.16b v0, v1, v0
+; CHECK-NEXT:    cmgt.16b v0, v1, v0
 ; CHECK-NEXT:    ret
   %za = sext <16 x i8> %a to <16 x i32>
   %zb = sext <16 x i8> %b to <16 x i32>