Redesign

[jordens]

Now that the hardware changes have landed in recent Urukul hw_revs, we can consider redesigning the CPLD gateware and the ARTIQ coredevice layer to expose more features and expose the existing ones in a better way.

Precursor changes:

• c.f. redo CPLD wiring sinara-hw/Urukul#30 for the hardware changes
• per-channel IO_UPDATE #6 for IO_UPDATE decoupling that is not being used/exposed in the ARTIQ coredevice driver yet

Potential tasks

• Mirny-style SPI address-CS demux
• decouple channels
• implement independent profile/osk/attenuator
• DRG
• better RAM usage pattern

[newell]

Hello, I’ve been assigned to work on these items (in addition to the core device driver) and have a question:

• What is meant by "better RAM usage pattern"?

[jordens]

Means supporting more of the AD9910 feature set around RAM in an efficient way. Currently due to the channel/profile coupling it's hard to make optimal use of.

[newell]

Some asynchronous inputs are reportedly driven by combinational logic:

#11 (comment)
#11 (comment)

The current design appears to work well, with no reported issues or forum posts regarding the CS signals and one-hot implementation. Does this actually need fixing?