SystemVerilog_Coding_Practice/flipflop.sv at main · tech-learner1/SystemVerilog_Coding_Practice · GitHub

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///////////////////////////////////////////////////////////////////////////
// (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved.
//
// File name   : flipflop.sv
// Title       : Flipflop Module
// Project     : SystemVerilog Training
// Created     : 2013-4-8
// Description : Defines the Flipflop module
// Notes       :
//
///////////////////////////////////////////////////////////////////////////

module flipflop (input logic clk, reset,
                 input logic [7:0] qin,
                 output logic [7:0] qout);
timeunit 1ns;

always @(posedge clk or posedge reset)
  if (reset)
    qout = '0;
  else
    qout = qin;

endmodule