[Tools][RISCV] Implement ISA Registry & Boilerplate Generator

[copparihollmann]

Context

Integrating new RISC-V extensions (like SpacemiT vmadot) requires coordinated changes across LLVM intrinsics, IREE Attributes (IREECPUAttrs.td), Enums (IREECPUEnums.td), and unit tests. Currently, this is a manual, error-prone process involving scattered C++ and TableGen files. We need a single source of truth (a "Spec") to drive the generation of these artifacts and validat alignment between the LLVM backend and IREE compiler.

Objective

Develop a Python-based ISA Capability Registry (src/tools/isa_registry/) that parses a high-level YAML definition of a machine instruction and generates: 1) MLIR TableGen definitions, 2) MLIR Roundtrip/Lowering tests, and 3) LLVM Intrinsic verification scripts.

Scope of Work

1. Schema Definition (isa_spec_schema.yaml):
   • Define a strict schema for RISC-V extensions.
   • Fields: mnemonic, intrinsic_name, tile_shape (M,N,K), operand_types (lhs, rhs, acc), attributes (enums like signed/unsigned).
2. Artifact Generator (gen_compiler_artifacts.py):
   • Input: A YAML spec (e.g., spacemit_vmadot.yaml).
   • Output 1 (TableGen): Snippets for IREECPUEnums.td (e.g., def VMADOT_I32_4x4x4_I8 : I32EnumAttrCase...) and IREECPUAttrs.td.
   • Output 2 (Tests): Fully formed .mlir test files for:
     • roundtrip.mlir (verifies attribute parsing).
     • lower_inner_tiled.mlir (verifies buildUnderlyingOperations logic via Transform dialect).
3. Backend Validator (verify_backend.py):
   • Action: Generates a minimal .ll (LLVM IR) file calling the intrinsic defined in the Spec.
   • Check: Runs llc -march=riscv64 -mattr=+<feature> to ensure the backend actually recognizes the intrinsic (prevents "use of undefined value" errors).

Acceptance Criteria (Definition of Done)

Test 1: Spec-to-TableGen Generation

• Input: A mock spec test_vmadot.yaml defining a 4x4x4 i8->i32 instruction.
• Condition: Run gen_compiler_artifacts.py --mode=tablegen.
• Success: Output matches the expected I32EnumAttrCase definition structure found in IREECPUEnums.td.

Test 2: Automated Test Generation

• Input: The same test_vmadot.yaml.
• Condition: Run gen_compiler_artifacts.py --mode=tests.
• Success: Generates a valid .mlir file containing a func @test_roundtrip with attributes matching #iree_cpu.spacemit_vmadot_mma<...>.

Test 3: Backend Intrinsic Validation

• Input: A spec defining llvm.riscv.smt.vmadot.
• Condition: Run verify_backend.py.
• Success:
  • If llc fails (backend missing), the tool returns EXIT_FAILURE and logs "Intrinsic not found in LLVM".
  • If llc succeeds (asm generated), the tool returns EXIT_SUCCESS.

Test 4: Integration with IREE

• Condition: The generated lower_inner_tiled.mlir file is fed into iree-opt --iree-transform-dialect-interpreter.
• Success: iree-opt processes the file without crashing, proving the generated test aligns with the C++ buildUnderlyingOperations implementation.