Researcher in computer architecture and system reliability
Chair of Electronic Design Automation - Electronic System Level
Technical University of Munich (TUM)
My research focuses on improving the reliability and security of computing systems through architecture, compiler, and tooling support.
Key topics include:
- fault injection and reliability evaluation
- instruction set architectures and extensions
- compiler-assisted security and fault tolerance
- architectural simulation and virtual prototypes
- reliability of machine learning workloads (TinyML)
Here are some selected publications to which I contributed, which you can also find on GitHub:
-
Quantifying Compiler-induced Reliability Loss in Software-Implemented Hardware Fault Tolerance
ASP-DAC 2026
DOI · Code: t.b.d. -
Rapid Fault Injection Simulation by Hash-Based Differential Fault Effect Equivalence Checks
DATE 2025
DOI · Code -
Automated Graph-level Passes for TinyML Fault Tolerance
IJCNN 2025
DOI · Code: t.b.d. -
vRTLmod: An LLVM-Based Open-Source Tool to Enable Fault Injection in Verilator RTL Simulations
ACM Computing Frontiers 2023
DOI · Code -
CompaSeC: A Compiler-Assisted Security Countermeasure for Instruction Skip Fault Attacks on RISC-V
ASP-DAC 2023
DOI · Code -
Exploring the RISC-V Vector Extension for the Classic McEliece Post-Quantum Cryptosystem
ISQED 2021
DOI · Code
Google Scholar
https://scholar.google.com/citations?user=8y5ZQvUAAAAJ
ORCID
https://orcid.org/0000-0002-9439-3890
TUM Profile
https://www.ce.cit.tum.de/eda/personen/johannes-geier/
GitHub
https://github.com/JoGei
Here are some projects I currently enjoy on the side:
- Latchup - Think you're good at RTL? Prove it.
Well... I do not claim to be excellent at RTL. I tend to work on tools that generate, synthesize, and/or analyze RTL
¯\_(ツ)_/¯· Code - esel-proc - Know you're bad at RTL and let a CPU do it.]
A fun little project that synthesizes a tiny RISC-V SoC into latchup framework, allowing you to solve the RTL problems with C!
