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Expose public accessor for CycleAwareCircuit hierarchical Design

Status: Open.

#57 In LinxISA/pyCircuit;

· HLEE80 opened on May 7, 2026

compile_cycle_aware should support reset port naming/polarity customization

Status: Open.

#52 In LinxISA/pyCircuit;

· HLEE80 opened on Apr 29, 2026

[discussion] Clarify PyCircuit's abstraction boundary for RTL state logic and occurrence-based auto-alignment

enhancementNew feature or requestNew feature or request

Status: Open.

#51 In LinxISA/pyCircuit;

· mightyerwa opened on Apr 28, 2026

[bug] V5 counter example emits an unexpected extra balance register after domain.next()

bugSomething isn't workingSomething isn't working

Status: Open.

#50 In LinxISA/pyCircuit;

· mightyerwa opened on Apr 28, 2026

Performance Benchmark: Pure C++ Cycle-Accurate TLM against pyCircuit Simulator

Status: Open.

#44 In LinxISA/pyCircuit;

· winfredsu opened on Mar 24, 2026

[RFC] Testbench architecture: expressiveness vs. compilation model

Status: Open.

#42 In LinxISA/pyCircuit;

· winfredsu opened on Mar 24, 2026