Flexible, Loop-Optimized, Sparse Co-Processor for Energy-Efficient RISC-V-based Neuromorphic Systems

This repository contains the design of a flexible, loop-optimized, sparse co-processor for energy-efficient RISC-V-based neuromorphic systems. The co-processor implements an instruction set architecture and proposes two architectures to further exploit weight sparsity. The thesis explaining the ISA and the architectures of the co-processor can be found at: Thesis

This repository further contains the NEORV32 design and C code to run one VGG16 layer on the co-processor. In addition, .nasm files are provided that contain the initialization and programs to run the layers on the co-processor. The file make_app.sh contains all the required steps to generate the application and data hex files for the initialization of both instruction and data memory. The run_sim.sh, run_genus.sh and run_joules.sh files can be used to simulate and synthesize the design with Cadence tools, provided that technology and SRAM libraries are provided.