sched_mic: add sched_mic(4) manual page#387
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SCHED_MIC was added in 8856847 without a manual page, while the other schedulers ship sched_ule(4) and sched_4bsd(4). Add sched_mic(4), modeled on sched_ule(4), documenting the four hybrid core priority classes, the per-CPU class detection, and the kern.sched.* tunables (class_weight_eff, class_weight_lp, smt_busy_penalty, prefer_compute, detect_lpe, and the read-only core_class dump). Wire it into share/man/man4/Makefile and add cross-references from sched_ule(4) and sched_4bsd(4). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Reviewer's GuideAdds a new sched_mic(4) manual page documenting the hybrid-core-aware scheduler, wires it into the man4 Makefile, and updates existing scheduler man pages to cross-reference it. Flow diagram for sched_mic(4) hybrid core placement logicflowchart TD
A[Thread ready to run] --> B[Scheduler sched_mic selects CPU]
B --> C[Detect CPU core_class via CPUID or L3 size]
C --> D{Core class}
D -->|class 1 performance| E[Apply base load]
D -->|class 2 efficiency| F[Apply class_weight_eff penalty]
D -->|class 4 low power| G[Apply class_weight_lp penalty]
D -->|SMT sibling busy| H[Apply smt_busy_penalty]
F --> I[Compute effective load per CPU]
G --> I
E --> I
H --> I
I --> J{AMD hybrid CCD?}
J -->|yes & prefer_compute=0| K[Prefer 3D V-Cache CCD]
J -->|yes & prefer_compute=1| L[Prefer compute CCD]
J -->|no| M[No CCD preference]
K --> N[Choose CPU with lowest effective load]
L --> N
M --> N
N --> O[Run thread on selected CPU]
subgraph Sysctls influencing placement
F -. controlled by .-> S1[kern.sched.class_weight_eff]
G -. controlled by .-> S2[kern.sched.class_weight_lp]
H -. controlled by .-> S3[kern.sched.smt_busy_penalty]
K -. controlled by .-> S4[kern.sched.prefer_compute]
end
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Code Review
This pull request adds the man page for the new hybrid-core-aware scheduler, sched_mic.4, and updates the Makefile and other scheduler man pages with cross-references. Feedback suggests removing the reference to sched_mic in the description of sched_ule.4, as sched_mic is derived from sched_ule and inherits its features, and including it there breaks the sentence structure.
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| .Xr sched_4bsd 4 , | ||
| .Xr sched_mic 4 , |
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The sched_ule scheduler does not provide features that are missing from sched_mic. In fact, sched_mic is derived from sched_ule and inherits all of its features. Additionally, listing sched_mic here breaks the grammar of the sentence, as "the traditional system scheduler" only refers to sched_4bsd. This cross-reference should be removed from this sentence (it is already correctly placed in the SEE ALSO section).
.Xr sched_4bsd 4 ,
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Claude finished @laffer1's task —— View job Code Review for PR #387: sched_mic(4) Manual PageReviewing the merged PR for correctness, style(9) compliance, and technical accuracy. Todo List:
Review Findings:Style Compliance: ✅ PASS
Technical Accuracy: ✅ GOOD
Critical Issue: Cross-Reference Placement
Recommendation: Other Changes: ✅ GOOD
Security/Safety: ✅ N/A
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Hey - I've found 1 issue, and left some high level feedback:
- The
.Dddate insched_mic.4is set to June 11, 2026, which looks like a future/typo date relative to this change and should be updated to the actual commit date. - In the HISTORY section,
Mx 4.0is ambiguous and likely a placeholder or typo; consider replacing it with the correct OS name and release wheresched_micactually first appears.
Prompt for AI Agents
Please address the comments from this code review:
## Overall Comments
- The `.Dd` date in `sched_mic.4` is set to June 11, 2026, which looks like a future/typo date relative to this change and should be updated to the actual commit date.
- In the HISTORY section, `Mx 4.0` is ambiguous and likely a placeholder or typo; consider replacing it with the correct OS name and release where `sched_mic` actually first appears.
## Individual Comments
### Comment 1
<location path="share/man/man4/sched_mic.4" line_range="41-42" />
<code_context>
+and retains all of its behavior, adding awareness of heterogeneous
+.Pq Dq hybrid
+CPU cores on x86 systems.
+On processors that mix fast and efficient cores it weighs four core
+priority classes when placing a thread, preferring, in order:
+.Pp
+.Bl -enum -compact -offset indent
+.It
+performance cores
+.Pq Intel P-cores, AMD 3D V-Cache CCD cores ;
+.It
+efficiency cores
+.Pq Intel E-cores, AMD compute-CCD cores, AMD mobile \(dqC\(dq cores ;
+.It
+the second SMT thread of an already busy core; and
+.It
+Intel low-power
+.Pq LP-E
+cores, which are used last.
</code_context>
<issue_to_address>
**suggestion (typo):** Clarify the "four core priority classes" wording to better match the described items
The list mixes three core classes with one SMT occupancy condition. Consider rephrasing to something like “it weighs core classes and SMT occupancy when placing a thread” so the terminology aligns with what’s actually being prioritized and doesn’t imply four distinct core classes.
```suggestion
On processors that mix fast and efficient cores it weighs core classes
and SMT occupancy when placing a thread, preferring, in order:
```
</issue_to_address>Help me be more useful! Please click 👍 or 👎 on each comment and I'll use the feedback to improve your reviews.
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| On processors that mix fast and efficient cores it weighs four core | ||
| priority classes when placing a thread, preferring, in order: |
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suggestion (typo): Clarify the "four core priority classes" wording to better match the described items
The list mixes three core classes with one SMT occupancy condition. Consider rephrasing to something like “it weighs core classes and SMT occupancy when placing a thread” so the terminology aligns with what’s actually being prioritized and doesn’t imply four distinct core classes.
Suggested change
| On processors that mix fast and efficient cores it weighs four core | |
| priority classes when placing a thread, preferring, in order: | |
| On processors that mix fast and efficient cores it weighs core classes | |
| and SMT occupancy when placing a thread, preferring, in order: |
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Summary
SCHED_MICwas merged (#385) without a manual page, while the other schedulersship
sched_ule(4)andsched_4bsd(4). This addssched_mic(4).share/man/man4/sched_mic.4, modeled onsched_ule.4, documenting thefour hybrid core priority classes, per-CPU class detection (Intel P/E via
CPUID, AMD cache/compute dies via L3 size), the soft placement preference, and
the
kern.sched.*tunables:class_weight_eff,class_weight_lp,smt_busy_penalty,prefer_compute,detect_lpe, and the read-onlycore_classdump.share/man/man4/Makefile(alphabetical)..Xr sched_mic 4cross-references tosched_ule.4andsched_4bsd.4.Testing
mandoc -Tlintis clean onsched_mic.4. The only lint output for the twoexisting pages is the expected
referenced manual not found: Xr sched_mic 4STYLE note, which resolves once the new page is installed.
🤖 Generated with Claude Code
Summary by Sourcery
Add a new manual page documenting the sched_mic(4) hybrid-core-aware scheduler and integrate it with the existing scheduler manpage set.
Documentation: