Skip to content

Accumulator instructions #77

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
alqotel wants to merge 14 commits into from
Closed

Accumulator instructions #77

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
14 commits
Select commit Hold shift + click to select a range
153c0d6
target/ppc: Fix FPSCR.FI bit being cleared when it shouldn't
vcoracolombo May 17, 2022
8d0df54
target/ppc: Fix FPSCR.FI changing in float_overflow_excp()
vcoracolombo May 17, 2022
561a03d
target/ppc: Rename sfprf to sfifprf where it's also used as set fi flag
vcoracolombo May 17, 2022
1f8e116
target/ppc: Implement xxm[tf]acc and xxsetaccz
May 16, 2022
6711120
target/ppc: Implemented xvi*ger* instructions
May 16, 2022
616d136
target/ppc: Implemented pmxvi*ger* instructions
May 16, 2022
3211e42
target/ppc: Implemented xvf*ger*
May 16, 2022
4c109d1
target/ppc: Implemented xvf16ger*
May 16, 2022
a0e28a4
target/ppc: vsxger16 accumulation rth requested changes
May 18, 2022
ab883f1
target/ppc: vsxger16: adapt rth's solution give same result as mambo
May 18, 2022
c227603
target/ppc: Implemented pmxvf*ger*
May 16, 2022
9672156
target/ppc: Implemented [pm]xvbf16ger2*
May 16, 2022
67e90b3
linux-user: Add PowerPC ISA 3.1 and MMA to hwcap
shenki Apr 27, 2022
6f23817
target/ppc: Change to work on risu
May 17, 2022
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions linux-user/elfload.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -779,6 +779,8 @@ enum {
QEMU_PPC_FEATURE2_DARN = 0x00200000, /* darn random number insn */
QEMU_PPC_FEATURE2_SCV = 0x00100000, /* scv syscall */
QEMU_PPC_FEATURE2_HTM_NO_SUSPEND = 0x00080000, /* TM w/o suspended state */
QEMU_PPC_FEATURE2_ARCH_3_1 = 0x00040000, /* ISA 3.1 */
QEMU_PPC_FEATURE2_MMA = 0x00020000, /* Matrix-Multiply Assist */
};

#define ELF_HWCAP get_elf_hwcap()
Expand Down Expand Up @@ -836,6 +838,8 @@ static uint32_t get_elf_hwcap2(void)
QEMU_PPC_FEATURE2_VEC_CRYPTO);
GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 |
QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128);
GET_FEATURE2(PPC2_ISA310, QEMU_PPC_FEATURE2_ARCH_3_1 |
QEMU_PPC_FEATURE2_MMA);

#undef GET_FEATURE
#undef GET_FEATURE2
Expand Down
15 changes: 15 additions & 0 deletions target/ppc/cpu.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -227,6 +227,7 @@ typedef union _ppc_vsr_t {
int16_t s16[8];
int32_t s32[4];
int64_t s64[2];
float16 f16[8];
float32 f32[4];
float64 f64[2];
float128 f128;
Expand All @@ -238,6 +239,7 @@ typedef union _ppc_vsr_t {

typedef ppc_vsr_t ppc_avr_t;
typedef ppc_vsr_t ppc_fprp_t;
typedef ppc_vsr_t ppc_acc_t;

#if !defined(CONFIG_USER_ONLY)
/* Software TLB cache */
Expand Down Expand Up @@ -735,6 +737,8 @@ enum {
(1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
(1 << FPSCR_VXCVI))

FIELD(FPSCR, FI, FPSCR_FI, 1)

#define FP_DRN2 (1ull << FPSCR_DRN2)
#define FP_DRN1 (1ull << FPSCR_DRN1)
#define FP_DRN0 (1ull << FPSCR_DRN0)
Expand Down Expand Up @@ -2638,6 +2642,9 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx)
#define VsrSW(i) s32[i]
#define VsrD(i) u64[i]
#define VsrSD(i) s64[i]
#define VsrHF(i) f16[i]
#define VsrSF(i) f32[i]
#define VsrDF(i) f64[i]
#else
#define VsrB(i) u8[15 - (i)]
#define VsrSB(i) s8[15 - (i)]
Expand All @@ -2647,6 +2654,9 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx)
#define VsrSW(i) s32[3 - (i)]
#define VsrD(i) u64[1 - (i)]
#define VsrSD(i) s64[1 - (i)]
#define VsrHF(i) f16[7 - (i)]
#define VsrSF(i) f32[3 - (i)]
#define VsrDF(i) f64[1 - (i)]
#endif

static inline int vsr64_offset(int i, bool high)
Expand All @@ -2659,6 +2669,11 @@ static inline int vsr_full_offset(int i)
return offsetof(CPUPPCState, vsr[i].u64[0]);
}

static inline int acc_full_offset(int i)
{
return vsr_full_offset(i * 4);
}

static inline int fpr_offset(int i)
{
return vsr64_offset(i, true);
Expand Down
549 changes: 439 additions & 110 deletions target/ppc/fpu_helper.c
View file
Open in desktop

Large diffs are not rendered by default.

33 changes: 33 additions & 0 deletions target/ppc/helper.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -133,6 +133,10 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64)
#define dh_ctype_vsr ppc_vsr_t *
#define dh_typecode_vsr dh_typecode_ptr

#define dh_alias_acc ptr
#define dh_ctype_acc ppc_acc_t *
#define dh_typecode_acc dh_typecode_ptr

DEF_HELPER_3(vavgub, void, avr, avr, avr)
DEF_HELPER_3(vavguh, void, avr, avr, avr)
DEF_HELPER_3(vavguw, void, avr, avr, avr)
Expand Down Expand Up @@ -537,6 +541,35 @@ DEF_HELPER_5(XXBLENDVB, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_5(XXBLENDVH, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_5(XXBLENDVW, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_5(XXBLENDVD, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_5(XVI4GER8, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI4GER8PP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI8GER4, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI8GER4PP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI8GER4SPP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI16GER2, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI16GER2S, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI16GER2PP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI16GER2SPP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF16GER2, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF16GER2PP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF16GER2PN, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF16GER2NP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF16GER2NN, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVBF16GER2, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVBF16GER2PP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVBF16GER2PN, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVBF16GER2NP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVBF16GER2NN, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF32GER, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF32GERPP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF32GERPN, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF32GERNP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF32GERNN, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF64GER, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF64GERPP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF64GERPN, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF64GERNP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVF64GERNN, void, env, vsr, vsr, acc, i32)

DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
Expand Down
52 changes: 52 additions & 0 deletions target/ppc/insn32.decode
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -151,6 +151,9 @@
&X_vrt_frbp vrt frbp
@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp

&X_a ra
@X_a ...... ra:3 .. ..... ..... .......... . &X_a

%xx_xt 0:1 21:5
%xx_xb 1:1 11:5
%xx_xa 2:1 16:5
Expand All @@ -167,6 +170,13 @@
&XX3 xt xa xb
@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb

# 32 bit GER instructions have all mask bits considered 1
&MMIRR_XX3 xa xb xt pmsk xmsk ymsk
%xx_at 23:3
%xx_xa_pair 2:1 17:4 !function=times_2
@XX3_at ...... ... .. ..... ..... ........ ... &MMIRR_XX3 xt=%xx_at xb=%xx_xb \
pmsk=255 xmsk=15 ymsk=15

&XX3_dm xt xa xb dm
@XX3_dm ...... ..... ..... ..... . dm:2 ..... ... &XX3_dm xt=%xx_xt xa=%xx_xa xb=%xx_xb

Expand Down Expand Up @@ -710,3 +720,45 @@ XVTLSBB 111100 ... -- 00010 ..... 111011011 . - @XX2_bf_xb
&XL_s s:uint8_t
@XL_s ......-------------- s:1 .......... - &XL_s
RFEBB 010011-------------- . 0010010010 - @XL_s

## Accumulator Instructions

XXMFACC 011111 ... -- 00000 ----- 0010110001 - @X_a
XXMTACC 011111 ... -- 00001 ----- 0010110001 - @X_a
XXSETACCZ 011111 ... -- 00011 ----- 0010110001 - @X_a

## VSX GER instruction

XVI4GER8 111011 ... -- ..... ..... 00100011 ..- @XX3_at xa=%xx_xa
Copy link
Copy Markdown

@vcoracolombo vcoracolombo Apr 18, 2022

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Interesting, I didn't know this xa=%xx_xa worked here

XVI4GER8PP 111011 ... -- ..... ..... 00100010 ..- @XX3_at xa=%xx_xa
XVI8GER4 111011 ... -- ..... ..... 00000011 ..- @XX3_at xa=%xx_xa
XVI8GER4PP 111011 ... -- ..... ..... 00000010 ..- @XX3_at xa=%xx_xa
XVI16GER2 111011 ... -- ..... ..... 01001011 ..- @XX3_at xa=%xx_xa
XVI16GER2PP 111011 ... -- ..... ..... 01101011 ..- @XX3_at xa=%xx_xa
XVI8GER4SPP 111011 ... -- ..... ..... 01100011 ..- @XX3_at xa=%xx_xa
XVI16GER2S 111011 ... -- ..... ..... 00101011 ..- @XX3_at xa=%xx_xa
XVI16GER2SPP 111011 ... -- ..... ..... 00101010 ..- @XX3_at xa=%xx_xa

XVBF16GER2 111011 ... -- ..... ..... 00110011 ..- @XX3_at xa=%xx_xa
XVBF16GER2PP 111011 ... -- ..... ..... 00110010 ..- @XX3_at xa=%xx_xa
XVBF16GER2PN 111011 ... -- ..... ..... 10110010 ..- @XX3_at xa=%xx_xa
XVBF16GER2NP 111011 ... -- ..... ..... 01110010 ..- @XX3_at xa=%xx_xa
XVBF16GER2NN 111011 ... -- ..... ..... 11110010 ..- @XX3_at xa=%xx_xa

XVF16GER2 111011 ... -- ..... ..... 00010011 ..- @XX3_at xa=%xx_xa
XVF16GER2PP 111011 ... -- ..... ..... 00010010 ..- @XX3_at xa=%xx_xa
XVF16GER2PN 111011 ... -- ..... ..... 10010010 ..- @XX3_at xa=%xx_xa
XVF16GER2NP 111011 ... -- ..... ..... 01010010 ..- @XX3_at xa=%xx_xa
XVF16GER2NN 111011 ... -- ..... ..... 11010010 ..- @XX3_at xa=%xx_xa

XVF32GER 111011 ... -- ..... ..... 00011011 ..- @XX3_at xa=%xx_xa
XVF32GERPP 111011 ... -- ..... ..... 00011010 ..- @XX3_at xa=%xx_xa
XVF32GERPN 111011 ... -- ..... ..... 10011010 ..- @XX3_at xa=%xx_xa
XVF32GERNP 111011 ... -- ..... ..... 01011010 ..- @XX3_at xa=%xx_xa
XVF32GERNN 111011 ... -- ..... ..... 11011010 ..- @XX3_at xa=%xx_xa

XVF64GER 111011 ... -- .... 0 ..... 00111011 ..- @XX3_at xa=%xx_xa_pair
XVF64GERPP 111011 ... -- .... 0 ..... 00111010 ..- @XX3_at xa=%xx_xa_pair
XVF64GERPN 111011 ... -- .... 0 ..... 10111010 ..- @XX3_at xa=%xx_xa_pair
XVF64GERNP 111011 ... -- .... 0 ..... 01111010 ..- @XX3_at xa=%xx_xa_pair
XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=%xx_xa_pair
79 changes: 79 additions & 0 deletions target/ppc/insn64.decode
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,20 @@
...... ..... ..... ..... ..... .. .... \
&8RR_XX4_uim3 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc

# Format MMIRR:XX3
&MMIRR_XX3 !extern xa xb xt pmsk xmsk ymsk
%xx3_xa 2:1 16:5
%xx3_xb 1:1 11:5
%xx3_at 23:3
%xx3_xa_pair 2:1 17:4 !function=times_2
@MMIRR_XX3 ...... .. .... .. . . ........ xmsk:4 ymsk:4 \
...... ... .. ..... ..... ........ ... \
&MMIRR_XX3 xa=%xx3_xa xb=%xx3_xb xt=%xx3_at

@MMIRR_XX3_NO_P ...... .. .... .. . . ........ xmsk:4 .... \
...... ... .. ..... ..... ........ ... \
&MMIRR_XX3 xb=%xx3_xb xt=%xx3_at pmsk=1

### Fixed-Point Load Instructions

PLBZ 000001 10 0--.-- .................. \
Expand Down Expand Up @@ -115,6 +129,71 @@ PSTFS 000001 10 0--.-- .................. \
PSTFD 000001 10 0--.-- .................. \
110110 ..... ..... ................ @PLS_D

## VSX GER instruction

PMXVI4GER8 000001 11 1001 -- - - pmsk:8 ........ \
111011 ... -- ..... ..... 00100011 ..- @MMIRR_XX3
PMXVI4GER8PP 000001 11 1001 -- - - pmsk:8 ........ \
111011 ... -- ..... ..... 00100010 ..- @MMIRR_XX3
PMXVI8GER4 000001 11 1001 -- - - pmsk:4 ---- ........ \
111011 ... -- ..... ..... 00000011 ..- @MMIRR_XX3
PMXVI8GER4PP 000001 11 1001 -- - - pmsk:4 ---- ........ \
111011 ... -- ..... ..... 00000010 ..- @MMIRR_XX3
PMXVI16GER2 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 01001011 ..- @MMIRR_XX3
PMXVI16GER2PP 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 01101011 ..- @MMIRR_XX3
PMXVI8GER4SPP 000001 11 1001 -- - - pmsk:4 ---- ........ \
111011 ... -- ..... ..... 01100011 ..- @MMIRR_XX3
PMXVI16GER2S 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 00101011 ..- @MMIRR_XX3
PMXVI16GER2SPP 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 00101010 ..- @MMIRR_XX3

PMXVBF16GER2 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 00110011 ..- @MMIRR_XX3
PMXVBF16GER2PP 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 00110010 ..- @MMIRR_XX3
PMXVBF16GER2PN 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 10110010 ..- @MMIRR_XX3
PMXVBF16GER2NP 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 01110010 ..- @MMIRR_XX3
PMXVBF16GER2NN 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 11110010 ..- @MMIRR_XX3

PMXVF16GER2 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 00010011 ..- @MMIRR_XX3
PMXVF16GER2PP 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 00010010 ..- @MMIRR_XX3
PMXVF16GER2PN 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 10010010 ..- @MMIRR_XX3
PMXVF16GER2NP 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 01010010 ..- @MMIRR_XX3
PMXVF16GER2NN 000001 11 1001 -- - - pmsk:2 ------ ........ \
111011 ... -- ..... ..... 11010010 ..- @MMIRR_XX3

PMXVF32GER 000001 11 1001 -- - - -------- .... ymsk:4 \
111011 ... -- ..... ..... 00011011 ..- @MMIRR_XX3_NO_P xa=%xx3_xa
PMXVF32GERPP 000001 11 1001 -- - - -------- .... ymsk:4 \
111011 ... -- ..... ..... 00011010 ..- @MMIRR_XX3_NO_P xa=%xx3_xa
PMXVF32GERPN 000001 11 1001 -- - - -------- .... ymsk:4 \
111011 ... -- ..... ..... 10011010 ..- @MMIRR_XX3_NO_P xa=%xx3_xa
PMXVF32GERNP 000001 11 1001 -- - - -------- .... ymsk:4 \
111011 ... -- ..... ..... 01011010 ..- @MMIRR_XX3_NO_P xa=%xx3_xa
PMXVF32GERNN 000001 11 1001 -- - - -------- .... ymsk:4 \
111011 ... -- ..... ..... 11011010 ..- @MMIRR_XX3_NO_P xa=%xx3_xa

PMXVF64GER 000001 11 1001 -- - - -------- .... ymsk:2 -- \
111011 ... -- ....0 ..... 00111011 ..- @MMIRR_XX3_NO_P xa=%xx3_xa_pair
PMXVF64GERPP 000001 11 1001 -- - - -------- .... ymsk:2 -- \
111011 ... -- ....0 ..... 00111010 ..- @MMIRR_XX3_NO_P xa=%xx3_xa_pair
PMXVF64GERPN 000001 11 1001 -- - - -------- .... ymsk:2 -- \
111011 ... -- ....0 ..... 10111010 ..- @MMIRR_XX3_NO_P xa=%xx3_xa_pair
PMXVF64GERNP 000001 11 1001 -- - - -------- .... ymsk:2 -- \
111011 ... -- ....0 ..... 01111010 ..- @MMIRR_XX3_NO_P xa=%xx3_xa_pair
PMXVF64GERNN 000001 11 1001 -- - - -------- .... ymsk:2 -- \
111011 ... -- ....0 ..... 11111010 ..- @MMIRR_XX3_NO_P xa=%xx3_xa_pair

### Prefixed No-operation Instruction

@PNOP 000001 11 0000-- 000000000000000000 \
Expand Down
Loading