16-bit Arithmetic Logic Unit (ALU) Documentation

Overview

This is a 16-bit Arithmetic Logic Unit (ALU) designed in Verilog. The ALU performs various arithmetic and logical operations on two 16-bit inputs and produces a 16-bit output with a carry flag.

Architecture

The ALU is built with a modular hierarchical design consisting of four functional units:

┌─────────────────────────────────┐
│      ALU_top (Top Module)       │
├─────────────────────────────────┤
│  • Opcode decoder (4-bit)       │
│  • Output multiplexer           │
│  • Carry flag control           │
└─────────────────┬───────────────┘
    ┌───────────┬─┴──┬─────────┐
    ▼           ▼    ▼         ▼
┌─────────┐ ┌────────┐ ┌──────┐ ┌─────────┐
│Adder/   │ │Logic   │ │Shift │ │  (Res.) │
│Subtractor│ │Unit    │ │Unit  │ │         │
└─────────┘ └────────┘ └──────┘ └─────────┘

Module Descriptions

1. ALU_top (Top-Level Module)

File: ALU_top.v

The top-level module that orchestrates the operation of all functional units.

Ports:

• Input Ports:

  • [15:0] A - First operand (16-bit)
  • [15:0] B - Second operand (16-bit)
  • [3:0] opcode - Operation select code (4-bit)

• Output Ports:

  • [15:0] Y - Result (16-bit)
  • carry - Carry flag output

Functionality:

• Routes inputs to appropriate functional units based on opcode
• Selects the correct output via multiplexer logic
• Handles carry flag for arithmetic operations

---

2. Adder/Subtractor Module

File: adder_sub.v

Performs 16-bit addition and subtraction operations.

Ports:

• Inputs:

  • [15:0] A - First operand
  • [15:0] B - Second operand
  • sub - Control signal (0 = Add, 1 = Subtract)

• Outputs:

  • [15:0] Y - Result
  • carry - Carry/Borrow flag

Logic:

if sub == 0:
    Result = A + B
else:
    Result = A - B

---

3. Logic Unit Module

File: logic_unit.v

Performs bitwise logical operations on two 16-bit operands.

Ports:

• Inputs:

  • [15:0] A - First operand
  • [15:0] B - Second operand
  • [1:0] sel - Operation select (2-bit)

• Outputs:

  • [15:0] Y - Result

Operations:

sel[1:0]	Operation	Function
2'b00	AND	Y = A & B
2'b01	OR	Y = A | B
2'b10	XOR	Y = A ^ B
2'b11	NOT	Y = ~A

---

4. Shift Unit Module

File: shift_unit.v

Performs logical shift operations on a 16-bit operand.

Ports:

• Inputs:

  • [15:0] A - Operand to shift
  • dir - Direction control (0 = Left, 1 = Right)

• Outputs:

  • [15:0] Y - Shifted result

Operations:

dir	Operation	Function
1'b0	Left Shift	Y = A << 1
1'b1	Right Shift	Y = A >> 1

---

Opcode Definitions

The 4-bit opcode controls which operation is performed:

Opcode	Operation	Functional Unit	Notes
4'b0000	AND	Logic Unit	sel[1:0] = 00
4'b0001	OR	Logic Unit	sel[1:0] = 01
4'b0010	XOR	Logic Unit	sel[1:0] = 10
4'b0011	NOT	Logic Unit	sel[1:0] = 11
4'b0100	ADD	Adder/Subtractor	sub = 0, carry enabled
4'b0101	SUBTRACT	Adder/Subtractor	sub = 1, carry enabled
4'b0110	SHIFT LEFT	Shift Unit	dir = 0
4'b0111	SHIFT RIGHT	Shift Unit	dir = 1
Others	Reserved	-	Output = 0, carry = 0

---

Test Bench

File: tb_alu.v

The test bench provides comprehensive testing of the ALU functionality.

Test Cases:

1. Logic Operations (Opcode 0000-0011)

   • Test Inputs: A = 0x00F0, B = 0x0F0F
   • Tests AND, OR, XOR, NOT operations

2. Arithmetic Operations (Opcode 0100-0101)

   • Test Inputs: A = 25, B = 10
   • Tests ADD and SUBTRACT with carry flag

3. Shift Operations (Opcode 1000-1001)

   • Test Inputs: A = 0b0000_0000_0001_1111 (31 in decimal)
   • Tests LEFT SHIFT and RIGHT SHIFT

Simulation Output:

• VCD dump file: alu.vcd
• Can be viewed with GTKWave or similar waveform viewers

---

Pin Configuration Summary

16-bit ALU
┌──────────────────────────┐
│      ALU_top             │
├──────────────────────────┤
│ A[15:0]   ──────────┤   │
│ B[15:0]   ──────────┤   │
│ opcode[3:0] ─────────┤ ├─────Y[15:0]
│            │         │ ├─────carry
│ ┌─────────┴────────┐ │
│ │  ALU Logic       │ │
│ └──────────────────┘ │
└──────────────────────────┘

---

Features

✓ Modular Design - Separate functional units for easy maintenance
✓ 16-bit Width - Operates on 16-bit operands
✓ 8 Operations - AND, OR, XOR, NOT, ADD, SUB, SHL, SHR
✓ Carry Flag - Supported for arithmetic operations
✓ Combinational Logic - All operations are asynchronous
✓ Comprehensive Testing - Includes test bench with multiple test cases

---

Files Included

File	Purpose
ALU_top.v	Top-level ALU module
adder_sub.v	Adder/Subtractor functional unit
logic_unit.v	Logic operations functional unit
shift_unit.v	Shift operations functional unit
tb_alu.v	Test bench for simulation
alu.vcd	Simulation waveform output
README.md	This documentation file

---

How to Run Simulation

Using Icarus Verilog (IVerilog) and GTKWave:

# Compile
iverilog -o alu.vvp ALU_top.v adder_sub.v logic_unit.v shift_unit.v tb_alu.v

# Simulate
vvp alu.vvp

# View waveforms
gtkwave alu.vcd

---

Design Notes

• Combinational Logic: All operations are combinational (no clock required)
• Bit Width: Fixed 16-bit width for all primary operations
• Carry Handling: Carry flag is only meaningful for ADD/SUB operations
• Shift Amount: Both shift operations shift by exactly 1 bit
• Default Behavior: Unknown opcodes default to zero output

---

Future Enhancement Suggestions

• Add multi-bit shift capability (variable shift amount)
• Implement multiplication and division units
• Add status flags (zero, negative, overflow)
• Integrate sequential control for complex operations
• Optimize for lower power consumption
• Add parameterizable bit width

---

Version: 1.0
Date: January 2026
Language: Verilog