This 4-stage pipelined Multiply-and-Add module is designed with ready-valid handshaking for reliable data processing.
The module performs result = (in_a * in_b) + in_c in a pipelined manner over four stages:
- Register Inputs: Capture
in_a,in_b, andin_c. - Multiplication: Compute
in_a * in_b. - Addition: Add stored
cvalue from the previous cycle. - Output Stage: Provide the final result.
The full behaviour of the pipeline is shown here
- Log all the data in the clock edges
- Compare values expected vs calculated
- Verilator
- gtkwave

