Enhancements to the timing_report_to_verilog script

[gnersisy]

Script enhancements needed for new timer testing

Fixed issues:

• Improved timing report parsing (previously failed to parse some port names).
• Timing reports containing a pblock column are now parsed correctly.
• Some Verilog files had empty output declarations; outputs are now generated correctly.
• In some cases macro cells could not be found from internal cells; this is now resolved.
• Verilog instantiations can now be written even when cells have unconnected pins.

Other updates:

• Added a note in -help that the script does not support DFX designs.