GitHub - YSawc/uarty: Uart implementation for FPGA with veryl.

Uart implementation for FPGA.

Name		Name	Last commit message	Last commit date
Latest commit History 43 Commits
HDL		HDL
.gitignore		.gitignore
LICENCE.md		LICENCE.md
README.md		README.md
Veryl.lock		Veryl.lock
Veryl.pub		Veryl.pub
Veryl.toml		Veryl.toml

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