Interested in FPGA/ASIC design and verification, analog design, EDA and software development
- Egypt
Highlights
- Pro
Pinned Loading
-
aes-coprocessor
aes-coprocessor PublicCoprocessor Implementation of the RISC-V Scalar Cryptography Extension Using the CV-X-IF Interface
SystemVerilog 2
-
-
rich-slate
rich-slate PublicOpinionated rich text editor on top of slate (Under development)
TypeScript 5
-
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.

