v2.0.0#23
Draft
renshi-code wants to merge 109 commits into
Draft
Conversation
- Introduced Disk class for disk operations including read and write functionalities. - Added ExecuteUnit class for executing ALU and branch operations. - Created Machine class to manage the overall simulation, including CPU, Disk, and Console interactions. - Implemented Module functions for instruction decoding and ALU operations. - Established PipelineContext structure to hold transient values across pipeline stages. - Developed State class for CPU state management, including CSR handling and TLB entries. - Introduced StateControl classes for managing TLB, interrupts, and traps. - Implemented CsrFile for CSR read/write operations and state management. - Added StateControl implementation for TLB flushing, interrupt handling, and exception raising.
…copilot instructions
- Replaced the old argument parsing logic with a more structured approach using `std::expected` for better error handling. - Introduced `RuntimeOptions` struct to encapsulate command line options. - Added `TerminalModeGuard` class to manage terminal raw mode settings. - Updated usage message to reflect new command line options and improved formatting. - Enhanced numeric parsing functions to return errors instead of default values. - Refactored `apply_runtime_options` to set machine options from the parsed command line. - Improved readability and maintainability of the code by using modern C++ features. Other changes: - Updated MMIO device list initialization to use smart pointers. - Fixed type casting in ALU operations for better clarity and correctness. - Changed return types of `page_walk` functions to `bool` for clearer error handling. - Minor adjustments in memory subsystem and state control for consistency and clarity.
- Updated `run-isa-tests.sh` script to reflect new command for building ISA tests. - Modified `Machine.cpp` to allow MISA profile overrides via command-line options. - Expanded `Main.cpp` to support assembly source files with `-A/--asm` option, enabling automatic assembly and execution of RISC-V programs. - Added error handling for missing or invalid assembly files and MISA profiles. - Improved command-line parsing to ensure mutually exclusive options for memory image and assembly source.
* docs: Add RV64GC migration tracking to agent instructions - Update copilot-instructions.md with phase status and timelines - Document Phase 2 OOP Refactor as active (due April 24) - Link to tracking issues #12-17, milestones, and project board - Include branch naming conventions and performance guardrails Closes #14 * refactor(phase2-slice3): Integrate PipelineContext in Microcn::exec() Replace local r_* variables with PipelineContext struct fields in the Microcn optional I/O controller execution path. This consolidates per-instruction transient state into the structured PipelineContext, improving clarity and preparing for future stages. Changes: - Create local PipelineContext ctx in Microcn::exec() - Replace all r_ir, r_opcode, r_rd, r_rs1/2, r_funct*, r_imm fields - Replace r_rrs1/2, r_tkn, r_jmp_pc, r_wb_data, r_mem_addr, r_mem_rdata Behavior: No change - purely mechanical struct field access refactor Test: phase1-gate must pass, perf <3% regression * docs: Add Doxygen-style comments to Microcn::exec() - Add comprehensive function-level Doxygen documentation - Document pipeline stages: Fetch, Decode, Operand Fetch, Execute, Memory, Writeback, Commit - Include execution flow notes and caveats - Add inline section comments for code clarity Improves code documentation without changing behavior. --------- Co-authored-by: Lennart Trunk <trunk.l.588d@m.isct.ac.jp>
* docs: Add RV64GC migration tracking to agent instructions - Update copilot-instructions.md with phase status and timelines - Document Phase 2 OOP Refactor as active (due April 24) - Link to tracking issues #12-17, milestones, and project board - Include branch naming conventions and performance guardrails Closes #14 * refactor(phase2-slice3): Integrate PipelineContext in Microcn::exec() Replace local r_* variables with PipelineContext struct fields in the Microcn optional I/O controller execution path. This consolidates per-instruction transient state into the structured PipelineContext, improving clarity and preparing for future stages. Changes: - Create local PipelineContext ctx in Microcn::exec() - Replace all r_ir, r_opcode, r_rd, r_rs1/2, r_funct*, r_imm fields - Replace r_rrs1/2, r_tkn, r_jmp_pc, r_wb_data, r_mem_addr, r_mem_rdata Behavior: No change - purely mechanical struct field access refactor Test: phase1-gate must pass, perf <3% regression * docs: Add Doxygen-style comments to Microcn::exec() - Add comprehensive function-level Doxygen documentation - Document pipeline stages: Fetch, Decode, Operand Fetch, Execute, Memory, Writeback, Commit - Include execution flow notes and caveats - Add inline section comments for code clarity Improves code documentation without changing behavior. * refactor(phase2-slice4): Extract and enhance Microcontroller (Microcn) - Remove unused r_* member variables from Microcn class (now using PipelineContext) - Add System opcode support with proper warnings for ECALL, EBREAK, CSR operations - Add comprehensive error handling for unsupported instructions instead of silent failures - Improve error messages for compressed instruction detection Microcn enhancements: - All unsupported opcodes now log warnings with PC and instruction details - System instruction failures provide context (funct3, CSR number) - Better diagnostics for debugging I/O controller behavior Closes #14 * docs: Update agent instructions with Phase 2 Slice 4 completion - Mark Slices 1-4 as complete - Add detailed slice descriptions - Add PR #19 to tracking - Update branch pattern notes * refactor(phase2-slice4): Extract IoController to dedicated files with C++23 Major refactoring: - Extract Microcn class to new IoController.hpp/cpp with 1:1 renaming - Update to C++23 standards throughout - Use std::string_view for parameters - Use std::array<Register, 32> for register file - Initialize std::byte members with {} syntax - Add [[nodiscard]] attribute to exec() method - Improve error messages with std::fprintf - Simplify memory handling with std::memcpy Benefits: - Cleaner separation of concerns (IoController in own files) - Modern C++ idioms and standards alignment - Better code organization for future RV64 work - Improved diagnostics and error reporting Updates: - Machine.hpp: Remove Microcn definition, include IoController.hpp - Machine.cpp: Update to use IoController, remove Microcn impl - Disk.cpp/Console.cpp: Update reset function to use IoController - CMakeLists.txt: Add src/IoController.cpp to build Verification: - ✅ Build: Successful (ninja-clang-release) - ✅ Regression: PASS=2 baseline tests - ✅ No functional changes to I/O controller behavior Closes #14 --------- Co-authored-by: Lennart Trunk <trunk.l.588d@m.isct.ac.jp>
- Updated function declarations and definitions across multiple files to use trailing return types for better clarity and consistency. - Enhanced the handling of UART register decoding in MmioRouter with new functions for byte and word access. - Improved the page walk logic in MemorySubsystem to simplify fault detection. - Consolidated repetitive code in CPU stages (EX, MEM, WB) by using auto for type inference. - Added logging for unhandled MMIO operations in MmioRouter. - Cleaned up the instruction decoding logic in Module to enhance maintainability.
- Improved code readability by adding missing braces for single-line if statements across various stages (e.g., StageCommit, StageEX, StageIF). - Standardized the use of `0u` and `0U` for unsigned integer literals for consistency. - Changed variable declarations to use `const` where applicable to enhance code safety and clarity. - Updated function signatures to use `const` where methods do not modify class state (e.g., `get_mstatus`, `read_csr`). - Enhanced memory access logic in `MemorySubsystem` to ensure better handling of page faults and address translation. - Cleaned up the handling of pending exceptions and interrupts in the commit and execution stages. - Improved the handling of floating-point operations and memory accesses in the memory stage. - Ensured consistent formatting and spacing throughout the code for better maintainability.
- Introduced `VirtioUtil.hpp` with utility functions for Virtio MMIO device queue operations, including byte/word conversions and memory operations. - Refactored `Console.cpp` and `Disk.cpp` to utilize the new utility functions, removing redundant code. - Updated `XLen.hpp` to change `PrivilegeLevel` from `Word` to `uint8_t` for better memory efficiency. - Enhanced `build-linux-image.sh` script formatting for improved readability. - Modified `Machine.cpp` to improve image loading error handling and ensure proper memory allocation. - Updated various source files to replace direct array indexing with `.at()` for safer access. - Adjusted exception handling to use `~Word(0)` instead of `~0U` for consistency across the codebase. Co-authored-by: Copilot <copilot@github.com>
Co-authored-by: Copilot <copilot@github.com>
- Added Mmu.cpp for the implementation of the Memory Management Unit (MMU) supporting SV32 virtual memory translation. - Implemented address translation, page table walking, and permission validation in the MMU. - Introduced TileLinkBus.cpp to handle TileLink-style bus communication, including request handling and response management. - Removed outdated commit and execution stages (StageCommit.cpp, StageEX.cpp, StageID.cpp, StageIF.cpp, StageMEM.cpp, StageWB.cpp) to streamline the pipeline architecture. - Added trace_symbols.txt for debugging and tracing purposes.
…lege execution bugs
…ve layout thresholds, and floating-point register page navigation.
…nt RISC-V doubleword atomic instructions, and add cache-aware SBI fence handlers.
…n to v2.0.0-beta.9
…ion explainer and bump version to v2.0.0-beta.10
…cache statistics tracking
…vmaxu Fix incorrect funct6/funct3 decoder values for vector integer arithmetic: - vdiv/vdivu: were using OPIVV (funct3=0/4), now correctly OPMVV/OPMVX (funct3=2/6) with proper funct6 values (0x21/0x20) - vmul: was using wrong funct3 (OPIVV); now correctly OPMVV/OPMVX (funct3=2/6) - vsll: was funct6=0x2D, now correct 0x25 (shares case with vmul, distinguished by funct3) - vsra: was funct6=0x2C, now correct 0x29 Add missing vector min/max instructions: - Add VMIN_VV/VX, VMINU_VV/VX, VMAX_VV/VX, VMAXU_VV/VX to OperationId - Add decoder cases for funct6=0x04-0x07 (vminu/vmin/vmaxu/vmax) - Implement signed/unsigned min/max lambdas in ExecuteUnitVector - Extend vector op range check in execute_core to include new ops Map Custom0 opcode (0x0B) to VCHECK NOP for vector test harness compatibility. All 141 vector ISA tests pass (408/408 gate suite clean).
Track vector instructions (VSETVLI..VMAXU_VX) as a separate VEC category in the instruction mix counter. Expand the category LUT from 256 to 512 entries so vector op indices (206-279) are covered. The Inst Mix line now shows: ALU / MEM / CTRL / SYS / VEC percentages.
- Change VEC color from kSakuraVal (lavender) to kSakuraCoral (coral) so it's visually distinct from MEM (kSakuraSky/blue) - Suppress zero-percentage categories from inst mix line (<0.05%) so SYS/VEC don't clutter the display when they're unused - ICache stat row now shows 'bypassed (high-perf mode)' instead of misleading 0/0 stats when s_high_performance=true, since that path reads directly from mmem[] without touching the cache structures
…bump to 2.0.0-beta.15
…ster formatting in TUI
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
No description provided.