Clock Management Unit (CMU)

A comprehensive clock management IP core with multiple clock divider types, clock gating, and glitch-free multiplexing capabilities.

Features

• Multiple Clock Divider Types

  • Even Divider: Guaranteed 50% duty cycle for even division ratios
  • Odd Divider: 50% duty cycle for odd division ratios using dual-edge technique
  • Fractional Divider: Precise fractional frequency division using Sigma-Delta
  • Preset Divider: Common frequencies with adjustable duty cycle

• Power Management

  • Individual clock gating for each channel
  • Clock gating placed before dividers for maximum power saving

• Glitch-Free Clock Switching

  • Dynamic clock source selection without glitches
  • Handshake protocol ensures safe switching

• Industry-Standard Interface

  • APB (Advanced Peripheral Bus) slave interface
  • Software-configurable parameters

Architecture

                     CMU Top Module
                           |
        +---------+--------+--------+---------+
        |         |        |        |         |
    [Gate0]   [Gate1]  [Gate2]  [Gate3]    [APB]
        |         |        |        |         |
    [Even]    [Odd]    [Frac]   [Preset]     |
     Div       Div      Div       Div        |
        |         |        |        |         |
    clk_out[0-3] -----> [Glitch-Free Mux] ---+
                              |
                        clk_dynamic

See ARCHITECTURE.md for detailed design information.

Quick Start

Prerequisites

• ModelSim or QuestaSim (for simulation)
• Quartus Prime or Vivado (for synthesis)

Running Simulation

Windows:

cd sim
run_modelsim.bat

Linux:

cd sim
chmod +x run_modelsim.sh
./run_modelsim.sh

Register Map

See REGISTER_MAP.md for complete register definitions.

Offset	Name	Description
0x00	CMU_CTRL	Global control
0x10	CH0_CFG	Channel 0 configuration
0x20	CH1_CFG	Channel 1 configuration
0x30	CH2_CFG	Channel 2 configuration
0x40	CH3_PRESET	Channel 3 preset selection
0x60	DYNAMIC_CFG	Dynamic output configuration

Key Technical Highlights

1. Odd Divider with 50% Duty Cycle

The odd divider achieves true 50% duty cycle using a dual-edge technique with AND logic:

// Use AND instead of OR for 50% duty cycle
assign clk_out = clkp_div & clkn_div;

Why AND instead of OR?

• Posedge and negedge clocks have 0.5T phase difference
• AND keeps only the overlapping region → 50% duty cycle
• OR would create nearly 100% duty cycle

2. Clock Gating Before Dividers

clk_50m → [Gating] → [Divider] → clk_out
          ↑
       enable

Power savings: Divider logic completely stops when gated.

3. Glitch-Free Multiplexer

Uses handshake protocol to ensure safe clock switching:

1. Synchronize select signal on posedge
2. Update gate signals on negedge
3. Ensure mutual exclusion of gate signals

Verification Results

All tests passed:

• ✓ APB protocol compliance
• ✓ Even divider: 12.5 MHz (div=4), 6.25 MHz (div=8)
• ✓ Odd divider: 10 MHz (div=5), 7.14 MHz (div=7)
• ✓ Fractional divider: 8 MHz (div=6.25)
• ✓ Clock gating functionality
• ✓ Glitch-free switching verified

File Structure

rtl/                  # RTL source files
  ├── cmu_top.v              # Top module
  ├── apb_slave_regs.v       # APB interface
  ├── clock_dividers/        # Divider modules
  └── clock_utils/           # Utility modules

tb/                   # Testbench
  └── tb_cmu_top.sv          # SystemVerilog testbench

docs/                 # Documentation
  ├── ARCHITECTURE.md        # Detailed architecture
  ├── REGISTER_MAP.md        # Register definitions
  └── DESIGN_SPEC.md         # Design specification

Design Rationale

Why Different Divider Types?

Each divider serves different purposes:

• Even Divider: General-purpose, guaranteed 50% duty cycle
• Odd Divider: Timing-critical applications requiring 50% duty with odd ratios
• Fractional Divider: Precise frequency control (e.g., 6.25x, 8.5x)
• Preset Divider: Common protocols (UART, SPI) with flexible duty cycle

The variety demonstrates understanding of different application requirements.

License

This project is licensed under the MIT License - see the LICENSE file for details.

Author

Created as a demonstration of digital IC design skills, focusing on:

• Clock domain management
• Low-power design techniques
• Industry-standard interfaces
• Comprehensive verification methodology

Acknowledgments

• Odd divider technique inspired by CSDN community discussions
• APB protocol based on ARM AMBA specification

Contact

For questions or collaboration opportunities, please open an issue on GitHub.

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Note: This is a portfolio project demonstrating IC design capabilities. Suitable for educational purposes and as a reference for clock management IP design.