Digital CMOS IC Design and Simulation Using Electric VLSI Tool ⚡

📖 Overview

This repository presents the design, layout implementation, and simulation of fundamental CMOS digital integrated circuits using the Electric VLSI EDA Tool and LTspice. It serves as a practical learning resource for understanding CMOS logic design, VLSI layout development, SPICE simulation, and digital IC verification techniques. The project covers the complete workflow of CMOS digital circuit design, including schematic creation and stick/layout design to netlist extraction and transient waveform analysis.

🚀 Tools Used

• Electric VLSI EDA Tool (electricBinaryFull-9.08)
• Eclipse Temurin
• LTspice

🔧 CMOS Digital Circuit Projects

• CMOS Inverter
• NAND Gate
• AND Gate
• NOR Gate
• OR Gate
• XOR Gate
• Half Adder

Each project may include:

• Schematic designs
• IC layouts
• SPICE netlists
• Simulation files
• Waveform outputs

🔗 Circuit Layouts & Netlists

CMOS NAND Gate

Fig. 1 CMOS NAND gate schematic and layout

• Transient Analysis
  In LTspice, open the generated netlist (nand-gate/nand.spi) and plot the following traces:
  
  • V(a) upper pane
    
  • V(b) mid pane
  • V(NAND_Out) lower pane

    vdd vdd 0 dc 5
    va A 0 pulse(0 5 0 1n 1n 10n 20n)
    vb B 0 pulse(0 5 0 1n 1n 10n 20n)
    .tran 1n 100n
    .include "C:\C5_models.txt"
  

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CMOS AND Gate

Fig. 2 CMOS AND gate schematic and layout

• Transient Analysis
  In LTspice, open the generated netlist (and-gate/and.spi) and plot the following traces:
  
  • V(a) upper pane
    
  • V(b) mid pane
  • V(AND_Out) lower pane

    vdd vdd 0 dc 5
    va A 0 pulse(0 5 0 1n 1n 10n 20n)
    vb B 0 pulse(0 5 0 1n 1n 10n 40n)
    .tran 1n 100n
    .include "C:\C5_models.txt"
  

  Note: Before running the SPICE simulation, all SPICE code in the CMOS inverter and CMOS NAND Gate schematic and layout should be removed.

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NOR Gate

Fig. 3 NOR gate schematic and layout

• Transient Analysis
  In LTspice, open the generated netlist (nor-gate/nor.spi) and plot the following traces:
  
  • V(a) upper pane
    
  • V(b) mid pane
  • V(NOR_Out) lower pane

    vdd vdd 0 dc 5
    va A 0 pulse(0 5 0 1n 1n 2u 4u)
    vb B 0 pulse(0 5 0 1n 1n 1u 2u)
    .tran 1n 10u
    .include "C:\C5_models.txt"
  

---

OR Gate

Fig. 4 OR gate schematic and layout

• Transient Analysis
  In LTspice, open the generated netlist (or-gate/or.spi) and plot the following traces:
  
  • V(a) upper pane
    
  • V(b) mid pane
  • V(OR_Out) lower pane

    vdd vdd 0 dc 5
    va A 0 pulse(0 5 0 1n 1n 2u 4u)
    vb B 0 pulse(0 5 0 1n 1n 1u 2u)
    .tran 1n 10u
    .include "C:\C5_models.txt"
  

  Note: Before running the SPICE simulation, all SPICE code in the CMOS inverter and NOR Gate schematic and layout should be removed.

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XOR Gate

Fig. 5 XOR gate schematic and layout

• Transient Analysis
  In LTspice, open the generated netlist (xor-gate/xor.spi) and plot the following traces:
  
  • V(a) upper pane
    
  • V(b) mid pane
  • V(XOR_Out) lower pane

    vdd vdd 0 dc 5
    va A 0 pulse(0 5 0 1n 1n 2u 4u)
    vb B 0 pulse(0 5 0 1n 1n 1u 2u)
    .tran 1n 10u
    .include "C:\C5_models.txt"
  

  Note: Before running the SPICE simulation, all SPICE code in the OR, NAND, and AND Gates schematic and layout should be removed.

---

Half Adder

Fig. 6 Half Adder schematic and layout

• Transient Analysis
  In LTspice, open the generated netlist (half-adder/half-adder.spi) and plot the following traces:
  
  • V(a) upper pane
    
  • V(b) mid pane
  • V(Sum) and V(Carry) lower panes

    vdd vdd 0 dc 5
    va A 0 pulse(0 5 0 1n 1n 2u 4u)
    vb B 0 pulse(0 5 0 1n 1n 1u 2u)
    .tran 1n 10u
    .include "C:\C5_models.txt"
  

  Note: Before running the SPICE simulation, all SPICE code in the XOR and AND Gates schematic and layout should be removed.