add: integrate tacit-driver submodule

.gitignore

@@ -10,3 +10,4 @@ boards/default/distros/ubuntu/rootfs.img*
 *#
 .conda-env
 .conda-lock-env
+.vscode

.gitmodules

@@ -16,3 +16,6 @@
 [submodule "boards/firechip/drivers/iceblk-driver"]
 	path = boards/firechip/drivers/iceblk-driver
 	url = https://github.com/firesim/iceblk-driver.git
+[submodule "boards/firechip/drivers/tacit-driver"]
+	path = boards/firechip/drivers/tacit-driver
+	url = https://github.com/riscv-tacit/tacit_driver.git

boards/firechip/base-workloads/br-base.json

@@ -12,7 +12,8 @@
       "config" : "linux-config",
       "modules" : {
           "icenet" : "../../drivers/icenet-driver",
-          "iceblk" : "../../drivers/iceblk-driver"
+          "iceblk" : "../../drivers/iceblk-driver",
+          "tacit" : "../../drivers/tacit-driver"
       }
   },
   "firmware" : {

boards/firechip/base-workloads/br-base/linux-config

@@ -64,4 +64,5 @@ CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
 # CONFIG_RISCV_PMU is not set
 CONFIG_OVERRIDE_RNG_ENTROPY=y
 CONFIG_OVERRIDE_RNG_ENTROPY_VALUE=256
-
+CONFIG_JUMP_LABEL_PATCH_LOG_SNAPSHOT=y
+CONFIG_TRACEPOINTS=y

example-workloads/bare-hello.json

@@ -0,0 +1,7 @@
+{
+  "name" : "bare-hello",
+  "base" : "bare-base.json",
+  "host-init" : "build.sh",
+  "bin" : "trace-hello.elf",
+  "spike-args" : "--extlib libspikedevices.so --device=trace_encoder_ctrl --trace l "
+}

example-workloads/bare-hello/Makefile

@@ -0,0 +1,19 @@
+CC = riscv64-unknown-elf-gcc
+DUMP = riscv64-unknown-elf-objdump
+CFLAGS = -fno-common -fno-builtin-printf -specs=htif_nano.specs -std=gnu99 -O2 -ffast-math -funroll-loops -I. -mcmodel=medany -g
+LD_FLAGS = -ffast-math -static -specs=htif_nano.specs
+
+DEPS := tacit.h rocketcore.h riscv.h mmio.h metal.h
+
+trace-hello.elf: trace-hello.c $(DEPS)
+	${CC} ${CFLAGS} -c trace-hello.c
+	${CC} ${LD_FLAGS} trace-hello.o -o trace-hello.elf
+
+dump: trace-hello.elf
+	${DUMP} -d trace-hello.elf > trace-hello.dump
+
+dump-symbols: trace-hello.elf
+	${DUMP} -t trace-hello.elf > trace-hello.symbols
+
+clean:
+	rm -f trace-hello.elf trace-hello.o

example-workloads/bare-hello/build.sh

@@ -0,0 +1,3 @@
+#!/bin/bash
+
+make trace-hello.elf

example-workloads/bare-hello/metal.h

@@ -0,0 +1,60 @@
+/**
+ * @file metal.h
+ * @brief Baremetal programming helpers
+ *
+ * This file provides some common definitions for baremetal programming.
+ * It includes memory register attributes, bit operation definitions,
+ * and common enumerations for state and status values that is used by
+ * the Hardware Abstraction Layer (HAL) library.
+ * 
+ */
+
+ #ifndef __METAL_H
+ #define __METAL_H
+
+ #include <stdint.h>
+ #include <stddef.h>
+
+ /* ================ Memory register attributes ================ */
+ #ifdef __cplusplus
+   #define   __I     volatile             /** Defines "read only" permissions */
+ #else
+   #define   __I     volatile const       /** Defines "read only" permissions */
+ #endif
+ #define     __O     volatile             /** Defines "write only" permissions */
+ #define     __IO    volatile             /** Defines "read / write" permissions */
+
+ /* following defines should be used for structure members */
+ #define     __IM     volatile const      /** Defines "read only" structure member permissions */
+ #define     __OM     volatile            /** Defines "write only" structure member permissions */
+ #define     __IOM    volatile            /** Defines "read / write" structure member permissions */
+
+
+ /* ================ Bit Operation definitions ================ */
+ #define SET_BITS(REG, BIT)                    ((REG) |= (BIT))
+ #define CLEAR_BITS(REG, BIT)                  ((REG) &= ~(BIT))
+ #define READ_BITS(REG, BIT)                   ((REG) & (BIT))
+ #define WRITE_BITS(REG, CLEARMASK, SETMASK)   ((REG) = (((REG) & (~(CLEARMASK))) | (SETMASK)))
+
+
+ /* ================ Common definitions ================ */
+ typedef enum {
+   RESET = 0UL,
+   SET   = !RESET,
+
+   DISABLE = RESET,
+   ENABLE  = SET,
+
+   LOW   = RESET,
+   HIGH  = SET,
+ } State;
+
+ typedef enum {
+   OK = 0U,
+   ERROR,
+   BUSY,
+   TIMEOUT
+ } Status;
+
+ #endif  /* __METAL_H */
+

example-workloads/bare-hello/mmio.h

@@ -0,0 +1,54 @@
+#ifndef __MMIO_H__
+#define __MMIO_H__
+
+#include <stdint.h>
+
+static inline void reg_write8(uintptr_t addr, uint8_t data)
+{
+	volatile uint8_t *ptr = (volatile uint8_t *) addr;
+	*ptr = data;
+}
+
+static inline uint8_t reg_read8(uintptr_t addr)
+{
+	volatile uint8_t *ptr = (volatile uint8_t *) addr;
+	return *ptr;
+}
+
+static inline void reg_write16(uintptr_t addr, uint16_t data)
+{
+	volatile uint16_t *ptr = (volatile uint16_t *) addr;
+	*ptr = data;
+}
+
+static inline uint16_t reg_read16(uintptr_t addr)
+{
+	volatile uint16_t *ptr = (volatile uint16_t *) addr;
+	return *ptr;
+}
+
+static inline void reg_write32(uintptr_t addr, uint32_t data)
+{
+	volatile uint32_t *ptr = (volatile uint32_t *) addr;
+	*ptr = data;
+}
+
+static inline uint32_t reg_read32(uintptr_t addr)
+{
+	volatile uint32_t *ptr = (volatile uint32_t *) addr;
+	return *ptr;
+}
+
+static inline void reg_write64(unsigned long addr, uint64_t data)
+{
+	volatile uint64_t *ptr = (volatile uint64_t *) addr;
+	*ptr = data;
+}
+
+static inline uint64_t reg_read64(unsigned long addr)
+{
+	volatile uint64_t *ptr = (volatile uint64_t *) addr;
+	return *ptr;
+}
+
+#endif

example-workloads/bare-hello/riscv.h

@@ -0,0 +1,70 @@
+/**
+ * @file rv_common.h
+ * @brief RISC-V Definitions
+ * 
+ * This header file provides common definitions and operations for RISC-V core programming.
+ * It includes memory register attributes, bit operation definitions, RISC-V specific definitions,
+ * and common enumerations for state and status values.
+ *
+ * The memory register attributes define volatile permissions for read-only, write-only, and read/write access.
+ * The bit operation definitions provide macros for setting, clearing, reading, and writing specific bits in a register.
+ * The RISC-V specific definitions include macros for reading and writing control and status registers (CSRs),
+ * as well as operations to swap, set, and clear specific bits in a CSR.
+ * The common definitions include enumerations for state values (such as RESET and SET), and status values (such as OK and ERROR).
+ *
+ * @note This file should be included to access RISC-V core-specific definitions and perform common operations.
+ *
+ * @author -T.K.-
+ * @date 2023-05-20
+ */
+
+ #ifndef __RV_H
+ #define __RV_H
+
+ #ifdef __riscv_xlen
+   #define RISCV_XLEN __riscv_xlen
+ #else
+   #warning "__riscv_xlen not defined, defaulting to 64"
+   #define RISCV_XLEN 64
+ #endif
+
+ #if RISCV_XLEN == 64
+   #define LREG ld
+   #define SREG sd
+   #define REGBYTES 8
+ #elif RISCV_XLEN == 32
+   #define LREG lw
+   #define SREG sw
+   #define REGBYTES 4
+ #else
+   #error "Unsupported RISCV_XLEN"
+ #endif
+
+
+ /* ================ RISC-V specific definitions ================ */
+ #define READ_CSR(REG) ({                          \
+   unsigned long __tmp;                            \
+   asm volatile ("csrr %0, " REG : "=r"(__tmp));  \
+   __tmp; })
+
+ #define WRITE_CSR(REG, VAL) ({                    \
+   asm volatile ("csrw " REG ", %0" :: "rK"(VAL)); })
+
+ #define SWAP_CSR(REG, VAL) ({                     \
+   unsigned long __tmp;                            \
+   asm volatile ("csrrw %0, " REG ", %1" : "=r"(__tmp) : "rK"(VAL)); \
+   __tmp; })
+
+ #define SET_CSR_BITS(REG, BIT) ({                 \
+   unsigned long __tmp;                            \
+   asm volatile ("csrrs %0, " REG ", %1" : "=r"(__tmp) : "rK"(BIT)); \
+   __tmp; })
+
+ #define CLEAR_CSR_BITS(REG, BIT) ({               \
+   unsigned long __tmp;                            \
+   asm volatile ("csrrc %0, " REG ", %1" : "=r"(__tmp) : "rK"(BIT)); \
+   __tmp; })
+
+
+ #endif /* __RV_H */
+

example-workloads/bare-hello/rocketcore.h

@@ -0,0 +1,118 @@
+/**
+ * @file rocketcore.h
+ * @author -T.K.- / t_k_233@outlook.com
+ * @brief 
+ * @version 0.1
+ * 
+ * @copyright Copyright (c) 2023
+ * 
+ */
+
+ #ifndef __ROCKETCORE_H
+ #define __ROCKETCORE_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include <stdint.h>
+ #include <stddef.h>
+
+ #include "riscv.h"
+
+
+ /* Core CSR Bit Field Definition */
+ #define MIE_USIE_POS                  0x00U
+ #define MIE_USIE_MSK                  (1U << MIE_USIE_POS)
+ #define MIE_SSIE_POS                  0x01U
+ #define MIE_SSIE_MSK                  (1U << MIE_SSIE_POS)
+ #define MIE_VSSIE_POS                 0x02U
+ #define MIE_VSSIE_MSK                 (1U << MIE_VSSIE_POS)
+ #define MIE_MSIE_POS                  0x03U
+ #define MIE_MSIE_MSK                  (1U << MIE_MSIE_POS)
+ #define MIE_UTIE_POS                  0x04U
+ #define MIE_UTIE_MSK                  (1U << MIE_UTIE_POS)
+ #define MIE_STIE_POS                  0x05U
+ #define MIE_STIE_MSK                  (1U << MIE_STIE_POS)
+ #define MIE_VSTIE_POS                 0x06U
+ #define MIE_VSTIE_MSK                 (1U << MIE_VSTIE_POS)
+ #define MIE_MTIE_POS                  0x07U
+ #define MIE_MTIE_MSK                  (1U << MIE_MTIE_POS)
+ #define MIE_UEIE_POS                  0x08U
+ #define MIE_UEIE_MSK                  (1U << MIE_UEIE_POS)
+ #define MIE_SEIE_POS                  0x09U
+ #define MIE_SEIE_MSK                  (1U << MIE_SEIE_POS)
+ #define MIE_VSEIE_POS                 0x0AU
+ #define MIE_VSEIE_MSK                 (1U << MIE_VSEIE_POS)
+ #define MIE_MEIE_POS                  0x0BU
+ #define MIE_MEIE_MSK                  (1U << MIE_MEIE_POS)
+ #define MIE_SGEIE_POS                 0x0CU
+ #define MIE_SGEIE_MSK                 (1U << MIE_SGEIE_POS)
+
+ #define MIE_USIP_POS                  0x00U
+ #define MIE_USIP_MSK                  (1U << MIE_USIP_POS)
+ #define MIP_SSIP_POS                  0x01U
+ #define MIP_SSIP_MSK                  (1U << MIP_SSIP_POS)
+ #define MIP_VSSIP_POS                 0x02U
+ #define MIP_VSSIP_MSK                 (1U << MIP_VSSIP_POS)
+ #define MIP_MSIP_POS                  0x03U
+ #define MIP_MSIP_MSK                  (1U << MIP_MSIP_POS)
+ #define MIE_UTIP_POS                  0x04U
+ #define MIE_UTIP_MSK                  (1U << MIE_UTIP_POS)
+ #define MIP_STIP_POS                  0x05U
+ #define MIP_STIP_MSK                  (1U << MIP_STIP_POS)
+ #define MIP_VSTIP_POS                 0x06U
+ #define MIP_VSTIP_MSK                 (1U << MIP_VSTIP_POS)
+ #define MIP_MTIP_POS                  0x07U
+ #define MIP_MTIP_MSK                  (1U << MIP_MTIP_POS)
+ #define MIP_SEIP_POS                  0x09U
+ #define MIP_SEIP_MSK                  (1U << MIP_SEIP_POS)
+ #define MIP_VSEIP_POS                 0x0AU
+ #define MIP_VSEIP_MSK                 (1U << MIP_VSEIP_POS)
+ #define MIP_MEIP_POS                  0x0BU
+ #define MIP_MEIP_MSK                  (1U << MIP_MEIP_POS)
+ #define MIP_SGEIP_POS                 0x0CU
+ #define MIP_SGEIP_MSK                 (1U << MIP_SGEIP_POS)
+
+ static inline size_t get_hart_id() {
+   return READ_CSR("mhartid");
+ }
+
+ static inline uint64_t get_cycles() {
+   return READ_CSR("mcycle");
+ }
+
+ static inline void disable_global_interrupt() {
+   CLEAR_CSR_BITS("mstatus", 1U << 3U);
+ }
+
+ static inline void enable_global_interrupt() {
+   SET_CSR_BITS("mstatus", 1U << 3U);
+ }
+
+ static inline void disable_timer_interrupt() {
+   CLEAR_CSR_BITS("mie", 1U << 7U);
+ }
+
+ static inline void enable_timer_interrupt() {
+   SET_CSR_BITS("mie", 1U << 7U);
+ }
+
+ static inline void disable_irq(uint32_t IRQn) {
+   CLEAR_CSR_BITS("mie", 1U << IRQn);
+ }
+
+ static inline void enable_irq(uint32_t IRQn) {
+   SET_CSR_BITS("mie", 1U << IRQn);
+ }
+
+ static inline void clear_irq(uint32_t IRQn) {
+   CLEAR_CSR_BITS("mip", 1U << IRQn);
+ }
+
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+ #endif /* __ROCKETCORE_H */