v1.10.0

v1.10.0 (2025-01-19)

Bug Fixes

• Divide by zero in make_hdiag() when system has no losses (1036877)

Documentation

• Correct make_diag() docstring (f947070)

Features

• Add plane_res() function to utils package (a7ffd49)

Refactoring

• Add pytest package to test_utils.py (65159e9)

• Change dtype in _prep_loss() (7c8a463)

---

Detailed Changes: v1.9.0...v1.10.0

v1.9.0

v1.9.0 (2024-12-30)

Documentation

• Add heat diagram to "Power tree diagrams" tutorial, set default font to Arial and default component color to light gray (9792759)

• Add PCB trace resistance to PCIe FPGA tutorial (8c505dc)

• Include highlights only in rtd changelog (7421be3)

Features

• Add heat diagram function, make_hdiag(), to diagram package (2e4a563)

• Add utils package with trace_REs() function (c1606ad)

Refactoring

• Remove unused package (04d1e61)

---

Detailed Changes: v1.8.1...v1.9.0

v1.8.1

v1.8.1 (2024-12-27)

Build System

• Add pytest-codspeed to dev dependencies (eb14c66)

Continuous Integration

• Add Codspeed benchmarking (9914d8a)

• Add CodSpeed dependencies (1b1d522)

• Add matplotlib to CodSpeed (9045184)

• Add missing dependencies for CodSpeed (26e449b)

• Add pydot to CodSpeed deps (52eb41d)

• Add tqdm to CodSpeed deps. (c681974)

Documentation

• Add changelog to documentation (1836349)

Performance Improvements

• Add benchmark tests (0ba69e6)

---

Detailed Changes: v1.8.0...v1.8.1

v1.8.0

v1.8.0 (2024-12-21)

Documentation

• Add Rectifier to component parameter files tutorial (73f2be9)

• New tutorial: power over ethernet analysis (cce4a1f)

Features

• New component PMux (Power Multiplexer) (ad3079f)

• New component Rectifier - diode and MOSFET modes (2e4ea83)

• Source component can now have load phases defined (653321d)

Refactoring

• Add check for component interpolation data format (b5575f7)

• Change to generic .from_file() method in Component class (ad4b91d)

---

Detailed Changes: v1.7.0...v1.8.0

v1.7.0

v1.7.0 (2024-11-10)

Bug Fixes

• Add loss parameter reading to System.from_file()
  (94b419a)

Continuous Integration

• Use "apt_packages" to install graphviz for rtd
  (41168e0)

• Remove sudo from readthedocs .yml
  (2e17b54)

Documentation

• Update readme.md with make_diag()
  (13c3923)

Features

• Add group parameter to make_diag() function
  (1d8f9e4)

• Add .rail_rep() method to System (voltage rail report)
  (92ec728)

• Allow power rail name as parent parameter in add_comp(), change_comp()
  (6019576)

• Add the option to add voltage rail names in System
  (a956ecb)

• Add "loss" parameter to all loads, optionally configuring power as a loss
  (8168a26)

Refactoring

• Create generic _solv_get_warns() method in Component class
  (4e2e8cc)

• Add check of limit values format
  (3136295)

v1.6.0

v1.6.0 (2024-10-31)

Bug Fixes

• fix: when saving system to .json, only include applicable limits for each component (fd5dea7)

Continuous Integration

• ci: add sudo to graphviz install (20185f6)

• ci: fix Graphviz install (a46675b)

• ci: install Graphviz in ci step (eb026a2)

• ci: add graphviz to rtd config (8fb1728)

• ci: remove grayscull steps (553c2ed)

Documentation

• docs: update LinReg ground current parameter name in PCIe tutorial (b9da44b)

Features

• feat: add group parameter in System, allowing grouping of components (83d9965)

• feat: add graphical power tree diagrams module (e3bb445)

Refactoring

• refactor: use pydot in make_diagram() to support clusters (component groups) (6a53558)

• refactor: remove duplicate code in Components (488d451)

• refactor: add generic component class (31873dd)

v1.5.0

v1.5.0 (2024-10-14)

Documentation

• docs: update LinReg parameters in component files notebook (e65d5a9)

• docs: fix component parameter interpolation data dict examples in API (a0b9ed7)

• docs: add limit definitions to component parameter files notebook. (9110379)

Features

• feat: add power switch (PSwitch) component (8880ec1)

• feat: new limit added: vd (voltage difference) (7e599b1)

• feat: add method .limits() to system, which returns all user defined component limits (3dc8bf9)

Refactoring

• refactor: deprecate LinReg iq parameter, replace with ig (9183e37)

• refactor: add checking of sysLoss version when loading System from file (29eb5a4)

• refactor: set state to off when phase in not active (bee1610)

• refactor: add state vector to solver parameters (f290f6d)

v1.4.0

v1.4.0 (2024-09-02)

Build

• build: fix CITATION.cff version update variable (298ea1c)

Ci

• ci: switch to codacy github action (a5b758c)

• ci: add codacy token (532b850)

• ci: add codacy job (15bb292)

Documentation

• docs: fix typos in battery life tutorial (fa36896)

• docs: add links to PyPI and Anaconda on badges (0ee0f96)

• docs: add Codacy badge to README.md (2d09974)

• docs: add examples to System class api (5f95963)

• docs: explicit define default parameter values (47aa0f1)

• docs: update security.md (c3522d9)

Feature

• feat: add ambient temperature (ta) as new parameter to .solve() and peak temperature (tp) as a new limit

If thermal resistance is specified on a component, peak temperature shows up as a new column in the results table. Peak temperature is calculated as ambient temperature plus temperature rise. (2e74afe)

Fix

• fix(system): add check of component name and set default load phase in change_comp() (1a06e47)

Unknown

• Create SECURITY.md (94145e2)

• Merge branch 'main' of https://github.com/geddy11/sysloss (26227ac)

v1.3.0

v1.3.0 (2024-06-19)

Build

• build: add PyPI classifiers (f8a0a9f)

Ci

• ci: remove unused jobs in pipeline (4849845)

Documentation

• docs: update sysLoss version in CITATION.cff (6fb8ad8)

• docs: add ROV battery pack tutorial (61afdba)

Feature

• feat: add thermal resistance parameter and temperature rise calculation (b8481a2)

• feat: add tags argument to .batt_life() (495eea5)

v1.2.0

v1.2.0 (2024-05-27)

Ci

• ci: fix maintainer in conda receipe (1d27b0c)

Documentation

• docs: correct toml interpolation data format in "Component parameter files" page (9275463)

• docs: remove output from import packages cell (0b56c35)

Feature

• feat: add power limits to all components (pi, po, pl) (ce36738)

• feat(components): add interpolation option to LinReg ground current parameter (2393767)

Fix

• fix(system): add correct title to LinReg interpolation data plots (8ade81d)

Refactor

• refactor: system .params() method now gets component parameters from ._get_params() method (320fc09)

• refactor: system method .plot_interp() gets figure annotations from component method ._get_annot() (bb2f017)

Unknown

• Merge branch 'main' of https://github.com/geddy11/sysloss (ebce939)