feat(x86_64): use userspace emulated IOAPIC

alioth/src/arch/x86_64/intr.rs

@@ -14,21 +14,60 @@
 
 use bitfield::bitfield;
 
+use crate::consts;
+
+consts! {
+    pub struct DeliveryMode(u8) {
+        FIXED = 0b000;
+        LOW_PRIORITY = 0b001;
+        SMI = 0b010;
+        NMI = 0b100;
+        INIT = 0b101;
+        STARTUP_IPI = 0b110;
+        EXTINT = 0b111;
+    }
+}
+
+consts! {
+    pub struct TriggerMode(bool) {
+        EDGE = false;
+        LEVEL = true;
+    }
+}
+
+consts! {
+    pub struct DestinationMode(bool) {
+        PHYSICAL = false;
+        LOGICAL = true;
+    }
+}
+
 bitfield! {
     #[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]
     pub struct MsiAddrLo(u32);
     impl Debug;
     pub mode, set_mode : 2;
     pub redirection, set_redirection : 3;
     pub remappable, set_remappable : 4;
-    pub reserved, set_reserved : 11, 5;
-    pub dest_id, set_dest_id : 19, 12;
+    pub u8, virt_dest_id_hi, set_virt_dest_id_hi : 11, 5;
+    pub u8, dest_id, set_dest_id : 19, 12;
     pub identifier, _: 31, 20;
 }
 
 bitfield! {
     #[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]
     pub struct MsiAddrHi(u32);
     impl Debug;
-    pub dest_id, set_dest_id : 31, 8;
+    pub dest_id_hi, set_dest_id_hi : 31, 8;
+}
+
+bitfield! {
+    #[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]
+    pub struct MsiData(u32);
+    impl Debug;
+    impl new;
+    pub u8, vector, set_vector : 7, 0;
+    pub u8, from into DeliveryMode, delivery_mode, set_delivery_mode : 11, 8;
+    pub u8, level, set_level : 14;
+    pub trigger_mode, set_trigger_mode : 15;
 }

alioth/src/arch/x86_64/ioapic.rs

@@ -0,0 +1,63 @@
+// Copyright 2026 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+use bitfield::bitfield;
+
+use crate::arch::intr::DeliveryMode;
+
+pub const IOREGSEL: u64 = 0x00;
+pub const IOWIN: u64 = 0x10;
+
+pub const IOAPICID: u8 = 0x00;
+pub const IOAPICVER: u8 = 0x01;
+pub const IOAPICARB: u8 = 0x02;
+pub const IOREDTBL_BASE: u8 = 0x10;
+pub const IOREDTBL_MAX: u8 = 0x3f;
+
+pub const NUM_PINS: u8 = 24;
+
+pub const IOAPIC_VER: u8 = 0x11;
+
+bitfield! {
+    #[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]
+    pub struct RegId(u32);
+    impl Debug;
+    impl new;
+    pub u8, id, set_id : 27, 24;
+}
+
+bitfield! {
+    #[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]
+    pub struct RegVer(u32);
+    impl Debug;
+    impl new;
+    pub u8, version, set_version : 7, 0;
+    pub u8, max_entry, set_max_entry : 23, 16;
+}
+
+bitfield! {
+    #[derive(Copy, Clone, Default, PartialEq, Eq, Hash)]
+    pub struct RedirectEntry(u64);
+    impl Debug;
+    pub u8,	vector, set_vector : 7, 0;
+    pub u8, from into DeliveryMode, delivery_mode, set_delivery_mode : 10, 8;
+    pub dest_mode, set_dest_mode : 11;
+    pub delivery_status, set_delivery_status : 12;
+    pub riority, set_priority : 13;
+    pub irr, set_irr : 14;
+    pub trigger_mode, set_trigger_mode : 15;
+    pub masked, set_masked : 16;
+    pub u8, virt_dest_id_hi, set_virt_dest_id_hi : 55, 49;
+    pub u8, dest_id, set_dest_id : 63, 56;
+}

alioth/src/arch/x86_64/layout.rs

@@ -52,6 +52,8 @@ pub const PCIE_CONFIG_START: u64 = 0xe000_0000; // 3.5 GiB
 pub const PCIE_CONFIG_END: u64 = 0xf000_0000; // 3.75 GiB, size = 256 MiB
 
 pub const IOAPIC_START: u64 = 0xfec0_0000;
+pub const IOAPIC_END: u64 = IOAPIC_START + 0x100;
+
 pub const APIC_START: u64 = 0xfee0_0000;
 
 pub const MEM_64_START: u64 = 0x1_0000_0000; // 4GiB

alioth/src/arch/x86_64/x86_64.rs

@@ -14,6 +14,7 @@
 
 pub mod cpuid;
 pub mod intr;
+pub mod ioapic;
 pub mod layout;
 pub mod msr;
 pub mod paging;

alioth/src/board/board.rs

@@ -211,7 +211,6 @@ where
     pub config: BoardConfig,
     pub payload: RwLock<Option<Payload>>,
     pub io_devs: RwLock<Vec<(u16, Arc<dyn MmioDev>)>>,
-    #[cfg(target_arch = "aarch64")]
     pub mmio_devs: RwLock<Vec<(u64, Arc<dyn MmioDev>)>>,
     pub pci_bus: PciBus,
     #[cfg(target_arch = "x86_64")]
@@ -238,7 +237,6 @@ where
             payload: RwLock::new(None),
             vcpus: Arc::new(RwLock::new(Vec::new())),
             io_devs: RwLock::new(Vec::new()),
-            #[cfg(target_arch = "aarch64")]
             mmio_devs: RwLock::new(Vec::new()),
             pci_bus: PciBus::new(),
             #[cfg(target_arch = "x86_64")]
@@ -417,7 +415,6 @@ where
             for (port, dev) in self.io_devs.read().iter() {
                 self.memory.add_io_dev(*port, dev.clone())?;
             }
-            #[cfg(target_arch = "aarch64")]
             for (addr, dev) in self.mmio_devs.read().iter() {
                 self.memory.add_mmio_dev(*addr, dev.clone())?;
             }

alioth/src/board/board_x86_64.rs

@@ -15,7 +15,6 @@
 use std::arch::x86_64::{__cpuid, CpuidResult};
 use std::collections::HashMap;
 use std::iter::zip;
-use std::marker::PhantomData;
 use std::mem::{offset_of, size_of, size_of_val};
 use std::path::Path;
 use std::sync::Arc;
@@ -27,13 +26,14 @@ use zerocopy::{FromBytes, FromZeros, Immutable, IntoBytes};
 
 use crate::arch::cpuid::CpuidIn;
 use crate::arch::layout::{
-    BIOS_DATA_END, EBDA_END, EBDA_START, MEM_64_START, PORT_ACPI_RESET, PORT_ACPI_SLEEP_CONTROL,
-    RAM_32_SIZE,
+    BIOS_DATA_END, EBDA_END, EBDA_START, IOAPIC_START, MEM_64_START, PORT_ACPI_RESET,
+    PORT_ACPI_SLEEP_CONTROL, RAM_32_SIZE,
 };
 use crate::arch::msr::{IA32_MISC_ENABLE, MiscEnable};
 use crate::arch::reg::{Reg, SegAccess, SegReg, SegRegVal};
 use crate::arch::sev::SnpPageType;
 use crate::board::{Board, BoardConfig, CpuTopology, PCIE_MMIO_64_SIZE, Result, VcpuGuard, error};
+use crate::device::ioapic::IoApic;
 use crate::firmware::acpi::bindings::{
     AcpiTableFadt, AcpiTableHeader, AcpiTableRsdp, AcpiTableXsdt3,
 };
@@ -47,10 +47,13 @@ use crate::mem::mapped::ArcMemPages;
 use crate::mem::{MemRange, MemRegion, MemRegionEntry, MemRegionType};
 use crate::utils::wrapping_sum;
 
-pub struct ArchBoard<V> {
+pub struct ArchBoard<V>
+where
+    V: Vm,
+{
     cpuids: HashMap<CpuidIn, CpuidResult>,
     sev_ap_eip: AtomicU32,
-    _phantom: PhantomData<V>,
+    pub(crate) io_apic: Arc<IoApic<V::MsiSender>>,
 }
 
 fn add_topology(cpuids: &mut HashMap<CpuidIn, CpuidResult>, func: u32, levels: &[(u8, u16)]) {
@@ -70,7 +73,7 @@ fn add_topology(cpuids: &mut HashMap<CpuidIn, CpuidResult>, func: u32, levels: &
 }
 
 impl<V: Vm> ArchBoard<V> {
-    pub fn new<H>(hv: &H, _vm: &V, config: &BoardConfig) -> Result<Self>
+    pub fn new<H>(hv: &H, vm: &V, config: &BoardConfig) -> Result<Self>
     where
         H: Hypervisor<Vm = V>,
     {
@@ -147,10 +150,11 @@ impl<V: Vm> ArchBoard<V> {
             let host_cpuid = unsafe { __cpuid(func) };
             cpuids.insert(CpuidIn { func, index: None }, host_cpuid);
         }
+
         Ok(Self {
             cpuids,
             sev_ap_eip: AtomicU32::new(0),
-            _phantom: PhantomData,
+            io_apic: Arc::new(IoApic::new(vm.create_msi_sender()?)),
         })
     }
 }
@@ -538,6 +542,8 @@ where
     }
 
     pub fn arch_init(&self) -> Result<()> {
+        let io_apic = self.arch.io_apic.clone();
+        self.mmio_devs.write().push((IOAPIC_START, io_apic));
         Ok(())
     }
 }

alioth/src/device/device.rs

@@ -22,6 +22,8 @@ pub mod console;
 #[cfg(target_arch = "x86_64")]
 #[path = "fw_cfg/fw_cfg.rs"]
 pub mod fw_cfg;
+#[cfg(target_arch = "x86_64")]
+pub mod ioapic;
 pub mod net;
 #[cfg(target_arch = "aarch64")]
 pub mod pl011;