fix(pause): loong64 zero register and riscv64 PAUSE hint#5
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Summary
pauseNusing R0 (zero register) → R4FENCEwithPAUSE(Zihintpause)Details
loong64
R0 in LoongArch64 is hardwired to zero. Loop counter was broken.
riscv64
PAUSE(0x0100000F) is a lightweight power-saving hint.Testing