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test
test
 
 
testcase
testcase
 
 
ALU.v
ALU.v
 
 
ALUControl.v
ALUControl.v
 
 
ALUControl_test.v
ALUControl_test.v
 
 
ALU_test.v
ALU_test.v
 
 
Add4.v
Add4.v
 
 
Add4_test.v
Add4_test.v
 
 
AddBranch.v
AddBranch.v
 
 
And.v
And.v
 
 
BranchCtrl.v
BranchCtrl.v
 
 
BranchHazardCheck.v
BranchHazardCheck.v
 
 
CPU.v
CPU.v
 
 
DM.v
DM.v
 
 
DMData.data
DMData.data
 
 
EXMEM.v
EXMEM.v
 
 
HazardCheckUnit.v
HazardCheckUnit.v
 
 
IDEX.v
IDEX.v
 
 
IFID.v
IFID.v
 
 
IM.v
IM.v
 
 
IMData.data
IMData.data
 
 
IMData1.data
IMData1.data
 
 
IMData2.data
IMData2.data
 
 
IMData3.data
IMData3.data
 
 
IMTest.data
IMTest.data
 
 
IM_test.v
IM_test.v
 
 
IM_test.vcd
IM_test.vcd
 
 
IsBranch.v
IsBranch.v
 
 
MEMWB.v
MEMWB.v
 
 
MIPSCPU.cr.mti
MIPSCPU.cr.mti
 
 
MIPSCPU.mpf
MIPSCPU.mpf
 
 
PC.v
PC.v
 
 
PC_test.v
PC_test.v
 
 
README.md
README.md
 
 
RegHeap.v
RegHeap.v
 
 
RegHeap_test.v
RegHeap_test.v
 
 
SL2.v
SL2.v
 
 
SL2Add.v
SL2Add.v
 
 
SwapUnit.v
SwapUnit.v
 
 
TempPc.v
TempPc.v
 
 
a.out
a.out
 
 
controlHazard.data
controlHazard.data
 
 
controlUnit.v
controlUnit.v
 
 
controlUnit_test.v
controlUnit_test.v
 
 
cu.vcd
cu.vcd
 
 
dataHazard.data
dataHazard.data
 
 
div_clk.v
div_clk.v
 
 
first.v
first.v
 
 
j.data
j.data
 
 
loadUseHazard.data
loadUseHazard.data
 
 
memData.data
memData.data
 
 
mt.vcd
mt.vcd
 
 
muxthree.v
muxthree.v
 
 
muxthree_test.v
muxthree_test.v
 
 
muxtwo_32.v
muxtwo_32.v
 
 
muxtwo_4.v
muxtwo_4.v
 
 
muxtwo_4_test.v
muxtwo_4_test.v
 
 
muxtwo_5.v
muxtwo_5.v
 
 
muxtwo_6.v
muxtwo_6.v
 
 
muxtwo_9.v
muxtwo_9.v
 
 
overflow.data
overflow.data
 
 
pipelineNoHazard.data
pipelineNoHazard.data
 
 
rHazard.vcd
rHazard.vcd
 
 
readWriteHazard.data
readWriteHazard.data
 
 
reg
reg
 
 
regHeapData.data
regHeapData.data
 
 
signExt.v
signExt.v
 
 
sublime-verilog.md
sublime-verilog.md
 
 
test1.vcd
test1.vcd
 
 
test2.vcd
test2.vcd
 
 
testBench.v
testBench.v
 
 
writeReadHazard.data
writeReadHazard.data
 
 

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MIPS-CPU

Pipeline CPU ，support 50+ MIPS instructions ##Done##

  • pipeline
  • data hazard
  • control hazard
  • 10 instructions

###To Do#

  • more instructions
  • memory management

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Single-Cycle CPU and Pipeline CPU ，support 50+ MIPS instructions

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