RISC-V Emulator
This is my first RISC-V coding project. It supports the base RV32I unpriveleged ISA.
This was an educational project to teach me about the details of all the instructions in the base RISC-V architecture, to learn more about the instruction encodings, and to discover any missing hidden traps. I wrote it in C++ so I could gain some experience with RISC-V before implementing it in SystemVerilog.
I have now moved on to the SystemVerilog implementation (linuxuser314/nano-rv32i) and have sucesfully ran it, passed RISC-V tests, and synthesized it to an FPGA (Sipeed Tang Nano 20K). As a result, this repository is no longer maintained.