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[AMDGPU][GlobalISel] Add RegBankLegalize rules for mul24 and fmul.leg… #173123

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8 changes: 8 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1039,4 +1039,12 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
// readfirstlaning just in case register is not in sgpr.
.Any({{UniS32, _, UniS32}, {{}, {Sgpr32, None, Vgpr32}}});

addRulesForIOpcs({amdgcn_mul_u24, amdgcn_mul_i24, amdgcn_mulhi_u24,
amdgcn_mulhi_i24, amdgcn_fmul_legacy},
Standard)
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32}})
.Uni(S64, {{UniInVgprS64}, {IntrId, Vgpr32, Vgpr32}})
.Div(S64, {{Vgpr64}, {IntrId, Vgpr32, Vgpr32}});

} // end initialize rules
57 changes: 51 additions & 6 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
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Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX101 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck --check-prefix=GFX103 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=GFX8 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX101 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck --check-prefix=GFX103 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s

define float @v_mul_legacy_f32(float %a, float %b) {
; GFX6-LABEL: v_mul_legacy_f32:
Expand Down Expand Up @@ -426,6 +426,51 @@ define amdgpu_ps float @s_mul_legacy_f32(float inreg %a, float inreg %b) {
ret float %result
}

define amdgpu_ps i32 @s_mul_legacy_f32_uniform(float inreg %a, float inreg %b) {
; GFX6-LABEL: s_mul_legacy_f32_uniform:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v0, s1
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
; GFX6-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_mul_legacy_f32_uniform:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_mul_legacy_f32_uniform:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX101-LABEL: s_mul_legacy_f32_uniform:
; GFX101: ; %bb.0:
; GFX101-NEXT: v_mul_legacy_f32_e64 v0, s0, s1
; GFX101-NEXT: v_readfirstlane_b32 s0, v0
; GFX101-NEXT: ; return to shader part epilog
;
; GFX103-LABEL: s_mul_legacy_f32_uniform:
; GFX103: ; %bb.0:
; GFX103-NEXT: v_mul_legacy_f32_e64 v0, s0, s1
; GFX103-NEXT: v_readfirstlane_b32 s0, v0
; GFX103-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_mul_legacy_f32_uniform:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, s0, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
%result = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)
%cast = bitcast float %result to i32
ret i32 %cast
}

define float @v_mul_legacy_f32_1.0(float %a) {
; GFX6-LABEL: v_mul_legacy_f32_1.0:
; GFX6: ; %bb.0:
Expand Down
232 changes: 232 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mul24.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,232 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s

define i32 @mul_u24_s32_divergent(i32 %a, i32 %b) {
; GFX9-LABEL: mul_u24_s32_divergent:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: mul_u24_s32_divergent:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_u32_u24_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.amdgcn.mul.u24.i32(i32 %a, i32 %b)
ret i32 %result
}

define amdgpu_ps i32 @mul_u24_s32_uniform(i32 inreg %a, i32 inreg %b) {
; GFX9-LABEL: mul_u24_s32_uniform:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_mul_u32_u24_e32 v0, s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: mul_u24_s32_uniform:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mul_u32_u24_e64 v0, s0, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.amdgcn.mul.u24.i32(i32 %a, i32 %b)
ret i32 %result
}

define i64 @mul_u24_s64_divergent(i32 %a, i32 %b) {
; GFX9-LABEL: mul_u24_s64_divergent:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mul_hi_u32_u24_e32 v2, v0, v1
; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: mul_u24_s64_divergent:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_u32_u24_e32 v2, v0, v1
; GFX11-NEXT: v_mul_hi_u32_u24_e32 v1, v0, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_mov_b32_e32 v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.amdgcn.mul.u24.i64(i32 %a, i32 %b)
ret i64 %result
}

define amdgpu_ps i64 @mul_u24_s64_uniform(i32 inreg %a, i32 inreg %b) {
; GFX9-LABEL: mul_u24_s64_uniform:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_mul_hi_u32_u24_e32 v1, s0, v0
; GFX9-NEXT: v_mul_u32_u24_e32 v0, s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: mul_u24_s64_uniform:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mul_u32_u24_e64 v0, s0, s1
; GFX11-NEXT: v_mul_hi_u32_u24_e64 v1, s0, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: ; return to shader part epilog
%result = call i64 @llvm.amdgcn.mul.u24.i64(i32 %a, i32 %b)
ret i64 %result
}

define i32 @mul_i24_s32_divergent(i32 %a, i32 %b) {
; GFX9-LABEL: mul_i24_s32_divergent:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: mul_i24_s32_divergent:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_i32_i24_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.amdgcn.mul.i24.i32(i32 %a, i32 %b)
ret i32 %result
}

define amdgpu_ps i32 @mul_i24_s32_uniform(i32 inreg %a, i32 inreg %b) {
; GFX9-LABEL: mul_i24_s32_uniform:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_mul_i32_i24_e32 v0, s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: mul_i24_s32_uniform:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mul_i32_i24_e64 v0, s0, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.amdgcn.mul.i24.i32(i32 %a, i32 %b)
ret i32 %result
}

define i64 @mul_i24_s64_divergent(i32 %a, i32 %b) {
; GFX9-LABEL: mul_i24_s64_divergent:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mul_hi_i32_i24_e32 v2, v0, v1
; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: mul_i24_s64_divergent:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_i32_i24_e32 v2, v0, v1
; GFX11-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_mov_b32_e32 v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.amdgcn.mul.i24.i64(i32 %a, i32 %b)
ret i64 %result
}

define amdgpu_ps i64 @mul_i24_s64_uniform(i32 inreg %a, i32 inreg %b) {
; GFX9-LABEL: mul_i24_s64_uniform:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_mul_hi_i32_i24_e32 v1, s0, v0
; GFX9-NEXT: v_mul_i32_i24_e32 v0, s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: mul_i24_s64_uniform:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mul_i32_i24_e64 v0, s0, s1
; GFX11-NEXT: v_mul_hi_i32_i24_e64 v1, s0, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: ; return to shader part epilog
%result = call i64 @llvm.amdgcn.mul.i24.i64(i32 %a, i32 %b)
ret i64 %result
}

define i32 @mulhi_u24_s32_divergent(i32 %a, i32 %b) {
; GFX9-LABEL: mulhi_u24_s32_divergent:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mul_hi_u32_u24_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: mulhi_u24_s32_divergent:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_hi_u32_u24_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.amdgcn.mulhi.u24(i32 %a, i32 %b)
ret i32 %result
}

define amdgpu_ps i32 @mulhi_u24_s32_uniform(i32 inreg %a, i32 inreg %b) {
; GFX9-LABEL: mulhi_u24_s32_uniform:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_mul_hi_u32_u24_e32 v0, s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: mulhi_u24_s32_uniform:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mul_hi_u32_u24_e64 v0, s0, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.amdgcn.mulhi.u24(i32 %a, i32 %b)
ret i32 %result
}

define i32 @mulhi_i24_s32_divergent(i32 %a, i32 %b) {
; GFX9-LABEL: mulhi_i24_s32_divergent:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mul_hi_i32_i24_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: mulhi_i24_s32_divergent:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mul_hi_i32_i24_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.amdgcn.mulhi.i24(i32 %a, i32 %b)
ret i32 %result
}

define amdgpu_ps i32 @mulhi_i24_s32_uniform(i32 inreg %a, i32 inreg %b) {
; GFX9-LABEL: mulhi_i24_s32_uniform:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_mul_hi_i32_i24_e32 v0, s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: mulhi_i24_s32_uniform:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mul_hi_i32_i24_e64 v0, s0, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.amdgcn.mulhi.i24(i32 %a, i32 %b)
ret i32 %result
}

declare i32 @llvm.amdgcn.mul.u24.i32(i32, i32)
declare i64 @llvm.amdgcn.mul.u24.i64(i32, i32)
declare i32 @llvm.amdgcn.mul.i24.i32(i32, i32)
declare i64 @llvm.amdgcn.mul.i24.i64(i32, i32)
declare i32 @llvm.amdgcn.mulhi.u24(i32, i32)
declare i32 @llvm.amdgcn.mulhi.i24(i32, i32)
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
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Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s

---
name: fmul_legacy_ss
Expand All @@ -17,6 +16,7 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[COPY2]](s32), [[COPY3]](s32)
; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[INT]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), %0, %1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.i24.ll
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s

define i32 @basic(i32 %a, i32 %b) {
; CHECK-LABEL: basic:
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.u24.ll
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s

define i32 @basic(i32 %a, i32 %b) {
; CHECK-LABEL: basic:
Expand Down