CS-552-Direct-Mapped-Cache-Project

The design of direct-mapped cache with a cache controller and cache datapath to work with a four bank memory written in Verilog.

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
cache.v		cache.v
clkrst.v		clkrst.v
dff.v		dff.v
final_memory.v		final_memory.v
four_bank_mem.v		four_bank_mem.v
loadfile_0.img		loadfile_0.img
loadfile_1.img		loadfile_1.img
loadfile_2.img		loadfile_2.img
loadfile_3.img		loadfile_3.img
loadfile_all.img		loadfile_all.img
mem-1.addr		mem-1.addr
mem-2.addr		mem-2.addr
mem-3.addr		mem-3.addr
mem-4.addr		mem-4.addr
mem-5.addr		mem-5.addr
mem.addr		mem.addr
mem_system.v		mem_system.v
mem_system_hier.v		mem_system_hier.v
mem_system_perfbench.v		mem_system_perfbench.v
mem_system_randbench.v		mem_system_randbench.v
mem_system_ref.v		mem_system_ref.v
memc.v		memc.v
memv.v		memv.v

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