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README.md
README.md
 
 
Vcheck.class
Vcheck.class
 
 
VerFile.class
VerFile.class
 
 
alu.v
alu.v
 
 
alu.vcheck.out
alu.vcheck.out
 
 
bit_shifter.v
bit_shifter.v
 
 
bit_shifter.vcheck.out
bit_shifter.vcheck.out
 
 
btr.v
btr.v
 
 
btr.vcheck.out
btr.vcheck.out
 
 
cla16.v
cla16.v
 
 
cla16.vcheck.out
cla16.vcheck.out
 
 
cla4.v
cla4.v
 
 
cla4.vcheck.out
cla4.vcheck.out
 
 
clkrst.v
clkrst.v
 
 
clkrst.vcheck.out
clkrst.vcheck.out
 
 
complex.list
complex.list
 
 
complex.summary.log
complex.summary.log
 
 
complex_pipelined.list
complex_pipelined.list
 
 
cu.v
cu.v
 
 
cu.vcheck.out
cu.vcheck.out
 
 
de.v
de.v
 
 
de.vcheck.out
de.vcheck.out
 
 
decode.v
decode.v
 
 
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decode.vcheck.out
 
 
dff.v
dff.v
 
 
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dff.vcheck.out
 
 
dxpr.v
dxpr.v
 
 
execute.v
execute.v
 
 
execute.vcheck.out
execute.vcheck.out
 
 
extra_credits.list
extra_credits.list
 
 
fdpr.v
fdpr.v
 
 
fetch.v
fetch.v
 
 
fetch.vcheck.out
fetch.vcheck.out
 
 
forwardingunit.v
forwardingunit.v
 
 
fulladder1.v
fulladder1.v
 
 
fulladder1.vcheck.out
fulladder1.vcheck.out
 
 
fulladder16.v
fulladder16.v
 
 
fulladder16.vcheck.out
fulladder16.vcheck.out
 
 
fulladder4.v
fulladder4.v
 
 
fulladder4.vcheck.out
fulladder4.vcheck.out
 
 
hazardunit.v
hazardunit.v
 
 
ie.v
ie.v
 
 
ie.vcheck.out
ie.vcheck.out
 
 
lu.v
lu.v
 
 
lu.vcheck.out
lu.vcheck.out
 
 
memory.v
memory.v
 
 
memory.vcheck.out
memory.vcheck.out
 
 
memory2c.v
memory2c.v
 
 
memory2c.vcheck.out
memory2c.vcheck.out
 
 
mwpr.v
mwpr.v
 
 
nand2.v
nand2.v
 
 
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nand2.vcheck.out
 
 
nor2.v
nor2.v
 
 
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nor2.vcheck.out
 
 
not1.v
not1.v
 
 
not1.vcheck.out
not1.vcheck.out
 
 
proc.v
proc.v
 
 
proc.vcheck.out
proc.vcheck.out
 
 
proc_hier.v
proc_hier.v
 
 
proc_hier.vcheck.out
proc_hier.vcheck.out
 
 
proc_hier_bench.v
proc_hier_bench.v
 
 
proc_hier_bench.vcheck.out
proc_hier_bench.vcheck.out
 
 
proc_hier_pbench.v
proc_hier_pbench.v
 
 
r16.v
r16.v
 
 
r16.vcheck.out
r16.vcheck.out
 
 
rand_complex.list
rand_complex.list
 
 
rand_ctrl.list
rand_ctrl.list
 
 
rand_ctrl.summary.log
rand_ctrl.summary.log
 
 
rand_mem.list
rand_mem.list
 
 
rand_mem.summary.log
rand_mem.summary.log
 
 
rand_simple.list
rand_simple.list
 
 
rand_simple.summary.log
rand_simple.summary.log
 
 
rf.v
rf.v
 
 
rf.vcheck.out
rf.vcheck.out
 
 
rfb.v
rfb.v
 
 
shifter.v
shifter.v
 
 
shifter.vcheck.out
shifter.vcheck.out
 
 
simple.list
simple.list
 
 
simple.summary.log
simple.summary.log
 
 
transcript
transcript
 
 
write.v
write.v
 
 
write.vcheck.out
write.vcheck.out
 
 
xmpr.v
xmpr.v
 
 
xor2.v
xor2.v
 
 
xor2.vcheck.out
xor2.vcheck.out
 
 

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CS-552-Pipelined-Microprocessor-Project

A complete functional design of a pipelined microprocessor based on MIPS R2000 written in Verilog.

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A design of a pipelined microprocessor for CS 552 at UW Madison.

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