CS-552-Unpipelined-Microprocessor-Project

A complete functional design of an unpipelined microprocessor based on MIPS R2000 written in Verilog.

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
work		work
README.md		README.md
Vcheck.class		Vcheck.class
VerFile.class		VerFile.class
alu.v		alu.v
bit_shifter.v		bit_shifter.v
btr.v		btr.v
cla16.v		cla16.v
cla4.v		cla4.v
clkrst.v		clkrst.v
complex.list		complex.list
cu.v		cu.v
de.v		de.v
decode.v		decode.v
dff.v		dff.v
execute.v		execute.v
fetch.v		fetch.v
fulladder1.v		fulladder1.v
fulladder16.v		fulladder16.v
fulladder4.v		fulladder4.v
ie.v		ie.v
lu.v		lu.v
memory.v		memory.v
memory2c.v		memory2c.v
nand2.v		nand2.v
nor2.v		nor2.v
not1.v		not1.v
proc.v		proc.v
proc_hier.v		proc_hier.v
proc_hier_bench.v		proc_hier_bench.v
project-unpipelined.cr.mti		project-unpipelined.cr.mti
project-unpipelined.mpf		project-unpipelined.mpf
r16.v		r16.v
rand_complex.list		rand_complex.list
rand_ctrl.list		rand_ctrl.list
rand_mem.list		rand_mem.list
rand_simple.list		rand_simple.list
rf.v		rf.v
shifter.v		shifter.v
simple.list		simple.list
transcript		transcript
write.v		write.v
xor2.v		xor2.v

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