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4 repositories

Single-Cycle-Processor
Public
Single Cycle Non-Pipelined Processor for RV32I.
risc-v processor-design
risc-v processor-design
Verilog
•1•0•0•0•Updated Apr 13, 2025Apr 13, 2025
Pipelined-Processor
Public
5-Stage Pipelined Processor for RV32I with Hazard Control and Branch Prediction.
risc-v processor-design pipelined-processor
risc-v processor-design pipelined-processor
Verilog
•1•0•0•0•Updated Apr 13, 2025Apr 13, 2025
UART_Tx_Rx
Public
transmit instructions and receive the register file for debugging
SystemVerilog
•0•0•0•0•Updated Apr 13, 2025Apr 13, 2025
Instruction_Binaries_Generate
Public
generate bit stream for given RISC RV32I instructions
Python
•
MIT License
•0•0•0•0•Updated Apr 13, 2025Apr 13, 2025

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