Skip to content
View r4hulrr's full-sized avatar
1 follower · 1 following

Block or report r4hulrr

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. exchange exchange Public

    Multi-symbol exchange with price-time priority matching, TCP ingestion, and UDP multicast market data. Benchmarked with Google Benchmark

    C++

  2. logic-gate-learner logic-gate-learner Public

    Hardware accelerator implemented on an Arty A7 100T FPGA for a custom neural network, designed from scratch in Python using only NumPy, trained for MNIST digit recognition

    Verilog 1

  3. chess_engine chess_engine Public

    UCI-compatible C++ chess engine with bitboards, negamax search, alpha-beta pruning, move ordering, and piece-square evaluation

    C++

  4. rv32i rv32i Public

    rv32i cpu in systemverilog

    SystemVerilog

  5. stm-32-bms stm-32-bms Public

    A Battery Management System (BMS) developed using the STM32F446RET6 MCU, featuring real-time monitoring, overcharge and overheat protection, and cell balancing.

    C 7 1

  6. ausign ausign Public

    Real-time Auslan (Australian Sign Language) to English speech translation glove. Built with ESP32-S3, flex sensors, IMU on a custom PCB, and a Bluetooth-connected Python GUI.

    C++ 2 1