3-operand MULT/MULTU & delay slot exception handling#71
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aslanhudajev wants to merge 0 commit intoran-j:mainfrom
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3-operand MULT/MULTU & delay slot exception handling#71aslanhudajev wants to merge 0 commit intoran-j:mainfrom
aslanhudajev wants to merge 0 commit intoran-j:mainfrom
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ran-j
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Feb 21, 2026
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ran-j
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Hey nice work, the Vu0 implementations seens good to me but please create a new PR with only thouse changes, we have a lot of "noise" from your recompilation like gitignore changed and some cursor thing.
.cursor/data/funDefsZDataError.md
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ok you have some files like this one that is specific for you project and can't be merge like this one.
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Yes, I will fix that.
I'll make a new PR.
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ps2xRuntime/CMakeLists.txt
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we can't have this deep on the runtime this scene specific for your project.
.gitignore
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| ps2xRuntime/src/runner/register_functions.cpp | ||
| ps2xRuntime/output No newline at end of file | ||
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Also the build are fail |
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This commit:
6821c69eb5674807569416cbac236510491f41a4fixes a lot of runtime errors.The MULT/MULTU fix is the most impactful I would say. Not super sure about the delay slot fix, it did however fix many issues in the game I am trying to get to run.
Fix R5900 3-operand MULT/MULTU:
Standard MIPS MULT rs, rt only writes HI/LO. The R5900 extends this with a 3-operand form MULT rd, rs, rt that also writes the low 32 bits of the result into rd. The code generator was omitting the rd write, leaving the destination register stale. Any game code that reads rd after a multiply (instead of using MFLO) would get garbage, causing infinite loops and incorrect computations. This was found in Gauntlet: Dark Legacy's InitAtreeSeqs where the loop counter was computed via 3-operand MULT and never advanced.
Fix delay slot exception handling:
When a MIPS exception occurs on a delay slot instruction, the CPU sets the BD (Branch Delay) bit in the Cause register and EPC points to the branch instruction, not the delay slot. The runtime's exception handler needs to know it was in a delay slot to correctly re-execute the branch after returning from the exception. The code generator now emits ctx->in_delay_slot = 1 / = 0 around delay slot instruction code, allowing raiseCop0Exception to set EPC and BD correctly and preserve the branch target.