16-Bit CPU from Scratch

A learning project to understand computer architecture by building a CPU from first principles using Verilog HDL.

📊 Project Status

Timeline: 2-3 weeks of intensive development (November 2025)
Completion: ~65-70%
Current State: All major components built and tested individually. System integration is incomplete.

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✅ What I Built

Completed & Tested Components

All individual modules compile successfully and pass their testbenches:

• Logic Gates & Combinational Circuits - AND, OR, NOT, XOR, NAND, NOR gates
• Adders - Half adder, full adder, 16-bit ripple-carry adder
• Multiplier - 16-bit multiplication unit
• Arithmetic Logic Unit (ALU) - Arithmetic and logical operations
• D Flip-Flop - Basic sequential logic element
• Register File - 16-bit registers with read/write operations
• Program Counter (PC) - Learnt about byte-address & word-address instructions
• RAM Module - Memory read/write interface
• Control Unit - Instruction decode logic (partial)
• Finite State Machine (FSM) - Instruction cycle control

Testing Approach: Used AI-assisted testbench generation (which I reviewed and understood) to verify each component works correctly in isolation.

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❌ What's Missing

Incomplete Components

1. Instruction Set Architecture (ISA)

• Challenge: Designing efficient instruction encoding within 16-bit constraint
• Problem: Balancing opcode space, register addressing, and immediate values
• Trade-offs: Number of registers vs operation types vs addressing modes

2. System Integration (cpu_top.v)

• Depends on completing ISA design first
• Requires wiring all components together
• Need to implement instruction memory and instruction register
• Control signal routing between all modules

Why I Stopped: After 2-3 weeks of intense component-level work, I hit the architectural design phase (ISA specification and system integration). This requires different thinking than component implementation - more design philosophy than coding execution. Rather than force a broken integration, I paused to strengthen my understanding of computer architecture principles.

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🧠 What I Learned

Technical Skills

• Digital Logic Design - Combinational vs sequential circuits, timing, state machines
• Verilog HDL - Syntax, simulation, module design, testbench creation
• CPU Architecture - Datapath design, control logic, instruction execution cycles
• Component Testing - Writing comprehensive testbenches, debugging hardware designs
• Tool Usage - [Icarus Verilog]
• Using AI Smartly - Leveraged AI for testbench generation and debugging suggestions, but ensured I understood every line of code

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🛠️ Tech Stack

• HDL: Verilog
• Simulator: [Icarus Verilog]
• Testing: Custom testbenches (AI-assisted generation, manually reviewed)
• Version Control: Git/GitHub

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📚 Learning Resources

Books and materials that helped:

• The Elements of Computing Systems by Nisan & Schocken (Nand2Tetris)
• Computer Organization and Design by Patterson & Hennessy
• Digital Design and Computer Architecture by David Money Harris & Sarah L. Harris(HELPED ME ALOT!)

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🔄 What's Next (When I Return)

To complete this project, I plan to:

1. Study Existing ISAs - Analyze MIPS, RISC-V, ARM instruction sets to understand design patterns
2. Design Custom 16-bit ISA - Create complete instruction format specification
3. Build Missing Components - Instruction memory, instruction register
4. System Integration - Wire all modules together in cpu_top.v
5. Integration Testing - Write tests for complete instruction execution
6. Debug & Iterate - Fix timing issues, control signal problems, edge cases

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📊 Honest Assessment

What "~65-70% complete" means:

• Component implementation: 90%+ ✅
• System integration: 10-20% ❌
• ISA design: 0% ❌

Is this a "complete CPU"? No.
Did I learn computer architecture? Yes.
Can I explain how CPUs work? Yes.
Would I do it differently next time? Absolutely-- I'd design the ISA FIRST, then build components to match it.

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