align CIPO message to COPI and CS

[floesche]

• align TX to RX
• add more debug messages
• version currently used for 10 panel test

[mbreiser]

Bench-validated against Frank's arena main (acd5286, 25 MHz), both panels on this branch (pico_v0xx_spidiag):

• CIPO reads back 100% byte-perfect (01 30 62) on both SPI buses (50/50 each), cipo_realign=1; panels received ~15k frames/run, all sampled validity gates passing, 0 parity/queue/skip errors.
• The busy_wait_us(2) [VERIFY] drain showed no byte truncation at 25 MHz — tag can be retired with a pointer to this run.
• Confirms this PR composes cleanly with Frank's realignCipo (panel emits aligned bytes; arena compensates the 1-bit wire delay).

LGTM to merge. One latent edge case for a follow-up (not a blocker): prime_tx_confirmation() busy-waits unbounded with no TX-FIFO flush, so a sub-5-byte/zero-clock CS window could overflow the 8-deep FIFO and hang.