AXIOM-4 Microprocessor

AXIOM-4 is a 4-bit RISC-inspired microprocessor designed for FPGA synthesis and advanced architectural simulation. It features a robust Banked Memory Architecture, enabling a 256-byte unified address space across a compact 4-bit datapath.

Designed for educational excellence and transparency, AXIOM-4 bridges the gap between digital logic theory and practical modern processor design.

Core Architecture

• Datapath: 4-bit arithmetic and logic operations.
• Address Space: 256 Bytes (16 Pages x 16 Nibbles), managed via a dedicated 4-bit Page Register (PG).
• Pipeline: 2-Stage Finite State Machine (Fetch → Execute) for predictable timing.
• ISA: 17 Optimized Instructions including SET_PG for banking control, plus comprehensive Arithmetic, Logic, and I/O support.
• Modularity: Clean Verilog 2005 implementation with distinct Control Unit, ALU, and Datapath modules.

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Directory Structure

├── src
│   ├── modules          # Core Verilog Logic
│   │   ├── alu.v        # Arithmetic Logic Unit (Math & Logic)
│   │   ├── control.v    # Control Unit (FSM & Decoder)
│   │   ├── datapath.v   # Registers, Buses & Interconnects
│   │   └── top.v        # System integration (Core + Memory + I/O)
│   └── sim
│       └── top_tb.v     # Verification Testbench
├── scripts
│   └── asm.py           # AXIOM-4 Assembler (Python)
├── programs
│   └── test_suite_banked.asm  # Verification Suite
└── ARCHITECTURE.md      # Detailed Technical Specification

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Quick Start

1. Prerequisites

• Icarus Verilog: For simulation compilation.
• GTKWave: For signal visualization.
• Python 3: For the assembler toolchain.

2. Assembly

Compile your assembly code into machine-readable hex format:

python3 scripts/asm.py programs/test_suite_banked.asm test_suite.hex

3. Simulation

Build and execute the Verilog simulation:

# Compile
iverilog -o sim.out src/modules/*.v src/sim/top_tb.v

# Run Verification Mode
vvp sim.out +sub_test

4. Verification

Inspect the internal processor state using the generated VCD file:

gtkwave cpu_sim.vcd

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Technical Specifications

Feature	Details
Program Counter	8-bit ({Page, Offset} architecture)
Accumulator	4-bit General Purpose Register
Banking	4-bit Page Register allowing 16 Memory Pages
Instruction Set	17 Opcodes (Arithmetic, Logic, Control, I/O)
I/O Ports	4-bit Input / 4-bit Output (Memory Mapped)

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