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Add gpuEnableRx/Tx, avoid setting internal regs in rdmaTest#273

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JJL772 wants to merge 3 commits into
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pr-do-not-set-internal-regs
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Add gpuEnableRx/Tx, avoid setting internal regs in rdmaTest#273
JJL772 wants to merge 3 commits into
pre-releasefrom
pr-do-not-set-internal-regs

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@JJL772

@JJL772 JJL772 commented May 8, 2026

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  • These are internal registers and should not be set by userspace in most cases.

@JJL772 JJL772 requested a review from ruck314 May 8, 2026 15:42
@ruck314 ruck314 changed the base branch from main to pre-release May 8, 2026 16:06
@JJL772 JJL772 force-pushed the pr-do-not-set-internal-regs branch from f3c2f57 to 07866a9 Compare May 11, 2026 17:59
@JJL772 JJL772 changed the title Do not set internal regs in rmdatest Add gpuEnableRx/Tx, avoid setting internal regs in rdmaTest May 11, 2026
JJL772 added 3 commits June 12, 2026 16:41
…than the driver

We rely on MAX_GPU_BUFFERS to allocate static arrays in a number of
places. The assumption is that the hardware register will never give us
more than that number of buffers.

It's unlikely that MAX_GPU_BUFFERS will be upped to >1024 in the future,
but just in case, add a sanity check so we don't end up with memory
corruption in the kernel, if that day comes.
since gpuAddNvidiaMemory implicitly sets the write/read enable bits,
there are some concerns that the FPGA may initiate transactions before
the GPU is ready.

For the GpuAsyncCore V4+ path, we'll mandate the usage of gpuEnableRx
and gpuEnableTx after gpuAddNvidiaMemory to avoid this potential issue.
gpuAddNvidiaMemory will also clear the write/read enable bits.

The old V3 and earlier path remains unchanged.
@JJL772 JJL772 force-pushed the pr-do-not-set-internal-regs branch from 07866a9 to aa08814 Compare June 12, 2026 23:42
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