GitHub - steverowe44/VHDL-Processor: Developed in Xilinx Vivado. Fully functional processor consisting of Control Unit and Datapath.

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
testbenches		testbenches
Computer Arch Assignment 3.docx		Computer Arch Assignment 3.docx
car_register.vhd		car_register.vhd
control_mem_256x28.vhd		control_mem_256x28.vhd
datapath_9x16bit.vhd		datapath_9x16bit.vhd
decoder_4to9.vhd		decoder_4to9.vhd
full_adder.vhd		full_adder.vhd
func_operand_modifier.vhd		func_operand_modifier.vhd
function_unit.vhd		function_unit.vhd
logic_1bit.vhd		logic_1bit.vhd
logic_unit.vhd		logic_unit.vhd
mem_512x16.vhd		mem_512x16.vhd
mp_control_256x28.vhd		mp_control_256x28.vhd
mux2_16bit.vhd		mux2_16bit.vhd
mux2_1bit.vhd		mux2_1bit.vhd
mux4_1bit.vhd		mux4_1bit.vhd
mux8_1bit.vhd		mux8_1bit.vhd
mux9_16bit.vhd		mux9_16bit.vhd
processor_full.vhd		processor_full.vhd
program_counter.vhd		program_counter.vhd
register_16bit.vhd		register_16bit.vhd
register_file_9x16bit.vhd		register_file_9x16bit.vhd
ripple_carry_16bit.vhd		ripple_carry_16bit.vhd
shifter_16bit.vhd		shifter_16bit.vhd
zero_detect.vhd		zero_detect.vhd