Skip to content

ARM64 JIT: Optimize Group E register conversion #324

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
SChernykh merged 1 commit into from
Apr 25, 2026
+8 −15
Merged

ARM64 JIT: Optimize Group E register conversion #324

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 2 additions & 5 deletions src/jit_compiler_a64.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1001,11 +1001,8 @@ void JitCompilerA64::h_FDIV_M(Instruction& instr, uint32_t& codePos)
constexpr uint32_t tmp_reg_fp = 28;
emitMemLoadFP<tmp_reg_fp>(src, instr, code, k);

// and tmp_reg_fp, tmp_reg_fp, and_mask_reg
emit32(0x4E201C00 | tmp_reg_fp | (tmp_reg_fp << 5) | (29 << 16), code, k);

// orr tmp_reg_fp, tmp_reg_fp, or_mask_reg
emit32(0x4EA01C00 | tmp_reg_fp | (tmp_reg_fp << 5) | (30 << 16), code, k);
// bif tmp_reg_fp, or_mask_reg, and_mask_reg
emit32(0x6EE01C00 | tmp_reg_fp | (30 << 5) | (29 << 16), code, k);

emit32(ARMV8A::FDIV | dst | (dst << 5) | (tmp_reg_fp << 16), code, k);

Expand Down
16 changes: 6 additions & 10 deletions src/jit_compiler_a64_static.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -114,7 +114,7 @@
# v26 -> "a2"
# v27 -> "a3"
# v28 -> temporary
# v29 -> E 'and' mask = 0x00ffffffffffffff00ffffffffffffff
# v29 -> E 'and' mask = 0x00ffffffffc0000000ffffffffc00000
# v30 -> E 'or' mask = 0x3*00000000******3*00000000******
# v31 -> scale mask = 0x81f000000000000081f0000000000000

Expand Down Expand Up @@ -156,7 +156,7 @@ DECL(randomx_program_aarch64):
ldp q26, q27, [x0, 224]

# Load E 'and' mask
mov x16, 0x00FFFFFFFFFFFFFF
mov x16, 0x00FFFFFFFFC00000
ins v29.d[0], x16
ins v29.d[1], x16

Expand Down Expand Up @@ -269,14 +269,10 @@ DECL(randomx_program_aarch64_main_loop):
scvtf v21.2d, v21.2d
scvtf v22.2d, v22.2d
scvtf v23.2d, v23.2d
and v20.16b, v20.16b, v29.16b
and v21.16b, v21.16b, v29.16b
and v22.16b, v22.16b, v29.16b
and v23.16b, v23.16b, v29.16b
orr v20.16b, v20.16b, v30.16b
orr v21.16b, v21.16b, v30.16b
orr v22.16b, v22.16b, v30.16b
orr v23.16b, v23.16b, v30.16b
bif v20.16b, v30.16b, v29.16b
bif v21.16b, v30.16b, v29.16b
bif v22.16b, v30.16b, v29.16b
bif v23.16b, v30.16b, v29.16b

# Execute VM instructions
DECL(randomx_program_aarch64_vm_instructions):
Expand Down
Loading